diff options
author | Markos Chandras <markos.chandras@imgtec.com> | 2014-11-10 07:25:34 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-11-24 01:44:05 -0500 |
commit | cf0a8aa0226da5de88011e7f30eff22a894b2f49 (patch) | |
tree | b508470022cd20f8cf0fcb8be10ee7f2904e07bc /arch | |
parent | 4ec8f9e9b08451303253249e4e302f10ee23d565 (diff) |
MIPS: cpu-probe: Set the FTLB probability bit on supported cores
Make use of the Config6/FLTBP bit to set the probability of a TLBWR
instruction to hit the FTLB or the VTLB. A value of 0 (which may be
the default value on certain cores, such as proAptiv or P5600)
means that a TLBWR instruction will never hit the VTLB which
leads to performance limitations since it effectively decreases
the number of available TLB slots.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8368/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/include/asm/mipsregs.h | 2 | ||||
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 33 |
2 files changed, 34 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b46cd220a018..22a135ac91de 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h | |||
@@ -661,6 +661,8 @@ | |||
661 | #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) | 661 | #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) |
662 | /* proAptiv FTLB on/off bit */ | 662 | /* proAptiv FTLB on/off bit */ |
663 | #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) | 663 | #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) |
664 | /* FTLB probability bits */ | ||
665 | #define MIPS_CONF6_FTLBP_SHIFT (16) | ||
664 | 666 | ||
665 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) | 667 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
666 | 668 | ||
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index d5a4f380b019..dc49cf30c2db 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -193,6 +193,32 @@ static void set_isa(struct cpuinfo_mips *c, unsigned int isa) | |||
193 | static char unknown_isa[] = KERN_ERR \ | 193 | static char unknown_isa[] = KERN_ERR \ |
194 | "Unsupported ISA type, c0.config0: %d."; | 194 | "Unsupported ISA type, c0.config0: %d."; |
195 | 195 | ||
196 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) | ||
197 | { | ||
198 | |||
199 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; | ||
200 | |||
201 | /* | ||
202 | * 0 = All TLBWR instructions go to FTLB | ||
203 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the | ||
204 | * FTLB and 1 goes to the VTLB. | ||
205 | * 2 = 7:1: As above with 7:1 ratio. | ||
206 | * 3 = 3:1: As above with 3:1 ratio. | ||
207 | * | ||
208 | * Use the linear midpoint as the probability threshold. | ||
209 | */ | ||
210 | if (probability >= 12) | ||
211 | return 1; | ||
212 | else if (probability >= 6) | ||
213 | return 2; | ||
214 | else | ||
215 | /* | ||
216 | * So FTLB is less than 4 times bigger than VTLB. | ||
217 | * A 3:1 ratio can still be useful though. | ||
218 | */ | ||
219 | return 3; | ||
220 | } | ||
221 | |||
196 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) | 222 | static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) |
197 | { | 223 | { |
198 | unsigned int config6; | 224 | unsigned int config6; |
@@ -203,9 +229,14 @@ static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) | |||
203 | case CPU_P5600: | 229 | case CPU_P5600: |
204 | /* proAptiv & related cores use Config6 to enable the FTLB */ | 230 | /* proAptiv & related cores use Config6 to enable the FTLB */ |
205 | config6 = read_c0_config6(); | 231 | config6 = read_c0_config6(); |
232 | /* Clear the old probability value */ | ||
233 | config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); | ||
206 | if (enable) | 234 | if (enable) |
207 | /* Enable FTLB */ | 235 | /* Enable FTLB */ |
208 | write_c0_config6(config6 | MIPS_CONF6_FTLBEN); | 236 | write_c0_config6(config6 | |
237 | (calculate_ftlb_probability(c) | ||
238 | << MIPS_CONF6_FTLBP_SHIFT) | ||
239 | | MIPS_CONF6_FTLBEN); | ||
209 | else | 240 | else |
210 | /* Disable FTLB */ | 241 | /* Disable FTLB */ |
211 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); | 242 | write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); |