Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3533/1: Implement the __raw_(read|write)_can_lock functions on ARM
  [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia
  [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction

2 files changed, 6 insertions, 5 deletions

diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 98356f810007..02e188d98e7d 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void)
         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
                 set_irq_chip(irq, &mainstone_irq_chip);
                 set_irq_handler(irq, do_level_IRQ);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
+                else
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
         set_irq_flags(MAINSTONE_IRQ(8), 0);
         set_irq_flags(MAINSTONE_IRQ(12), 0);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 832fb86a03b4..73de2eaca22a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
         mrc     p15, 0, r5, c13, c0, 0  @ PID
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 0   @ translation table base address
-        mrc     p15, 0, r8, c2, c0, 0   @ auxiliary control register
-        mrc     p15, 0, r9, c1, c0, 0   @ control register
+        mrc     p15, 0, r8, c1, c0, 0   @ control register
 
         stmia   r0, { r4 - r13 }
 
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
         mcr     p15, 0, r5, c13, c0, 0          @ PID
         mcr     p15, 0, r6, c3, c0, 0           @ Domain ID
         mcr     p15, 0, r7, c2, c0, 0           @ translation table base
-        mcr     p15, 0, r8, c1, c1, 0           @ auxilliary control
 
 #ifdef CONFIG_DEBUG_RESUME
         mov     r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
 #endif
 
         ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, etc
+        mcr     p15, 0, r8, c1, c0, 0           @ turn on MMU, etc
         nop                                     @ second-to-last before mmu
         mov     pc, r2                          @ go back to virtual address