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authorLinus Torvalds <torvalds@g5.osdl.org>2006-05-19 19:42:11 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-05-19 19:42:11 -0400
commit890f74291c9133eaed6c0eb8514f7618d43d0925 (patch)
tree445a9de7b2e554bde5ec9d18d67f2c56e8477d16
parentb0c51b7d650d5109c8e71e19d5e7ce9b71af7dff (diff)
parentc2a4c40651e08e465d3a6130bd9f6dcc1ce21d83 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3533/1: Implement the __raw_(read|write)_can_lock functions on ARM [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction
-rw-r--r--arch/arm/mach-pxa/mainstone.c5
-rw-r--r--arch/arm/mach-s3c2410/sleep.S6
-rw-r--r--include/asm-arm/spinlock.h6
3 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 98356f810007..02e188d98e7d 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void)
95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { 95 for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
96 set_irq_chip(irq, &mainstone_irq_chip); 96 set_irq_chip(irq, &mainstone_irq_chip);
97 set_irq_handler(irq, do_level_IRQ); 97 set_irq_handler(irq, do_level_IRQ);
98 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 98 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
99 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
100 else
101 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
99 } 102 }
100 set_irq_flags(MAINSTONE_IRQ(8), 0); 103 set_irq_flags(MAINSTONE_IRQ(8), 0);
101 set_irq_flags(MAINSTONE_IRQ(12), 0); 104 set_irq_flags(MAINSTONE_IRQ(12), 0);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 832fb86a03b4..73de2eaca22a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
59 mrc p15, 0, r5, c13, c0, 0 @ PID 59 mrc p15, 0, r5, c13, c0, 0 @ PID
60 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 60 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
61 mrc p15, 0, r7, c2, c0, 0 @ translation table base address 61 mrc p15, 0, r7, c2, c0, 0 @ translation table base address
62 mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register 62 mrc p15, 0, r8, c1, c0, 0 @ control register
63 mrc p15, 0, r9, c1, c0, 0 @ control register
64 63
65 stmia r0, { r4 - r13 } 64 stmia r0, { r4 - r13 }
66 65
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
165 mcr p15, 0, r5, c13, c0, 0 @ PID 164 mcr p15, 0, r5, c13, c0, 0 @ PID
166 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 165 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
167 mcr p15, 0, r7, c2, c0, 0 @ translation table base 166 mcr p15, 0, r7, c2, c0, 0 @ translation table base
168 mcr p15, 0, r8, c1, c1, 0 @ auxilliary control
169 167
170#ifdef CONFIG_DEBUG_RESUME 168#ifdef CONFIG_DEBUG_RESUME
171 mov r3, #'R' 169 mov r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
173#endif 171#endif
174 172
175 ldr r2, =resume_with_mmu 173 ldr r2, =resume_with_mmu
176 mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc 174 mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc
177 nop @ second-to-last before mmu 175 nop @ second-to-last before mmu
178 mov pc, r2 @ go back to virtual address 176 mov pc, r2 @ go back to virtual address
179 177
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index 43ad4e55878c..406ca97a8ab2 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -142,6 +142,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
142 : "cc"); 142 : "cc");
143} 143}
144 144
145/* write_can_lock - would write_trylock() succeed? */
146#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
147
145/* 148/*
146 * Read locks are a bit more hairy: 149 * Read locks are a bit more hairy:
147 * - Exclusively load the lock value. 150 * - Exclusively load the lock value.
@@ -198,4 +201,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
198 201
199#define __raw_read_trylock(lock) generic__raw_read_trylock(lock) 202#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
200 203
204/* read_can_lock - would read_trylock() succeed? */
205#define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
206
201#endif /* __ASM_SPINLOCK_H */ 207#endif /* __ASM_SPINLOCK_H */