diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2013-07-21 23:14:00 -0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-07-22 00:10:03 -0400 |
| commit | 7be914f2a333a4d74cf1ae0abdb162bff350be6c (patch) | |
| tree | efa7a04ae40fb5f41d75c17573442d0675b49d50 /arch | |
| parent | 45ffdd324c92d3b64b6b2874aaf0ac305d25504e (diff) | |
ARM: OMAP3: PRM/CM: Cleanup unused header
Cleanup unused parts of the PRM and CM regbit headers leaving only whats
used.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-33xx.h | 749 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 632 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-33xx.h | 306 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 481 |
4 files changed, 0 insertions, 2168 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index adf7bb79b18f..c0823fd6d5e0 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h | |||
| @@ -20,798 +20,49 @@ | |||
| 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | 20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H |
| 21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | 21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H |
| 22 | 22 | ||
| 23 | /* | ||
| 24 | * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, | ||
| 25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER | ||
| 26 | */ | ||
| 27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 | ||
| 28 | #define AM33XX_AUTO_DPLL_MODE_WIDTH 3 | ||
| 29 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | ||
| 30 | |||
| 31 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 | ||
| 33 | #define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 | ||
| 34 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) | ||
| 35 | |||
| 36 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 37 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 | ||
| 38 | #define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 | ||
| 39 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) | ||
| 40 | |||
| 41 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ | ||
| 42 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 | ||
| 43 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 | ||
| 44 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) | ||
| 45 | |||
| 46 | /* Used by CM_PER_CPSW_CLKSTCTRL */ | ||
| 47 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 | ||
| 48 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 | ||
| 49 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) | ||
| 50 | |||
| 51 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 52 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 | ||
| 53 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 | ||
| 54 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) | ||
| 55 | |||
| 56 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 57 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 | ||
| 58 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 | ||
| 59 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) | ||
| 60 | |||
| 61 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 62 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 | ||
| 63 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 | ||
| 64 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) | ||
| 65 | |||
| 66 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 67 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 | ||
| 68 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 | ||
| 69 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) | ||
| 70 | |||
| 71 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 72 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
| 73 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 | ||
| 74 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
| 75 | |||
| 76 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 77 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 | ||
| 78 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 | ||
| 79 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) | ||
| 80 | |||
| 81 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 82 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 | ||
| 83 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 | ||
| 84 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) | ||
| 85 | |||
| 86 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 87 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 | ||
| 88 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 | ||
| 89 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) | ||
| 90 | |||
| 91 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
| 92 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 | ||
| 93 | #define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 | ||
| 94 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) | ||
| 95 | |||
| 96 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
| 97 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 | ||
| 98 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 | ||
| 99 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) | ||
| 100 | |||
| 101 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 102 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 | ||
| 103 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 | ||
| 104 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) | ||
| 105 | |||
| 106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 107 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 | ||
| 108 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 | ||
| 109 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) | ||
| 110 | |||
| 111 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 112 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 | ||
| 113 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 | ||
| 114 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) | ||
| 115 | |||
| 116 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 117 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 | ||
| 118 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 | ||
| 119 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) | ||
| 120 | |||
| 121 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 122 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 | ||
| 123 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 | ||
| 124 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) | ||
| 125 | |||
| 126 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 127 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 | ||
| 128 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 | ||
| 129 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) | ||
| 130 | |||
| 131 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 132 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 | ||
| 133 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 | ||
| 134 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) | ||
| 135 | |||
| 136 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 137 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 | ||
| 138 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 | ||
| 139 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) | ||
| 140 | |||
| 141 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 142 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 | ||
| 143 | #define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 | ||
| 144 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) | ||
| 145 | |||
| 146 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 147 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 | ||
| 148 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 | ||
| 149 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) | ||
| 150 | |||
| 151 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 152 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 | ||
| 153 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 | ||
| 154 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) | ||
| 155 | |||
| 156 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
| 157 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 | ||
| 158 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 | ||
| 159 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) | ||
| 160 | |||
| 161 | /* Used by CM_PER_L3S_CLKSTCTRL */ | ||
| 162 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 | ||
| 163 | #define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 | ||
| 164 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) | ||
| 165 | |||
| 166 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
| 167 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 | ||
| 168 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 | ||
| 169 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) | ||
| 170 | |||
| 171 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 172 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 | ||
| 173 | #define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 | ||
| 174 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) | ||
| 175 | |||
| 176 | /* Used by CM_PER_L4FW_CLKSTCTRL */ | ||
| 177 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 | ||
| 178 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 | ||
| 179 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) | ||
| 180 | |||
| 181 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
| 182 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 | ||
| 183 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 | ||
| 184 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) | ||
| 185 | |||
| 186 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 187 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 | ||
| 188 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 | ||
| 189 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) | ||
| 190 | |||
| 191 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ | ||
| 192 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 | ||
| 193 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 | ||
| 194 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) | ||
| 195 | |||
| 196 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 197 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
| 198 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 | ||
| 199 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
| 200 | |||
| 201 | /* Used by CM_RTC_CLKSTCTRL */ | ||
| 202 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 | ||
| 203 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 | ||
| 204 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) | ||
| 205 | |||
| 206 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ | ||
| 207 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 | ||
| 208 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 | ||
| 209 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) | ||
| 210 | |||
| 211 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 212 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 | ||
| 213 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 | ||
| 214 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) | ||
| 215 | |||
| 216 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 217 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 | ||
| 218 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 | ||
| 219 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) | ||
| 220 | |||
| 221 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
| 222 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 | ||
| 223 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 | ||
| 224 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) | ||
| 225 | |||
| 226 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
| 227 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 | ||
| 228 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 | ||
| 229 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) | ||
| 230 | |||
| 231 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 232 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 | ||
| 233 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 | ||
| 234 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) | ||
| 235 | |||
| 236 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
| 237 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 | ||
| 238 | #define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 | ||
| 239 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) | ||
| 240 | |||
| 241 | /* Used by CM_MPU_CLKSTCTRL */ | ||
| 242 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 | ||
| 243 | #define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 | ||
| 244 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) | ||
| 245 | |||
| 246 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
| 247 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 | ||
| 248 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 | ||
| 249 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) | ||
| 250 | |||
| 251 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
| 252 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 | ||
| 253 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 | ||
| 254 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) | ||
| 255 | |||
| 256 | /* Used by CM_RTC_CLKSTCTRL */ | ||
| 257 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 | ||
| 258 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 | ||
| 259 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) | ||
| 260 | |||
| 261 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 262 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 | ||
| 263 | #define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 | ||
| 264 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) | ||
| 265 | |||
| 266 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 267 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 | ||
| 268 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 | ||
| 269 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) | ||
| 270 | |||
| 271 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 272 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 | ||
| 273 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 | ||
| 274 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) | ||
| 275 | |||
| 276 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 277 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 | ||
| 278 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 | ||
| 279 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) | ||
| 280 | |||
| 281 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 282 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 | ||
| 283 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 | ||
| 284 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) | ||
| 285 | |||
| 286 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 287 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 | ||
| 288 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 | ||
| 289 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) | ||
| 290 | |||
| 291 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 292 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 | ||
| 293 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 | ||
| 294 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) | ||
| 295 | |||
| 296 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 297 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 | ||
| 298 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 | ||
| 299 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) | ||
| 300 | |||
| 301 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 302 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 | ||
| 303 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 | ||
| 304 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) | ||
| 305 | |||
| 306 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 307 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 | ||
| 308 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 | ||
| 309 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) | ||
| 310 | |||
| 311 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 312 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 | ||
| 313 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 | ||
| 314 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) | ||
| 315 | |||
| 316 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
| 317 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 | ||
| 318 | #define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 | ||
| 319 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) | ||
| 320 | |||
| 321 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 322 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 | ||
| 323 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 | ||
| 324 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) | ||
| 325 | |||
| 326 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 327 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 | ||
| 328 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 | ||
| 329 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) | ||
| 330 | |||
| 331 | /* Used by CLKSEL_GFX_FCLK */ | ||
| 332 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 | ||
| 333 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 | ||
| 334 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) | ||
| 335 | |||
| 336 | /* Used by CM_CLKOUT_CTRL */ | ||
| 337 | #define AM33XX_CLKOUT2DIV_SHIFT 3 | 23 | #define AM33XX_CLKOUT2DIV_SHIFT 3 |
| 338 | #define AM33XX_CLKOUT2DIV_WIDTH 3 | 24 | #define AM33XX_CLKOUT2DIV_WIDTH 3 |
| 339 | #define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) | ||
| 340 | |||
| 341 | /* Used by CM_CLKOUT_CTRL */ | ||
| 342 | #define AM33XX_CLKOUT2EN_SHIFT 7 | 25 | #define AM33XX_CLKOUT2EN_SHIFT 7 |
| 343 | #define AM33XX_CLKOUT2EN_WIDTH 1 | ||
| 344 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) | ||
| 345 | |||
| 346 | /* Used by CM_CLKOUT_CTRL */ | ||
| 347 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 | ||
| 348 | #define AM33XX_CLKOUT2SOURCE_WIDTH 3 | ||
| 349 | #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) | 26 | #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) |
| 350 | |||
| 351 | /* | ||
| 352 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, | ||
| 353 | * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, | ||
| 354 | * CLKSEL_TIMER7_CLK | ||
| 355 | */ | ||
| 356 | #define AM33XX_CLKSEL_SHIFT 0 | ||
| 357 | #define AM33XX_CLKSEL_WIDTH 1 | ||
| 358 | #define AM33XX_CLKSEL_MASK (0x01 << 0) | ||
| 359 | |||
| 360 | /* | ||
| 361 | * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, | ||
| 362 | * CM_CPTS_RFT_CLKSEL | ||
| 363 | */ | ||
| 364 | #define AM33XX_CLKSEL_0_0_SHIFT 0 | 27 | #define AM33XX_CLKSEL_0_0_SHIFT 0 |
| 365 | #define AM33XX_CLKSEL_0_0_WIDTH 1 | 28 | #define AM33XX_CLKSEL_0_0_WIDTH 1 |
| 366 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) | 29 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) |
| 367 | |||
| 368 | #define AM33XX_CLKSEL_0_1_SHIFT 0 | ||
| 369 | #define AM33XX_CLKSEL_0_1_WIDTH 2 | ||
| 370 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) | 30 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) |
| 371 | |||
| 372 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ | ||
| 373 | #define AM33XX_CLKSEL_0_2_SHIFT 0 | ||
| 374 | #define AM33XX_CLKSEL_0_2_WIDTH 3 | ||
| 375 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) | 31 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) |
| 376 | |||
| 377 | /* Used by CLKSEL_GFX_FCLK */ | ||
| 378 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 | ||
| 379 | #define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 | ||
| 380 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) | 32 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) |
| 381 | |||
| 382 | /* | ||
| 383 | * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, | ||
| 384 | * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, | ||
| 385 | * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, | ||
| 386 | * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, | ||
| 387 | * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, | ||
| 388 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL | ||
| 389 | */ | ||
| 390 | #define AM33XX_CLKTRCTRL_SHIFT 0 | 33 | #define AM33XX_CLKTRCTRL_SHIFT 0 |
| 391 | #define AM33XX_CLKTRCTRL_WIDTH 2 | ||
| 392 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) | 34 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) |
| 393 | |||
| 394 | /* | ||
| 395 | * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, | ||
| 396 | * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, | ||
| 397 | * CM_SSC_DELTAMSTEP_DPLL_PER | ||
| 398 | */ | ||
| 399 | #define AM33XX_DELTAMSTEP_SHIFT 0 | ||
| 400 | #define AM33XX_DELTAMSTEP_WIDTH 20 | ||
| 401 | #define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) | ||
| 402 | |||
| 403 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ | ||
| 404 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 | ||
| 405 | #define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 | ||
| 406 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
| 407 | |||
| 408 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 409 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
| 410 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 | ||
| 411 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
| 412 | |||
| 413 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 414 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 | ||
| 415 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 | ||
| 416 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) | ||
| 417 | |||
| 418 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
| 419 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 | 35 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 |
| 420 | #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 | 36 | #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 |
| 421 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 422 | |||
| 423 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ | ||
| 424 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
| 425 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 | ||
| 426 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) | ||
| 427 | |||
| 428 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
| 429 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
| 430 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 | ||
| 431 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
| 432 | |||
| 433 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ | ||
| 434 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 | ||
| 435 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 | ||
| 436 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) | ||
| 437 | |||
| 438 | /* | ||
| 439 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
| 440 | * CM_DIV_M2_DPLL_PER | ||
| 441 | */ | ||
| 442 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
| 443 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 | ||
| 444 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | ||
| 445 | |||
| 446 | /* | ||
| 447 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
| 448 | * CM_CLKSEL_DPLL_MPU | ||
| 449 | */ | ||
| 450 | #define AM33XX_DPLL_DIV_SHIFT 0 | ||
| 451 | #define AM33XX_DPLL_DIV_WIDTH 7 | ||
| 452 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) | 37 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) |
| 453 | |||
| 454 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) | 38 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) |
| 455 | |||
| 456 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 457 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 | ||
| 458 | #define AM33XX_DPLL_DIV_0_7_WIDTH 8 | ||
| 459 | #define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) | ||
| 460 | |||
| 461 | /* | ||
| 462 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 463 | * CM_CLKMODE_DPLL_MPU | ||
| 464 | */ | ||
| 465 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
| 466 | #define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 | ||
| 467 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
| 468 | |||
| 469 | /* | ||
| 470 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 471 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 472 | */ | ||
| 473 | #define AM33XX_DPLL_EN_SHIFT 0 | ||
| 474 | #define AM33XX_DPLL_EN_WIDTH 3 | ||
| 475 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) | 39 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) |
| 476 | |||
| 477 | /* | ||
| 478 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 479 | * CM_CLKMODE_DPLL_MPU | ||
| 480 | */ | ||
| 481 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 | ||
| 482 | #define AM33XX_DPLL_LPMODE_EN_WIDTH 1 | ||
| 483 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) | ||
| 484 | |||
| 485 | /* | ||
| 486 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
| 487 | * CM_CLKSEL_DPLL_MPU | ||
| 488 | */ | ||
| 489 | #define AM33XX_DPLL_MULT_SHIFT 8 | ||
| 490 | #define AM33XX_DPLL_MULT_WIDTH 11 | ||
| 491 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) | 40 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) |
| 492 | |||
| 493 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 494 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 | ||
| 495 | #define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 | ||
| 496 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) | 41 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) |
| 497 | |||
| 498 | /* | ||
| 499 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 500 | * CM_CLKMODE_DPLL_MPU | ||
| 501 | */ | ||
| 502 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 | ||
| 503 | #define AM33XX_DPLL_REGM4XEN_WIDTH 1 | ||
| 504 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) | ||
| 505 | |||
| 506 | /* Used by CM_CLKSEL_DPLL_PERIPH */ | ||
| 507 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 | ||
| 508 | #define AM33XX_DPLL_SD_DIV_WIDTH 8 | ||
| 509 | #define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) | ||
| 510 | |||
| 511 | /* | ||
| 512 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 513 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 514 | */ | ||
| 515 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 | ||
| 516 | #define AM33XX_DPLL_SSC_ACK_WIDTH 1 | ||
| 517 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) | ||
| 518 | |||
| 519 | /* | ||
| 520 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 521 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 522 | */ | ||
| 523 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
| 524 | #define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 | ||
| 525 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
| 526 | |||
| 527 | /* | ||
| 528 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
| 529 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 530 | */ | ||
| 531 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 | ||
| 532 | #define AM33XX_DPLL_SSC_EN_WIDTH 1 | ||
| 533 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) | ||
| 534 | |||
| 535 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 536 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | 42 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 |
| 537 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 | 43 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 |
| 538 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | ||
| 539 | |||
| 540 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 541 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
| 542 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 | ||
| 543 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
| 544 | |||
| 545 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 546 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
| 547 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 | ||
| 548 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
| 549 | |||
| 550 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 551 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
| 552 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 | ||
| 553 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
| 554 | |||
| 555 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 556 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | 44 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 |
| 557 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 | 45 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 |
| 558 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | ||
| 559 | |||
| 560 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 561 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
| 562 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 | ||
| 563 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
| 564 | |||
| 565 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 566 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
| 567 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 | ||
| 568 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
| 569 | |||
| 570 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 571 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
| 572 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 | ||
| 573 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
| 574 | |||
| 575 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 576 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | 46 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 |
| 577 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 | 47 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 |
| 578 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) | ||
| 579 | |||
| 580 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 581 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
| 582 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 | ||
| 583 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
| 584 | |||
| 585 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 586 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
| 587 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 | ||
| 588 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
| 589 | |||
| 590 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 591 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
| 592 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 | ||
| 593 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
| 594 | |||
| 595 | /* | ||
| 596 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
| 597 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
| 598 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
| 599 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
| 600 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
| 601 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
| 602 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
| 603 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
| 604 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
| 605 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
| 606 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
| 607 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
| 608 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
| 609 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
| 610 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 611 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
| 612 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
| 613 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
| 614 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
| 615 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
| 616 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
| 617 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 618 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
| 619 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
| 620 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
| 621 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
| 622 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
| 623 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
| 624 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
| 625 | * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
| 626 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL | ||
| 627 | */ | ||
| 628 | #define AM33XX_IDLEST_SHIFT 16 | 48 | #define AM33XX_IDLEST_SHIFT 16 |
| 629 | #define AM33XX_IDLEST_WIDTH 2 | ||
| 630 | #define AM33XX_IDLEST_MASK (0x3 << 16) | 49 | #define AM33XX_IDLEST_MASK (0x3 << 16) |
| 631 | |||
| 632 | /* Used by CM_MAC_CLKSEL */ | ||
| 633 | #define AM33XX_MII_CLK_SEL_SHIFT 2 | ||
| 634 | #define AM33XX_MII_CLK_SEL_WIDTH 1 | ||
| 635 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) | ||
| 636 | |||
| 637 | /* | ||
| 638 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
| 639 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
| 640 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
| 641 | */ | ||
| 642 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 | ||
| 643 | #define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 | ||
| 644 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
| 645 | |||
| 646 | /* | ||
| 647 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
| 648 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
| 649 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
| 650 | */ | ||
| 651 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 | ||
| 652 | #define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 | ||
| 653 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
| 654 | |||
| 655 | /* | ||
| 656 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
| 657 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
| 658 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
| 659 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
| 660 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
| 661 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
| 662 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
| 663 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
| 664 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
| 665 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
| 666 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
| 667 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
| 668 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
| 669 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
| 670 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 671 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
| 672 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
| 673 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
| 674 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
| 675 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
| 676 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
| 677 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 678 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
| 679 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
| 680 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
| 681 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
| 682 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
| 683 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
| 684 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
| 685 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, | ||
| 686 | * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, | ||
| 687 | * CM_CEFUSE_CEFUSE_CLKCTRL | ||
| 688 | */ | ||
| 689 | #define AM33XX_MODULEMODE_SHIFT 0 | 50 | #define AM33XX_MODULEMODE_SHIFT 0 |
| 690 | #define AM33XX_MODULEMODE_WIDTH 2 | ||
| 691 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) | 51 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) |
| 692 | |||
| 693 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 694 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 | 52 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 |
| 695 | #define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 | ||
| 696 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) | ||
| 697 | |||
| 698 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 699 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 | 53 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 |
| 700 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 | ||
| 701 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) | ||
| 702 | |||
| 703 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ | ||
| 704 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 | 54 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 |
| 705 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 | ||
| 706 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) | ||
| 707 | |||
| 708 | /* Used by CM_PER_GPIO1_CLKCTRL */ | ||
| 709 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 | 55 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 |
| 710 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 | ||
| 711 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) | ||
| 712 | |||
| 713 | /* Used by CM_PER_GPIO2_CLKCTRL */ | ||
| 714 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 | 56 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 |
| 715 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 | ||
| 716 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) | ||
| 717 | |||
| 718 | /* Used by CM_PER_GPIO3_CLKCTRL */ | ||
| 719 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 | 57 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 |
| 720 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 | ||
| 721 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) | ||
| 722 | |||
| 723 | /* Used by CM_PER_GPIO4_CLKCTRL */ | ||
| 724 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 | ||
| 725 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 | ||
| 726 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) | ||
| 727 | |||
| 728 | /* Used by CM_PER_GPIO5_CLKCTRL */ | ||
| 729 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 | ||
| 730 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 | ||
| 731 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) | ||
| 732 | |||
| 733 | /* Used by CM_PER_GPIO6_CLKCTRL */ | ||
| 734 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 | ||
| 735 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 | ||
| 736 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) | ||
| 737 | |||
| 738 | /* | ||
| 739 | * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, | ||
| 740 | * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, | ||
| 741 | * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
| 742 | * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
| 743 | * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, | ||
| 744 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL | ||
| 745 | */ | ||
| 746 | #define AM33XX_STBYST_SHIFT 18 | ||
| 747 | #define AM33XX_STBYST_WIDTH 1 | ||
| 748 | #define AM33XX_STBYST_MASK (1 << 18) | ||
| 749 | |||
| 750 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 751 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 | 58 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 |
| 752 | #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 | 59 | #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 |
| 753 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) | ||
| 754 | |||
| 755 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 756 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 | 60 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 |
| 757 | #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 | 61 | #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 |
| 758 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) | ||
| 759 | |||
| 760 | /* | ||
| 761 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
| 762 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
| 763 | */ | ||
| 764 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 | ||
| 765 | #define AM33XX_ST_DPLL_CLK_WIDTH 1 | ||
| 766 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) | 62 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) |
| 767 | |||
| 768 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
| 769 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 | 63 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 |
| 770 | #define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 | ||
| 771 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) | ||
| 772 | |||
| 773 | /* | ||
| 774 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
| 775 | * CM_DIV_M2_DPLL_PER | ||
| 776 | */ | ||
| 777 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 | ||
| 778 | #define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 | ||
| 779 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
| 780 | |||
| 781 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
| 782 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
| 783 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 | ||
| 784 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
| 785 | |||
| 786 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
| 787 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
| 788 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 | ||
| 789 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
| 790 | |||
| 791 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
| 792 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
| 793 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 | ||
| 794 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
| 795 | |||
| 796 | /* | ||
| 797 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
| 798 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
| 799 | */ | ||
| 800 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 | ||
| 801 | #define AM33XX_ST_MN_BYPASS_WIDTH 1 | ||
| 802 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) | ||
| 803 | |||
| 804 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 805 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 | 64 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 |
| 806 | #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 | 65 | #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 |
| 807 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) | ||
| 808 | |||
| 809 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
| 810 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 | 66 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 |
| 811 | #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 | 67 | #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 |
| 812 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) | ||
| 813 | |||
| 814 | /* Used by CONTROL_SEC_CLK_CTRL */ | ||
| 815 | #define AM33XX_TIMER0_CLKSEL_WIDTH 2 | ||
| 816 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) | ||
| 817 | #endif | 68 | #endif |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index adf78d325804..04dab2fcf862 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -14,833 +14,201 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | /* Bits shared between registers */ | ||
| 18 | |||
| 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 20 | #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) | ||
| 21 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 | 17 | #define OMAP3430ES2_EN_MMC3_SHIFT 30 |
| 22 | #define OMAP3430_EN_MSPRO_MASK (1 << 23) | ||
| 23 | #define OMAP3430_EN_MSPRO_SHIFT 23 | 18 | #define OMAP3430_EN_MSPRO_SHIFT 23 |
| 24 | #define OMAP3430_EN_HDQ_MASK (1 << 22) | ||
| 25 | #define OMAP3430_EN_HDQ_SHIFT 22 | 19 | #define OMAP3430_EN_HDQ_SHIFT 22 |
| 26 | #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) | ||
| 27 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 | 20 | #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 |
| 28 | #define OMAP3430ES1_EN_D2D_MASK (1 << 3) | ||
| 29 | #define OMAP3430ES1_EN_D2D_SHIFT 3 | 21 | #define OMAP3430ES1_EN_D2D_SHIFT 3 |
| 30 | #define OMAP3430_EN_SSI_MASK (1 << 0) | ||
| 31 | #define OMAP3430_EN_SSI_SHIFT 0 | 22 | #define OMAP3430_EN_SSI_SHIFT 0 |
| 32 | |||
| 33 | /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ | ||
| 34 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 | 23 | #define OMAP3430ES2_EN_USBTLL_SHIFT 2 |
| 35 | #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) | ||
| 36 | |||
| 37 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 38 | #define OMAP3430_EN_WDT2_MASK (1 << 5) | ||
| 39 | #define OMAP3430_EN_WDT2_SHIFT 5 | 24 | #define OMAP3430_EN_WDT2_SHIFT 5 |
| 40 | |||
| 41 | /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ | ||
| 42 | #define OMAP3430_EN_CAM_MASK (1 << 0) | ||
| 43 | #define OMAP3430_EN_CAM_SHIFT 0 | 25 | #define OMAP3430_EN_CAM_SHIFT 0 |
| 44 | |||
| 45 | /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ | ||
| 46 | #define OMAP3430_EN_WDT3_MASK (1 << 12) | ||
| 47 | #define OMAP3430_EN_WDT3_SHIFT 12 | 26 | #define OMAP3430_EN_WDT3_SHIFT 12 |
| 48 | |||
| 49 | /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ | ||
| 50 | #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) | ||
| 51 | |||
| 52 | |||
| 53 | /* Bits specific to each register */ | ||
| 54 | |||
| 55 | /* CM_FCLKEN_IVA2 */ | ||
| 56 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) | 27 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) |
| 57 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 | 28 | #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 |
| 58 | |||
| 59 | /* CM_CLKEN_PLL_IVA2 */ | ||
| 60 | #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 | ||
| 61 | #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 62 | #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 | ||
| 63 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) | 29 | #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) |
| 64 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 | 30 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 |
| 65 | #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 66 | #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 | ||
| 67 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) | 31 | #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) |
| 68 | |||
| 69 | /* CM_IDLEST_IVA2 */ | ||
| 70 | #define OMAP3430_ST_IVA2_SHIFT 0 | 32 | #define OMAP3430_ST_IVA2_SHIFT 0 |
| 71 | #define OMAP3430_ST_IVA2_MASK (1 << 0) | ||
| 72 | |||
| 73 | /* CM_IDLEST_PLL_IVA2 */ | ||
| 74 | #define OMAP3430_ST_IVA2_CLK_SHIFT 0 | ||
| 75 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) | 33 | #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) |
| 76 | |||
| 77 | /* CM_AUTOIDLE_PLL_IVA2 */ | ||
| 78 | #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 | ||
| 79 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) | 34 | #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) |
| 80 | |||
| 81 | /* CM_CLKSEL1_PLL_IVA2 */ | ||
| 82 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 | 35 | #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 |
| 83 | #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) | ||
| 84 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 | 36 | #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 |
| 85 | #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 | ||
| 86 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) | 37 | #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) |
| 87 | #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 | ||
| 88 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) | 38 | #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) |
| 89 | |||
| 90 | /* CM_CLKSEL2_PLL_IVA2 */ | ||
| 91 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 | 39 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 |
| 92 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 93 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 | 40 | #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 |
| 94 | |||
| 95 | /* CM_CLKSTCTRL_IVA2 */ | ||
| 96 | #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 | ||
| 97 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) | 41 | #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) |
| 98 | |||
| 99 | /* CM_CLKSTST_IVA2 */ | ||
| 100 | #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 | ||
| 101 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) | 42 | #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) |
| 102 | |||
| 103 | /* CM_REVISION specific bits */ | ||
| 104 | |||
| 105 | /* CM_SYSCONFIG specific bits */ | ||
| 106 | |||
| 107 | /* CM_CLKEN_PLL_MPU */ | ||
| 108 | #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 | ||
| 109 | #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 110 | #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 | ||
| 111 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) | 43 | #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) |
| 112 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 | 44 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 |
| 113 | #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 114 | #define OMAP3430_EN_MPU_DPLL_SHIFT 0 | ||
| 115 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) | 45 | #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) |
| 116 | |||
| 117 | /* CM_IDLEST_MPU */ | ||
| 118 | #define OMAP3430_ST_MPU_MASK (1 << 0) | ||
| 119 | |||
| 120 | /* CM_IDLEST_PLL_MPU */ | ||
| 121 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 | 46 | #define OMAP3430_ST_MPU_CLK_SHIFT 0 |
| 122 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) | 47 | #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) |
| 123 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 | 48 | #define OMAP3430_ST_MPU_CLK_WIDTH 1 |
| 124 | |||
| 125 | /* CM_AUTOIDLE_PLL_MPU */ | ||
| 126 | #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 | ||
| 127 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) | 49 | #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) |
| 128 | |||
| 129 | /* CM_CLKSEL1_PLL_MPU */ | ||
| 130 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 | 50 | #define OMAP3430_MPU_CLK_SRC_SHIFT 19 |
| 131 | #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) | ||
| 132 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 | 51 | #define OMAP3430_MPU_CLK_SRC_WIDTH 3 |
| 133 | #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 | ||
| 134 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) | 52 | #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) |
| 135 | #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 | ||
| 136 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) | 53 | #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) |
| 137 | |||
| 138 | /* CM_CLKSEL2_PLL_MPU */ | ||
| 139 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 | 54 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 |
| 140 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
| 141 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 | 55 | #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 |
| 142 | |||
| 143 | /* CM_CLKSTCTRL_MPU */ | ||
| 144 | #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 | ||
| 145 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) | 56 | #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) |
| 146 | |||
| 147 | /* CM_CLKSTST_MPU */ | ||
| 148 | #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 | ||
| 149 | #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) | ||
| 150 | |||
| 151 | /* CM_FCLKEN1_CORE specific bits */ | ||
| 152 | #define OMAP3430_EN_MODEM_MASK (1 << 31) | ||
| 153 | #define OMAP3430_EN_MODEM_SHIFT 31 | 57 | #define OMAP3430_EN_MODEM_SHIFT 31 |
| 154 | |||
| 155 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 156 | #define OMAP3430_EN_ICR_MASK (1 << 29) | ||
| 157 | #define OMAP3430_EN_ICR_SHIFT 29 | 58 | #define OMAP3430_EN_ICR_SHIFT 29 |
| 158 | #define OMAP3430_EN_AES2_MASK (1 << 28) | ||
| 159 | #define OMAP3430_EN_AES2_SHIFT 28 | 59 | #define OMAP3430_EN_AES2_SHIFT 28 |
| 160 | #define OMAP3430_EN_SHA12_MASK (1 << 27) | ||
| 161 | #define OMAP3430_EN_SHA12_SHIFT 27 | 60 | #define OMAP3430_EN_SHA12_SHIFT 27 |
| 162 | #define OMAP3430_EN_DES2_MASK (1 << 26) | ||
| 163 | #define OMAP3430_EN_DES2_SHIFT 26 | 61 | #define OMAP3430_EN_DES2_SHIFT 26 |
| 164 | #define OMAP3430ES1_EN_FAC_MASK (1 << 8) | ||
| 165 | #define OMAP3430ES1_EN_FAC_SHIFT 8 | 62 | #define OMAP3430ES1_EN_FAC_SHIFT 8 |
| 166 | #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) | ||
| 167 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 | 63 | #define OMAP3430_EN_MAILBOXES_SHIFT 7 |
| 168 | #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) | ||
| 169 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 | 64 | #define OMAP3430_EN_OMAPCTRL_SHIFT 6 |
| 170 | #define OMAP3430_EN_SAD2D_MASK (1 << 3) | ||
| 171 | #define OMAP3430_EN_SAD2D_SHIFT 3 | 65 | #define OMAP3430_EN_SAD2D_SHIFT 3 |
| 172 | #define OMAP3430_EN_SDRC_MASK (1 << 1) | ||
| 173 | #define OMAP3430_EN_SDRC_SHIFT 1 | 66 | #define OMAP3430_EN_SDRC_SHIFT 1 |
| 174 | |||
| 175 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | ||
| 176 | #define AM35XX_EN_IPSS_MASK (1 << 4) | ||
| 177 | #define AM35XX_EN_IPSS_SHIFT 4 | 67 | #define AM35XX_EN_IPSS_SHIFT 4 |
| 178 | |||
| 179 | /* CM_ICLKEN2_CORE */ | ||
| 180 | #define OMAP3430_EN_PKA_MASK (1 << 4) | ||
| 181 | #define OMAP3430_EN_PKA_SHIFT 4 | 68 | #define OMAP3430_EN_PKA_SHIFT 4 |
| 182 | #define OMAP3430_EN_AES1_MASK (1 << 3) | ||
| 183 | #define OMAP3430_EN_AES1_SHIFT 3 | 69 | #define OMAP3430_EN_AES1_SHIFT 3 |
| 184 | #define OMAP3430_EN_RNG_MASK (1 << 2) | ||
| 185 | #define OMAP3430_EN_RNG_SHIFT 2 | 70 | #define OMAP3430_EN_RNG_SHIFT 2 |
| 186 | #define OMAP3430_EN_SHA11_MASK (1 << 1) | ||
| 187 | #define OMAP3430_EN_SHA11_SHIFT 1 | 71 | #define OMAP3430_EN_SHA11_SHIFT 1 |
| 188 | #define OMAP3430_EN_DES1_MASK (1 << 0) | ||
| 189 | #define OMAP3430_EN_DES1_SHIFT 0 | 72 | #define OMAP3430_EN_DES1_SHIFT 0 |
| 190 | |||
| 191 | /* CM_ICLKEN3_CORE */ | ||
| 192 | #define OMAP3430_EN_MAD2D_SHIFT 3 | 73 | #define OMAP3430_EN_MAD2D_SHIFT 3 |
| 193 | #define OMAP3430_EN_MAD2D_MASK (1 << 3) | ||
| 194 | |||
| 195 | /* CM_FCLKEN3_CORE specific bits */ | ||
| 196 | #define OMAP3430ES2_EN_TS_SHIFT 1 | 74 | #define OMAP3430ES2_EN_TS_SHIFT 1 |
| 197 | #define OMAP3430ES2_EN_TS_MASK (1 << 1) | ||
| 198 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 | 75 | #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 |
| 199 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | ||
| 200 | |||
| 201 | /* CM_IDLEST1_CORE specific bits */ | ||
| 202 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 | ||
| 203 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) | ||
| 204 | #define OMAP3430_ST_ICR_SHIFT 29 | ||
| 205 | #define OMAP3430_ST_ICR_MASK (1 << 29) | ||
| 206 | #define OMAP3430_ST_AES2_SHIFT 28 | 76 | #define OMAP3430_ST_AES2_SHIFT 28 |
| 207 | #define OMAP3430_ST_AES2_MASK (1 << 28) | ||
| 208 | #define OMAP3430_ST_SHA12_SHIFT 27 | 77 | #define OMAP3430_ST_SHA12_SHIFT 27 |
| 209 | #define OMAP3430_ST_SHA12_MASK (1 << 27) | ||
| 210 | #define OMAP3430_ST_DES2_SHIFT 26 | ||
| 211 | #define OMAP3430_ST_DES2_MASK (1 << 26) | ||
| 212 | #define OMAP3430_ST_MSPRO_SHIFT 23 | ||
| 213 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | ||
| 214 | #define AM35XX_ST_UART4_SHIFT 23 | 78 | #define AM35XX_ST_UART4_SHIFT 23 |
| 215 | #define AM35XX_ST_UART4_MASK (1 << 23) | ||
| 216 | #define OMAP3430_ST_HDQ_SHIFT 22 | 79 | #define OMAP3430_ST_HDQ_SHIFT 22 |
| 217 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
| 218 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
| 219 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
| 220 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | 80 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 |
| 221 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
| 222 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | 81 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 |
| 223 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
| 224 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
| 225 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
| 226 | #define OMAP3430_ST_SAD2D_SHIFT 3 | 82 | #define OMAP3430_ST_SAD2D_SHIFT 3 |
| 227 | #define OMAP3430_ST_SAD2D_MASK (1 << 3) | ||
| 228 | #define OMAP3430_ST_SDMA_SHIFT 2 | 83 | #define OMAP3430_ST_SDMA_SHIFT 2 |
| 229 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
| 230 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
| 231 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
| 232 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
| 233 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
| 234 | |||
| 235 | /* AM35xx specific CM_IDLEST1_CORE bits */ | ||
| 236 | #define AM35XX_ST_IPSS_SHIFT 5 | 84 | #define AM35XX_ST_IPSS_SHIFT 5 |
| 237 | #define AM35XX_ST_IPSS_MASK (1 << 5) | ||
| 238 | |||
| 239 | /* CM_IDLEST2_CORE */ | ||
| 240 | #define OMAP3430_ST_PKA_SHIFT 4 | ||
| 241 | #define OMAP3430_ST_PKA_MASK (1 << 4) | ||
| 242 | #define OMAP3430_ST_AES1_SHIFT 3 | ||
| 243 | #define OMAP3430_ST_AES1_MASK (1 << 3) | ||
| 244 | #define OMAP3430_ST_RNG_SHIFT 2 | ||
| 245 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
| 246 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
| 247 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
| 248 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
| 249 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
| 250 | |||
| 251 | /* CM_IDLEST3_CORE */ | ||
| 252 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 85 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
| 253 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | ||
| 254 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
| 255 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
| 256 | |||
| 257 | /* CM_AUTOIDLE1_CORE */ | ||
| 258 | #define OMAP3430_AUTO_MODEM_MASK (1 << 31) | ||
| 259 | #define OMAP3430_AUTO_MODEM_SHIFT 31 | ||
| 260 | #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) | ||
| 261 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | ||
| 262 | #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) | ||
| 263 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | ||
| 264 | #define OMAP3430_AUTO_AES2_MASK (1 << 28) | ||
| 265 | #define OMAP3430_AUTO_AES2_SHIFT 28 | ||
| 266 | #define OMAP3430_AUTO_SHA12_MASK (1 << 27) | ||
| 267 | #define OMAP3430_AUTO_SHA12_SHIFT 27 | ||
| 268 | #define OMAP3430_AUTO_DES2_MASK (1 << 26) | ||
| 269 | #define OMAP3430_AUTO_DES2_SHIFT 26 | ||
| 270 | #define OMAP3430_AUTO_MMC2_MASK (1 << 25) | ||
| 271 | #define OMAP3430_AUTO_MMC2_SHIFT 25 | ||
| 272 | #define OMAP3430_AUTO_MMC1_MASK (1 << 24) | ||
| 273 | #define OMAP3430_AUTO_MMC1_SHIFT 24 | ||
| 274 | #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) | ||
| 275 | #define OMAP3430_AUTO_MSPRO_SHIFT 23 | ||
| 276 | #define OMAP3430_AUTO_HDQ_MASK (1 << 22) | ||
| 277 | #define OMAP3430_AUTO_HDQ_SHIFT 22 | ||
| 278 | #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) | ||
| 279 | #define OMAP3430_AUTO_MCSPI4_SHIFT 21 | ||
| 280 | #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) | ||
| 281 | #define OMAP3430_AUTO_MCSPI3_SHIFT 20 | ||
| 282 | #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) | ||
| 283 | #define OMAP3430_AUTO_MCSPI2_SHIFT 19 | ||
| 284 | #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) | ||
| 285 | #define OMAP3430_AUTO_MCSPI1_SHIFT 18 | ||
| 286 | #define OMAP3430_AUTO_I2C3_MASK (1 << 17) | ||
| 287 | #define OMAP3430_AUTO_I2C3_SHIFT 17 | ||
| 288 | #define OMAP3430_AUTO_I2C2_MASK (1 << 16) | ||
| 289 | #define OMAP3430_AUTO_I2C2_SHIFT 16 | ||
| 290 | #define OMAP3430_AUTO_I2C1_MASK (1 << 15) | ||
| 291 | #define OMAP3430_AUTO_I2C1_SHIFT 15 | ||
| 292 | #define OMAP3430_AUTO_UART2_MASK (1 << 14) | ||
| 293 | #define OMAP3430_AUTO_UART2_SHIFT 14 | ||
| 294 | #define OMAP3430_AUTO_UART1_MASK (1 << 13) | ||
| 295 | #define OMAP3430_AUTO_UART1_SHIFT 13 | ||
| 296 | #define OMAP3430_AUTO_GPT11_MASK (1 << 12) | ||
| 297 | #define OMAP3430_AUTO_GPT11_SHIFT 12 | ||
| 298 | #define OMAP3430_AUTO_GPT10_MASK (1 << 11) | ||
| 299 | #define OMAP3430_AUTO_GPT10_SHIFT 11 | ||
| 300 | #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) | ||
| 301 | #define OMAP3430_AUTO_MCBSP5_SHIFT 10 | ||
| 302 | #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) | ||
| 303 | #define OMAP3430_AUTO_MCBSP1_SHIFT 9 | ||
| 304 | #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) | ||
| 305 | #define OMAP3430ES1_AUTO_FAC_SHIFT 8 | ||
| 306 | #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) | ||
| 307 | #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 | ||
| 308 | #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) | ||
| 309 | #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 | ||
| 310 | #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) | ||
| 311 | #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 | ||
| 312 | #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) | ||
| 313 | #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 | ||
| 314 | #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) | ||
| 315 | #define OMAP3430ES1_AUTO_D2D_SHIFT 3 | ||
| 316 | #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) | ||
| 317 | #define OMAP3430_AUTO_SAD2D_SHIFT 3 | ||
| 318 | #define OMAP3430_AUTO_SSI_MASK (1 << 0) | ||
| 319 | #define OMAP3430_AUTO_SSI_SHIFT 0 | ||
| 320 | |||
| 321 | /* CM_AUTOIDLE2_CORE */ | ||
| 322 | #define OMAP3430_AUTO_PKA_MASK (1 << 4) | ||
| 323 | #define OMAP3430_AUTO_PKA_SHIFT 4 | ||
| 324 | #define OMAP3430_AUTO_AES1_MASK (1 << 3) | ||
| 325 | #define OMAP3430_AUTO_AES1_SHIFT 3 | ||
| 326 | #define OMAP3430_AUTO_RNG_MASK (1 << 2) | ||
| 327 | #define OMAP3430_AUTO_RNG_SHIFT 2 | ||
| 328 | #define OMAP3430_AUTO_SHA11_MASK (1 << 1) | ||
| 329 | #define OMAP3430_AUTO_SHA11_SHIFT 1 | ||
| 330 | #define OMAP3430_AUTO_DES1_MASK (1 << 0) | ||
| 331 | #define OMAP3430_AUTO_DES1_SHIFT 0 | ||
| 332 | |||
| 333 | /* CM_AUTOIDLE3_CORE */ | ||
| 334 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) | ||
| 335 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 336 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | ||
| 337 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | ||
| 338 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | ||
| 339 | #define OMAP3430_AUTO_MAD2D_SHIFT 3 | ||
| 340 | #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) | ||
| 341 | |||
| 342 | /* CM_CLKSEL_CORE */ | ||
| 343 | #define OMAP3430_CLKSEL_SSI_SHIFT 8 | ||
| 344 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) | 86 | #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) |
| 345 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) | 87 | #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) |
| 346 | #define OMAP3430_CLKSEL_GPT11_SHIFT 7 | ||
| 347 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) | 88 | #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) |
| 348 | #define OMAP3430_CLKSEL_GPT10_SHIFT 6 | ||
| 349 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 | ||
| 350 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) | 89 | #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) |
| 351 | #define OMAP3430_CLKSEL_L4_SHIFT 2 | 90 | #define OMAP3430_CLKSEL_L4_SHIFT 2 |
| 352 | #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) | ||
| 353 | #define OMAP3430_CLKSEL_L4_WIDTH 2 | 91 | #define OMAP3430_CLKSEL_L4_WIDTH 2 |
| 354 | #define OMAP3430_CLKSEL_L3_SHIFT 0 | 92 | #define OMAP3430_CLKSEL_L3_SHIFT 0 |
| 355 | #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) | ||
| 356 | #define OMAP3430_CLKSEL_L3_WIDTH 2 | 93 | #define OMAP3430_CLKSEL_L3_WIDTH 2 |
| 357 | #define OMAP3630_CLKSEL_96M_SHIFT 12 | ||
| 358 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) | 94 | #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) |
| 359 | #define OMAP3630_CLKSEL_96M_WIDTH 2 | ||
| 360 | |||
| 361 | /* CM_CLKSTCTRL_CORE */ | ||
| 362 | #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 | ||
| 363 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) | 95 | #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) |
| 364 | #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 | ||
| 365 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) | 96 | #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) |
| 366 | #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 | ||
| 367 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) | 97 | #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) |
| 368 | |||
| 369 | /* CM_CLKSTST_CORE */ | ||
| 370 | #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 | ||
| 371 | #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) | ||
| 372 | #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 | ||
| 373 | #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) | ||
| 374 | #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 | ||
| 375 | #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) | ||
| 376 | |||
| 377 | /* CM_FCLKEN_GFX */ | ||
| 378 | #define OMAP3430ES1_EN_3D_MASK (1 << 2) | ||
| 379 | #define OMAP3430ES1_EN_3D_SHIFT 2 | 98 | #define OMAP3430ES1_EN_3D_SHIFT 2 |
| 380 | #define OMAP3430ES1_EN_2D_MASK (1 << 1) | ||
| 381 | #define OMAP3430ES1_EN_2D_SHIFT 1 | 99 | #define OMAP3430ES1_EN_2D_SHIFT 1 |
| 382 | |||
| 383 | /* CM_ICLKEN_GFX specific bits */ | ||
| 384 | |||
| 385 | /* CM_IDLEST_GFX specific bits */ | ||
| 386 | |||
| 387 | /* CM_CLKSEL_GFX specific bits */ | ||
| 388 | |||
| 389 | /* CM_SLEEPDEP_GFX specific bits */ | ||
| 390 | |||
| 391 | /* CM_CLKSTCTRL_GFX */ | ||
| 392 | #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 | ||
| 393 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) | 100 | #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) |
| 394 | |||
| 395 | /* CM_CLKSTST_GFX */ | ||
| 396 | #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 | ||
| 397 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | ||
| 398 | |||
| 399 | /* CM_FCLKEN_SGX */ | ||
| 400 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 | 101 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 401 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) | ||
| 402 | |||
| 403 | /* CM_IDLEST_SGX */ | ||
| 404 | #define OMAP3430ES2_ST_SGX_SHIFT 1 | ||
| 405 | #define OMAP3430ES2_ST_SGX_MASK (1 << 1) | ||
| 406 | |||
| 407 | /* CM_ICLKEN_SGX */ | ||
| 408 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | 102 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 |
| 409 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | ||
| 410 | |||
| 411 | /* CM_CLKSEL_SGX */ | ||
| 412 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | ||
| 413 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) | 103 | #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) |
| 414 | |||
| 415 | /* CM_CLKSTCTRL_SGX */ | ||
| 416 | #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 | ||
| 417 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) | 104 | #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) |
| 418 | |||
| 419 | /* CM_CLKSTST_SGX */ | ||
| 420 | #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 | ||
| 421 | #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) | ||
| 422 | |||
| 423 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 424 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 105 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
| 425 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
| 426 | |||
| 427 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 428 | #define OMAP3430_EN_WDT1_MASK (1 << 4) | ||
| 429 | #define OMAP3430_EN_WDT1_SHIFT 4 | 106 | #define OMAP3430_EN_WDT1_SHIFT 4 |
| 430 | #define OMAP3430_EN_32KSYNC_MASK (1 << 2) | ||
| 431 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 107 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 432 | |||
| 433 | /* CM_IDLEST_WKUP specific bits */ | ||
| 434 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 | ||
| 435 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) | ||
| 436 | #define OMAP3430_ST_WDT2_SHIFT 5 | 108 | #define OMAP3430_ST_WDT2_SHIFT 5 |
| 437 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
| 438 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
| 439 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
| 440 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | 109 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
| 441 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
| 442 | |||
| 443 | /* CM_AUTOIDLE_WKUP */ | ||
| 444 | #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) | ||
| 445 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
| 446 | #define OMAP3430_AUTO_WDT2_MASK (1 << 5) | ||
| 447 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | ||
| 448 | #define OMAP3430_AUTO_WDT1_MASK (1 << 4) | ||
| 449 | #define OMAP3430_AUTO_WDT1_SHIFT 4 | ||
| 450 | #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) | ||
| 451 | #define OMAP3430_AUTO_GPIO1_SHIFT 3 | ||
| 452 | #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) | ||
| 453 | #define OMAP3430_AUTO_32KSYNC_SHIFT 2 | ||
| 454 | #define OMAP3430_AUTO_GPT12_MASK (1 << 1) | ||
| 455 | #define OMAP3430_AUTO_GPT12_SHIFT 1 | ||
| 456 | #define OMAP3430_AUTO_GPT1_MASK (1 << 0) | ||
| 457 | #define OMAP3430_AUTO_GPT1_SHIFT 0 | ||
| 458 | |||
| 459 | /* CM_CLKSEL_WKUP */ | ||
| 460 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) | 110 | #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) |
| 461 | #define OMAP3430_CLKSEL_RM_SHIFT 1 | 111 | #define OMAP3430_CLKSEL_RM_SHIFT 1 |
| 462 | #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) | ||
| 463 | #define OMAP3430_CLKSEL_RM_WIDTH 2 | 112 | #define OMAP3430_CLKSEL_RM_WIDTH 2 |
| 464 | #define OMAP3430_CLKSEL_GPT1_SHIFT 0 | ||
| 465 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) | 113 | #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) |
| 466 | |||
| 467 | /* CM_CLKEN_PLL */ | ||
| 468 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 | 114 | #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 |
| 469 | #define OMAP3430_PWRDN_CAM_SHIFT 30 | 115 | #define OMAP3430_PWRDN_CAM_SHIFT 30 |
| 470 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 | 116 | #define OMAP3430_PWRDN_DSS1_SHIFT 29 |
| 471 | #define OMAP3430_PWRDN_TV_SHIFT 28 | 117 | #define OMAP3430_PWRDN_TV_SHIFT 28 |
| 472 | #define OMAP3430_PWRDN_96M_SHIFT 27 | 118 | #define OMAP3430_PWRDN_96M_SHIFT 27 |
| 473 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 | ||
| 474 | #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) | ||
| 475 | #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 | ||
| 476 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) | 119 | #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) |
| 477 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 | 120 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 |
| 478 | #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) | ||
| 479 | #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 | ||
| 480 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) | 121 | #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) |
| 481 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 | 122 | #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 |
| 482 | #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 | ||
| 483 | #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 484 | #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 | ||
| 485 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) | 123 | #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) |
| 486 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 | 124 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 |
| 487 | #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) | ||
| 488 | #define OMAP3430_EN_CORE_DPLL_SHIFT 0 | ||
| 489 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) | 125 | #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) |
| 490 | |||
| 491 | /* CM_CLKEN2_PLL */ | ||
| 492 | #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 | ||
| 493 | #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) | ||
| 494 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 | ||
| 495 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) | 126 | #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) |
| 496 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 | 127 | #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 |
| 497 | #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 | ||
| 498 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) | 128 | #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) |
| 499 | |||
| 500 | /* CM_IDLEST_CKGEN */ | ||
| 501 | #define OMAP3430_ST_54M_CLK_MASK (1 << 5) | ||
| 502 | #define OMAP3430_ST_12M_CLK_MASK (1 << 4) | ||
| 503 | #define OMAP3430_ST_48M_CLK_MASK (1 << 3) | ||
| 504 | #define OMAP3430_ST_96M_CLK_MASK (1 << 2) | ||
| 505 | #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 | ||
| 506 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) | 129 | #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) |
| 507 | #define OMAP3430_ST_CORE_CLK_SHIFT 0 | ||
| 508 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 130 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
| 509 | |||
| 510 | /* CM_IDLEST2_CKGEN */ | ||
| 511 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
| 512 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
| 513 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | ||
| 514 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | ||
| 515 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | ||
| 516 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) | 131 | #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) |
| 517 | |||
| 518 | /* CM_AUTOIDLE_PLL */ | ||
| 519 | #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 | ||
| 520 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) | 132 | #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) |
| 521 | #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 | ||
| 522 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) | 133 | #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) |
| 523 | |||
| 524 | /* CM_AUTOIDLE2_PLL */ | ||
| 525 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 | ||
| 526 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) | 134 | #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) |
| 527 | |||
| 528 | /* CM_CLKSEL1_PLL */ | ||
| 529 | /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ | ||
| 530 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 | 135 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 |
| 531 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) | ||
| 532 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 | 136 | #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 |
| 533 | #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 | ||
| 534 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 137 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
| 535 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | ||
| 536 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 138 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
| 537 | #define OMAP3430_SOURCE_96M_SHIFT 6 | 139 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 538 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) | ||
| 539 | #define OMAP3430_SOURCE_96M_WIDTH 1 | 140 | #define OMAP3430_SOURCE_96M_WIDTH 1 |
| 540 | #define OMAP3430_SOURCE_54M_SHIFT 5 | 141 | #define OMAP3430_SOURCE_54M_SHIFT 5 |
| 541 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | ||
| 542 | #define OMAP3430_SOURCE_54M_WIDTH 1 | 142 | #define OMAP3430_SOURCE_54M_WIDTH 1 |
| 543 | #define OMAP3430_SOURCE_48M_SHIFT 3 | ||
| 544 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | 143 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) |
| 545 | |||
| 546 | /* CM_CLKSEL2_PLL */ | ||
| 547 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | ||
| 548 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) | 144 | #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) |
| 549 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) | 145 | #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) |
| 550 | #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 | ||
| 551 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) | 146 | #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) |
| 552 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 | ||
| 553 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) | 147 | #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) |
| 554 | #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 | ||
| 555 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) | 148 | #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) |
| 556 | |||
| 557 | /* CM_CLKSEL3_PLL */ | ||
| 558 | #define OMAP3430_DIV_96M_SHIFT 0 | 149 | #define OMAP3430_DIV_96M_SHIFT 0 |
| 559 | #define OMAP3430_DIV_96M_MASK (0x1f << 0) | ||
| 560 | #define OMAP3430_DIV_96M_WIDTH 5 | ||
| 561 | #define OMAP3630_DIV_96M_MASK (0x3f << 0) | ||
| 562 | #define OMAP3630_DIV_96M_WIDTH 6 | 150 | #define OMAP3630_DIV_96M_WIDTH 6 |
| 563 | |||
| 564 | /* CM_CLKSEL4_PLL */ | ||
| 565 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 | ||
| 566 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) | 151 | #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) |
| 567 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 | ||
| 568 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) | 152 | #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) |
| 569 | |||
| 570 | /* CM_CLKSEL5_PLL */ | ||
| 571 | #define OMAP3430ES2_DIV_120M_SHIFT 0 | 153 | #define OMAP3430ES2_DIV_120M_SHIFT 0 |
| 572 | #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) | ||
| 573 | #define OMAP3430ES2_DIV_120M_WIDTH 5 | 154 | #define OMAP3430ES2_DIV_120M_WIDTH 5 |
| 574 | |||
| 575 | /* CM_CLKOUT_CTRL */ | ||
| 576 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 | 155 | #define OMAP3430_CLKOUT2_EN_SHIFT 7 |
| 577 | #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) | ||
| 578 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 | 156 | #define OMAP3430_CLKOUT2_DIV_SHIFT 3 |
| 579 | #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) | ||
| 580 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 | 157 | #define OMAP3430_CLKOUT2_DIV_WIDTH 3 |
| 581 | #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 | ||
| 582 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) | 158 | #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) |
| 583 | |||
| 584 | /* CM_FCLKEN_DSS */ | ||
| 585 | #define OMAP3430_EN_TV_MASK (1 << 2) | ||
| 586 | #define OMAP3430_EN_TV_SHIFT 2 | 159 | #define OMAP3430_EN_TV_SHIFT 2 |
| 587 | #define OMAP3430_EN_DSS2_MASK (1 << 1) | ||
| 588 | #define OMAP3430_EN_DSS2_SHIFT 1 | 160 | #define OMAP3430_EN_DSS2_SHIFT 1 |
| 589 | #define OMAP3430_EN_DSS1_MASK (1 << 0) | ||
| 590 | #define OMAP3430_EN_DSS1_SHIFT 0 | 161 | #define OMAP3430_EN_DSS1_SHIFT 0 |
| 591 | |||
| 592 | /* CM_ICLKEN_DSS */ | ||
| 593 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) | ||
| 594 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 162 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 595 | |||
| 596 | /* CM_IDLEST_DSS */ | ||
| 597 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 | 163 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 598 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
| 599 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | 164 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 |
| 600 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
| 601 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | 165 | #define OMAP3430ES1_ST_DSS_SHIFT 0 |
| 602 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
| 603 | |||
| 604 | /* CM_AUTOIDLE_DSS */ | ||
| 605 | #define OMAP3430_AUTO_DSS_MASK (1 << 0) | ||
| 606 | #define OMAP3430_AUTO_DSS_SHIFT 0 | ||
| 607 | |||
| 608 | /* CM_CLKSEL_DSS */ | ||
| 609 | #define OMAP3430_CLKSEL_TV_SHIFT 8 | 166 | #define OMAP3430_CLKSEL_TV_SHIFT 8 |
| 610 | #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) | ||
| 611 | #define OMAP3430_CLKSEL_TV_WIDTH 5 | ||
| 612 | #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) | ||
| 613 | #define OMAP3630_CLKSEL_TV_WIDTH 6 | 167 | #define OMAP3630_CLKSEL_TV_WIDTH 6 |
| 614 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 | 168 | #define OMAP3430_CLKSEL_DSS1_SHIFT 0 |
| 615 | #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) | ||
| 616 | #define OMAP3430_CLKSEL_DSS1_WIDTH 5 | ||
| 617 | #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) | ||
| 618 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 | 169 | #define OMAP3630_CLKSEL_DSS1_WIDTH 6 |
| 619 | |||
| 620 | /* CM_SLEEPDEP_DSS specific bits */ | ||
| 621 | |||
| 622 | /* CM_CLKSTCTRL_DSS */ | ||
| 623 | #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 | ||
| 624 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) | 170 | #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) |
| 625 | |||
| 626 | /* CM_CLKSTST_DSS */ | ||
| 627 | #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 | ||
| 628 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | ||
| 629 | |||
| 630 | /* CM_FCLKEN_CAM specific bits */ | ||
| 631 | #define OMAP3430_EN_CSI2_MASK (1 << 1) | ||
| 632 | #define OMAP3430_EN_CSI2_SHIFT 1 | 171 | #define OMAP3430_EN_CSI2_SHIFT 1 |
| 633 | |||
| 634 | /* CM_ICLKEN_CAM specific bits */ | ||
| 635 | |||
| 636 | /* CM_IDLEST_CAM */ | ||
| 637 | #define OMAP3430_ST_CAM_MASK (1 << 0) | ||
| 638 | |||
| 639 | /* CM_AUTOIDLE_CAM */ | ||
| 640 | #define OMAP3430_AUTO_CAM_MASK (1 << 0) | ||
| 641 | #define OMAP3430_AUTO_CAM_SHIFT 0 | ||
| 642 | |||
| 643 | /* CM_CLKSEL_CAM */ | ||
| 644 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 | 172 | #define OMAP3430_CLKSEL_CAM_SHIFT 0 |
| 645 | #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) | ||
| 646 | #define OMAP3430_CLKSEL_CAM_WIDTH 5 | ||
| 647 | #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) | ||
| 648 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 | 173 | #define OMAP3630_CLKSEL_CAM_WIDTH 6 |
| 649 | |||
| 650 | /* CM_SLEEPDEP_CAM specific bits */ | ||
| 651 | |||
| 652 | /* CM_CLKSTCTRL_CAM */ | ||
| 653 | #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 | ||
| 654 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) | 174 | #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) |
| 655 | |||
| 656 | /* CM_CLKSTST_CAM */ | ||
| 657 | #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 | ||
| 658 | #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) | ||
| 659 | |||
| 660 | /* CM_FCLKEN_PER specific bits */ | ||
| 661 | |||
| 662 | /* CM_ICLKEN_PER specific bits */ | ||
| 663 | |||
| 664 | /* CM_IDLEST_PER */ | ||
| 665 | #define OMAP3430_ST_WDT3_SHIFT 12 | ||
| 666 | #define OMAP3430_ST_WDT3_MASK (1 << 12) | ||
| 667 | #define OMAP3430_ST_MCBSP4_SHIFT 2 | 175 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
| 668 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) | ||
| 669 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | 176 | #define OMAP3430_ST_MCBSP3_SHIFT 1 |
| 670 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
| 671 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | 177 | #define OMAP3430_ST_MCBSP2_SHIFT 0 |
| 672 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
| 673 | |||
| 674 | /* CM_AUTOIDLE_PER */ | ||
| 675 | #define OMAP3630_AUTO_UART4_MASK (1 << 18) | ||
| 676 | #define OMAP3630_AUTO_UART4_SHIFT 18 | ||
| 677 | #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) | ||
| 678 | #define OMAP3430_AUTO_GPIO6_SHIFT 17 | ||
| 679 | #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) | ||
| 680 | #define OMAP3430_AUTO_GPIO5_SHIFT 16 | ||
| 681 | #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) | ||
| 682 | #define OMAP3430_AUTO_GPIO4_SHIFT 15 | ||
| 683 | #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) | ||
| 684 | #define OMAP3430_AUTO_GPIO3_SHIFT 14 | ||
| 685 | #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) | ||
| 686 | #define OMAP3430_AUTO_GPIO2_SHIFT 13 | ||
| 687 | #define OMAP3430_AUTO_WDT3_MASK (1 << 12) | ||
| 688 | #define OMAP3430_AUTO_WDT3_SHIFT 12 | ||
| 689 | #define OMAP3430_AUTO_UART3_MASK (1 << 11) | ||
| 690 | #define OMAP3430_AUTO_UART3_SHIFT 11 | ||
| 691 | #define OMAP3430_AUTO_GPT9_MASK (1 << 10) | ||
| 692 | #define OMAP3430_AUTO_GPT9_SHIFT 10 | ||
| 693 | #define OMAP3430_AUTO_GPT8_MASK (1 << 9) | ||
| 694 | #define OMAP3430_AUTO_GPT8_SHIFT 9 | ||
| 695 | #define OMAP3430_AUTO_GPT7_MASK (1 << 8) | ||
| 696 | #define OMAP3430_AUTO_GPT7_SHIFT 8 | ||
| 697 | #define OMAP3430_AUTO_GPT6_MASK (1 << 7) | ||
| 698 | #define OMAP3430_AUTO_GPT6_SHIFT 7 | ||
| 699 | #define OMAP3430_AUTO_GPT5_MASK (1 << 6) | ||
| 700 | #define OMAP3430_AUTO_GPT5_SHIFT 6 | ||
| 701 | #define OMAP3430_AUTO_GPT4_MASK (1 << 5) | ||
| 702 | #define OMAP3430_AUTO_GPT4_SHIFT 5 | ||
| 703 | #define OMAP3430_AUTO_GPT3_MASK (1 << 4) | ||
| 704 | #define OMAP3430_AUTO_GPT3_SHIFT 4 | ||
| 705 | #define OMAP3430_AUTO_GPT2_MASK (1 << 3) | ||
| 706 | #define OMAP3430_AUTO_GPT2_SHIFT 3 | ||
| 707 | #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) | ||
| 708 | #define OMAP3430_AUTO_MCBSP4_SHIFT 2 | ||
| 709 | #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) | ||
| 710 | #define OMAP3430_AUTO_MCBSP3_SHIFT 1 | ||
| 711 | #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) | ||
| 712 | #define OMAP3430_AUTO_MCBSP2_SHIFT 0 | ||
| 713 | |||
| 714 | /* CM_CLKSEL_PER */ | ||
| 715 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) | 178 | #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) |
| 716 | #define OMAP3430_CLKSEL_GPT9_SHIFT 7 | ||
| 717 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) | 179 | #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) |
| 718 | #define OMAP3430_CLKSEL_GPT8_SHIFT 6 | ||
| 719 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) | 180 | #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) |
| 720 | #define OMAP3430_CLKSEL_GPT7_SHIFT 5 | ||
| 721 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) | 181 | #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) |
| 722 | #define OMAP3430_CLKSEL_GPT6_SHIFT 4 | ||
| 723 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) | 182 | #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) |
| 724 | #define OMAP3430_CLKSEL_GPT5_SHIFT 3 | ||
| 725 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) | 183 | #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) |
| 726 | #define OMAP3430_CLKSEL_GPT4_SHIFT 2 | ||
| 727 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) | 184 | #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) |
| 728 | #define OMAP3430_CLKSEL_GPT3_SHIFT 1 | ||
| 729 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) | 185 | #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) |
| 730 | #define OMAP3430_CLKSEL_GPT2_SHIFT 0 | ||
| 731 | |||
| 732 | /* CM_SLEEPDEP_PER specific bits */ | ||
| 733 | #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) | ||
| 734 | |||
| 735 | /* CM_CLKSTCTRL_PER */ | ||
| 736 | #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 | ||
| 737 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) | 186 | #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) |
| 738 | |||
| 739 | /* CM_CLKSTST_PER */ | ||
| 740 | #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 | ||
| 741 | #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) | ||
| 742 | |||
| 743 | /* CM_CLKSEL1_EMU */ | ||
| 744 | #define OMAP3430_DIV_DPLL4_SHIFT 24 | 187 | #define OMAP3430_DIV_DPLL4_SHIFT 24 |
| 745 | #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) | ||
| 746 | #define OMAP3430_DIV_DPLL4_WIDTH 5 | ||
| 747 | #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) | ||
| 748 | #define OMAP3630_DIV_DPLL4_WIDTH 6 | 188 | #define OMAP3630_DIV_DPLL4_WIDTH 6 |
| 749 | #define OMAP3430_DIV_DPLL3_SHIFT 16 | 189 | #define OMAP3430_DIV_DPLL3_SHIFT 16 |
| 750 | #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) | ||
| 751 | #define OMAP3430_DIV_DPLL3_WIDTH 5 | 190 | #define OMAP3430_DIV_DPLL3_WIDTH 5 |
| 752 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 | 191 | #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 |
| 753 | #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) | ||
| 754 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 | 192 | #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 |
| 755 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 | 193 | #define OMAP3430_CLKSEL_PCLK_SHIFT 8 |
| 756 | #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) | ||
| 757 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 | 194 | #define OMAP3430_CLKSEL_PCLK_WIDTH 3 |
| 758 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 | 195 | #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 |
| 759 | #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) | ||
| 760 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 | 196 | #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 |
| 761 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 | 197 | #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 |
| 762 | #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) | ||
| 763 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 | 198 | #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 |
| 764 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 | 199 | #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 |
| 765 | #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) | ||
| 766 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 | 200 | #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 |
| 767 | #define OMAP3430_MUX_CTRL_SHIFT 0 | ||
| 768 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) | 201 | #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) |
| 769 | #define OMAP3430_MUX_CTRL_WIDTH 2 | ||
| 770 | |||
| 771 | /* CM_CLKSTCTRL_EMU */ | ||
| 772 | #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 | ||
| 773 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) | 202 | #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) |
| 774 | |||
| 775 | /* CM_CLKSTST_EMU */ | ||
| 776 | #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 | ||
| 777 | #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) | ||
| 778 | |||
| 779 | /* CM_CLKSEL2_EMU specific bits */ | ||
| 780 | #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
| 781 | #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 782 | #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
| 783 | #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 784 | |||
| 785 | /* CM_CLKSEL3_EMU specific bits */ | ||
| 786 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 | ||
| 787 | #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 788 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 | ||
| 789 | #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 790 | |||
| 791 | /* CM_POLCTRL */ | ||
| 792 | #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) | ||
| 793 | |||
| 794 | /* CM_IDLEST_NEON */ | ||
| 795 | #define OMAP3430_ST_NEON_MASK (1 << 0) | ||
| 796 | |||
| 797 | /* CM_CLKSTCTRL_NEON */ | ||
| 798 | #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 | ||
| 799 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) | 203 | #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) |
| 800 | |||
| 801 | /* CM_FCLKEN_USBHOST */ | ||
| 802 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 | 204 | #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 |
| 803 | #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) | ||
| 804 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 | 205 | #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 |
| 805 | #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) | ||
| 806 | |||
| 807 | /* CM_ICLKEN_USBHOST */ | ||
| 808 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 | 206 | #define OMAP3430ES2_EN_USBHOST_SHIFT 0 |
| 809 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | ||
| 810 | |||
| 811 | /* CM_IDLEST_USBHOST */ | ||
| 812 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | 207 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 |
| 813 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
| 814 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | 208 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 |
| 815 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
| 816 | |||
| 817 | /* CM_AUTOIDLE_USBHOST */ | ||
| 818 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 819 | #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) | ||
| 820 | |||
| 821 | /* CM_SLEEPDEP_USBHOST */ | ||
| 822 | #define OMAP3430ES2_EN_MPU_SHIFT 1 | ||
| 823 | #define OMAP3430ES2_EN_MPU_MASK (1 << 1) | ||
| 824 | #define OMAP3430ES2_EN_IVA2_SHIFT 2 | ||
| 825 | #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) | ||
| 826 | |||
| 827 | /* CM_CLKSTCTRL_USBHOST */ | ||
| 828 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 | ||
| 829 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) | 209 | #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) |
| 830 | |||
| 831 | /* CM_CLKSTST_USBHOST */ | ||
| 832 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 | ||
| 833 | #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) | ||
| 834 | |||
| 835 | /* | ||
| 836 | * | ||
| 837 | */ | ||
| 838 | |||
| 839 | /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ | ||
| 840 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 | 210 | #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
| 841 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 | 211 | #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 |
| 842 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 | 212 | #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 |
| 843 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 | 213 | #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 |
| 844 | |||
| 845 | |||
| 846 | #endif | 214 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h index 0221b5c20e87..bbffc03c595f 100644 --- a/arch/arm/mach-omap2/prm-regbits-33xx.h +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h | |||
| @@ -18,340 +18,34 @@ | |||
| 18 | 18 | ||
| 19 | #include "prm.h" | 19 | #include "prm.h" |
| 20 | 20 | ||
| 21 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 22 | #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
| 23 | #define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
| 24 | |||
| 25 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 26 | #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
| 27 | #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
| 28 | |||
| 29 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 30 | #define AM33XX_AIPOFF_SHIFT 8 | ||
| 31 | #define AM33XX_AIPOFF_MASK (1 << 8) | ||
| 32 | |||
| 33 | /* Used by PM_WKUP_PWRSTST */ | ||
| 34 | #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 | ||
| 35 | #define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) | ||
| 36 | |||
| 37 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 38 | #define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 | ||
| 39 | #define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
| 40 | |||
| 41 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 42 | #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 | ||
| 43 | #define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) | ||
| 44 | |||
| 45 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 46 | #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 | ||
| 47 | #define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) | ||
| 48 | |||
| 49 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 50 | #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 | ||
| 51 | #define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) | ||
| 52 | |||
| 53 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 54 | #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 | ||
| 55 | #define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) | ||
| 56 | |||
| 57 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 58 | #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 | ||
| 59 | #define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) | ||
| 60 | |||
| 61 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 62 | #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 | ||
| 63 | #define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) | ||
| 64 | |||
| 65 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 66 | #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 | ||
| 67 | #define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) | ||
| 68 | |||
| 69 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 70 | #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 | ||
| 71 | #define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) | ||
| 72 | |||
| 73 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 74 | #define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 | ||
| 75 | #define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) | ||
| 76 | |||
| 77 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 78 | #define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 | ||
| 79 | #define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) | ||
| 80 | |||
| 81 | /* Used by RM_WKUP_RSTST */ | ||
| 82 | #define AM33XX_EMULATION_M3_RST_SHIFT 6 | ||
| 83 | #define AM33XX_EMULATION_M3_RST_MASK (1 << 6) | ||
| 84 | |||
| 85 | /* Used by RM_MPU_RSTST */ | ||
| 86 | #define AM33XX_EMULATION_MPU_RST_SHIFT 5 | ||
| 87 | #define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) | ||
| 88 | |||
| 89 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 90 | #define AM33XX_ENFUNC1_EXPORT_SHIFT 3 | ||
| 91 | #define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) | ||
| 92 | |||
| 93 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 94 | #define AM33XX_ENFUNC3_EXPORT_SHIFT 5 | ||
| 95 | #define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) | ||
| 96 | |||
| 97 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 98 | #define AM33XX_ENFUNC4_SHIFT 6 | ||
| 99 | #define AM33XX_ENFUNC4_MASK (1 << 6) | ||
| 100 | |||
| 101 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
| 102 | #define AM33XX_ENFUNC5_SHIFT 7 | ||
| 103 | #define AM33XX_ENFUNC5_MASK (1 << 7) | ||
| 104 | |||
| 105 | /* Used by PRM_RSTST */ | ||
| 106 | #define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 | ||
| 107 | #define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
| 108 | |||
| 109 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 110 | #define AM33XX_FORCEWKUP_EN_SHIFT 10 | ||
| 111 | #define AM33XX_FORCEWKUP_EN_MASK (1 << 10) | ||
| 112 | |||
| 113 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 114 | #define AM33XX_FORCEWKUP_ST_SHIFT 10 | ||
| 115 | #define AM33XX_FORCEWKUP_ST_MASK (1 << 10) | ||
| 116 | |||
| 117 | /* Used by PM_GFX_PWRSTCTRL */ | ||
| 118 | #define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 | ||
| 119 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) | 21 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) |
| 120 | |||
| 121 | /* Used by PM_GFX_PWRSTCTRL */ | ||
| 122 | #define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 | ||
| 123 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) | 22 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) |
| 124 | |||
| 125 | /* Used by PM_GFX_PWRSTST */ | ||
| 126 | #define AM33XX_GFX_MEM_STATEST_SHIFT 4 | ||
| 127 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) | 23 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) |
| 128 | |||
| 129 | /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ | ||
| 130 | #define AM33XX_GFX_RST_SHIFT 0 | ||
| 131 | #define AM33XX_GFX_RST_MASK (1 << 0) | ||
| 132 | |||
| 133 | /* Used by PRM_RSTST */ | ||
| 134 | #define AM33XX_GLOBAL_COLD_RST_SHIFT 0 | ||
| 135 | #define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) | ||
| 136 | |||
| 137 | /* Used by PRM_RSTST */ | ||
| 138 | #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 | ||
| 139 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) | 24 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
| 140 | |||
| 141 | /* Used by RM_WKUP_RSTST */ | ||
| 142 | #define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 | ||
| 143 | #define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) | ||
| 144 | |||
| 145 | /* Used by RM_MPU_RSTST */ | ||
| 146 | #define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 | ||
| 147 | #define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) | ||
| 148 | |||
| 149 | /* Used by PRM_RSTST */ | ||
| 150 | #define AM33XX_ICEPICK_RST_SHIFT 9 | ||
| 151 | #define AM33XX_ICEPICK_RST_MASK (1 << 9) | ||
| 152 | |||
| 153 | /* Used by RM_PER_RSTCTRL */ | ||
| 154 | #define AM33XX_PRUSS_LRST_SHIFT 1 | ||
| 155 | #define AM33XX_PRUSS_LRST_MASK (1 << 1) | ||
| 156 | |||
| 157 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 158 | #define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 | ||
| 159 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) | 25 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) |
| 160 | |||
| 161 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 162 | #define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 | ||
| 163 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) | 26 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) |
| 164 | |||
| 165 | /* Used by PM_PER_PWRSTST */ | ||
| 166 | #define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 | ||
| 167 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) | 27 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) |
| 168 | |||
| 169 | /* | ||
| 170 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
| 171 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
| 172 | */ | ||
| 173 | #define AM33XX_INTRANSITION_SHIFT 20 | ||
| 174 | #define AM33XX_INTRANSITION_MASK (1 << 20) | ||
| 175 | |||
| 176 | /* Used by PM_CEFUSE_PWRSTST */ | ||
| 177 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 | 28 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 |
| 178 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | 29 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
| 179 | |||
| 180 | /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ | ||
| 181 | #define AM33XX_LOGICRETSTATE_SHIFT 2 | ||
| 182 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) | 30 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) |
| 183 | |||
| 184 | /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ | ||
| 185 | #define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 | ||
| 186 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) | 31 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) |
| 187 | |||
| 188 | /* | ||
| 189 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
| 190 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
| 191 | */ | ||
| 192 | #define AM33XX_LOGICSTATEST_SHIFT 2 | 32 | #define AM33XX_LOGICSTATEST_SHIFT 2 |
| 193 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) | 33 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) |
| 194 | |||
| 195 | /* | ||
| 196 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
| 197 | * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL | ||
| 198 | */ | ||
| 199 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 | 34 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 |
| 200 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | 35 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 201 | |||
| 202 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 203 | #define AM33XX_MPU_L1_ONSTATE_SHIFT 18 | ||
| 204 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) | 36 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) |
| 205 | |||
| 206 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 207 | #define AM33XX_MPU_L1_RETSTATE_SHIFT 22 | ||
| 208 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) | 37 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) |
| 209 | |||
| 210 | /* Used by PM_MPU_PWRSTST */ | ||
| 211 | #define AM33XX_MPU_L1_STATEST_SHIFT 6 | ||
| 212 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) | 38 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) |
| 213 | |||
| 214 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 215 | #define AM33XX_MPU_L2_ONSTATE_SHIFT 20 | ||
| 216 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) | 39 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) |
| 217 | |||
| 218 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 219 | #define AM33XX_MPU_L2_RETSTATE_SHIFT 23 | ||
| 220 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) | 40 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) |
| 221 | |||
| 222 | /* Used by PM_MPU_PWRSTST */ | ||
| 223 | #define AM33XX_MPU_L2_STATEST_SHIFT 8 | ||
| 224 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) | 41 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) |
| 225 | |||
| 226 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 227 | #define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 | ||
| 228 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) | 42 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) |
| 229 | |||
| 230 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 231 | #define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 | ||
| 232 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) | 43 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) |
| 233 | |||
| 234 | /* Used by PM_MPU_PWRSTST */ | ||
| 235 | #define AM33XX_MPU_RAM_STATEST_SHIFT 4 | ||
| 236 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) | 44 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) |
| 237 | |||
| 238 | /* Used by PRM_RSTST */ | ||
| 239 | #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 | ||
| 240 | #define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
| 241 | |||
| 242 | /* Used by PRM_SRAM_COUNT */ | ||
| 243 | #define AM33XX_PCHARGECNT_VALUE_SHIFT 0 | ||
| 244 | #define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
| 245 | |||
| 246 | /* Used by RM_PER_RSTCTRL */ | ||
| 247 | #define AM33XX_PCI_LRST_SHIFT 0 | ||
| 248 | #define AM33XX_PCI_LRST_MASK (1 << 0) | ||
| 249 | |||
| 250 | /* Renamed from PCI_LRST Used by RM_PER_RSTST */ | ||
| 251 | #define AM33XX_PCI_LRST_5_5_SHIFT 5 | ||
| 252 | #define AM33XX_PCI_LRST_5_5_MASK (1 << 5) | ||
| 253 | |||
| 254 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 255 | #define AM33XX_PER_MEM_ONSTATE_SHIFT 25 | ||
| 256 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) | 45 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) |
| 257 | |||
| 258 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 259 | #define AM33XX_PER_MEM_RETSTATE_SHIFT 29 | ||
| 260 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) | 46 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) |
| 261 | |||
| 262 | /* Used by PM_PER_PWRSTST */ | ||
| 263 | #define AM33XX_PER_MEM_STATEST_SHIFT 17 | ||
| 264 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) | 47 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) |
| 265 | |||
| 266 | /* | ||
| 267 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
| 268 | * PM_MPU_PWRSTCTRL | ||
| 269 | */ | ||
| 270 | #define AM33XX_POWERSTATE_SHIFT 0 | ||
| 271 | #define AM33XX_POWERSTATE_MASK (0x3 << 0) | ||
| 272 | |||
| 273 | /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ | ||
| 274 | #define AM33XX_POWERSTATEST_SHIFT 0 | ||
| 275 | #define AM33XX_POWERSTATEST_MASK (0x3 << 0) | ||
| 276 | |||
| 277 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 278 | #define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 | ||
| 279 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) | 48 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) |
| 280 | |||
| 281 | /* Used by PM_PER_PWRSTCTRL */ | ||
| 282 | #define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 | ||
| 283 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) | 49 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) |
| 284 | |||
| 285 | /* Used by PM_PER_PWRSTST */ | ||
| 286 | #define AM33XX_RAM_MEM_STATEST_SHIFT 21 | ||
| 287 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) | 50 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) |
| 288 | |||
| 289 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 290 | #define AM33XX_RETMODE_ENABLE_SHIFT 0 | ||
| 291 | #define AM33XX_RETMODE_ENABLE_MASK (1 << 0) | ||
| 292 | |||
| 293 | /* Used by REVISION_PRM */ | ||
| 294 | #define AM33XX_REV_SHIFT 0 | ||
| 295 | #define AM33XX_REV_MASK (0xff << 0) | ||
| 296 | |||
| 297 | /* Used by PRM_RSTTIME */ | ||
| 298 | #define AM33XX_RSTTIME1_SHIFT 0 | ||
| 299 | #define AM33XX_RSTTIME1_MASK (0xff << 0) | ||
| 300 | |||
| 301 | /* Used by PRM_RSTTIME */ | ||
| 302 | #define AM33XX_RSTTIME2_SHIFT 8 | ||
| 303 | #define AM33XX_RSTTIME2_MASK (0x1f << 8) | ||
| 304 | |||
| 305 | /* Used by PRM_RSTCTRL */ | ||
| 306 | #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
| 307 | #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
| 308 | |||
| 309 | /* Used by PRM_RSTCTRL */ | ||
| 310 | #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
| 311 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | ||
| 312 | |||
| 313 | /* Used by PRM_SRAM_COUNT */ | ||
| 314 | #define AM33XX_SLPCNT_VALUE_SHIFT 16 | ||
| 315 | #define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) | ||
| 316 | |||
| 317 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 318 | #define AM33XX_SRAMLDO_STATUS_SHIFT 8 | ||
| 319 | #define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) | ||
| 320 | |||
| 321 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
| 322 | #define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 | ||
| 323 | #define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
| 324 | |||
| 325 | /* Used by PRM_SRAM_COUNT */ | ||
| 326 | #define AM33XX_STARTUP_COUNT_SHIFT 24 | ||
| 327 | #define AM33XX_STARTUP_COUNT_MASK (0xff << 24) | ||
| 328 | |||
| 329 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
| 330 | #define AM33XX_TRANSITION_EN_SHIFT 8 | ||
| 331 | #define AM33XX_TRANSITION_EN_MASK (1 << 8) | ||
| 332 | |||
| 333 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
| 334 | #define AM33XX_TRANSITION_ST_SHIFT 8 | ||
| 335 | #define AM33XX_TRANSITION_ST_MASK (1 << 8) | ||
| 336 | |||
| 337 | /* Used by PRM_SRAM_COUNT */ | ||
| 338 | #define AM33XX_VSETUPCNT_VALUE_SHIFT 8 | ||
| 339 | #define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
| 340 | |||
| 341 | /* Used by PRM_RSTST */ | ||
| 342 | #define AM33XX_WDT0_RST_SHIFT 3 | ||
| 343 | #define AM33XX_WDT0_RST_MASK (1 << 3) | ||
| 344 | |||
| 345 | /* Used by PRM_RSTST */ | ||
| 346 | #define AM33XX_WDT1_RST_SHIFT 4 | ||
| 347 | #define AM33XX_WDT1_RST_MASK (1 << 4) | ||
| 348 | |||
| 349 | /* Used by RM_WKUP_RSTCTRL */ | ||
| 350 | #define AM33XX_WKUP_M3_LRST_SHIFT 3 | ||
| 351 | #define AM33XX_WKUP_M3_LRST_MASK (1 << 3) | ||
| 352 | |||
| 353 | /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ | ||
| 354 | #define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 | ||
| 355 | #define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) | ||
| 356 | |||
| 357 | #endif | 51 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index b0a2142eeb91..cebad565ed37 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -16,115 +16,25 @@ | |||
| 16 | 16 | ||
| 17 | #include "prm3xxx.h" | 17 | #include "prm3xxx.h" |
| 18 | 18 | ||
| 19 | /* Shared register bits */ | ||
| 20 | |||
| 21 | /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ | ||
| 22 | #define OMAP3430_ON_SHIFT 24 | ||
| 23 | #define OMAP3430_ON_MASK (0xff << 24) | ||
| 24 | #define OMAP3430_ONLP_SHIFT 16 | ||
| 25 | #define OMAP3430_ONLP_MASK (0xff << 16) | ||
| 26 | #define OMAP3430_RET_SHIFT 8 | ||
| 27 | #define OMAP3430_RET_MASK (0xff << 8) | ||
| 28 | #define OMAP3430_OFF_SHIFT 0 | ||
| 29 | #define OMAP3430_OFF_MASK (0xff << 0) | ||
| 30 | |||
| 31 | /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ | ||
| 32 | #define OMAP3430_ERROROFFSET_SHIFT 24 | ||
| 33 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) | 19 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) |
| 34 | #define OMAP3430_ERRORGAIN_SHIFT 16 | ||
| 35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | 20 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) |
| 36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | ||
| 37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | 21 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) |
| 38 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) | 22 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) |
| 39 | #define OMAP3430_INITVDD_MASK (1 << 2) | 23 | #define OMAP3430_INITVDD_MASK (1 << 2) |
| 40 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) | 24 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) |
| 41 | #define OMAP3430_VPENABLE_MASK (1 << 0) | 25 | #define OMAP3430_VPENABLE_MASK (1 << 0) |
| 42 | |||
| 43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | ||
| 44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | 26 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 |
| 45 | #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
| 46 | #define OMAP3430_VSTEPMIN_SHIFT 0 | 27 | #define OMAP3430_VSTEPMIN_SHIFT 0 |
| 47 | #define OMAP3430_VSTEPMIN_MASK (0xff << 0) | ||
| 48 | |||
| 49 | /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ | ||
| 50 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 | 28 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 |
| 51 | #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
| 52 | #define OMAP3430_VSTEPMAX_SHIFT 0 | 29 | #define OMAP3430_VSTEPMAX_SHIFT 0 |
| 53 | #define OMAP3430_VSTEPMAX_MASK (0xff << 0) | ||
| 54 | |||
| 55 | /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ | ||
| 56 | #define OMAP3430_VDDMAX_SHIFT 24 | 30 | #define OMAP3430_VDDMAX_SHIFT 24 |
| 57 | #define OMAP3430_VDDMAX_MASK (0xff << 24) | ||
| 58 | #define OMAP3430_VDDMIN_SHIFT 16 | 31 | #define OMAP3430_VDDMIN_SHIFT 16 |
| 59 | #define OMAP3430_VDDMIN_MASK (0xff << 16) | ||
| 60 | #define OMAP3430_TIMEOUT_SHIFT 0 | 32 | #define OMAP3430_TIMEOUT_SHIFT 0 |
| 61 | #define OMAP3430_TIMEOUT_MASK (0xffff << 0) | ||
| 62 | |||
| 63 | /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ | ||
| 64 | #define OMAP3430_VPVOLTAGE_SHIFT 0 | ||
| 65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | 33 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) |
| 66 | |||
| 67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | ||
| 68 | #define OMAP3430_VPINIDLE_MASK (1 << 0) | ||
| 69 | |||
| 70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | ||
| 71 | #define OMAP3430_EN_PER_SHIFT 7 | 34 | #define OMAP3430_EN_PER_SHIFT 7 |
| 72 | #define OMAP3430_EN_PER_MASK (1 << 7) | ||
| 73 | |||
| 74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | ||
| 75 | #define OMAP3430_MEMORYCHANGE_MASK (1 << 3) | ||
| 76 | |||
| 77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | ||
| 78 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) | 35 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) |
| 79 | |||
| 80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | ||
| 81 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) | 36 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) |
| 82 | |||
| 83 | /* | ||
| 84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | ||
| 85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | ||
| 86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | ||
| 87 | */ | ||
| 88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 | ||
| 89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | 37 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) |
| 90 | |||
| 91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | ||
| 92 | #define OMAP3430_WKUP_ST_MASK (1 << 0) | ||
| 93 | |||
| 94 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | ||
| 95 | #define OMAP3430_WKUP_EN_MASK (1 << 0) | ||
| 96 | |||
| 97 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | ||
| 98 | #define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) | ||
| 99 | #define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) | ||
| 100 | #define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) | ||
| 101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) | ||
| 102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) | ||
| 103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) | ||
| 104 | #define OMAP3430_GRPSEL_I2C3_SHIFT 17 | ||
| 105 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) | ||
| 106 | #define OMAP3430_GRPSEL_I2C2_SHIFT 16 | ||
| 107 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) | ||
| 108 | #define OMAP3430_GRPSEL_I2C1_SHIFT 15 | ||
| 109 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) | ||
| 110 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) | ||
| 111 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) | ||
| 112 | #define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) | ||
| 113 | #define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) | ||
| 114 | #define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) | ||
| 115 | #define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) | ||
| 116 | #define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) | ||
| 117 | #define OMAP3430_GRPSEL_D2D_MASK (1 << 3) | ||
| 118 | |||
| 119 | /* | ||
| 120 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | ||
| 121 | * PM_PWSTCTRL_PER shared bits | ||
| 122 | */ | ||
| 123 | #define OMAP3430_MEMONSTATE_SHIFT 16 | ||
| 124 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | ||
| 125 | #define OMAP3430_MEMRETSTATE_MASK (1 << 8) | ||
| 126 | |||
| 127 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | ||
| 128 | #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) | 38 | #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) |
| 129 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) | 39 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) |
| 130 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) | 40 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) |
| @@ -132,480 +42,89 @@ | |||
| 132 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) | 42 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) |
| 133 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) | 43 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) |
| 134 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) | 44 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) |
| 135 | #define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) | ||
| 136 | #define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) | ||
| 137 | #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) | ||
| 138 | #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) | ||
| 139 | #define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) | ||
| 140 | #define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) | ||
| 141 | #define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) | ||
| 142 | #define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) | ||
| 143 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) | 45 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) |
| 144 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) | 46 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) |
| 145 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) | 47 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) |
| 146 | |||
| 147 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | ||
| 148 | #define OMAP3430_GRPSEL_IO_MASK (1 << 8) | ||
| 149 | #define OMAP3430_GRPSEL_SR2_MASK (1 << 7) | ||
| 150 | #define OMAP3430_GRPSEL_SR1_MASK (1 << 6) | ||
| 151 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) | 48 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) |
| 152 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) | 49 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) |
| 153 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) | 50 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) |
| 154 | |||
| 155 | /* Bits specific to each register */ | ||
| 156 | |||
| 157 | /* RM_RSTCTRL_IVA2 */ | ||
| 158 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) | 51 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) |
| 159 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) | 52 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) |
| 160 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) | 53 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) |
| 161 | |||
| 162 | /* RM_RSTST_IVA2 specific bits */ | ||
| 163 | #define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) | ||
| 164 | #define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) | ||
| 165 | #define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) | ||
| 166 | #define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) | ||
| 167 | #define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) | ||
| 168 | #define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) | ||
| 169 | |||
| 170 | /* PM_WKDEP_IVA2 specific bits */ | ||
| 171 | |||
| 172 | /* PM_PWSTCTRL_IVA2 specific bits */ | ||
| 173 | #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 | ||
| 174 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) | 54 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) |
| 175 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 | ||
| 176 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) | 55 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) |
| 177 | #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 | ||
| 178 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | 56 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) |
| 179 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | ||
| 180 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | 57 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) |
| 181 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) | 58 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) |
| 182 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) | 59 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) |
| 183 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) | 60 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) |
| 184 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) | 61 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) |
| 185 | |||
| 186 | /* PM_PWSTST_IVA2 specific bits */ | ||
| 187 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | ||
| 188 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) | 62 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) |
| 189 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 | ||
| 190 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) | 63 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) |
| 191 | #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 | ||
| 192 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) | 64 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) |
| 193 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 | ||
| 194 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) | 65 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) |
| 195 | |||
| 196 | /* PM_PREPWSTST_IVA2 specific bits */ | ||
| 197 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 | ||
| 198 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) | 66 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) |
| 199 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 | ||
| 200 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) | 67 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) |
| 201 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 | ||
| 202 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) | ||
| 203 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 | ||
| 204 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | ||
| 205 | |||
| 206 | /* PRM_IRQSTATUS_IVA2 specific bits */ | ||
| 207 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) | ||
| 208 | #define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) | ||
| 209 | |||
| 210 | /* PRM_IRQENABLE_IVA2 specific bits */ | ||
| 211 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) | ||
| 212 | #define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) | ||
| 213 | |||
| 214 | /* PRM_REVISION specific bits */ | ||
| 215 | |||
| 216 | /* PRM_SYSCONFIG specific bits */ | ||
| 217 | |||
| 218 | /* PRM_IRQSTATUS_MPU specific bits */ | ||
| 219 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | 68 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 |
| 220 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) | ||
| 221 | #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) | ||
| 222 | #define OMAP3430_VC_RAERR_ST_MASK (1 << 23) | ||
| 223 | #define OMAP3430_VC_SAERR_ST_MASK (1 << 22) | ||
| 224 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) | 69 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) |
| 225 | #define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) | ||
| 226 | #define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) | ||
| 227 | #define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) | ||
| 228 | #define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) | ||
| 229 | #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) | ||
| 230 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) | 70 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) |
| 231 | #define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) | ||
| 232 | #define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) | ||
| 233 | #define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) | ||
| 234 | #define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) | ||
| 235 | #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) | ||
| 236 | #define OMAP3430_IO_ST_MASK (1 << 9) | ||
| 237 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) | ||
| 238 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 | 71 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 |
| 239 | #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) | ||
| 240 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 | 72 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 |
| 241 | #define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) | ||
| 242 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 | 73 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 |
| 243 | #define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) | ||
| 244 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 | 74 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 |
| 245 | #define OMAP3430_TRANSITION_ST_MASK (1 << 4) | ||
| 246 | #define OMAP3430_EVGENOFF_ST_MASK (1 << 3) | ||
| 247 | #define OMAP3430_EVGENON_ST_MASK (1 << 2) | ||
| 248 | #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) | ||
| 249 | |||
| 250 | /* PRM_IRQENABLE_MPU specific bits */ | ||
| 251 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | 75 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 |
| 252 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) | ||
| 253 | #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) | ||
| 254 | #define OMAP3430_VC_RAERR_EN_MASK (1 << 23) | ||
| 255 | #define OMAP3430_VC_SAERR_EN_MASK (1 << 22) | ||
| 256 | #define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) | ||
| 257 | #define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) | ||
| 258 | #define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) | ||
| 259 | #define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) | ||
| 260 | #define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) | ||
| 261 | #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) | ||
| 262 | #define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) | ||
| 263 | #define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) | ||
| 264 | #define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) | ||
| 265 | #define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) | ||
| 266 | #define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) | ||
| 267 | #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) | ||
| 268 | #define OMAP3430_IO_EN_MASK (1 << 9) | ||
| 269 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) | ||
| 270 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 | 76 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 |
| 271 | #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) | ||
| 272 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 | 77 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 |
| 273 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) | ||
| 274 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 | 78 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 |
| 275 | #define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) | ||
| 276 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 | 79 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 |
| 277 | #define OMAP3430_TRANSITION_EN_MASK (1 << 4) | ||
| 278 | #define OMAP3430_EVGENOFF_EN_MASK (1 << 3) | ||
| 279 | #define OMAP3430_EVGENON_EN_MASK (1 << 2) | ||
| 280 | #define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) | ||
| 281 | |||
| 282 | /* RM_RSTST_MPU specific bits */ | ||
| 283 | #define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) | ||
| 284 | |||
| 285 | /* PM_WKDEP_MPU specific bits */ | ||
| 286 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 | 80 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 |
| 287 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) | ||
| 288 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 | 81 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 |
| 289 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) | ||
| 290 | |||
| 291 | /* PM_EVGENCTRL_MPU */ | ||
| 292 | #define OMAP3430_OFFLOADMODE_SHIFT 3 | ||
| 293 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | ||
| 294 | #define OMAP3430_ONLOADMODE_SHIFT 1 | ||
| 295 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | ||
| 296 | #define OMAP3430_ENABLE_MASK (1 << 0) | ||
| 297 | |||
| 298 | /* PM_EVGENONTIM_MPU */ | ||
| 299 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | ||
| 300 | #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) | ||
| 301 | |||
| 302 | /* PM_EVGENOFFTIM_MPU */ | ||
| 303 | #define OMAP3430_OFFTIMEVAL_SHIFT 0 | ||
| 304 | #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) | ||
| 305 | |||
| 306 | /* PM_PWSTCTRL_MPU specific bits */ | ||
| 307 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | ||
| 308 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | ||
| 309 | #define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) | ||
| 310 | #define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) | ||
| 311 | |||
| 312 | /* PM_PWSTST_MPU specific bits */ | ||
| 313 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | ||
| 314 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | ||
| 315 | #define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) | ||
| 316 | |||
| 317 | /* PM_PREPWSTST_MPU specific bits */ | ||
| 318 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | ||
| 319 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | ||
| 320 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) | ||
| 321 | |||
| 322 | /* RM_RSTCTRL_CORE */ | ||
| 323 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) | 82 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) |
| 324 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) | 83 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) |
| 325 | |||
| 326 | /* RM_RSTST_CORE specific bits */ | ||
| 327 | #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) | ||
| 328 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) | ||
| 329 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) | ||
| 330 | |||
| 331 | /* PM_WKEN1_CORE specific bits */ | ||
| 332 | |||
| 333 | /* PM_MPUGRPSEL1_CORE specific bits */ | ||
| 334 | #define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) | ||
| 335 | |||
| 336 | /* PM_IVA2GRPSEL1_CORE specific bits */ | ||
| 337 | |||
| 338 | /* PM_WKST1_CORE specific bits */ | ||
| 339 | |||
| 340 | /* PM_PWSTCTRL_CORE specific bits */ | ||
| 341 | #define OMAP3430_MEM2ONSTATE_SHIFT 18 | ||
| 342 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | ||
| 343 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | ||
| 344 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | ||
| 345 | #define OMAP3430_MEM2RETSTATE_MASK (1 << 9) | ||
| 346 | #define OMAP3430_MEM1RETSTATE_MASK (1 << 8) | ||
| 347 | |||
| 348 | /* PM_PWSTST_CORE specific bits */ | ||
| 349 | #define OMAP3430_MEM2STATEST_SHIFT 6 | ||
| 350 | #define OMAP3430_MEM2STATEST_MASK (0x3 << 6) | ||
| 351 | #define OMAP3430_MEM1STATEST_SHIFT 4 | ||
| 352 | #define OMAP3430_MEM1STATEST_MASK (0x3 << 4) | ||
| 353 | |||
| 354 | /* PM_PREPWSTST_CORE specific bits */ | ||
| 355 | #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 | ||
| 356 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) | 84 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) |
| 357 | #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 | ||
| 358 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) | 85 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) |
| 359 | |||
| 360 | /* RM_RSTST_GFX specific bits */ | ||
| 361 | |||
| 362 | /* PM_WKDEP_GFX specific bits */ | ||
| 363 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) | ||
| 364 | |||
| 365 | /* PM_PWSTCTRL_GFX specific bits */ | ||
| 366 | |||
| 367 | /* PM_PWSTST_GFX specific bits */ | ||
| 368 | |||
| 369 | /* PM_PREPWSTST_GFX specific bits */ | ||
| 370 | |||
| 371 | /* PM_WKEN_WKUP specific bits */ | ||
| 372 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) | 86 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) |
| 373 | #define OMAP3430_EN_IO_MASK (1 << 8) | 87 | #define OMAP3430_EN_IO_MASK (1 << 8) |
| 374 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) | 88 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
| 375 | |||
| 376 | /* PM_MPUGRPSEL_WKUP specific bits */ | ||
| 377 | |||
| 378 | /* PM_IVA2GRPSEL_WKUP specific bits */ | ||
| 379 | |||
| 380 | /* PM_WKST_WKUP specific bits */ | ||
| 381 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) | 89 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) |
| 382 | #define OMAP3430_ST_IO_MASK (1 << 8) | 90 | #define OMAP3430_ST_IO_MASK (1 << 8) |
| 383 | |||
| 384 | /* PRM_CLKSEL */ | ||
| 385 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | 91 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 |
| 386 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | ||
| 387 | #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 | 92 | #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 |
| 388 | |||
| 389 | /* PRM_CLKOUT_CTRL */ | ||
| 390 | #define OMAP3430_CLKOUT_EN_MASK (1 << 7) | ||
| 391 | #define OMAP3430_CLKOUT_EN_SHIFT 7 | 93 | #define OMAP3430_CLKOUT_EN_SHIFT 7 |
| 392 | |||
| 393 | /* RM_RSTST_DSS specific bits */ | ||
| 394 | |||
| 395 | /* PM_WKEN_DSS */ | ||
| 396 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) | 94 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) |
| 397 | |||
| 398 | /* PM_WKDEP_DSS specific bits */ | ||
| 399 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) | ||
| 400 | |||
| 401 | /* PM_PWSTCTRL_DSS specific bits */ | ||
| 402 | |||
| 403 | /* PM_PWSTST_DSS specific bits */ | ||
| 404 | |||
| 405 | /* PM_PREPWSTST_DSS specific bits */ | ||
| 406 | |||
| 407 | /* RM_RSTST_CAM specific bits */ | ||
| 408 | |||
| 409 | /* PM_WKDEP_CAM specific bits */ | ||
| 410 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) | ||
| 411 | |||
| 412 | /* PM_PWSTCTRL_CAM specific bits */ | ||
| 413 | |||
| 414 | /* PM_PWSTST_CAM specific bits */ | ||
| 415 | |||
| 416 | /* PM_PREPWSTST_CAM specific bits */ | ||
| 417 | |||
| 418 | /* PM_PWSTCTRL_USBHOST specific bits */ | ||
| 419 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 | 95 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 |
| 420 | |||
| 421 | /* RM_RSTST_PER specific bits */ | ||
| 422 | |||
| 423 | /* PM_WKEN_PER specific bits */ | ||
| 424 | |||
| 425 | /* PM_MPUGRPSEL_PER specific bits */ | ||
| 426 | |||
| 427 | /* PM_IVA2GRPSEL_PER specific bits */ | ||
| 428 | |||
| 429 | /* PM_WKST_PER specific bits */ | ||
| 430 | |||
| 431 | /* PM_WKDEP_PER specific bits */ | ||
| 432 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) | ||
| 433 | |||
| 434 | /* PM_PWSTCTRL_PER specific bits */ | ||
| 435 | |||
| 436 | /* PM_PWSTST_PER specific bits */ | ||
| 437 | |||
| 438 | /* PM_PREPWSTST_PER specific bits */ | ||
| 439 | |||
| 440 | /* RM_RSTST_EMU specific bits */ | ||
| 441 | |||
| 442 | /* PM_PWSTST_EMU specific bits */ | ||
| 443 | |||
| 444 | /* PRM_VC_SMPS_SA */ | ||
| 445 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 | 96 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 |
| 446 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) | 97 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) |
| 447 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 | 98 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 |
| 448 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) | 99 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) |
| 449 | |||
| 450 | /* PRM_VC_SMPS_VOL_RA */ | ||
| 451 | #define OMAP3430_VOLRA1_SHIFT 16 | ||
| 452 | #define OMAP3430_VOLRA1_MASK (0xff << 16) | 100 | #define OMAP3430_VOLRA1_MASK (0xff << 16) |
| 453 | #define OMAP3430_VOLRA0_SHIFT 0 | ||
| 454 | #define OMAP3430_VOLRA0_MASK (0xff << 0) | 101 | #define OMAP3430_VOLRA0_MASK (0xff << 0) |
| 455 | |||
| 456 | /* PRM_VC_SMPS_CMD_RA */ | ||
| 457 | #define OMAP3430_CMDRA1_SHIFT 16 | ||
| 458 | #define OMAP3430_CMDRA1_MASK (0xff << 16) | 102 | #define OMAP3430_CMDRA1_MASK (0xff << 16) |
| 459 | #define OMAP3430_CMDRA0_SHIFT 0 | ||
| 460 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | 103 | #define OMAP3430_CMDRA0_MASK (0xff << 0) |
| 461 | |||
| 462 | /* PRM_VC_CMD_VAL_0 specific bits */ | ||
| 463 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | 104 | #define OMAP3430_VC_CMD_ON_SHIFT 24 |
| 464 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | 105 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) |
| 465 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | 106 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 |
| 466 | #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) | ||
| 467 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | 107 | #define OMAP3430_VC_CMD_RET_SHIFT 8 |
| 468 | #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) | ||
| 469 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | 108 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 |
| 470 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | ||
| 471 | |||
| 472 | /* PRM_VC_CMD_VAL_1 specific bits */ | ||
| 473 | |||
| 474 | /* PRM_VC_CH_CONF */ | ||
| 475 | #define OMAP3430_CMD1_MASK (1 << 20) | ||
| 476 | #define OMAP3430_RACEN1_MASK (1 << 19) | ||
| 477 | #define OMAP3430_RAC1_MASK (1 << 18) | ||
| 478 | #define OMAP3430_RAV1_MASK (1 << 17) | ||
| 479 | #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) | ||
| 480 | #define OMAP3430_CMD0_MASK (1 << 4) | ||
| 481 | #define OMAP3430_RACEN0_MASK (1 << 3) | ||
| 482 | #define OMAP3430_RAC0_MASK (1 << 2) | ||
| 483 | #define OMAP3430_RAV0_MASK (1 << 1) | ||
| 484 | #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) | ||
| 485 | |||
| 486 | /* PRM_VC_I2C_CFG */ | ||
| 487 | #define OMAP3430_HSMASTER_MASK (1 << 5) | ||
| 488 | #define OMAP3430_SREN_MASK (1 << 4) | ||
| 489 | #define OMAP3430_HSEN_MASK (1 << 3) | 109 | #define OMAP3430_HSEN_MASK (1 << 3) |
| 490 | #define OMAP3430_MCODE_SHIFT 0 | ||
| 491 | #define OMAP3430_MCODE_MASK (0x7 << 0) | 110 | #define OMAP3430_MCODE_MASK (0x7 << 0) |
| 492 | |||
| 493 | /* PRM_VC_BYPASS_VAL */ | ||
| 494 | #define OMAP3430_VALID_MASK (1 << 24) | 111 | #define OMAP3430_VALID_MASK (1 << 24) |
| 495 | #define OMAP3430_DATA_SHIFT 16 | 112 | #define OMAP3430_DATA_SHIFT 16 |
| 496 | #define OMAP3430_DATA_MASK (0xff << 16) | ||
| 497 | #define OMAP3430_REGADDR_SHIFT 8 | 113 | #define OMAP3430_REGADDR_SHIFT 8 |
| 498 | #define OMAP3430_REGADDR_MASK (0xff << 8) | ||
| 499 | #define OMAP3430_SLAVEADDR_SHIFT 0 | 114 | #define OMAP3430_SLAVEADDR_SHIFT 0 |
| 500 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | ||
| 501 | |||
| 502 | /* PRM_RSTCTRL */ | ||
| 503 | #define OMAP3430_RST_DPLL3_MASK (1 << 2) | ||
| 504 | #define OMAP3430_RST_GS_MASK (1 << 1) | ||
| 505 | |||
| 506 | /* PRM_RSTTIME */ | ||
| 507 | #define OMAP3430_RSTTIME2_SHIFT 8 | ||
| 508 | #define OMAP3430_RSTTIME2_MASK (0x1f << 8) | ||
| 509 | #define OMAP3430_RSTTIME1_SHIFT 0 | ||
| 510 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | ||
| 511 | |||
| 512 | /* PRM_RSTST */ | ||
| 513 | #define OMAP3430_ICECRUSHER_RST_SHIFT 10 | 115 | #define OMAP3430_ICECRUSHER_RST_SHIFT 10 |
| 514 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) | ||
| 515 | #define OMAP3430_ICEPICK_RST_SHIFT 9 | 116 | #define OMAP3430_ICEPICK_RST_SHIFT 9 |
| 516 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) | ||
| 517 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 | 117 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 |
| 518 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) | ||
| 519 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 | 118 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 |
| 520 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) | ||
| 521 | #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 | 119 | #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 |
| 522 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) | ||
| 523 | #define OMAP3430_SECURE_WD_RST_SHIFT 5 | 120 | #define OMAP3430_SECURE_WD_RST_SHIFT 5 |
| 524 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) | ||
| 525 | #define OMAP3430_MPU_WD_RST_SHIFT 4 | 121 | #define OMAP3430_MPU_WD_RST_SHIFT 4 |
| 526 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) | ||
| 527 | #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 | 122 | #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 |
| 528 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) | ||
| 529 | #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 | 123 | #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 |
| 530 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) | ||
| 531 | #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 | 124 | #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 |
| 532 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) | 125 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) |
| 533 | |||
| 534 | /* PRM_VOLTCTRL */ | ||
| 535 | #define OMAP3430_SEL_VMODE_MASK (1 << 4) | ||
| 536 | #define OMAP3430_SEL_OFF_MASK (1 << 3) | 126 | #define OMAP3430_SEL_OFF_MASK (1 << 3) |
| 537 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) | 127 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) |
| 538 | #define OMAP3430_AUTO_RET_MASK (1 << 1) | ||
| 539 | #define OMAP3430_AUTO_SLEEP_MASK (1 << 0) | ||
| 540 | |||
| 541 | /* PRM_SRAM_PCHARGE */ | ||
| 542 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | ||
| 543 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | ||
| 544 | |||
| 545 | /* PRM_CLKSRC_CTRL */ | ||
| 546 | #define OMAP3430_SYSCLKDIV_SHIFT 6 | ||
| 547 | #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) | ||
| 548 | #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 | ||
| 549 | #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) | ||
| 550 | #define OMAP3430_SYSCLKSEL_SHIFT 0 | ||
| 551 | #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) | ||
| 552 | |||
| 553 | /* PRM_VOLTSETUP1 */ | ||
| 554 | #define OMAP3430_SETUP_TIME2_SHIFT 16 | ||
| 555 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) | 128 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) |
| 556 | #define OMAP3430_SETUP_TIME1_SHIFT 0 | ||
| 557 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) | 129 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) |
| 558 | |||
| 559 | /* PRM_VOLTOFFSET */ | ||
| 560 | #define OMAP3430_OFFSET_TIME_SHIFT 0 | ||
| 561 | #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) | ||
| 562 | |||
| 563 | /* PRM_CLKSETUP */ | ||
| 564 | #define OMAP3430_SETUP_TIME_SHIFT 0 | ||
| 565 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | ||
| 566 | |||
| 567 | /* PRM_POLCTRL */ | ||
| 568 | #define OMAP3430_OFFMODE_POL_MASK (1 << 3) | ||
| 569 | #define OMAP3430_CLKOUT_POL_MASK (1 << 2) | ||
| 570 | #define OMAP3430_CLKREQ_POL_MASK (1 << 1) | ||
| 571 | #define OMAP3430_EXTVOL_POL_MASK (1 << 0) | ||
| 572 | |||
| 573 | /* PRM_VOLTSETUP2 */ | ||
| 574 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | ||
| 575 | #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) | ||
| 576 | |||
| 577 | /* PRM_VP1_CONFIG specific bits */ | ||
| 578 | |||
| 579 | /* PRM_VP1_VSTEPMIN specific bits */ | ||
| 580 | |||
| 581 | /* PRM_VP1_VSTEPMAX specific bits */ | ||
| 582 | |||
| 583 | /* PRM_VP1_VLIMITTO specific bits */ | ||
| 584 | |||
| 585 | /* PRM_VP1_VOLTAGE specific bits */ | ||
| 586 | |||
| 587 | /* PRM_VP1_STATUS specific bits */ | ||
| 588 | |||
| 589 | /* PRM_VP2_CONFIG specific bits */ | ||
| 590 | |||
| 591 | /* PRM_VP2_VSTEPMIN specific bits */ | ||
| 592 | |||
| 593 | /* PRM_VP2_VSTEPMAX specific bits */ | ||
| 594 | |||
| 595 | /* PRM_VP2_VLIMITTO specific bits */ | ||
| 596 | |||
| 597 | /* PRM_VP2_VOLTAGE specific bits */ | ||
| 598 | |||
| 599 | /* PRM_VP2_STATUS specific bits */ | ||
| 600 | |||
| 601 | /* RM_RSTST_NEON specific bits */ | ||
| 602 | |||
| 603 | /* PM_WKDEP_NEON specific bits */ | ||
| 604 | |||
| 605 | /* PM_PWSTCTRL_NEON specific bits */ | ||
| 606 | |||
| 607 | /* PM_PWSTST_NEON specific bits */ | ||
| 608 | |||
| 609 | /* PM_PREPWSTST_NEON specific bits */ | ||
| 610 | |||
| 611 | #endif | 130 | #endif |