diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2013-07-21 23:13:59 -0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-07-21 23:13:59 -0400 |
| commit | 45ffdd324c92d3b64b6b2874aaf0ac305d25504e (patch) | |
| tree | 1b6714915cf0739c0ad24ee9cd48c84bdc5793f7 /arch | |
| parent | 3b2f64d00c46e1e4e9bd0bb9bb12619adac27a4b (diff) | |
ARM: OMAP2: PRM/CM: Cleanup unused header
Cleanup unused parts of the PRM and CM regbit headers leaving only whats
used.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-24xx.h | 318 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-24xx.h | 247 |
2 files changed, 0 insertions, 565 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 669ef51b17a8..8538669cc2ad 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -14,439 +14,121 @@ | |||
| 14 | * published by the Free Software Foundation. | 14 | * published by the Free Software Foundation. |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | /* Bits shared between registers */ | ||
| 18 | |||
| 19 | /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ | ||
| 20 | #define OMAP24XX_EN_CAM_SHIFT 31 | 17 | #define OMAP24XX_EN_CAM_SHIFT 31 |
| 21 | #define OMAP24XX_EN_CAM_MASK (1 << 31) | ||
| 22 | #define OMAP24XX_EN_WDT4_SHIFT 29 | 18 | #define OMAP24XX_EN_WDT4_SHIFT 29 |
| 23 | #define OMAP24XX_EN_WDT4_MASK (1 << 29) | ||
| 24 | #define OMAP2420_EN_WDT3_SHIFT 28 | 19 | #define OMAP2420_EN_WDT3_SHIFT 28 |
| 25 | #define OMAP2420_EN_WDT3_MASK (1 << 28) | ||
| 26 | #define OMAP24XX_EN_MSPRO_SHIFT 27 | 20 | #define OMAP24XX_EN_MSPRO_SHIFT 27 |
| 27 | #define OMAP24XX_EN_MSPRO_MASK (1 << 27) | ||
| 28 | #define OMAP24XX_EN_FAC_SHIFT 25 | 21 | #define OMAP24XX_EN_FAC_SHIFT 25 |
| 29 | #define OMAP24XX_EN_FAC_MASK (1 << 25) | ||
| 30 | #define OMAP2420_EN_EAC_SHIFT 24 | 22 | #define OMAP2420_EN_EAC_SHIFT 24 |
| 31 | #define OMAP2420_EN_EAC_MASK (1 << 24) | ||
| 32 | #define OMAP24XX_EN_HDQ_SHIFT 23 | 23 | #define OMAP24XX_EN_HDQ_SHIFT 23 |
| 33 | #define OMAP24XX_EN_HDQ_MASK (1 << 23) | ||
| 34 | #define OMAP2420_EN_I2C2_SHIFT 20 | 24 | #define OMAP2420_EN_I2C2_SHIFT 20 |
| 35 | #define OMAP2420_EN_I2C2_MASK (1 << 20) | ||
| 36 | #define OMAP2420_EN_I2C1_SHIFT 19 | 25 | #define OMAP2420_EN_I2C1_SHIFT 19 |
| 37 | #define OMAP2420_EN_I2C1_MASK (1 << 19) | ||
| 38 | |||
| 39 | /* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ | ||
| 40 | #define OMAP2430_EN_MCBSP5_SHIFT 5 | 26 | #define OMAP2430_EN_MCBSP5_SHIFT 5 |
| 41 | #define OMAP2430_EN_MCBSP5_MASK (1 << 5) | ||
| 42 | #define OMAP2430_EN_MCBSP4_SHIFT 4 | 27 | #define OMAP2430_EN_MCBSP4_SHIFT 4 |
| 43 | #define OMAP2430_EN_MCBSP4_MASK (1 << 4) | ||
| 44 | #define OMAP2430_EN_MCBSP3_SHIFT 3 | 28 | #define OMAP2430_EN_MCBSP3_SHIFT 3 |
| 45 | #define OMAP2430_EN_MCBSP3_MASK (1 << 3) | ||
| 46 | #define OMAP24XX_EN_SSI_SHIFT 1 | 29 | #define OMAP24XX_EN_SSI_SHIFT 1 |
| 47 | #define OMAP24XX_EN_SSI_MASK (1 << 1) | ||
| 48 | |||
| 49 | /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ | ||
| 50 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 | 30 | #define OMAP24XX_EN_MPU_WDT_SHIFT 3 |
| 51 | #define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) | ||
| 52 | |||
| 53 | /* Bits specific to each register */ | ||
| 54 | |||
| 55 | /* CM_IDLEST_MPU */ | ||
| 56 | /* 2430 only */ | ||
| 57 | #define OMAP2430_ST_MPU_MASK (1 << 0) | ||
| 58 | |||
| 59 | /* CM_CLKSEL_MPU */ | ||
| 60 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 | 31 | #define OMAP24XX_CLKSEL_MPU_SHIFT 0 |
| 61 | #define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) | ||
| 62 | #define OMAP24XX_CLKSEL_MPU_WIDTH 5 | 32 | #define OMAP24XX_CLKSEL_MPU_WIDTH 5 |
| 63 | |||
| 64 | /* CM_CLKSTCTRL_MPU */ | ||
| 65 | #define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 | ||
| 66 | #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) | 33 | #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) |
| 67 | |||
| 68 | /* CM_FCLKEN1_CORE specific bits*/ | ||
| 69 | #define OMAP24XX_EN_TV_SHIFT 2 | 34 | #define OMAP24XX_EN_TV_SHIFT 2 |
| 70 | #define OMAP24XX_EN_TV_MASK (1 << 2) | ||
| 71 | #define OMAP24XX_EN_DSS2_SHIFT 1 | 35 | #define OMAP24XX_EN_DSS2_SHIFT 1 |
| 72 | #define OMAP24XX_EN_DSS2_MASK (1 << 1) | ||
| 73 | #define OMAP24XX_EN_DSS1_SHIFT 0 | 36 | #define OMAP24XX_EN_DSS1_SHIFT 0 |
| 74 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) | 37 | #define OMAP24XX_EN_DSS1_MASK (1 << 0) |
| 75 | |||
| 76 | /* CM_FCLKEN2_CORE specific bits */ | ||
| 77 | #define OMAP2430_EN_I2CHS2_SHIFT 20 | 38 | #define OMAP2430_EN_I2CHS2_SHIFT 20 |
| 78 | #define OMAP2430_EN_I2CHS2_MASK (1 << 20) | ||
| 79 | #define OMAP2430_EN_I2CHS1_SHIFT 19 | 39 | #define OMAP2430_EN_I2CHS1_SHIFT 19 |
| 80 | #define OMAP2430_EN_I2CHS1_MASK (1 << 19) | ||
| 81 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 | 40 | #define OMAP2430_EN_MMCHSDB2_SHIFT 17 |
| 82 | #define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) | ||
| 83 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 | 41 | #define OMAP2430_EN_MMCHSDB1_SHIFT 16 |
| 84 | #define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) | ||
| 85 | |||
| 86 | /* CM_ICLKEN1_CORE specific bits */ | ||
| 87 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 | 42 | #define OMAP24XX_EN_MAILBOXES_SHIFT 30 |
| 88 | #define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) | ||
| 89 | #define OMAP24XX_EN_DSS_SHIFT 0 | ||
| 90 | #define OMAP24XX_EN_DSS_MASK (1 << 0) | ||
| 91 | |||
| 92 | /* CM_ICLKEN2_CORE specific bits */ | ||
| 93 | |||
| 94 | /* CM_ICLKEN3_CORE */ | ||
| 95 | /* 2430 only */ | ||
| 96 | #define OMAP2430_EN_SDRC_SHIFT 2 | 43 | #define OMAP2430_EN_SDRC_SHIFT 2 |
| 97 | #define OMAP2430_EN_SDRC_MASK (1 << 2) | ||
| 98 | |||
| 99 | /* CM_ICLKEN4_CORE */ | ||
| 100 | #define OMAP24XX_EN_PKA_SHIFT 4 | 44 | #define OMAP24XX_EN_PKA_SHIFT 4 |
| 101 | #define OMAP24XX_EN_PKA_MASK (1 << 4) | ||
| 102 | #define OMAP24XX_EN_AES_SHIFT 3 | 45 | #define OMAP24XX_EN_AES_SHIFT 3 |
| 103 | #define OMAP24XX_EN_AES_MASK (1 << 3) | ||
| 104 | #define OMAP24XX_EN_RNG_SHIFT 2 | 46 | #define OMAP24XX_EN_RNG_SHIFT 2 |
| 105 | #define OMAP24XX_EN_RNG_MASK (1 << 2) | ||
| 106 | #define OMAP24XX_EN_SHA_SHIFT 1 | 47 | #define OMAP24XX_EN_SHA_SHIFT 1 |
| 107 | #define OMAP24XX_EN_SHA_MASK (1 << 1) | ||
| 108 | #define OMAP24XX_EN_DES_SHIFT 0 | 48 | #define OMAP24XX_EN_DES_SHIFT 0 |
| 109 | #define OMAP24XX_EN_DES_MASK (1 << 0) | ||
| 110 | |||
| 111 | /* CM_IDLEST1_CORE specific bits */ | ||
| 112 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 | 49 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
| 113 | #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) | ||
| 114 | #define OMAP24XX_ST_WDT4_SHIFT 29 | ||
| 115 | #define OMAP24XX_ST_WDT4_MASK (1 << 29) | ||
| 116 | #define OMAP2420_ST_WDT3_SHIFT 28 | ||
| 117 | #define OMAP2420_ST_WDT3_MASK (1 << 28) | ||
| 118 | #define OMAP24XX_ST_MSPRO_SHIFT 27 | ||
| 119 | #define OMAP24XX_ST_MSPRO_MASK (1 << 27) | ||
| 120 | #define OMAP24XX_ST_FAC_SHIFT 25 | ||
| 121 | #define OMAP24XX_ST_FAC_MASK (1 << 25) | ||
| 122 | #define OMAP2420_ST_EAC_SHIFT 24 | ||
| 123 | #define OMAP2420_ST_EAC_MASK (1 << 24) | ||
| 124 | #define OMAP24XX_ST_HDQ_SHIFT 23 | 50 | #define OMAP24XX_ST_HDQ_SHIFT 23 |
| 125 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | ||
| 126 | #define OMAP2420_ST_I2C2_SHIFT 20 | 51 | #define OMAP2420_ST_I2C2_SHIFT 20 |
| 127 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | ||
| 128 | #define OMAP2430_ST_I2CHS1_SHIFT 19 | 52 | #define OMAP2430_ST_I2CHS1_SHIFT 19 |
| 129 | #define OMAP2430_ST_I2CHS1_MASK (1 << 19) | ||
| 130 | #define OMAP2420_ST_I2C1_SHIFT 19 | 53 | #define OMAP2420_ST_I2C1_SHIFT 19 |
| 131 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | ||
| 132 | #define OMAP2430_ST_I2CHS2_SHIFT 20 | 54 | #define OMAP2430_ST_I2CHS2_SHIFT 20 |
| 133 | #define OMAP2430_ST_I2CHS2_MASK (1 << 20) | ||
| 134 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | 55 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
| 135 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | ||
| 136 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | 56 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 |
| 137 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | ||
| 138 | #define OMAP24XX_ST_DSS_SHIFT 0 | 57 | #define OMAP24XX_ST_DSS_SHIFT 0 |
| 139 | #define OMAP24XX_ST_DSS_MASK (1 << 0) | ||
| 140 | |||
| 141 | /* CM_IDLEST2_CORE */ | ||
| 142 | #define OMAP2430_ST_MCBSP5_SHIFT 5 | 58 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
| 143 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) | ||
| 144 | #define OMAP2430_ST_MCBSP4_SHIFT 4 | 59 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
| 145 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) | ||
| 146 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | 60 | #define OMAP2430_ST_MCBSP3_SHIFT 3 |
| 147 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | ||
| 148 | #define OMAP24XX_ST_SSI_SHIFT 1 | ||
| 149 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | ||
| 150 | |||
| 151 | /* CM_IDLEST3_CORE */ | ||
| 152 | /* 2430 only */ | ||
| 153 | #define OMAP2430_ST_SDRC_MASK (1 << 2) | ||
| 154 | |||
| 155 | /* CM_IDLEST4_CORE */ | ||
| 156 | #define OMAP24XX_ST_PKA_SHIFT 4 | ||
| 157 | #define OMAP24XX_ST_PKA_MASK (1 << 4) | ||
| 158 | #define OMAP24XX_ST_AES_SHIFT 3 | 61 | #define OMAP24XX_ST_AES_SHIFT 3 |
| 159 | #define OMAP24XX_ST_AES_MASK (1 << 3) | ||
| 160 | #define OMAP24XX_ST_RNG_SHIFT 2 | 62 | #define OMAP24XX_ST_RNG_SHIFT 2 |
| 161 | #define OMAP24XX_ST_RNG_MASK (1 << 2) | ||
| 162 | #define OMAP24XX_ST_SHA_SHIFT 1 | 63 | #define OMAP24XX_ST_SHA_SHIFT 1 |
| 163 | #define OMAP24XX_ST_SHA_MASK (1 << 1) | ||
| 164 | #define OMAP24XX_ST_DES_SHIFT 0 | ||
| 165 | #define OMAP24XX_ST_DES_MASK (1 << 0) | ||
| 166 | |||
| 167 | /* CM_AUTOIDLE1_CORE */ | ||
| 168 | #define OMAP24XX_AUTO_CAM_MASK (1 << 31) | ||
| 169 | #define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) | ||
| 170 | #define OMAP24XX_AUTO_WDT4_MASK (1 << 29) | ||
| 171 | #define OMAP2420_AUTO_WDT3_MASK (1 << 28) | ||
| 172 | #define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) | ||
| 173 | #define OMAP2420_AUTO_MMC_MASK (1 << 26) | ||
| 174 | #define OMAP24XX_AUTO_FAC_MASK (1 << 25) | ||
| 175 | #define OMAP2420_AUTO_EAC_MASK (1 << 24) | ||
| 176 | #define OMAP24XX_AUTO_HDQ_MASK (1 << 23) | ||
| 177 | #define OMAP24XX_AUTO_UART2_MASK (1 << 22) | ||
| 178 | #define OMAP24XX_AUTO_UART1_MASK (1 << 21) | ||
| 179 | #define OMAP24XX_AUTO_I2C2_MASK (1 << 20) | ||
| 180 | #define OMAP24XX_AUTO_I2C1_MASK (1 << 19) | ||
| 181 | #define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) | ||
| 182 | #define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) | ||
| 183 | #define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) | ||
| 184 | #define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) | ||
| 185 | #define OMAP24XX_AUTO_GPT12_MASK (1 << 14) | ||
| 186 | #define OMAP24XX_AUTO_GPT11_MASK (1 << 13) | ||
| 187 | #define OMAP24XX_AUTO_GPT10_MASK (1 << 12) | ||
| 188 | #define OMAP24XX_AUTO_GPT9_MASK (1 << 11) | ||
| 189 | #define OMAP24XX_AUTO_GPT8_MASK (1 << 10) | ||
| 190 | #define OMAP24XX_AUTO_GPT7_MASK (1 << 9) | ||
| 191 | #define OMAP24XX_AUTO_GPT6_MASK (1 << 8) | ||
| 192 | #define OMAP24XX_AUTO_GPT5_MASK (1 << 7) | ||
| 193 | #define OMAP24XX_AUTO_GPT4_MASK (1 << 6) | ||
| 194 | #define OMAP24XX_AUTO_GPT3_MASK (1 << 5) | ||
| 195 | #define OMAP24XX_AUTO_GPT2_MASK (1 << 4) | ||
| 196 | #define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) | ||
| 197 | #define OMAP24XX_AUTO_DSS_MASK (1 << 0) | ||
| 198 | |||
| 199 | /* CM_AUTOIDLE2_CORE */ | ||
| 200 | #define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) | ||
| 201 | #define OMAP2430_AUTO_GPIO5_MASK (1 << 10) | ||
| 202 | #define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) | ||
| 203 | #define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) | ||
| 204 | #define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) | ||
| 205 | #define OMAP2430_AUTO_USBHS_MASK (1 << 6) | ||
| 206 | #define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) | ||
| 207 | #define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) | ||
| 208 | #define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) | ||
| 209 | #define OMAP24XX_AUTO_UART3_MASK (1 << 2) | ||
| 210 | #define OMAP24XX_AUTO_SSI_MASK (1 << 1) | ||
| 211 | #define OMAP24XX_AUTO_USB_MASK (1 << 0) | ||
| 212 | |||
| 213 | /* CM_AUTOIDLE3_CORE */ | ||
| 214 | #define OMAP24XX_AUTO_SDRC_SHIFT 2 | 64 | #define OMAP24XX_AUTO_SDRC_SHIFT 2 |
| 215 | #define OMAP24XX_AUTO_SDRC_MASK (1 << 2) | ||
| 216 | #define OMAP24XX_AUTO_GPMC_SHIFT 1 | 65 | #define OMAP24XX_AUTO_GPMC_SHIFT 1 |
| 217 | #define OMAP24XX_AUTO_GPMC_MASK (1 << 1) | ||
| 218 | #define OMAP24XX_AUTO_SDMA_SHIFT 0 | 66 | #define OMAP24XX_AUTO_SDMA_SHIFT 0 |
| 219 | #define OMAP24XX_AUTO_SDMA_MASK (1 << 0) | ||
| 220 | |||
| 221 | /* CM_AUTOIDLE4_CORE */ | ||
| 222 | #define OMAP24XX_AUTO_PKA_MASK (1 << 4) | ||
| 223 | #define OMAP24XX_AUTO_AES_MASK (1 << 3) | ||
| 224 | #define OMAP24XX_AUTO_RNG_MASK (1 << 2) | ||
| 225 | #define OMAP24XX_AUTO_SHA_MASK (1 << 1) | ||
| 226 | #define OMAP24XX_AUTO_DES_MASK (1 << 0) | ||
| 227 | |||
| 228 | /* CM_CLKSEL1_CORE */ | ||
| 229 | #define OMAP24XX_CLKSEL_USB_SHIFT 25 | ||
| 230 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) | 67 | #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) |
| 231 | #define OMAP24XX_CLKSEL_SSI_SHIFT 20 | ||
| 232 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) | 68 | #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) |
| 233 | #define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 | ||
| 234 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) | 69 | #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) |
| 235 | #define OMAP24XX_CLKSEL_DSS2_SHIFT 13 | ||
| 236 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) | 70 | #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) |
| 237 | #define OMAP24XX_CLKSEL_DSS1_SHIFT 8 | ||
| 238 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) | 71 | #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) |
| 239 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 | 72 | #define OMAP24XX_CLKSEL_L4_SHIFT 5 |
| 240 | #define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) | ||
| 241 | #define OMAP24XX_CLKSEL_L4_WIDTH 2 | 73 | #define OMAP24XX_CLKSEL_L4_WIDTH 2 |
| 242 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 | 74 | #define OMAP24XX_CLKSEL_L3_SHIFT 0 |
| 243 | #define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) | ||
| 244 | #define OMAP24XX_CLKSEL_L3_WIDTH 5 | 75 | #define OMAP24XX_CLKSEL_L3_WIDTH 5 |
| 245 | |||
| 246 | /* CM_CLKSEL2_CORE */ | ||
| 247 | #define OMAP24XX_CLKSEL_GPT12_SHIFT 22 | ||
| 248 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) | 76 | #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) |
| 249 | #define OMAP24XX_CLKSEL_GPT11_SHIFT 20 | ||
| 250 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) | 77 | #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) |
| 251 | #define OMAP24XX_CLKSEL_GPT10_SHIFT 18 | ||
| 252 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) | 78 | #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) |
| 253 | #define OMAP24XX_CLKSEL_GPT9_SHIFT 16 | ||
| 254 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) | 79 | #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) |
| 255 | #define OMAP24XX_CLKSEL_GPT8_SHIFT 14 | ||
| 256 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) | 80 | #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) |
| 257 | #define OMAP24XX_CLKSEL_GPT7_SHIFT 12 | ||
| 258 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) | 81 | #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) |
| 259 | #define OMAP24XX_CLKSEL_GPT6_SHIFT 10 | ||
| 260 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) | 82 | #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) |
| 261 | #define OMAP24XX_CLKSEL_GPT5_SHIFT 8 | ||
| 262 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) | 83 | #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) |
| 263 | #define OMAP24XX_CLKSEL_GPT4_SHIFT 6 | ||
| 264 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) | 84 | #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) |
| 265 | #define OMAP24XX_CLKSEL_GPT3_SHIFT 4 | ||
| 266 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) | 85 | #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) |
| 267 | #define OMAP24XX_CLKSEL_GPT2_SHIFT 2 | ||
| 268 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) | 86 | #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) |
| 269 | |||
| 270 | /* CM_CLKSTCTRL_CORE */ | ||
| 271 | #define OMAP24XX_AUTOSTATE_DSS_SHIFT 2 | ||
| 272 | #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) | 87 | #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) |
| 273 | #define OMAP24XX_AUTOSTATE_L4_SHIFT 1 | ||
| 274 | #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) | 88 | #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) |
| 275 | #define OMAP24XX_AUTOSTATE_L3_SHIFT 0 | ||
| 276 | #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) | 89 | #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) |
| 277 | |||
| 278 | /* CM_FCLKEN_GFX */ | ||
| 279 | #define OMAP24XX_EN_3D_SHIFT 2 | 90 | #define OMAP24XX_EN_3D_SHIFT 2 |
| 280 | #define OMAP24XX_EN_3D_MASK (1 << 2) | ||
| 281 | #define OMAP24XX_EN_2D_SHIFT 1 | 91 | #define OMAP24XX_EN_2D_SHIFT 1 |
| 282 | #define OMAP24XX_EN_2D_MASK (1 << 1) | ||
| 283 | |||
| 284 | /* CM_ICLKEN_GFX specific bits */ | ||
| 285 | |||
| 286 | /* CM_IDLEST_GFX specific bits */ | ||
| 287 | |||
| 288 | /* CM_CLKSEL_GFX specific bits */ | ||
| 289 | |||
| 290 | /* CM_CLKSTCTRL_GFX */ | ||
| 291 | #define OMAP24XX_AUTOSTATE_GFX_SHIFT 0 | ||
| 292 | #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) | 92 | #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) |
| 293 | |||
| 294 | /* CM_FCLKEN_WKUP specific bits */ | ||
| 295 | |||
| 296 | /* CM_ICLKEN_WKUP specific bits */ | ||
| 297 | #define OMAP2430_EN_ICR_SHIFT 6 | 93 | #define OMAP2430_EN_ICR_SHIFT 6 |
| 298 | #define OMAP2430_EN_ICR_MASK (1 << 6) | ||
| 299 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 | 94 | #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 |
| 300 | #define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) | ||
| 301 | #define OMAP24XX_EN_WDT1_SHIFT 4 | 95 | #define OMAP24XX_EN_WDT1_SHIFT 4 |
| 302 | #define OMAP24XX_EN_WDT1_MASK (1 << 4) | ||
| 303 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 | 96 | #define OMAP24XX_EN_32KSYNC_SHIFT 1 |
| 304 | #define OMAP24XX_EN_32KSYNC_MASK (1 << 1) | ||
| 305 | |||
| 306 | /* CM_IDLEST_WKUP specific bits */ | ||
| 307 | #define OMAP2430_ST_ICR_SHIFT 6 | ||
| 308 | #define OMAP2430_ST_ICR_MASK (1 << 6) | ||
| 309 | #define OMAP24XX_ST_OMAPCTRL_SHIFT 5 | ||
| 310 | #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) | ||
| 311 | #define OMAP24XX_ST_WDT1_SHIFT 4 | ||
| 312 | #define OMAP24XX_ST_WDT1_MASK (1 << 4) | ||
| 313 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 | 97 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 |
| 314 | #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) | ||
| 315 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 | 98 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 |
| 316 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | ||
| 317 | |||
| 318 | /* CM_AUTOIDLE_WKUP */ | ||
| 319 | #define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) | ||
| 320 | #define OMAP24XX_AUTO_WDT1_MASK (1 << 4) | ||
| 321 | #define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) | ||
| 322 | #define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) | ||
| 323 | #define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) | ||
| 324 | #define OMAP24XX_AUTO_GPT1_MASK (1 << 0) | ||
| 325 | |||
| 326 | /* CM_CLKSEL_WKUP */ | ||
| 327 | #define OMAP24XX_CLKSEL_GPT1_SHIFT 0 | ||
| 328 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) | 99 | #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) |
| 329 | |||
| 330 | /* CM_CLKEN_PLL */ | ||
| 331 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 | 100 | #define OMAP24XX_EN_54M_PLL_SHIFT 6 |
| 332 | #define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) | ||
| 333 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 | 101 | #define OMAP24XX_EN_96M_PLL_SHIFT 2 |
| 334 | #define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) | ||
| 335 | #define OMAP24XX_EN_DPLL_SHIFT 0 | ||
| 336 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) | 102 | #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) |
| 337 | |||
| 338 | /* CM_IDLEST_CKGEN */ | ||
| 339 | #define OMAP24XX_ST_54M_APLL_SHIFT 9 | 103 | #define OMAP24XX_ST_54M_APLL_SHIFT 9 |
| 340 | #define OMAP24XX_ST_54M_APLL_MASK (1 << 9) | ||
| 341 | #define OMAP24XX_ST_96M_APLL_SHIFT 8 | 104 | #define OMAP24XX_ST_96M_APLL_SHIFT 8 |
| 342 | #define OMAP24XX_ST_96M_APLL_MASK (1 << 8) | ||
| 343 | #define OMAP24XX_ST_54M_CLK_MASK (1 << 6) | ||
| 344 | #define OMAP24XX_ST_12M_CLK_MASK (1 << 5) | ||
| 345 | #define OMAP24XX_ST_48M_CLK_MASK (1 << 4) | ||
| 346 | #define OMAP24XX_ST_96M_CLK_MASK (1 << 2) | ||
| 347 | #define OMAP24XX_ST_CORE_CLK_SHIFT 0 | ||
| 348 | #define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) | ||
| 349 | |||
| 350 | /* CM_AUTOIDLE_PLL */ | ||
| 351 | #define OMAP24XX_AUTO_54M_SHIFT 6 | ||
| 352 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) | 105 | #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) |
| 353 | #define OMAP24XX_AUTO_96M_SHIFT 2 | ||
| 354 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) | 106 | #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) |
| 355 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 | 107 | #define OMAP24XX_AUTO_DPLL_SHIFT 0 |
| 356 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) | 108 | #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) |
| 357 | |||
| 358 | /* CM_CLKSEL1_PLL */ | ||
| 359 | #define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 | ||
| 360 | #define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) | ||
| 361 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 | 109 | #define OMAP24XX_APLLS_CLKIN_SHIFT 23 |
| 362 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) | 110 | #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) |
| 363 | #define OMAP24XX_DPLL_MULT_SHIFT 12 | ||
| 364 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) | 111 | #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) |
| 365 | #define OMAP24XX_DPLL_DIV_SHIFT 8 | ||
| 366 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) | 112 | #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) |
| 367 | #define OMAP24XX_54M_SOURCE_SHIFT 5 | 113 | #define OMAP24XX_54M_SOURCE_SHIFT 5 |
| 368 | #define OMAP24XX_54M_SOURCE_MASK (1 << 5) | ||
| 369 | #define OMAP24XX_54M_SOURCE_WIDTH 1 | 114 | #define OMAP24XX_54M_SOURCE_WIDTH 1 |
| 370 | #define OMAP2430_96M_SOURCE_SHIFT 4 | 115 | #define OMAP2430_96M_SOURCE_SHIFT 4 |
| 371 | #define OMAP2430_96M_SOURCE_MASK (1 << 4) | ||
| 372 | #define OMAP2430_96M_SOURCE_WIDTH 1 | 116 | #define OMAP2430_96M_SOURCE_WIDTH 1 |
| 373 | #define OMAP24XX_48M_SOURCE_SHIFT 3 | ||
| 374 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) | 117 | #define OMAP24XX_48M_SOURCE_MASK (1 << 3) |
| 375 | #define OMAP2430_ALTCLK_SOURCE_SHIFT 0 | ||
| 376 | #define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) | ||
| 377 | |||
| 378 | /* CM_CLKSEL2_PLL */ | ||
| 379 | #define OMAP24XX_CORE_CLK_SRC_SHIFT 0 | ||
| 380 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) | 118 | #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) |
| 381 | |||
| 382 | /* CM_FCLKEN_DSP */ | ||
| 383 | #define OMAP2420_EN_IVA_COP_SHIFT 10 | 119 | #define OMAP2420_EN_IVA_COP_SHIFT 10 |
| 384 | #define OMAP2420_EN_IVA_COP_MASK (1 << 10) | ||
| 385 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 | 120 | #define OMAP2420_EN_IVA_MPU_SHIFT 8 |
| 386 | #define OMAP2420_EN_IVA_MPU_MASK (1 << 8) | ||
| 387 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 | 121 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 |
| 388 | #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) | ||
| 389 | |||
| 390 | /* CM_ICLKEN_DSP */ | ||
| 391 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 | 122 | #define OMAP2420_EN_DSP_IPI_SHIFT 1 |
| 392 | #define OMAP2420_EN_DSP_IPI_MASK (1 << 1) | ||
| 393 | |||
| 394 | /* CM_IDLEST_DSP */ | ||
| 395 | #define OMAP2420_ST_IVA_MASK (1 << 8) | ||
| 396 | #define OMAP2420_ST_IPI_MASK (1 << 1) | ||
| 397 | #define OMAP24XX_ST_DSP_MASK (1 << 0) | ||
| 398 | |||
| 399 | /* CM_AUTOIDLE_DSP */ | ||
| 400 | #define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) | ||
| 401 | |||
| 402 | /* CM_CLKSEL_DSP */ | ||
| 403 | #define OMAP2420_SYNC_IVA_MASK (1 << 13) | ||
| 404 | #define OMAP2420_CLKSEL_IVA_SHIFT 8 | ||
| 405 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) | 123 | #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) |
| 406 | #define OMAP24XX_SYNC_DSP_MASK (1 << 7) | ||
| 407 | #define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 | ||
| 408 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) | 124 | #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) |
| 409 | #define OMAP24XX_CLKSEL_DSP_SHIFT 0 | ||
| 410 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) | 125 | #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) |
| 411 | |||
| 412 | /* CM_CLKSTCTRL_DSP */ | ||
| 413 | #define OMAP2420_AUTOSTATE_IVA_SHIFT 8 | ||
| 414 | #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) | 126 | #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) |
| 415 | #define OMAP24XX_AUTOSTATE_DSP_SHIFT 0 | ||
| 416 | #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) | 127 | #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) |
| 417 | |||
| 418 | /* CM_FCLKEN_MDM */ | ||
| 419 | /* 2430 only */ | ||
| 420 | #define OMAP2430_EN_OSC_SHIFT 1 | 128 | #define OMAP2430_EN_OSC_SHIFT 1 |
| 421 | #define OMAP2430_EN_OSC_MASK (1 << 1) | ||
| 422 | |||
| 423 | /* CM_ICLKEN_MDM */ | ||
| 424 | /* 2430 only */ | ||
| 425 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 | 129 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 |
| 426 | #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) | ||
| 427 | |||
| 428 | /* CM_IDLEST_MDM specific bits */ | ||
| 429 | /* 2430 only */ | ||
| 430 | |||
| 431 | /* CM_AUTOIDLE_MDM */ | ||
| 432 | /* 2430 only */ | ||
| 433 | #define OMAP2430_AUTO_OSC_MASK (1 << 1) | ||
| 434 | #define OMAP2430_AUTO_MDM_MASK (1 << 0) | ||
| 435 | |||
| 436 | /* CM_CLKSEL_MDM */ | ||
| 437 | /* 2430 only */ | ||
| 438 | #define OMAP2430_SYNC_MDM_MASK (1 << 4) | ||
| 439 | #define OMAP2430_CLKSEL_MDM_SHIFT 0 | ||
| 440 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) | 130 | #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) |
| 441 | |||
| 442 | /* CM_CLKSTCTRL_MDM */ | ||
| 443 | /* 2430 only */ | ||
| 444 | #define OMAP2430_AUTOSTATE_MDM_SHIFT 0 | ||
| 445 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) | 131 | #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) |
| 446 | |||
| 447 | /* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ | ||
| 448 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 | 132 | #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 |
| 449 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 | 133 | #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 |
| 450 | |||
| 451 | |||
| 452 | #endif | 134 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 91aa5106d637..37fc905c9636 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h | |||
| @@ -16,274 +16,27 @@ | |||
| 16 | 16 | ||
| 17 | #include "prm2xxx.h" | 17 | #include "prm2xxx.h" |
| 18 | 18 | ||
| 19 | /* Bits shared between registers */ | ||
| 20 | |||
| 21 | /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ | ||
| 22 | #define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) | ||
| 23 | #define OMAP24XX_WKUP2_ST_MASK (1 << 1) | ||
| 24 | #define OMAP24XX_WKUP1_ST_MASK (1 << 0) | ||
| 25 | |||
| 26 | /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ | ||
| 27 | #define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) | ||
| 28 | #define OMAP24XX_WKUP2_EN_MASK (1 << 1) | ||
| 29 | #define OMAP24XX_WKUP1_EN_MASK (1 << 0) | ||
| 30 | |||
| 31 | /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ | ||
| 32 | #define OMAP24XX_EN_MPU_SHIFT 1 | ||
| 33 | #define OMAP24XX_EN_MPU_MASK (1 << 1) | ||
| 34 | #define OMAP24XX_EN_CORE_SHIFT 0 | 19 | #define OMAP24XX_EN_CORE_SHIFT 0 |
| 35 | #define OMAP24XX_EN_CORE_MASK (1 << 0) | ||
| 36 | |||
| 37 | /* | ||
| 38 | * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM | ||
| 39 | * shared bits | ||
| 40 | */ | ||
| 41 | #define OMAP24XX_MEMONSTATE_SHIFT 10 | ||
| 42 | #define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) | ||
| 43 | #define OMAP24XX_MEMRETSTATE_MASK (1 << 3) | ||
| 44 | |||
| 45 | /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ | ||
| 46 | #define OMAP24XX_FORCESTATE_MASK (1 << 18) | 20 | #define OMAP24XX_FORCESTATE_MASK (1 << 18) |
| 47 | |||
| 48 | /* | ||
| 49 | * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, | ||
| 50 | * PM_PWSTST_MDM shared bits | ||
| 51 | */ | ||
| 52 | #define OMAP24XX_CLKACTIVITY_MASK (1 << 19) | ||
| 53 | |||
| 54 | /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ | ||
| 55 | #define OMAP24XX_LASTSTATEENTERED_SHIFT 4 | ||
| 56 | #define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) | ||
| 57 | |||
| 58 | /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ | ||
| 59 | #define OMAP2430_MEMSTATEST_SHIFT 10 | ||
| 60 | #define OMAP2430_MEMSTATEST_MASK (0x3 << 10) | ||
| 61 | |||
| 62 | /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ | ||
| 63 | #define OMAP24XX_POWERSTATEST_SHIFT 0 | ||
| 64 | #define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) | ||
| 65 | |||
| 66 | |||
| 67 | /* Bits specific to each register */ | ||
| 68 | |||
| 69 | /* PRCM_REVISION */ | ||
| 70 | #define OMAP24XX_REV_SHIFT 0 | ||
| 71 | #define OMAP24XX_REV_MASK (0xff << 0) | ||
| 72 | |||
| 73 | /* PRCM_SYSCONFIG */ | ||
| 74 | #define OMAP24XX_AUTOIDLE_MASK (1 << 0) | 21 | #define OMAP24XX_AUTOIDLE_MASK (1 << 0) |
| 75 | |||
| 76 | /* PRCM_IRQSTATUS_MPU specific bits */ | ||
| 77 | #define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) | ||
| 78 | #define OMAP24XX_TRANSITION_ST_MASK (1 << 5) | ||
| 79 | #define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) | ||
| 80 | #define OMAP24XX_EVGENON_ST_MASK (1 << 3) | ||
| 81 | |||
| 82 | /* PRCM_IRQENABLE_MPU specific bits */ | ||
| 83 | #define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) | ||
| 84 | #define OMAP24XX_TRANSITION_EN_MASK (1 << 5) | ||
| 85 | #define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) | ||
| 86 | #define OMAP24XX_EVGENON_EN_MASK (1 << 3) | ||
| 87 | |||
| 88 | /* PRCM_VOLTCTRL */ | ||
| 89 | #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) | 22 | #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) |
| 90 | #define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) | ||
| 91 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 | 23 | #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 |
| 92 | #define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) | ||
| 93 | #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) | 24 | #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) |
| 94 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 | 25 | #define OMAP24XX_SETRET_LEVEL_SHIFT 6 |
| 95 | #define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) | ||
| 96 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 | 26 | #define OMAP24XX_VOLT_LEVEL_SHIFT 0 |
| 97 | #define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) | ||
| 98 | |||
| 99 | /* PRCM_VOLTST */ | ||
| 100 | #define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 | ||
| 101 | #define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) | ||
| 102 | |||
| 103 | /* PRCM_CLKSRC_CTRL specific bits */ | ||
| 104 | |||
| 105 | /* PRCM_CLKOUT_CTRL */ | ||
| 106 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 | 27 | #define OMAP2420_CLKOUT2_EN_SHIFT 15 |
| 107 | #define OMAP2420_CLKOUT2_EN_MASK (1 << 15) | ||
| 108 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 | 28 | #define OMAP2420_CLKOUT2_DIV_SHIFT 11 |
| 109 | #define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) | ||
| 110 | #define OMAP2420_CLKOUT2_DIV_WIDTH 3 | 29 | #define OMAP2420_CLKOUT2_DIV_WIDTH 3 |
| 111 | #define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 | ||
| 112 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) | 30 | #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) |
| 113 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 | 31 | #define OMAP24XX_CLKOUT_EN_SHIFT 7 |
| 114 | #define OMAP24XX_CLKOUT_EN_MASK (1 << 7) | ||
| 115 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 | 32 | #define OMAP24XX_CLKOUT_DIV_SHIFT 3 |
| 116 | #define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) | ||
| 117 | #define OMAP24XX_CLKOUT_DIV_WIDTH 3 | 33 | #define OMAP24XX_CLKOUT_DIV_WIDTH 3 |
| 118 | #define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 | ||
| 119 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) | 34 | #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) |
| 120 | |||
| 121 | /* PRCM_CLKEMUL_CTRL */ | ||
| 122 | #define OMAP24XX_EMULATION_EN_SHIFT 0 | 35 | #define OMAP24XX_EMULATION_EN_SHIFT 0 |
| 123 | #define OMAP24XX_EMULATION_EN_MASK (1 << 0) | ||
| 124 | |||
| 125 | /* PRCM_CLKCFG_CTRL */ | ||
| 126 | #define OMAP24XX_VALID_CONFIG_MASK (1 << 0) | ||
| 127 | |||
| 128 | /* PRCM_CLKCFG_STATUS */ | ||
| 129 | #define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) | ||
| 130 | |||
| 131 | /* PRCM_VOLTSETUP specific bits */ | ||
| 132 | |||
| 133 | /* PRCM_CLKSSETUP specific bits */ | ||
| 134 | |||
| 135 | /* PRCM_POLCTRL */ | ||
| 136 | #define OMAP2420_CLKOUT2_POL_MASK (1 << 10) | ||
| 137 | #define OMAP24XX_CLKOUT_POL_MASK (1 << 9) | ||
| 138 | #define OMAP24XX_CLKREQ_POL_MASK (1 << 8) | ||
| 139 | #define OMAP2430_USE_POWEROK_MASK (1 << 2) | ||
| 140 | #define OMAP2430_POWEROK_POL_MASK (1 << 1) | ||
| 141 | #define OMAP24XX_EXTVOL_POL_MASK (1 << 0) | ||
| 142 | |||
| 143 | /* RM_RSTST_MPU specific bits */ | ||
| 144 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ | ||
| 145 | |||
| 146 | /* PM_WKDEP_MPU specific bits */ | ||
| 147 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 | 36 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 |
| 148 | #define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5) | ||
| 149 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 | 37 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 |
| 150 | #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2) | ||
| 151 | |||
| 152 | /* PM_EVGENCTRL_MPU specific bits */ | ||
| 153 | |||
| 154 | /* PM_EVEGENONTIM_MPU specific bits */ | ||
| 155 | |||
| 156 | /* PM_EVEGENOFFTIM_MPU specific bits */ | ||
| 157 | |||
| 158 | /* PM_PWSTCTRL_MPU specific bits */ | ||
| 159 | #define OMAP2430_FORCESTATE_MASK (1 << 18) | ||
| 160 | |||
| 161 | /* PM_PWSTST_MPU specific bits */ | ||
| 162 | /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ | ||
| 163 | |||
| 164 | /* PM_WKEN1_CORE specific bits */ | ||
| 165 | |||
| 166 | /* PM_WKEN2_CORE specific bits */ | ||
| 167 | |||
| 168 | /* PM_WKST1_CORE specific bits*/ | ||
| 169 | |||
| 170 | /* PM_WKST2_CORE specific bits */ | ||
| 171 | |||
| 172 | /* PM_WKDEP_CORE specific bits*/ | ||
| 173 | #define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) | ||
| 174 | #define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) | ||
| 175 | #define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) | ||
| 176 | |||
| 177 | /* PM_PWSTCTRL_CORE specific bits */ | ||
| 178 | #define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) | ||
| 179 | #define OMAP24XX_MEM3ONSTATE_SHIFT 14 | ||
| 180 | #define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) | ||
| 181 | #define OMAP24XX_MEM2ONSTATE_SHIFT 12 | ||
| 182 | #define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) | ||
| 183 | #define OMAP24XX_MEM1ONSTATE_SHIFT 10 | ||
| 184 | #define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) | ||
| 185 | #define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) | ||
| 186 | #define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) | ||
| 187 | #define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) | ||
| 188 | |||
| 189 | /* PM_PWSTST_CORE specific bits */ | ||
| 190 | #define OMAP24XX_MEM3STATEST_SHIFT 14 | ||
| 191 | #define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) | ||
| 192 | #define OMAP24XX_MEM2STATEST_SHIFT 12 | ||
| 193 | #define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) | ||
| 194 | #define OMAP24XX_MEM1STATEST_SHIFT 10 | ||
| 195 | #define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) | ||
| 196 | |||
| 197 | /* RM_RSTCTRL_GFX */ | ||
| 198 | #define OMAP24XX_GFX_RST_MASK (1 << 0) | ||
| 199 | |||
| 200 | /* RM_RSTST_GFX specific bits */ | ||
| 201 | #define OMAP24XX_GFX_SW_RST_MASK (1 << 4) | ||
| 202 | |||
| 203 | /* PM_PWSTCTRL_GFX specific bits */ | ||
| 204 | |||
| 205 | /* PM_WKDEP_GFX specific bits */ | ||
| 206 | /* 2430 often calls EN_WAKEUP "EN_WKUP" */ | ||
| 207 | |||
| 208 | /* RM_RSTCTRL_WKUP specific bits */ | ||
| 209 | |||
| 210 | /* RM_RSTTIME_WKUP specific bits */ | ||
| 211 | |||
| 212 | /* RM_RSTST_WKUP specific bits */ | ||
| 213 | /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 214 | #define OMAP24XX_EXTWMPU_RST_SHIFT 6 | 38 | #define OMAP24XX_EXTWMPU_RST_SHIFT 6 |
| 215 | #define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) | ||
| 216 | #define OMAP24XX_SECU_WD_RST_SHIFT 5 | 39 | #define OMAP24XX_SECU_WD_RST_SHIFT 5 |
| 217 | #define OMAP24XX_SECU_WD_RST_MASK (1 << 5) | ||
| 218 | #define OMAP24XX_MPU_WD_RST_SHIFT 4 | 40 | #define OMAP24XX_MPU_WD_RST_SHIFT 4 |
| 219 | #define OMAP24XX_MPU_WD_RST_MASK (1 << 4) | ||
| 220 | #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 | 41 | #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 |
| 221 | #define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) | ||
| 222 | |||
| 223 | /* PM_WKEN_WKUP specific bits */ | ||
| 224 | |||
| 225 | /* PM_WKST_WKUP specific bits */ | ||
| 226 | |||
| 227 | /* RM_RSTCTRL_DSP */ | ||
| 228 | #define OMAP2420_RST_IVA_MASK (1 << 8) | ||
| 229 | #define OMAP24XX_RST2_DSP_MASK (1 << 1) | ||
| 230 | #define OMAP24XX_RST1_DSP_MASK (1 << 0) | ||
| 231 | |||
| 232 | /* RM_RSTST_DSP specific bits */ | ||
| 233 | /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ | ||
| 234 | #define OMAP2420_IVA_SW_RST_MASK (1 << 8) | ||
| 235 | #define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) | ||
| 236 | #define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) | ||
| 237 | |||
| 238 | /* PM_WKDEP_DSP specific bits */ | ||
| 239 | |||
| 240 | /* PM_PWSTCTRL_DSP specific bits */ | ||
| 241 | /* 2430 only: MEMONSTATE, MEMRETSTATE */ | ||
| 242 | #define OMAP2420_MEMIONSTATE_SHIFT 12 | ||
| 243 | #define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) | ||
| 244 | #define OMAP2420_MEMIRETSTATE_MASK (1 << 4) | ||
| 245 | |||
| 246 | /* PM_PWSTST_DSP specific bits */ | ||
| 247 | /* MEMSTATEST is 2430 only */ | ||
| 248 | #define OMAP2420_MEMISTATEST_SHIFT 12 | ||
| 249 | #define OMAP2420_MEMISTATEST_MASK (0x3 << 12) | ||
| 250 | |||
| 251 | /* PRCM_IRQSTATUS_DSP specific bits */ | ||
| 252 | |||
| 253 | /* PRCM_IRQENABLE_DSP specific bits */ | ||
| 254 | |||
| 255 | /* RM_RSTCTRL_MDM */ | ||
| 256 | /* 2430 only */ | ||
| 257 | #define OMAP2430_PWRON1_MDM_MASK (1 << 1) | ||
| 258 | #define OMAP2430_RST1_MDM_MASK (1 << 0) | ||
| 259 | |||
| 260 | /* RM_RSTST_MDM specific bits */ | ||
| 261 | /* 2430 only */ | ||
| 262 | #define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) | ||
| 263 | #define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) | ||
| 264 | #define OMAP2430_MDM_SW_RST1_MASK (1 << 4) | ||
| 265 | |||
| 266 | /* PM_WKEN_MDM */ | ||
| 267 | /* 2430 only */ | ||
| 268 | #define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) | ||
| 269 | |||
| 270 | /* PM_WKST_MDM specific bits */ | ||
| 271 | /* 2430 only */ | ||
| 272 | |||
| 273 | /* PM_WKDEP_MDM specific bits */ | ||
| 274 | /* 2430 only */ | ||
| 275 | |||
| 276 | /* PM_PWSTCTRL_MDM specific bits */ | ||
| 277 | /* 2430 only */ | ||
| 278 | #define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) | ||
| 279 | |||
| 280 | /* PM_PWSTST_MDM specific bits */ | ||
| 281 | /* 2430 only */ | ||
| 282 | |||
| 283 | /* PRCM_IRQSTATUS_IVA */ | ||
| 284 | /* 2420 only */ | ||
| 285 | |||
| 286 | /* PRCM_IRQENABLE_IVA */ | ||
| 287 | /* 2420 only */ | ||
| 288 | |||
| 289 | #endif | 42 | #endif |