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-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h247
1 files changed, 0 insertions, 247 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 91aa5106d637..37fc905c9636 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -16,274 +16,27 @@
16 16
17#include "prm2xxx.h" 17#include "prm2xxx.h"
18 18
19/* Bits shared between registers */
20
21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
23#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
24#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
25
26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
28#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
29#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU_SHIFT 1
33#define OMAP24XX_EN_MPU_MASK (1 << 1)
34#define OMAP24XX_EN_CORE_SHIFT 0 19#define OMAP24XX_EN_CORE_SHIFT 0
35#define OMAP24XX_EN_CORE_MASK (1 << 0)
36
37/*
38 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
39 * shared bits
40 */
41#define OMAP24XX_MEMONSTATE_SHIFT 10
42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
43#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
44
45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
46#define OMAP24XX_FORCESTATE_MASK (1 << 18) 20#define OMAP24XX_FORCESTATE_MASK (1 << 18)
47
48/*
49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
50 * PM_PWSTST_MDM shared bits
51 */
52#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
53
54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
56#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
57
58/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
59#define OMAP2430_MEMSTATEST_SHIFT 10
60#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
61
62/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
63#define OMAP24XX_POWERSTATEST_SHIFT 0
64#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
65
66
67/* Bits specific to each register */
68
69/* PRCM_REVISION */
70#define OMAP24XX_REV_SHIFT 0
71#define OMAP24XX_REV_MASK (0xff << 0)
72
73/* PRCM_SYSCONFIG */
74#define OMAP24XX_AUTOIDLE_MASK (1 << 0) 21#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
75
76/* PRCM_IRQSTATUS_MPU specific bits */
77#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
78#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
79#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
80#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
81
82/* PRCM_IRQENABLE_MPU specific bits */
83#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
84#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
85#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
86#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
87
88/* PRCM_VOLTCTRL */
89#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) 22#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
90#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 23#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
93#define OMAP24XX_MEMRETCTRL_MASK (1 << 8) 24#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
94#define OMAP24XX_SETRET_LEVEL_SHIFT 6 25#define OMAP24XX_SETRET_LEVEL_SHIFT 6
95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
96#define OMAP24XX_VOLT_LEVEL_SHIFT 0 26#define OMAP24XX_VOLT_LEVEL_SHIFT 0
97#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
98
99/* PRCM_VOLTST */
100#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
101#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
102
103/* PRCM_CLKSRC_CTRL specific bits */
104
105/* PRCM_CLKOUT_CTRL */
106#define OMAP2420_CLKOUT2_EN_SHIFT 15 27#define OMAP2420_CLKOUT2_EN_SHIFT 15
107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 28#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110#define OMAP2420_CLKOUT2_DIV_WIDTH 3 29#define OMAP2420_CLKOUT2_DIV_WIDTH 3
111#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
112#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 30#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
113#define OMAP24XX_CLKOUT_EN_SHIFT 7 31#define OMAP24XX_CLKOUT_EN_SHIFT 7
114#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
115#define OMAP24XX_CLKOUT_DIV_SHIFT 3 32#define OMAP24XX_CLKOUT_DIV_SHIFT 3
116#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
117#define OMAP24XX_CLKOUT_DIV_WIDTH 3 33#define OMAP24XX_CLKOUT_DIV_WIDTH 3
118#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
119#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) 34#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
120
121/* PRCM_CLKEMUL_CTRL */
122#define OMAP24XX_EMULATION_EN_SHIFT 0 35#define OMAP24XX_EMULATION_EN_SHIFT 0
123#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
124
125/* PRCM_CLKCFG_CTRL */
126#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
127
128/* PRCM_CLKCFG_STATUS */
129#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
130
131/* PRCM_VOLTSETUP specific bits */
132
133/* PRCM_CLKSSETUP specific bits */
134
135/* PRCM_POLCTRL */
136#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
137#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
138#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
139#define OMAP2430_USE_POWEROK_MASK (1 << 2)
140#define OMAP2430_POWEROK_POL_MASK (1 << 1)
141#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
142
143/* RM_RSTST_MPU specific bits */
144/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
145
146/* PM_WKDEP_MPU specific bits */
147#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 36#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
148#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
149#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 37#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
150#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
151
152/* PM_EVGENCTRL_MPU specific bits */
153
154/* PM_EVEGENONTIM_MPU specific bits */
155
156/* PM_EVEGENOFFTIM_MPU specific bits */
157
158/* PM_PWSTCTRL_MPU specific bits */
159#define OMAP2430_FORCESTATE_MASK (1 << 18)
160
161/* PM_PWSTST_MPU specific bits */
162/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
163
164/* PM_WKEN1_CORE specific bits */
165
166/* PM_WKEN2_CORE specific bits */
167
168/* PM_WKST1_CORE specific bits*/
169
170/* PM_WKST2_CORE specific bits */
171
172/* PM_WKDEP_CORE specific bits*/
173#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
174#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
175#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
176
177/* PM_PWSTCTRL_CORE specific bits */
178#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
179#define OMAP24XX_MEM3ONSTATE_SHIFT 14
180#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
181#define OMAP24XX_MEM2ONSTATE_SHIFT 12
182#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
183#define OMAP24XX_MEM1ONSTATE_SHIFT 10
184#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
185#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
186#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
187#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
188
189/* PM_PWSTST_CORE specific bits */
190#define OMAP24XX_MEM3STATEST_SHIFT 14
191#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
192#define OMAP24XX_MEM2STATEST_SHIFT 12
193#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
194#define OMAP24XX_MEM1STATEST_SHIFT 10
195#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
196
197/* RM_RSTCTRL_GFX */
198#define OMAP24XX_GFX_RST_MASK (1 << 0)
199
200/* RM_RSTST_GFX specific bits */
201#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
202
203/* PM_PWSTCTRL_GFX specific bits */
204
205/* PM_WKDEP_GFX specific bits */
206/* 2430 often calls EN_WAKEUP "EN_WKUP" */
207
208/* RM_RSTCTRL_WKUP specific bits */
209
210/* RM_RSTTIME_WKUP specific bits */
211
212/* RM_RSTST_WKUP specific bits */
213/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
214#define OMAP24XX_EXTWMPU_RST_SHIFT 6 38#define OMAP24XX_EXTWMPU_RST_SHIFT 6
215#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
216#define OMAP24XX_SECU_WD_RST_SHIFT 5 39#define OMAP24XX_SECU_WD_RST_SHIFT 5
217#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
218#define OMAP24XX_MPU_WD_RST_SHIFT 4 40#define OMAP24XX_MPU_WD_RST_SHIFT 4
219#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
220#define OMAP24XX_SECU_VIOL_RST_SHIFT 3 41#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
221#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
222
223/* PM_WKEN_WKUP specific bits */
224
225/* PM_WKST_WKUP specific bits */
226
227/* RM_RSTCTRL_DSP */
228#define OMAP2420_RST_IVA_MASK (1 << 8)
229#define OMAP24XX_RST2_DSP_MASK (1 << 1)
230#define OMAP24XX_RST1_DSP_MASK (1 << 0)
231
232/* RM_RSTST_DSP specific bits */
233/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
234#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
235#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
236#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
237
238/* PM_WKDEP_DSP specific bits */
239
240/* PM_PWSTCTRL_DSP specific bits */
241/* 2430 only: MEMONSTATE, MEMRETSTATE */
242#define OMAP2420_MEMIONSTATE_SHIFT 12
243#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
244#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
245
246/* PM_PWSTST_DSP specific bits */
247/* MEMSTATEST is 2430 only */
248#define OMAP2420_MEMISTATEST_SHIFT 12
249#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
250
251/* PRCM_IRQSTATUS_DSP specific bits */
252
253/* PRCM_IRQENABLE_DSP specific bits */
254
255/* RM_RSTCTRL_MDM */
256/* 2430 only */
257#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
258#define OMAP2430_RST1_MDM_MASK (1 << 0)
259
260/* RM_RSTST_MDM specific bits */
261/* 2430 only */
262#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
263#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
264#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
265
266/* PM_WKEN_MDM */
267/* 2430 only */
268#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
269
270/* PM_WKST_MDM specific bits */
271/* 2430 only */
272
273/* PM_WKDEP_MDM specific bits */
274/* 2430 only */
275
276/* PM_PWSTCTRL_MDM specific bits */
277/* 2430 only */
278#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
279
280/* PM_PWSTST_MDM specific bits */
281/* 2430 only */
282
283/* PRCM_IRQSTATUS_IVA */
284/* 2420 only */
285
286/* PRCM_IRQENABLE_IVA */
287/* 2420 only */
288
289#endif 42#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 22:41:02 -0500