diff options
| author | Rajendra Nayak <rnayak@ti.com> | 2013-07-21 23:14:00 -0400 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2013-07-22 00:10:14 -0400 |
| commit | 7a2025a723046b4a9da40fbb93c605cfa4ed67ce (patch) | |
| tree | a646725599847997491bc5f6d0e26a5b10402833 /arch | |
| parent | 7be914f2a333a4d74cf1ae0abdb162bff350be6c (diff) | |
ARM: OMAP4: PRM/CM: Cleanup unused header
Cleanup unused parts of the PRM and CM regbit headers leaving only whats
used.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-44xx.h | 1558 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-44xx.h | 2226 |
2 files changed, 0 insertions, 3784 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 4c6c2f7de65b..4dbbd99b6e1e 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h | |||
| @@ -22,1683 +22,125 @@ | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H |
| 24 | 24 | ||
| 25 | /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
| 26 | #define OMAP4430_ABE_DYNDEP_SHIFT 3 | ||
| 27 | #define OMAP4430_ABE_DYNDEP_WIDTH 0x1 | ||
| 28 | #define OMAP4430_ABE_DYNDEP_MASK (1 << 3) | ||
| 29 | |||
| 30 | /* | ||
| 31 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
| 32 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 33 | */ | ||
| 34 | #define OMAP4430_ABE_STATDEP_SHIFT 3 | 25 | #define OMAP4430_ABE_STATDEP_SHIFT 3 |
| 35 | #define OMAP4430_ABE_STATDEP_WIDTH 0x1 | ||
| 36 | #define OMAP4430_ABE_STATDEP_MASK (1 << 3) | ||
| 37 | |||
| 38 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 39 | #define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 | ||
| 40 | #define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 | ||
| 41 | #define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) | ||
| 42 | |||
| 43 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
| 44 | #define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 | ||
| 45 | #define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 | ||
| 46 | #define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) | ||
| 47 | |||
| 48 | /* | ||
| 49 | * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, | ||
| 50 | * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, | ||
| 51 | * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB | ||
| 52 | */ | ||
| 53 | #define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 | ||
| 54 | #define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 | ||
| 55 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) | 26 | #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) |
| 56 | |||
| 57 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 58 | #define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 | ||
| 59 | #define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 | ||
| 60 | #define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) | ||
| 61 | |||
| 62 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ | ||
| 63 | #define OMAP4430_CEFUSE_STATDEP_SHIFT 17 | ||
| 64 | #define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 | ||
| 65 | #define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) | ||
| 66 | |||
| 67 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 68 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 | ||
| 69 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 | ||
| 70 | #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) | ||
| 71 | |||
| 72 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 73 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 | ||
| 74 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 | ||
| 75 | #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) | ||
| 76 | |||
| 77 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 78 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 | ||
| 79 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 | ||
| 80 | #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) | ||
| 81 | |||
| 82 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 83 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 | ||
| 84 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 | ||
| 85 | #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) | ||
| 86 | |||
| 87 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 88 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 | ||
| 89 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 | ||
| 90 | #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) | ||
| 91 | |||
| 92 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 93 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 | ||
| 94 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 | ||
| 95 | #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) | ||
| 96 | |||
| 97 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 98 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 | ||
| 99 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 | ||
| 100 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) | ||
| 101 | |||
| 102 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 103 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 | ||
| 104 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 | ||
| 105 | #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) | ||
| 106 | |||
| 107 | /* Used by CM_CAM_CLKSTCTRL */ | ||
| 108 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 | ||
| 109 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 | ||
| 110 | #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) | ||
| 111 | |||
| 112 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
| 113 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 | ||
| 114 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 | ||
| 115 | #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) | ||
| 116 | |||
| 117 | /* Used by CM_EMU_CLKSTCTRL */ | ||
| 118 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 | ||
| 119 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 | ||
| 120 | #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) | ||
| 121 | |||
| 122 | /* Used by CM_L4CFG_CLKSTCTRL */ | ||
| 123 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 | ||
| 124 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 | ||
| 125 | #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) | ||
| 126 | |||
| 127 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 128 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
| 129 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 | ||
| 130 | #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
| 131 | |||
| 132 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 133 | #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 | ||
| 134 | #define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 | ||
| 135 | #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) | ||
| 136 | |||
| 137 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 138 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 | ||
| 139 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 | ||
| 140 | #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) | ||
| 141 | |||
| 142 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 143 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 | ||
| 144 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 | ||
| 145 | #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) | ||
| 146 | |||
| 147 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 148 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 | ||
| 149 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 | ||
| 150 | #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) | ||
| 151 | |||
| 152 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 153 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 | ||
| 154 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 | ||
| 155 | #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) | ||
| 156 | |||
| 157 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 158 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 | ||
| 159 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 | ||
| 160 | #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) | ||
| 161 | |||
| 162 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 163 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 | ||
| 164 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 | ||
| 165 | #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) | ||
| 166 | |||
| 167 | /* Used by CM_DSS_CLKSTCTRL */ | ||
| 168 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 | ||
| 169 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 | ||
| 170 | #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) | ||
| 171 | |||
| 172 | /* Used by CM_DSS_CLKSTCTRL */ | ||
| 173 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 | ||
| 174 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 | ||
| 175 | #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) | ||
| 176 | |||
| 177 | /* Used by CM_DUCATI_CLKSTCTRL */ | ||
| 178 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 | ||
| 179 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 | ||
| 180 | #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) | ||
| 181 | |||
| 182 | /* Used by CM_EMU_CLKSTCTRL */ | ||
| 183 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 | ||
| 184 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 | ||
| 185 | #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) | ||
| 186 | |||
| 187 | /* Used by CM_CAM_CLKSTCTRL */ | ||
| 188 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 | ||
| 189 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 | ||
| 190 | #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) | ||
| 191 | |||
| 192 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 193 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 | ||
| 194 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 | ||
| 195 | #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) | ||
| 196 | |||
| 197 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 198 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 | ||
| 199 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 | ||
| 200 | #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) | ||
| 201 | |||
| 202 | /* Used by CM_DSS_CLKSTCTRL */ | ||
| 203 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 | ||
| 204 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 | ||
| 205 | #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) | ||
| 206 | |||
| 207 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 208 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 | ||
| 209 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 | ||
| 210 | #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) | ||
| 211 | |||
| 212 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 213 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 | ||
| 214 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 | ||
| 215 | #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) | ||
| 216 | |||
| 217 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 218 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 | ||
| 219 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 | ||
| 220 | #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) | ||
| 221 | |||
| 222 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 223 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 | ||
| 224 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 | ||
| 225 | #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) | ||
| 226 | |||
| 227 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 228 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 | ||
| 229 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 | ||
| 230 | #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) | ||
| 231 | |||
| 232 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 233 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 | ||
| 234 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 | ||
| 235 | #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) | ||
| 236 | |||
| 237 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 238 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 | ||
| 239 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 | ||
| 240 | #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) | ||
| 241 | |||
| 242 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 243 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 | ||
| 244 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 | ||
| 245 | #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) | ||
| 246 | |||
| 247 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 248 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 | ||
| 249 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 | ||
| 250 | #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) | ||
| 251 | |||
| 252 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 253 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 | ||
| 254 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 | ||
| 255 | #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) | ||
| 256 | |||
| 257 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 258 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 | ||
| 259 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 | ||
| 260 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) | ||
| 261 | |||
| 262 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 263 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 | ||
| 264 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 | ||
| 265 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) | ||
| 266 | |||
| 267 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 268 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 | ||
| 269 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 | ||
| 270 | #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) | ||
| 271 | |||
| 272 | /* Used by CM_CAM_CLKSTCTRL */ | ||
| 273 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 | ||
| 274 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 | ||
| 275 | #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) | ||
| 276 | |||
| 277 | /* Used by CM_IVAHD_CLKSTCTRL */ | ||
| 278 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 | ||
| 279 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 | ||
| 280 | #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) | ||
| 281 | |||
| 282 | /* Used by CM_D2D_CLKSTCTRL */ | ||
| 283 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 | ||
| 284 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 | ||
| 285 | #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) | ||
| 286 | |||
| 287 | /* Used by CM_L3_1_CLKSTCTRL */ | ||
| 288 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 | ||
| 289 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 | ||
| 290 | #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) | ||
| 291 | |||
| 292 | /* Used by CM_L3_2_CLKSTCTRL */ | ||
| 293 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 | ||
| 294 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 | ||
| 295 | #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) | ||
| 296 | |||
| 297 | /* Used by CM_D2D_CLKSTCTRL */ | ||
| 298 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 | ||
| 299 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 | ||
| 300 | #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) | ||
| 301 | |||
| 302 | /* Used by CM_SDMA_CLKSTCTRL */ | ||
| 303 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 | ||
| 304 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 | ||
| 305 | #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) | ||
| 306 | |||
| 307 | /* Used by CM_DSS_CLKSTCTRL */ | ||
| 308 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 | ||
| 309 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 | ||
| 310 | #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) | ||
| 311 | |||
| 312 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 313 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 | ||
| 314 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 | ||
| 315 | #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) | ||
| 316 | |||
| 317 | /* Used by CM_GFX_CLKSTCTRL */ | ||
| 318 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 | ||
| 319 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 | ||
| 320 | #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) | ||
| 321 | |||
| 322 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 323 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 | ||
| 324 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 | ||
| 325 | #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) | ||
| 326 | |||
| 327 | /* Used by CM_L3INSTR_CLKSTCTRL */ | ||
| 328 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 | ||
| 329 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 | ||
| 330 | #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) | ||
| 331 | |||
| 332 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
| 333 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 | ||
| 334 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 | ||
| 335 | #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) | ||
| 336 | |||
| 337 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
| 338 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 | ||
| 339 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 | ||
| 340 | #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) | ||
| 341 | |||
| 342 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
| 343 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
| 344 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 | ||
| 345 | #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
| 346 | |||
| 347 | /* Used by CM_L4CFG_CLKSTCTRL */ | ||
| 348 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 | ||
| 349 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 | ||
| 350 | #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) | ||
| 351 | |||
| 352 | /* Used by CM_D2D_CLKSTCTRL */ | ||
| 353 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 | ||
| 354 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 | ||
| 355 | #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) | ||
| 356 | |||
| 357 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 358 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 | ||
| 359 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 | ||
| 360 | #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) | ||
| 361 | |||
| 362 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 363 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 | ||
| 364 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 | ||
| 365 | #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) | ||
| 366 | |||
| 367 | /* Used by CM_L4SEC_CLKSTCTRL */ | ||
| 368 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 | ||
| 369 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 | ||
| 370 | #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) | ||
| 371 | |||
| 372 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 373 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 | ||
| 374 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 | ||
| 375 | #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) | ||
| 376 | |||
| 377 | /* Used by CM_MPU_CLKSTCTRL */ | ||
| 378 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 | ||
| 379 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 | ||
| 380 | #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) | ||
| 381 | |||
| 382 | /* Used by CM1_ABE_CLKSTCTRL */ | ||
| 383 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 | ||
| 384 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 | ||
| 385 | #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) | ||
| 386 | |||
| 387 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 388 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 | ||
| 389 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 | ||
| 390 | #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) | ||
| 391 | |||
| 392 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 393 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 | ||
| 394 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 | ||
| 395 | #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) | ||
| 396 | |||
| 397 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 398 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 | ||
| 399 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 | ||
| 400 | #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) | ||
| 401 | |||
| 402 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 403 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 | ||
| 404 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 | ||
| 405 | #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) | ||
| 406 | |||
| 407 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 408 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 | ||
| 409 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 | ||
| 410 | #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) | ||
| 411 | |||
| 412 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 413 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 | ||
| 414 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 | ||
| 415 | #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) | ||
| 416 | |||
| 417 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 418 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 | ||
| 419 | #define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) | ||
| 420 | |||
| 421 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 422 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 | ||
| 423 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 | ||
| 424 | #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) | ||
| 425 | |||
| 426 | /* Used by CM_L4PER_CLKSTCTRL */ | ||
| 427 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 | ||
| 428 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 | ||
| 429 | #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) | ||
| 430 | |||
| 431 | /* Used by CM_MEMIF_CLKSTCTRL */ | ||
| 432 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 | ||
| 433 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 | ||
| 434 | #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) | ||
| 435 | |||
| 436 | /* Used by CM_GFX_CLKSTCTRL */ | ||
| 437 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 | ||
| 438 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 | ||
| 439 | #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) | ||
| 440 | |||
| 441 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
| 442 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 | ||
| 443 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 | ||
| 444 | #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) | ||
| 445 | |||
| 446 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
| 447 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 | ||
| 448 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 | ||
| 449 | #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) | ||
| 450 | |||
| 451 | /* Used by CM_ALWON_CLKSTCTRL */ | ||
| 452 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 | ||
| 453 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 | ||
| 454 | #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) | ||
| 455 | |||
| 456 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 457 | #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 | ||
| 458 | #define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 | ||
| 459 | #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) | ||
| 460 | |||
| 461 | /* Used by CM_TESLA_CLKSTCTRL */ | ||
| 462 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 | ||
| 463 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 | ||
| 464 | #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) | ||
| 465 | |||
| 466 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 467 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 | ||
| 468 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 | ||
| 469 | #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) | ||
| 470 | |||
| 471 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 472 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 | ||
| 473 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 | ||
| 474 | #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) | ||
| 475 | |||
| 476 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 477 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 | ||
| 478 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 | ||
| 479 | #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) | ||
| 480 | |||
| 481 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 482 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 | ||
| 483 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 | ||
| 484 | #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) | ||
| 485 | |||
| 486 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 487 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 | ||
| 488 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 | ||
| 489 | #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) | ||
| 490 | |||
| 491 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 492 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 | ||
| 493 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 | ||
| 494 | #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) | ||
| 495 | |||
| 496 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 497 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 | ||
| 498 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 | ||
| 499 | #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) | ||
| 500 | |||
| 501 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 502 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 | ||
| 503 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 | ||
| 504 | #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) | ||
| 505 | |||
| 506 | /* Used by CM_L3INIT_CLKSTCTRL */ | ||
| 507 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 | ||
| 508 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 | ||
| 509 | #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) | ||
| 510 | |||
| 511 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 512 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 | ||
| 513 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 | ||
| 514 | #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) | ||
| 515 | |||
| 516 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
| 517 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 | ||
| 518 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 | ||
| 519 | #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) | ||
| 520 | |||
| 521 | /* | ||
| 522 | * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, | ||
| 523 | * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
| 524 | * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, | ||
| 525 | * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, | ||
| 526 | * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, | ||
| 527 | * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL | ||
| 528 | */ | ||
| 529 | #define OMAP4430_CLKSEL_SHIFT 24 | 27 | #define OMAP4430_CLKSEL_SHIFT 24 |
| 530 | #define OMAP4430_CLKSEL_WIDTH 0x1 | 28 | #define OMAP4430_CLKSEL_WIDTH 0x1 |
| 531 | #define OMAP4430_CLKSEL_MASK (1 << 24) | 29 | #define OMAP4430_CLKSEL_MASK (1 << 24) |
| 532 | |||
| 533 | /* | ||
| 534 | * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, | ||
| 535 | * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL | ||
| 536 | */ | ||
| 537 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 | 30 | #define OMAP4430_CLKSEL_0_0_SHIFT 0 |
| 538 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 | 31 | #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 |
| 539 | #define OMAP4430_CLKSEL_0_0_MASK (1 << 0) | ||
| 540 | |||
| 541 | /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ | ||
| 542 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 | 32 | #define OMAP4430_CLKSEL_0_1_SHIFT 0 |
| 543 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 | 33 | #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 |
| 544 | #define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) | ||
| 545 | |||
| 546 | /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ | ||
| 547 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 | 34 | #define OMAP4430_CLKSEL_24_25_SHIFT 24 |
| 548 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 | 35 | #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 |
| 549 | #define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) | ||
| 550 | |||
| 551 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
| 552 | #define OMAP4430_CLKSEL_60M_SHIFT 24 | 36 | #define OMAP4430_CLKSEL_60M_SHIFT 24 |
| 553 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 | 37 | #define OMAP4430_CLKSEL_60M_WIDTH 0x1 |
| 554 | #define OMAP4430_CLKSEL_60M_MASK (1 << 24) | ||
| 555 | |||
| 556 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
| 557 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 | ||
| 558 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 | ||
| 559 | #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) | ||
| 560 | |||
| 561 | /* Used by CM1_ABE_AESS_CLKCTRL */ | ||
| 562 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 | 38 | #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 |
| 563 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 | 39 | #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 |
| 564 | #define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) | ||
| 565 | |||
| 566 | /* Used by CM_CLKSEL_CORE */ | ||
| 567 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 | 40 | #define OMAP4430_CLKSEL_CORE_SHIFT 0 |
| 568 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 | 41 | #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 |
| 569 | #define OMAP4430_CLKSEL_CORE_MASK (1 << 0) | ||
| 570 | |||
| 571 | /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
| 572 | #define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 | ||
| 573 | #define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 | ||
| 574 | #define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) | ||
| 575 | |||
| 576 | /* Used by CM_WKUP_USIM_CLKCTRL */ | ||
| 577 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 | 42 | #define OMAP4430_CLKSEL_DIV_SHIFT 24 |
| 578 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 | 43 | #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 |
| 579 | #define OMAP4430_CLKSEL_DIV_MASK (1 << 24) | ||
| 580 | |||
| 581 | /* Used by CM_MPU_MPU_CLKCTRL */ | ||
| 582 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 | ||
| 583 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 | ||
| 584 | #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) | ||
| 585 | |||
| 586 | /* Used by CM_CAM_FDIF_CLKCTRL */ | ||
| 587 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 | 44 | #define OMAP4430_CLKSEL_FCLK_SHIFT 24 |
| 588 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 | 45 | #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 |
| 589 | #define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) | ||
| 590 | |||
| 591 | /* Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
| 592 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 | 46 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 |
| 593 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 | 47 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 |
| 594 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) | ||
| 595 | |||
| 596 | /* | ||
| 597 | * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, | ||
| 598 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
| 599 | * CM1_ABE_MCBSP3_CLKCTRL | ||
| 600 | */ | ||
| 601 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 | ||
| 602 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 | ||
| 603 | #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) | ||
| 604 | |||
| 605 | /* Used by CM_CLKSEL_CORE */ | ||
| 606 | #define OMAP4430_CLKSEL_L3_SHIFT 4 | 48 | #define OMAP4430_CLKSEL_L3_SHIFT 4 |
| 607 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 | 49 | #define OMAP4430_CLKSEL_L3_WIDTH 0x1 |
| 608 | #define OMAP4430_CLKSEL_L3_MASK (1 << 4) | ||
| 609 | |||
| 610 | /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
| 611 | #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 | ||
| 612 | #define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 | ||
| 613 | #define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) | ||
| 614 | |||
| 615 | /* Used by CM_CLKSEL_CORE */ | ||
| 616 | #define OMAP4430_CLKSEL_L4_SHIFT 8 | 50 | #define OMAP4430_CLKSEL_L4_SHIFT 8 |
| 617 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 | 51 | #define OMAP4430_CLKSEL_L4_WIDTH 0x1 |
| 618 | #define OMAP4430_CLKSEL_L4_MASK (1 << 8) | ||
| 619 | |||
| 620 | /* Used by CM_CLKSEL_ABE */ | ||
| 621 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 | 52 | #define OMAP4430_CLKSEL_OPP_SHIFT 0 |
| 622 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 | 53 | #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 |
| 623 | #define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) | ||
| 624 | |||
| 625 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
| 626 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 | 54 | #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 |
| 627 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 | 55 | #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 |
| 628 | #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) | ||
| 629 | |||
| 630 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
| 631 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 | ||
| 632 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 | ||
| 633 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) | 56 | #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) |
| 634 | |||
| 635 | /* Used by CM_GFX_GFX_CLKCTRL */ | ||
| 636 | #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 | ||
| 637 | #define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 | ||
| 638 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) | 57 | #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) |
| 639 | |||
| 640 | /* | ||
| 641 | * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, | ||
| 642 | * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL | ||
| 643 | */ | ||
| 644 | #define OMAP4430_CLKSEL_SOURCE_SHIFT 24 | ||
| 645 | #define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 | ||
| 646 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) | 58 | #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) |
| 647 | |||
| 648 | /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ | ||
| 649 | #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 | ||
| 650 | #define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 | ||
| 651 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) | 59 | #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) |
| 652 | |||
| 653 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 654 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 | 60 | #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 |
| 655 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 | 61 | #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 |
| 656 | #define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) | ||
| 657 | |||
| 658 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 659 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 | 62 | #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 |
| 660 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 | 63 | #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 |
| 661 | #define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) | ||
| 662 | |||
| 663 | /* | ||
| 664 | * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, | ||
| 665 | * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, | ||
| 666 | * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, | ||
| 667 | * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, | ||
| 668 | * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, | ||
| 669 | * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, | ||
| 670 | * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL | ||
| 671 | */ | ||
| 672 | #define OMAP4430_CLKTRCTRL_SHIFT 0 | 64 | #define OMAP4430_CLKTRCTRL_SHIFT 0 |
| 673 | #define OMAP4430_CLKTRCTRL_WIDTH 0x2 | ||
| 674 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) | 65 | #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) |
| 675 | |||
| 676 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
| 677 | #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 | ||
| 678 | #define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 | ||
| 679 | #define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) | ||
| 680 | |||
| 681 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
| 682 | #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 | ||
| 683 | #define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb | ||
| 684 | #define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) | ||
| 685 | |||
| 686 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 687 | #define OMAP4430_CUSTOM_SHIFT 6 | ||
| 688 | #define OMAP4430_CUSTOM_WIDTH 0x2 | ||
| 689 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | ||
| 690 | |||
| 691 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
| 692 | #define OMAP4430_D2D_DYNDEP_SHIFT 18 | ||
| 693 | #define OMAP4430_D2D_DYNDEP_WIDTH 0x1 | ||
| 694 | #define OMAP4430_D2D_DYNDEP_MASK (1 << 18) | ||
| 695 | |||
| 696 | /* Used by CM_MPU_STATICDEP */ | ||
| 697 | #define OMAP4430_D2D_STATDEP_SHIFT 18 | ||
| 698 | #define OMAP4430_D2D_STATDEP_WIDTH 0x1 | ||
| 699 | #define OMAP4430_D2D_STATDEP_MASK (1 << 18) | ||
| 700 | |||
| 701 | /* Used by CM_CLKSEL_DPLL_MPU */ | ||
| 702 | #define OMAP4460_DCC_COUNT_MAX_SHIFT 24 | ||
| 703 | #define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 | ||
| 704 | #define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) | ||
| 705 | |||
| 706 | /* Used by CM_CLKSEL_DPLL_MPU */ | ||
| 707 | #define OMAP4460_DCC_EN_SHIFT 22 | ||
| 708 | #define OMAP4460_DCC_EN_MASK (1 << 22) | ||
| 709 | |||
| 710 | /* | ||
| 711 | * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, | ||
| 712 | * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, | ||
| 713 | * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, | ||
| 714 | * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB | ||
| 715 | */ | ||
| 716 | #define OMAP4430_DELTAMSTEP_SHIFT 0 | ||
| 717 | #define OMAP4430_DELTAMSTEP_WIDTH 0x14 | ||
| 718 | #define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) | ||
| 719 | |||
| 720 | /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ | ||
| 721 | #define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 | ||
| 722 | #define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 | ||
| 723 | #define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) | ||
| 724 | |||
| 725 | /* Used by CM_DLL_CTRL */ | ||
| 726 | #define OMAP4430_DLL_OVERRIDE_SHIFT 0 | ||
| 727 | #define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 | ||
| 728 | #define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) | ||
| 729 | |||
| 730 | /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
| 731 | #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 | ||
| 732 | #define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 | ||
| 733 | #define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) | ||
| 734 | |||
| 735 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
| 736 | #define OMAP4430_DLL_RESET_SHIFT 3 | ||
| 737 | #define OMAP4430_DLL_RESET_WIDTH 0x1 | ||
| 738 | #define OMAP4430_DLL_RESET_MASK (1 << 3) | ||
| 739 | |||
| 740 | /* | ||
| 741 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
| 742 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
| 743 | * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB | ||
| 744 | */ | ||
| 745 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 | 66 | #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 |
| 746 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 | 67 | #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 |
| 747 | #define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
| 748 | |||
| 749 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
| 750 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
| 751 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 | ||
| 752 | #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
| 753 | |||
| 754 | /* Used by CM_CLKSEL_DPLL_CORE */ | ||
| 755 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 | ||
| 756 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 | ||
| 757 | #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) | ||
| 758 | |||
| 759 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
| 760 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 | ||
| 761 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 | ||
| 762 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) | 68 | #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) |
| 763 | |||
| 764 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
| 765 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 | ||
| 766 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 | ||
| 767 | #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) | ||
| 768 | |||
| 769 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
| 770 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 | 69 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 |
| 771 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 | ||
| 772 | #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) | ||
| 773 | |||
| 774 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ | ||
| 775 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 | ||
| 776 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 | ||
| 777 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) | 70 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) |
| 778 | |||
| 779 | /* | ||
| 780 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
| 781 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | ||
| 782 | */ | ||
| 783 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 | 71 | #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 |
| 784 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 | 72 | #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 |
| 785 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | 73 | #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) |
| 786 | |||
| 787 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ | ||
| 788 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
| 789 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 | ||
| 790 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) | 74 | #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) |
| 791 | |||
| 792 | /* | ||
| 793 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
| 794 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO | ||
| 795 | */ | ||
| 796 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
| 797 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 | ||
| 798 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
| 799 | |||
| 800 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ | ||
| 801 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 | ||
| 802 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 | ||
| 803 | #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) | ||
| 804 | |||
| 805 | /* | ||
| 806 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
| 807 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | ||
| 808 | */ | ||
| 809 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
| 810 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 | ||
| 811 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | 75 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) |
| 812 | |||
| 813 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
| 814 | #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 | ||
| 815 | #define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 | ||
| 816 | #define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) | ||
| 817 | |||
| 818 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
| 819 | #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 | ||
| 820 | #define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 | ||
| 821 | #define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) | ||
| 822 | |||
| 823 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
| 824 | #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 | ||
| 825 | #define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 | ||
| 826 | #define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) | ||
| 827 | |||
| 828 | /* | ||
| 829 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
| 830 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
| 831 | * CM_CLKSEL_DPLL_UNIPRO | ||
| 832 | */ | ||
| 833 | #define OMAP4430_DPLL_DIV_SHIFT 0 | ||
| 834 | #define OMAP4430_DPLL_DIV_WIDTH 0x7 | ||
| 835 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) | 76 | #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) |
| 836 | |||
| 837 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ | ||
| 838 | #define OMAP4430_DPLL_DIV_0_7_SHIFT 0 | ||
| 839 | #define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 | ||
| 840 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) | 77 | #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) |
| 841 | |||
| 842 | /* | ||
| 843 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 844 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
| 845 | */ | ||
| 846 | #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
| 847 | #define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 | ||
| 848 | #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
| 849 | |||
| 850 | /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ | ||
| 851 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 | ||
| 852 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 | ||
| 853 | #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) | ||
| 854 | |||
| 855 | /* | ||
| 856 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 857 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 858 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
| 859 | */ | ||
| 860 | #define OMAP4430_DPLL_EN_SHIFT 0 | ||
| 861 | #define OMAP4430_DPLL_EN_WIDTH 0x3 | ||
| 862 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) | 78 | #define OMAP4430_DPLL_EN_MASK (0x7 << 0) |
| 863 | |||
| 864 | /* | ||
| 865 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 866 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 867 | * CM_CLKMODE_DPLL_UNIPRO | ||
| 868 | */ | ||
| 869 | #define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 | ||
| 870 | #define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 | ||
| 871 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) | 79 | #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) |
| 872 | |||
| 873 | /* | ||
| 874 | * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, | ||
| 875 | * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, | ||
| 876 | * CM_CLKSEL_DPLL_UNIPRO | ||
| 877 | */ | ||
| 878 | #define OMAP4430_DPLL_MULT_SHIFT 8 | ||
| 879 | #define OMAP4430_DPLL_MULT_WIDTH 0xb | ||
| 880 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) | 80 | #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) |
| 881 | |||
| 882 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ | ||
| 883 | #define OMAP4430_DPLL_MULT_USB_SHIFT 8 | ||
| 884 | #define OMAP4430_DPLL_MULT_USB_WIDTH 0xc | ||
| 885 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) | 81 | #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) |
| 886 | |||
| 887 | /* | ||
| 888 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 889 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 890 | * CM_CLKMODE_DPLL_UNIPRO | ||
| 891 | */ | ||
| 892 | #define OMAP4430_DPLL_REGM4XEN_SHIFT 11 | ||
| 893 | #define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 | ||
| 894 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) | 82 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) |
| 895 | |||
| 896 | /* Used by CM_CLKSEL_DPLL_USB */ | ||
| 897 | #define OMAP4430_DPLL_SD_DIV_SHIFT 24 | ||
| 898 | #define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 | ||
| 899 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) | 83 | #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) |
| 900 | |||
| 901 | /* | ||
| 902 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 903 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 904 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
| 905 | */ | ||
| 906 | #define OMAP4430_DPLL_SSC_ACK_SHIFT 13 | ||
| 907 | #define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 | ||
| 908 | #define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) | ||
| 909 | |||
| 910 | /* | ||
| 911 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 912 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 913 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
| 914 | */ | ||
| 915 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
| 916 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 | ||
| 917 | #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
| 918 | |||
| 919 | /* | ||
| 920 | * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, | ||
| 921 | * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, | ||
| 922 | * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB | ||
| 923 | */ | ||
| 924 | #define OMAP4430_DPLL_SSC_EN_SHIFT 12 | ||
| 925 | #define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 | ||
| 926 | #define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) | ||
| 927 | |||
| 928 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
| 929 | #define OMAP4430_DSS_DYNDEP_SHIFT 8 | ||
| 930 | #define OMAP4430_DSS_DYNDEP_WIDTH 0x1 | ||
| 931 | #define OMAP4430_DSS_DYNDEP_MASK (1 << 8) | ||
| 932 | |||
| 933 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ | ||
| 934 | #define OMAP4430_DSS_STATDEP_SHIFT 8 | 84 | #define OMAP4430_DSS_STATDEP_SHIFT 8 |
| 935 | #define OMAP4430_DSS_STATDEP_WIDTH 0x1 | ||
| 936 | #define OMAP4430_DSS_STATDEP_MASK (1 << 8) | ||
| 937 | |||
| 938 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
| 939 | #define OMAP4430_DUCATI_DYNDEP_SHIFT 0 | ||
| 940 | #define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 | ||
| 941 | #define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) | ||
| 942 | |||
| 943 | /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ | ||
| 944 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 | 85 | #define OMAP4430_DUCATI_STATDEP_SHIFT 0 |
| 945 | #define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 | ||
| 946 | #define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) | ||
| 947 | |||
| 948 | /* Used by CM_SHADOW_FREQ_CONFIG1 */ | ||
| 949 | #define OMAP4430_FREQ_UPDATE_SHIFT 0 | ||
| 950 | #define OMAP4430_FREQ_UPDATE_WIDTH 0x1 | ||
| 951 | #define OMAP4430_FREQ_UPDATE_MASK (1 << 0) | ||
| 952 | |||
| 953 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 954 | #define OMAP4430_FUNC_SHIFT 16 | ||
| 955 | #define OMAP4430_FUNC_WIDTH 0xc | ||
| 956 | #define OMAP4430_FUNC_MASK (0xfff << 16) | ||
| 957 | |||
| 958 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
| 959 | #define OMAP4430_GFX_DYNDEP_SHIFT 10 | ||
| 960 | #define OMAP4430_GFX_DYNDEP_WIDTH 0x1 | ||
| 961 | #define OMAP4430_GFX_DYNDEP_MASK (1 << 10) | ||
| 962 | |||
| 963 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
| 964 | #define OMAP4430_GFX_STATDEP_SHIFT 10 | 86 | #define OMAP4430_GFX_STATDEP_SHIFT 10 |
| 965 | #define OMAP4430_GFX_STATDEP_WIDTH 0x1 | ||
| 966 | #define OMAP4430_GFX_STATDEP_MASK (1 << 10) | ||
| 967 | |||
| 968 | /* Used by CM_SHADOW_FREQ_CONFIG2 */ | ||
| 969 | #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 | ||
| 970 | #define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 | ||
| 971 | #define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) | ||
| 972 | |||
| 973 | /* | ||
| 974 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
| 975 | * CM_DIV_M4_DPLL_PER | ||
| 976 | */ | ||
| 977 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | ||
| 978 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 | ||
| 979 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | 87 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) |
| 980 | |||
| 981 | /* | ||
| 982 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
| 983 | * CM_DIV_M4_DPLL_PER | ||
| 984 | */ | ||
| 985 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
| 986 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 | ||
| 987 | #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
| 988 | |||
| 989 | /* | ||
| 990 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
| 991 | * CM_DIV_M4_DPLL_PER | ||
| 992 | */ | ||
| 993 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
| 994 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 | ||
| 995 | #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
| 996 | |||
| 997 | /* | ||
| 998 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
| 999 | * CM_DIV_M4_DPLL_PER | ||
| 1000 | */ | ||
| 1001 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
| 1002 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 | ||
| 1003 | #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
| 1004 | |||
| 1005 | /* | ||
| 1006 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
| 1007 | * CM_DIV_M5_DPLL_PER | ||
| 1008 | */ | ||
| 1009 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | ||
| 1010 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 | ||
| 1011 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | 88 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) |
| 1012 | |||
| 1013 | /* | ||
| 1014 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
| 1015 | * CM_DIV_M5_DPLL_PER | ||
| 1016 | */ | ||
| 1017 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
| 1018 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 | ||
| 1019 | #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
| 1020 | |||
| 1021 | /* | ||
| 1022 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
| 1023 | * CM_DIV_M5_DPLL_PER | ||
| 1024 | */ | ||
| 1025 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
| 1026 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 | ||
| 1027 | #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
| 1028 | |||
| 1029 | /* | ||
| 1030 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
| 1031 | * CM_DIV_M5_DPLL_PER | ||
| 1032 | */ | ||
| 1033 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
| 1034 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 | ||
| 1035 | #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
| 1036 | |||
| 1037 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
| 1038 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | ||
| 1039 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 | ||
| 1040 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) | 89 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) |
| 1041 | |||
| 1042 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
| 1043 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
| 1044 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 | ||
| 1045 | #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
| 1046 | |||
| 1047 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
| 1048 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
| 1049 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 | ||
| 1050 | #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
| 1051 | |||
| 1052 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
| 1053 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
| 1054 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 | ||
| 1055 | #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
| 1056 | |||
| 1057 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
| 1058 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 | ||
| 1059 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 | ||
| 1060 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) | 90 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) |
| 1061 | |||
| 1062 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
| 1063 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 | ||
| 1064 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 | ||
| 1065 | #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) | ||
| 1066 | |||
| 1067 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
| 1068 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 | ||
| 1069 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 | ||
| 1070 | #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) | ||
| 1071 | |||
| 1072 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
| 1073 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 | ||
| 1074 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 | ||
| 1075 | #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) | ||
| 1076 | |||
| 1077 | /* | ||
| 1078 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | ||
| 1079 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
| 1080 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | ||
| 1081 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | ||
| 1082 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, | ||
| 1083 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
| 1084 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | ||
| 1085 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | ||
| 1086 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
| 1087 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
| 1088 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
| 1089 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
| 1090 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
| 1091 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | ||
| 1092 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
| 1093 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
| 1094 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
| 1095 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
| 1096 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, | ||
| 1097 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | ||
| 1098 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | ||
| 1099 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, | ||
| 1100 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | ||
| 1101 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, | ||
| 1102 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | ||
| 1103 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
| 1104 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | ||
| 1105 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | ||
| 1106 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | ||
| 1107 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | ||
| 1108 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
| 1109 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, | ||
| 1110 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
| 1111 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, | ||
| 1112 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, | ||
| 1113 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, | ||
| 1114 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | ||
| 1115 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | ||
| 1116 | */ | ||
| 1117 | #define OMAP4430_IDLEST_SHIFT 16 | 91 | #define OMAP4430_IDLEST_SHIFT 16 |
| 1118 | #define OMAP4430_IDLEST_WIDTH 0x2 | ||
| 1119 | #define OMAP4430_IDLEST_MASK (0x3 << 16) | 92 | #define OMAP4430_IDLEST_MASK (0x3 << 16) |
| 1120 | |||
| 1121 | /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ | ||
| 1122 | #define OMAP4430_ISS_DYNDEP_SHIFT 9 | ||
| 1123 | #define OMAP4430_ISS_DYNDEP_WIDTH 0x1 | ||
| 1124 | #define OMAP4430_ISS_DYNDEP_MASK (1 << 9) | ||
| 1125 | |||
| 1126 | /* | ||
| 1127 | * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, | ||
| 1128 | * CM_TESLA_STATICDEP | ||
| 1129 | */ | ||
| 1130 | #define OMAP4430_ISS_STATDEP_SHIFT 9 | ||
| 1131 | #define OMAP4430_ISS_STATDEP_WIDTH 0x1 | ||
| 1132 | #define OMAP4430_ISS_STATDEP_MASK (1 << 9) | ||
| 1133 | |||
| 1134 | /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ | ||
| 1135 | #define OMAP4430_IVAHD_DYNDEP_SHIFT 2 | ||
| 1136 | #define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 | ||
| 1137 | #define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) | ||
| 1138 | |||
| 1139 | /* | ||
| 1140 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
| 1141 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, | ||
| 1142 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1143 | */ | ||
| 1144 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 | 93 | #define OMAP4430_IVAHD_STATDEP_SHIFT 2 |
| 1145 | #define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 | ||
| 1146 | #define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) | ||
| 1147 | |||
| 1148 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
| 1149 | #define OMAP4430_L3INIT_DYNDEP_SHIFT 7 | ||
| 1150 | #define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 | ||
| 1151 | #define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) | ||
| 1152 | |||
| 1153 | /* | ||
| 1154 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, | ||
| 1155 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1156 | */ | ||
| 1157 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 | 94 | #define OMAP4430_L3INIT_STATDEP_SHIFT 7 |
| 1158 | #define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 | ||
| 1159 | #define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) | ||
| 1160 | |||
| 1161 | /* | ||
| 1162 | * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, | ||
| 1163 | * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
| 1164 | */ | ||
| 1165 | #define OMAP4430_L3_1_DYNDEP_SHIFT 5 | ||
| 1166 | #define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 | ||
| 1167 | #define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) | ||
| 1168 | |||
| 1169 | /* | ||
| 1170 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
| 1171 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
| 1172 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
| 1173 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1174 | */ | ||
| 1175 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 | 95 | #define OMAP4430_L3_1_STATDEP_SHIFT 5 |
| 1176 | #define OMAP4430_L3_1_STATDEP_WIDTH 0x1 | ||
| 1177 | #define OMAP4430_L3_1_STATDEP_MASK (1 << 5) | ||
| 1178 | |||
| 1179 | /* | ||
| 1180 | * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, | ||
| 1181 | * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, | ||
| 1182 | * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
| 1183 | * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP | ||
| 1184 | */ | ||
| 1185 | #define OMAP4430_L3_2_DYNDEP_SHIFT 6 | ||
| 1186 | #define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 | ||
| 1187 | #define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) | ||
| 1188 | |||
| 1189 | /* | ||
| 1190 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
| 1191 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
| 1192 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
| 1193 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1194 | */ | ||
| 1195 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 | 96 | #define OMAP4430_L3_2_STATDEP_SHIFT 6 |
| 1196 | #define OMAP4430_L3_2_STATDEP_WIDTH 0x1 | ||
| 1197 | #define OMAP4430_L3_2_STATDEP_MASK (1 << 6) | ||
| 1198 | |||
| 1199 | /* Used by CM_L3_1_DYNAMICDEP */ | ||
| 1200 | #define OMAP4430_L4CFG_DYNDEP_SHIFT 12 | ||
| 1201 | #define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 | ||
| 1202 | #define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) | ||
| 1203 | |||
| 1204 | /* | ||
| 1205 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
| 1206 | * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1207 | */ | ||
| 1208 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 | 97 | #define OMAP4430_L4CFG_STATDEP_SHIFT 12 |
| 1209 | #define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 | ||
| 1210 | #define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) | ||
| 1211 | |||
| 1212 | /* Used by CM_L3_2_DYNAMICDEP */ | ||
| 1213 | #define OMAP4430_L4PER_DYNDEP_SHIFT 13 | ||
| 1214 | #define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 | ||
| 1215 | #define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) | ||
| 1216 | |||
| 1217 | /* | ||
| 1218 | * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, | ||
| 1219 | * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1220 | */ | ||
| 1221 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 | 98 | #define OMAP4430_L4PER_STATDEP_SHIFT 13 |
| 1222 | #define OMAP4430_L4PER_STATDEP_WIDTH 0x1 | ||
| 1223 | #define OMAP4430_L4PER_STATDEP_MASK (1 << 13) | ||
| 1224 | |||
| 1225 | /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ | ||
| 1226 | #define OMAP4430_L4SEC_DYNDEP_SHIFT 14 | ||
| 1227 | #define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 | ||
| 1228 | #define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) | ||
| 1229 | |||
| 1230 | /* | ||
| 1231 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, | ||
| 1232 | * CM_SDMA_STATICDEP | ||
| 1233 | */ | ||
| 1234 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 | 99 | #define OMAP4430_L4SEC_STATDEP_SHIFT 14 |
| 1235 | #define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 | ||
| 1236 | #define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) | ||
| 1237 | |||
| 1238 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 1239 | #define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 | ||
| 1240 | #define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 | ||
| 1241 | #define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) | ||
| 1242 | |||
| 1243 | /* | ||
| 1244 | * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, | ||
| 1245 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1246 | */ | ||
| 1247 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 | 100 | #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 |
| 1248 | #define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 | ||
| 1249 | #define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) | ||
| 1250 | |||
| 1251 | /* | ||
| 1252 | * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
| 1253 | * CM_MPU_DYNAMICDEP | ||
| 1254 | */ | ||
| 1255 | #define OMAP4430_MEMIF_DYNDEP_SHIFT 4 | ||
| 1256 | #define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 | ||
| 1257 | #define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) | ||
| 1258 | |||
| 1259 | /* | ||
| 1260 | * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, | ||
| 1261 | * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, | ||
| 1262 | * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, | ||
| 1263 | * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP | ||
| 1264 | */ | ||
| 1265 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 | 101 | #define OMAP4430_MEMIF_STATDEP_SHIFT 4 |
| 1266 | #define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 | ||
| 1267 | #define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) | ||
| 1268 | |||
| 1269 | /* | ||
| 1270 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
| 1271 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
| 1272 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | ||
| 1273 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | ||
| 1274 | */ | ||
| 1275 | #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 | ||
| 1276 | #define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 | ||
| 1277 | #define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) | ||
| 1278 | |||
| 1279 | /* | ||
| 1280 | * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, | ||
| 1281 | * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, | ||
| 1282 | * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, | ||
| 1283 | * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB | ||
| 1284 | */ | ||
| 1285 | #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 | ||
| 1286 | #define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 | ||
| 1287 | #define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) | ||
| 1288 | |||
| 1289 | /* | ||
| 1290 | * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, | ||
| 1291 | * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, | ||
| 1292 | * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, | ||
| 1293 | * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, | ||
| 1294 | * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, | ||
| 1295 | * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, | ||
| 1296 | * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, | ||
| 1297 | * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, | ||
| 1298 | * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
| 1299 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
| 1300 | * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, | ||
| 1301 | * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, | ||
| 1302 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
| 1303 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, | ||
| 1304 | * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, | ||
| 1305 | * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, | ||
| 1306 | * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, | ||
| 1307 | * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, | ||
| 1308 | * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, | ||
| 1309 | * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, | ||
| 1310 | * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, | ||
| 1311 | * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, | ||
| 1312 | * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, | ||
| 1313 | * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, | ||
| 1314 | * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, | ||
| 1315 | * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, | ||
| 1316 | * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, | ||
| 1317 | * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, | ||
| 1318 | * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, | ||
| 1319 | * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, | ||
| 1320 | * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, | ||
| 1321 | * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, | ||
| 1322 | * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, | ||
| 1323 | * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, | ||
| 1324 | * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, | ||
| 1325 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, | ||
| 1326 | * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, | ||
| 1327 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL | ||
| 1328 | */ | ||
| 1329 | #define OMAP4430_MODULEMODE_SHIFT 0 | 102 | #define OMAP4430_MODULEMODE_SHIFT 0 |
| 1330 | #define OMAP4430_MODULEMODE_WIDTH 0x2 | ||
| 1331 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) | 103 | #define OMAP4430_MODULEMODE_MASK (0x3 << 0) |
| 1332 | |||
| 1333 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 1334 | #define OMAP4460_MPU_DYNDEP_SHIFT 19 | ||
| 1335 | #define OMAP4460_MPU_DYNDEP_WIDTH 0x1 | ||
| 1336 | #define OMAP4460_MPU_DYNDEP_MASK (1 << 19) | ||
| 1337 | |||
| 1338 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
| 1339 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 | 104 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 |
| 1340 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 | ||
| 1341 | #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) | ||
| 1342 | |||
| 1343 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | ||
| 1344 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 | 105 | #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 |
| 1345 | #define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 | ||
| 1346 | #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) | ||
| 1347 | |||
| 1348 | /* Used by CM_ALWON_USBPHY_CLKCTRL */ | ||
| 1349 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 | 106 | #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 |
| 1350 | #define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 | ||
| 1351 | #define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) | ||
| 1352 | |||
| 1353 | /* Used by CM_CAM_ISS_CLKCTRL */ | ||
| 1354 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 | 107 | #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 |
| 1355 | #define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 | ||
| 1356 | #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) | ||
| 1357 | |||
| 1358 | /* | ||
| 1359 | * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, | ||
| 1360 | * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, | ||
| 1361 | * CM_WKUP_GPIO1_CLKCTRL | ||
| 1362 | */ | ||
| 1363 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 | 108 | #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 |
| 1364 | #define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 | ||
| 1365 | #define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) | ||
| 1366 | |||
| 1367 | /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ | ||
| 1368 | #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 | ||
| 1369 | #define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 | ||
| 1370 | #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) | ||
| 1371 | |||
| 1372 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
| 1373 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 | 109 | #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 |
| 1374 | #define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 | ||
| 1375 | #define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) | ||
| 1376 | |||
| 1377 | /* Used by CM_WKUP_USIM_CLKCTRL */ | ||
| 1378 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 | 110 | #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 |
| 1379 | #define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 | ||
| 1380 | #define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) | ||
| 1381 | |||
| 1382 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
| 1383 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 | 111 | #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 |
| 1384 | #define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 | ||
| 1385 | #define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) | ||
| 1386 | |||
| 1387 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
| 1388 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 | 112 | #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 |
| 1389 | #define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 | ||
| 1390 | #define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) | ||
| 1391 | |||
| 1392 | /* Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
| 1393 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 | 113 | #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 |
| 1394 | #define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 | ||
| 1395 | #define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) | ||
| 1396 | |||
| 1397 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1398 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 | 114 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 |
| 1399 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 | ||
| 1400 | #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) | ||
| 1401 | |||
| 1402 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1403 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 | 115 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 |
| 1404 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 | ||
| 1405 | #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) | ||
| 1406 | |||
| 1407 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1408 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 | 116 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 |
| 1409 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 | ||
| 1410 | #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) | ||
| 1411 | |||
| 1412 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1413 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 | 117 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 |
| 1414 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 | ||
| 1415 | #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) | ||
| 1416 | |||
| 1417 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1418 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 | 118 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 |
| 1419 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 | ||
| 1420 | #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) | ||
| 1421 | |||
| 1422 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
| 1423 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 | 119 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 |
| 1424 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 | ||
| 1425 | #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) | ||
| 1426 | |||
| 1427 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
| 1428 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 | 120 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 |
| 1429 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 | ||
| 1430 | #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) | ||
| 1431 | |||
| 1432 | /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ | ||
| 1433 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 | 121 | #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 |
| 1434 | #define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 | ||
| 1435 | #define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) | ||
| 1436 | |||
| 1437 | /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ | ||
| 1438 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 | 122 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 |
| 1439 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 | ||
| 1440 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) | ||
| 1441 | |||
| 1442 | /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ | ||
| 1443 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 | 123 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 |
| 1444 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 | ||
| 1445 | #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) | ||
| 1446 | |||
| 1447 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
| 1448 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 | 124 | #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 |
| 1449 | #define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 | ||
| 1450 | #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) | ||
| 1451 | |||
| 1452 | /* Used by CM_WKUP_BANDGAP_CLKCTRL */ | ||
| 1453 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 | 125 | #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 |
| 1454 | #define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 | ||
| 1455 | #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) | ||
| 1456 | |||
| 1457 | /* Used by CM_DSS_DSS_CLKCTRL */ | ||
| 1458 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 | 126 | #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 |
| 1459 | #define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 | ||
| 1460 | #define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) | ||
| 1461 | |||
| 1462 | /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ | ||
| 1463 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 | ||
| 1464 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 | ||
| 1465 | #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) | ||
| 1466 | |||
| 1467 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
| 1468 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 | 127 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 |
| 1469 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 | ||
| 1470 | #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) | ||
| 1471 | |||
| 1472 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
| 1473 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 | 128 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 |
| 1474 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 | ||
| 1475 | #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) | ||
| 1476 | |||
| 1477 | /* Used by CM_L3INIT_USB_TLL_CLKCTRL */ | ||
| 1478 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 | 129 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 |
| 1479 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 | ||
| 1480 | #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) | ||
| 1481 | |||
| 1482 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1483 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 | 130 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 |
| 1484 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 | ||
| 1485 | #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) | ||
| 1486 | |||
| 1487 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1488 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 | 131 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 |
| 1489 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 | ||
| 1490 | #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) | ||
| 1491 | |||
| 1492 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL */ | ||
| 1493 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 | 132 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 |
| 1494 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 | ||
| 1495 | #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) | ||
| 1496 | |||
| 1497 | /* Used by CM_L3INIT_USB_OTG_CLKCTRL */ | ||
| 1498 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 | 133 | #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 |
| 1499 | #define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 | ||
| 1500 | #define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) | ||
| 1501 | |||
| 1502 | /* Used by CM_EMU_OVERRIDE_DPLL_CORE */ | ||
| 1503 | #define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 | ||
| 1504 | #define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 | ||
| 1505 | #define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) | ||
| 1506 | |||
| 1507 | /* Used by CM_CLKSEL_ABE */ | ||
| 1508 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 | 134 | #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 |
| 1509 | #define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 | ||
| 1510 | #define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) | ||
| 1511 | |||
| 1512 | /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ | ||
| 1513 | #define OMAP4430_PERF_CURRENT_SHIFT 0 | ||
| 1514 | #define OMAP4430_PERF_CURRENT_WIDTH 0x8 | ||
| 1515 | #define OMAP4430_PERF_CURRENT_MASK (0xff << 0) | ||
| 1516 | |||
| 1517 | /* | ||
| 1518 | * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, | ||
| 1519 | * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, | ||
| 1520 | * CM_IVA_DVFS_PERF_TESLA | ||
| 1521 | */ | ||
| 1522 | #define OMAP4430_PERF_REQ_SHIFT 0 | ||
| 1523 | #define OMAP4430_PERF_REQ_WIDTH 0x8 | ||
| 1524 | #define OMAP4430_PERF_REQ_MASK (0xff << 0) | ||
| 1525 | |||
| 1526 | /* Used by CM_RESTORE_ST */ | ||
| 1527 | #define OMAP4430_PHASE1_COMPLETED_SHIFT 0 | ||
| 1528 | #define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 | ||
| 1529 | #define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) | ||
| 1530 | |||
| 1531 | /* Used by CM_RESTORE_ST */ | ||
| 1532 | #define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 | ||
| 1533 | #define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 | ||
| 1534 | #define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) | ||
| 1535 | |||
| 1536 | /* Used by CM_RESTORE_ST */ | ||
| 1537 | #define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 | ||
| 1538 | #define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 | ||
| 1539 | #define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) | ||
| 1540 | |||
| 1541 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
| 1542 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 | 135 | #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 |
| 1543 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 | 136 | #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 |
| 1544 | #define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) | ||
| 1545 | |||
| 1546 | /* Used by CM_EMU_DEBUGSS_CLKCTRL */ | ||
| 1547 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 | 137 | #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 |
| 1548 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 | 138 | #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 |
| 1549 | #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) | ||
| 1550 | |||
| 1551 | /* Used by CM_DYN_DEP_PRESCAL */ | ||
| 1552 | #define OMAP4430_PRESCAL_SHIFT 0 | ||
| 1553 | #define OMAP4430_PRESCAL_WIDTH 0x6 | ||
| 1554 | #define OMAP4430_PRESCAL_MASK (0x3f << 0) | ||
| 1555 | |||
| 1556 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 1557 | #define OMAP4430_R_RTL_SHIFT 11 | ||
| 1558 | #define OMAP4430_R_RTL_WIDTH 0x5 | ||
| 1559 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | ||
| 1560 | |||
| 1561 | /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ | ||
| 1562 | #define OMAP4430_SAR_MODE_SHIFT 4 | ||
| 1563 | #define OMAP4430_SAR_MODE_WIDTH 0x1 | ||
| 1564 | #define OMAP4430_SAR_MODE_MASK (1 << 4) | ||
| 1565 | |||
| 1566 | /* Used by CM_SCALE_FCLK */ | ||
| 1567 | #define OMAP4430_SCALE_FCLK_SHIFT 0 | 139 | #define OMAP4430_SCALE_FCLK_SHIFT 0 |
| 1568 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 | 140 | #define OMAP4430_SCALE_FCLK_WIDTH 0x1 |
| 1569 | #define OMAP4430_SCALE_FCLK_MASK (1 << 0) | ||
| 1570 | |||
| 1571 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 1572 | #define OMAP4430_SCHEME_SHIFT 30 | ||
| 1573 | #define OMAP4430_SCHEME_WIDTH 0x2 | ||
| 1574 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | ||
| 1575 | |||
| 1576 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 1577 | #define OMAP4430_SDMA_DYNDEP_SHIFT 11 | ||
| 1578 | #define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 | ||
| 1579 | #define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) | ||
| 1580 | |||
| 1581 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
| 1582 | #define OMAP4430_SDMA_STATDEP_SHIFT 11 | ||
| 1583 | #define OMAP4430_SDMA_STATDEP_WIDTH 0x1 | ||
| 1584 | #define OMAP4430_SDMA_STATDEP_MASK (1 << 11) | ||
| 1585 | |||
| 1586 | /* Used by CM_CLKSEL_ABE */ | ||
| 1587 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 | 141 | #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 |
| 1588 | #define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 | ||
| 1589 | #define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) | ||
| 1590 | |||
| 1591 | /* | ||
| 1592 | * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, | ||
| 1593 | * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, | ||
| 1594 | * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, | ||
| 1595 | * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, | ||
| 1596 | * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, | ||
| 1597 | * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, | ||
| 1598 | * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL | ||
| 1599 | */ | ||
| 1600 | #define OMAP4430_STBYST_SHIFT 18 | ||
| 1601 | #define OMAP4430_STBYST_WIDTH 0x1 | ||
| 1602 | #define OMAP4430_STBYST_MASK (1 << 18) | ||
| 1603 | |||
| 1604 | /* | ||
| 1605 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | ||
| 1606 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | ||
| 1607 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | ||
| 1608 | */ | ||
| 1609 | #define OMAP4430_ST_DPLL_CLK_SHIFT 0 | ||
| 1610 | #define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 | ||
| 1611 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) | 142 | #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) |
| 1612 | |||
| 1613 | /* Used by CM_CLKDCOLDO_DPLL_USB */ | ||
| 1614 | #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 | ||
| 1615 | #define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 | ||
| 1616 | #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) | ||
| 1617 | |||
| 1618 | /* | ||
| 1619 | * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, | ||
| 1620 | * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB | ||
| 1621 | */ | ||
| 1622 | #define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 | ||
| 1623 | #define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 | ||
| 1624 | #define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
| 1625 | |||
| 1626 | /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ | ||
| 1627 | #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 | ||
| 1628 | #define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 | ||
| 1629 | #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) | ||
| 1630 | |||
| 1631 | /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ | ||
| 1632 | #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 | ||
| 1633 | #define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 | ||
| 1634 | #define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) | ||
| 1635 | |||
| 1636 | /* | ||
| 1637 | * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, | ||
| 1638 | * CM_DIV_M4_DPLL_PER | ||
| 1639 | */ | ||
| 1640 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
| 1641 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 | ||
| 1642 | #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
| 1643 | |||
| 1644 | /* | ||
| 1645 | * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, | ||
| 1646 | * CM_DIV_M5_DPLL_PER | ||
| 1647 | */ | ||
| 1648 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
| 1649 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 | ||
| 1650 | #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
| 1651 | |||
| 1652 | /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ | ||
| 1653 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
| 1654 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 | ||
| 1655 | #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
| 1656 | |||
| 1657 | /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ | ||
| 1658 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 | ||
| 1659 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 | ||
| 1660 | #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) | ||
| 1661 | |||
| 1662 | /* | ||
| 1663 | * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, | ||
| 1664 | * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, | ||
| 1665 | * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB | ||
| 1666 | */ | ||
| 1667 | #define OMAP4430_ST_MN_BYPASS_SHIFT 8 | ||
| 1668 | #define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 | ||
| 1669 | #define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) | ||
| 1670 | |||
| 1671 | /* Used by CM_SYS_CLKSEL */ | ||
| 1672 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 | 143 | #define OMAP4430_SYS_CLKSEL_SHIFT 0 |
| 1673 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 | 144 | #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 |
| 1674 | #define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) | ||
| 1675 | |||
| 1676 | /* Used by CM_L4CFG_DYNAMICDEP */ | ||
| 1677 | #define OMAP4430_TESLA_DYNDEP_SHIFT 1 | ||
| 1678 | #define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 | ||
| 1679 | #define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) | ||
| 1680 | |||
| 1681 | /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ | ||
| 1682 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 | 145 | #define OMAP4430_TESLA_STATDEP_SHIFT 1 |
| 1683 | #define OMAP4430_TESLA_STATDEP_WIDTH 0x1 | ||
| 1684 | #define OMAP4430_TESLA_STATDEP_MASK (1 << 1) | ||
| 1685 | |||
| 1686 | /* | ||
| 1687 | * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, | ||
| 1688 | * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, | ||
| 1689 | * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP | ||
| 1690 | */ | ||
| 1691 | #define OMAP4430_WINDOWSIZE_SHIFT 24 | ||
| 1692 | #define OMAP4430_WINDOWSIZE_WIDTH 0x4 | ||
| 1693 | #define OMAP4430_WINDOWSIZE_MASK (0xf << 24) | ||
| 1694 | |||
| 1695 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 1696 | #define OMAP4430_X_MAJOR_SHIFT 8 | ||
| 1697 | #define OMAP4430_X_MAJOR_WIDTH 0x3 | ||
| 1698 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | ||
| 1699 | |||
| 1700 | /* Used by REVISION_CM1, REVISION_CM2 */ | ||
| 1701 | #define OMAP4430_Y_MINOR_SHIFT 0 | ||
| 1702 | #define OMAP4430_Y_MINOR_WIDTH 0x6 | ||
| 1703 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | ||
| 1704 | #endif | 146 | #endif |
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 3cb247bebdaa..b1c7a33e00e7 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h | |||
| @@ -22,2306 +22,80 @@ | |||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H |
| 24 | 24 | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 28 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 29 | */ | ||
| 30 | #define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
| 31 | #define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 35 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 36 | */ | ||
| 37 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
| 38 | #define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
| 39 | |||
| 40 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 41 | #define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 | ||
| 42 | #define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) | ||
| 43 | |||
| 44 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 45 | #define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 | ||
| 46 | #define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) | ||
| 47 | |||
| 48 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 49 | #define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 | ||
| 50 | #define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) | ||
| 51 | |||
| 52 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 53 | #define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 | ||
| 54 | #define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) | ||
| 55 | |||
| 56 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
| 57 | #define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 | ||
| 58 | #define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) | ||
| 59 | |||
| 60 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
| 61 | #define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 | ||
| 62 | #define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) | ||
| 63 | |||
| 64 | /* Used by PM_ABE_PWRSTCTRL */ | ||
| 65 | #define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 | ||
| 66 | #define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) | ||
| 67 | |||
| 68 | /* Used by PM_ABE_PWRSTCTRL */ | ||
| 69 | #define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 | ||
| 70 | #define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) | ||
| 71 | |||
| 72 | /* Used by PM_ABE_PWRSTST */ | ||
| 73 | #define OMAP4430_AESSMEM_STATEST_SHIFT 4 | ||
| 74 | #define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) | ||
| 75 | |||
| 76 | /* | ||
| 77 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 78 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 79 | */ | ||
| 80 | #define OMAP4430_AIPOFF_SHIFT 8 | ||
| 81 | #define OMAP4430_AIPOFF_MASK (1 << 8) | ||
| 82 | |||
| 83 | /* Used by PRM_VOLTCTRL */ | ||
| 84 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 | ||
| 85 | #define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) | ||
| 86 | |||
| 87 | /* Used by PRM_VOLTCTRL */ | ||
| 88 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 | ||
| 89 | #define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) | ||
| 90 | |||
| 91 | /* Used by PRM_VOLTCTRL */ | ||
| 92 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 | ||
| 93 | #define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) | ||
| 94 | |||
| 95 | /* Used by PRM_VC_ERRST */ | ||
| 96 | #define OMAP4430_BYPS_RA_ERR_SHIFT 25 | ||
| 97 | #define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) | ||
| 98 | |||
| 99 | /* Used by PRM_VC_ERRST */ | ||
| 100 | #define OMAP4430_BYPS_SA_ERR_SHIFT 24 | ||
| 101 | #define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) | ||
| 102 | |||
| 103 | /* Used by PRM_VC_ERRST */ | ||
| 104 | #define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 | ||
| 105 | #define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) | ||
| 106 | |||
| 107 | /* Used by PRM_RSTST */ | ||
| 108 | #define OMAP4430_C2C_RST_SHIFT 10 | 25 | #define OMAP4430_C2C_RST_SHIFT 10 |
| 109 | #define OMAP4430_C2C_RST_MASK (1 << 10) | ||
| 110 | |||
| 111 | /* Used by PM_CAM_PWRSTCTRL */ | ||
| 112 | #define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 | ||
| 113 | #define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) | ||
| 114 | |||
| 115 | /* Used by PM_CAM_PWRSTST */ | ||
| 116 | #define OMAP4430_CAM_MEM_STATEST_SHIFT 4 | ||
| 117 | #define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) | ||
| 118 | |||
| 119 | /* Used by PRM_CLKREQCTRL */ | ||
| 120 | #define OMAP4430_CLKREQ_COND_SHIFT 0 | ||
| 121 | #define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) | ||
| 122 | |||
| 123 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
| 124 | #define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 | ||
| 125 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) | 26 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
| 126 | |||
| 127 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
| 128 | #define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 | ||
| 129 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) | 27 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
| 130 | |||
| 131 | /* Used by PRM_VC_VAL_SMPS_RA_CMD */ | ||
| 132 | #define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 | ||
| 133 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) | 28 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
| 134 | |||
| 135 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 136 | #define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 | ||
| 137 | #define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) | ||
| 138 | |||
| 139 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 140 | #define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 | ||
| 141 | #define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) | ||
| 142 | |||
| 143 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 144 | #define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 | ||
| 145 | #define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) | ||
| 146 | |||
| 147 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 148 | #define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 | ||
| 149 | #define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) | ||
| 150 | |||
| 151 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 152 | #define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 | ||
| 153 | #define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) | ||
| 154 | |||
| 155 | /* Used by PM_CORE_PWRSTST */ | ||
| 156 | #define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 | ||
| 157 | #define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) | ||
| 158 | |||
| 159 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 160 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 | ||
| 161 | #define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) | ||
| 162 | |||
| 163 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 164 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 | ||
| 165 | #define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) | ||
| 166 | |||
| 167 | /* Used by PM_CORE_PWRSTST */ | ||
| 168 | #define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 | ||
| 169 | #define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) | ||
| 170 | |||
| 171 | /* Used by REVISION_PRM */ | ||
| 172 | #define OMAP4430_CUSTOM_SHIFT 6 | ||
| 173 | #define OMAP4430_CUSTOM_MASK (0x3 << 6) | ||
| 174 | |||
| 175 | /* Used by PRM_VC_VAL_BYPASS */ | ||
| 176 | #define OMAP4430_DATA_SHIFT 16 | 29 | #define OMAP4430_DATA_SHIFT 16 |
| 177 | #define OMAP4430_DATA_MASK (0xff << 16) | ||
| 178 | |||
| 179 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
| 180 | #define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 | ||
| 181 | #define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) | ||
| 182 | |||
| 183 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
| 184 | #define OMAP4430_DFILTEREN_SHIFT 6 | ||
| 185 | #define OMAP4430_DFILTEREN_MASK (1 << 6) | ||
| 186 | |||
| 187 | /* | ||
| 188 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 189 | * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP | ||
| 190 | */ | ||
| 191 | #define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 | ||
| 192 | #define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
| 193 | |||
| 194 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
| 195 | #define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 | ||
| 196 | #define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) | ||
| 197 | |||
| 198 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
| 199 | #define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 | ||
| 200 | #define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) | ||
| 201 | |||
| 202 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 203 | #define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 | ||
| 204 | #define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) | ||
| 205 | |||
| 206 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 207 | #define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 | ||
| 208 | #define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) | ||
| 209 | |||
| 210 | /* Used by PRM_IRQENABLE_MPU */ | ||
| 211 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 | ||
| 212 | #define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) | ||
| 213 | |||
| 214 | /* Used by PRM_IRQSTATUS_MPU */ | ||
| 215 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 | ||
| 216 | #define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) | ||
| 217 | |||
| 218 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ | ||
| 219 | #define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 | ||
| 220 | #define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) | ||
| 221 | |||
| 222 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ | ||
| 223 | #define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 | ||
| 224 | #define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) | ||
| 225 | |||
| 226 | /* Used by PRM_IRQENABLE_MPU */ | ||
| 227 | #define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 | ||
| 228 | #define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) | ||
| 229 | |||
| 230 | /* Used by PRM_IRQSTATUS_MPU */ | ||
| 231 | #define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 | ||
| 232 | #define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) | ||
| 233 | |||
| 234 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 235 | #define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 | ||
| 236 | #define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) | ||
| 237 | |||
| 238 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 239 | #define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 | ||
| 240 | #define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) | ||
| 241 | |||
| 242 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 243 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 | ||
| 244 | #define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) | ||
| 245 | |||
| 246 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 247 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 | ||
| 248 | #define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) | ||
| 249 | |||
| 250 | /* Used by PM_DSS_PWRSTCTRL */ | ||
| 251 | #define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 | ||
| 252 | #define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) | ||
| 253 | |||
| 254 | /* Used by PM_DSS_PWRSTCTRL */ | ||
| 255 | #define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 | ||
| 256 | #define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) | ||
| 257 | |||
| 258 | /* Used by PM_DSS_PWRSTST */ | ||
| 259 | #define OMAP4430_DSS_MEM_STATEST_SHIFT 4 | ||
| 260 | #define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) | ||
| 261 | |||
| 262 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 263 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 | ||
| 264 | #define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) | ||
| 265 | |||
| 266 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 267 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 | ||
| 268 | #define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) | ||
| 269 | |||
| 270 | /* Used by PM_CORE_PWRSTST */ | ||
| 271 | #define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 | ||
| 272 | #define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) | ||
| 273 | |||
| 274 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 275 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 | ||
| 276 | #define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) | ||
| 277 | |||
| 278 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 279 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 | ||
| 280 | #define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) | ||
| 281 | |||
| 282 | /* Used by PM_CORE_PWRSTST */ | ||
| 283 | #define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 | ||
| 284 | #define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) | ||
| 285 | |||
| 286 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
| 287 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8 | ||
| 288 | #define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) | ||
| 289 | |||
| 290 | /* Used by PRM_DEVICE_OFF_CTRL */ | ||
| 291 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9 | ||
| 292 | #define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) | ||
| 293 | |||
| 294 | /* Used by RM_MPU_RSTST */ | ||
| 295 | #define OMAP4430_EMULATION_RST_SHIFT 0 | ||
| 296 | #define OMAP4430_EMULATION_RST_MASK (1 << 0) | ||
| 297 | |||
| 298 | /* Used by RM_DUCATI_RSTST */ | ||
| 299 | #define OMAP4430_EMULATION_RST1ST_SHIFT 3 | ||
| 300 | #define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) | ||
| 301 | |||
| 302 | /* Used by RM_DUCATI_RSTST */ | ||
| 303 | #define OMAP4430_EMULATION_RST2ST_SHIFT 4 | ||
| 304 | #define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) | ||
| 305 | |||
| 306 | /* Used by RM_IVAHD_RSTST */ | ||
| 307 | #define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 | ||
| 308 | #define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) | ||
| 309 | |||
| 310 | /* Used by RM_IVAHD_RSTST */ | ||
| 311 | #define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 | ||
| 312 | #define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) | ||
| 313 | |||
| 314 | /* Used by PM_EMU_PWRSTCTRL */ | ||
| 315 | #define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 | ||
| 316 | #define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) | ||
| 317 | |||
| 318 | /* Used by PM_EMU_PWRSTST */ | ||
| 319 | #define OMAP4430_EMU_BANK_STATEST_SHIFT 4 | ||
| 320 | #define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) | ||
| 321 | |||
| 322 | /* | ||
| 323 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 324 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 325 | */ | ||
| 326 | #define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 | ||
| 327 | #define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) | ||
| 328 | |||
| 329 | /* | ||
| 330 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 331 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 332 | */ | ||
| 333 | #define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 | ||
| 334 | #define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) | ||
| 335 | |||
| 336 | /* | ||
| 337 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 338 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 339 | */ | ||
| 340 | #define OMAP4430_ENFUNC4_SHIFT 6 | ||
| 341 | #define OMAP4430_ENFUNC4_MASK (1 << 6) | ||
| 342 | |||
| 343 | /* | ||
| 344 | * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, | ||
| 345 | * PRM_LDO_SRAM_MPU_SETUP | ||
| 346 | */ | ||
| 347 | #define OMAP4430_ENFUNC5_SHIFT 7 | ||
| 348 | #define OMAP4430_ENFUNC5_MASK (1 << 7) | ||
| 349 | |||
| 350 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 351 | #define OMAP4430_ERRORGAIN_SHIFT 16 | ||
| 352 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) | 30 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
| 353 | |||
| 354 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 355 | #define OMAP4430_ERROROFFSET_SHIFT 24 | ||
| 356 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) | 31 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
| 357 | |||
| 358 | /* Used by PRM_RSTST */ | ||
| 359 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 | 32 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
| 360 | #define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
| 361 | |||
| 362 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 363 | #define OMAP4430_FORCEUPDATE_SHIFT 1 | ||
| 364 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) | 33 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
| 365 | |||
| 366 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
| 367 | #define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 | ||
| 368 | #define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) | ||
| 369 | |||
| 370 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ | ||
| 371 | #define OMAP4430_FORCEWKUP_EN_SHIFT 10 | ||
| 372 | #define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) | ||
| 373 | |||
| 374 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ | ||
| 375 | #define OMAP4430_FORCEWKUP_ST_SHIFT 10 | ||
| 376 | #define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) | ||
| 377 | |||
| 378 | /* Used by REVISION_PRM */ | ||
| 379 | #define OMAP4430_FUNC_SHIFT 16 | ||
| 380 | #define OMAP4430_FUNC_MASK (0xfff << 16) | ||
| 381 | |||
| 382 | /* Used by PM_GFX_PWRSTCTRL */ | ||
| 383 | #define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 | ||
| 384 | #define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) | ||
| 385 | |||
| 386 | /* Used by PM_GFX_PWRSTST */ | ||
| 387 | #define OMAP4430_GFX_MEM_STATEST_SHIFT 4 | ||
| 388 | #define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) | ||
| 389 | |||
| 390 | /* Used by PRM_RSTST */ | ||
| 391 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 | 34 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
| 392 | #define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) | ||
| 393 | |||
| 394 | /* Used by PRM_RSTST */ | ||
| 395 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 | 35 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 396 | #define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) | ||
| 397 | |||
| 398 | /* Used by PRM_IO_PMCTRL */ | ||
| 399 | #define OMAP4430_GLOBAL_WUEN_SHIFT 16 | ||
| 400 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) | 36 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
| 401 | |||
| 402 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
| 403 | #define OMAP4430_HSMCODE_SHIFT 0 | ||
| 404 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) | 37 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
| 405 | |||
| 406 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
| 407 | #define OMAP4430_HSMODEEN_SHIFT 3 | ||
| 408 | #define OMAP4430_HSMODEEN_MASK (1 << 3) | 38 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
| 409 | |||
| 410 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
| 411 | #define OMAP4430_HSSCLH_SHIFT 16 | ||
| 412 | #define OMAP4430_HSSCLH_MASK (0xff << 16) | ||
| 413 | |||
| 414 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
| 415 | #define OMAP4430_HSSCLL_SHIFT 24 | 39 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 416 | #define OMAP4430_HSSCLL_MASK (0xff << 24) | ||
| 417 | |||
| 418 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 419 | #define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 | ||
| 420 | #define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) | ||
| 421 | |||
| 422 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 423 | #define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 | ||
| 424 | #define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) | ||
| 425 | |||
| 426 | /* Used by PM_IVAHD_PWRSTST */ | ||
| 427 | #define OMAP4430_HWA_MEM_STATEST_SHIFT 4 | ||
| 428 | #define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) | ||
| 429 | |||
| 430 | /* Used by RM_MPU_RSTST */ | ||
| 431 | #define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 | ||
| 432 | #define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) | ||
| 433 | |||
| 434 | /* Used by RM_DUCATI_RSTST */ | ||
| 435 | #define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 | ||
| 436 | #define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) | ||
| 437 | |||
| 438 | /* Used by RM_DUCATI_RSTST */ | ||
| 439 | #define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 | ||
| 440 | #define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) | ||
| 441 | |||
| 442 | /* Used by RM_IVAHD_RSTST */ | ||
| 443 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 | ||
| 444 | #define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) | ||
| 445 | |||
| 446 | /* Used by RM_IVAHD_RSTST */ | ||
| 447 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 | ||
| 448 | #define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) | ||
| 449 | |||
| 450 | /* Used by PRM_RSTST */ | ||
| 451 | #define OMAP4430_ICEPICK_RST_SHIFT 9 | 40 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
| 452 | #define OMAP4430_ICEPICK_RST_MASK (1 << 9) | ||
| 453 | |||
| 454 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 455 | #define OMAP4430_INITVDD_SHIFT 2 | ||
| 456 | #define OMAP4430_INITVDD_MASK (1 << 2) | 41 | #define OMAP4430_INITVDD_MASK (1 << 2) |
| 457 | |||
| 458 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 459 | #define OMAP4430_INITVOLTAGE_SHIFT 8 | ||
| 460 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) | 42 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
| 461 | |||
| 462 | /* | ||
| 463 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
| 464 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
| 465 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
| 466 | */ | ||
| 467 | #define OMAP4430_INTRANSITION_SHIFT 20 | ||
| 468 | #define OMAP4430_INTRANSITION_MASK (1 << 20) | ||
| 469 | |||
| 470 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 471 | #define OMAP4430_IO_EN_SHIFT 9 | ||
| 472 | #define OMAP4430_IO_EN_MASK (1 << 9) | ||
| 473 | |||
| 474 | /* Used by PRM_IO_PMCTRL */ | ||
| 475 | #define OMAP4430_IO_ON_STATUS_SHIFT 5 | ||
| 476 | #define OMAP4430_IO_ON_STATUS_MASK (1 << 5) | ||
| 477 | |||
| 478 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 479 | #define OMAP4430_IO_ST_SHIFT 9 | ||
| 480 | #define OMAP4430_IO_ST_MASK (1 << 9) | ||
| 481 | |||
| 482 | /* Used by PRM_IO_PMCTRL */ | ||
| 483 | #define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 | ||
| 484 | #define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) | ||
| 485 | |||
| 486 | /* Used by PRM_IO_PMCTRL */ | ||
| 487 | #define OMAP4430_ISOCLK_STATUS_SHIFT 1 | ||
| 488 | #define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) | ||
| 489 | |||
| 490 | /* Used by PRM_IO_PMCTRL */ | ||
| 491 | #define OMAP4430_ISOOVR_EXTEND_SHIFT 4 | ||
| 492 | #define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) | ||
| 493 | |||
| 494 | /* Used by PRM_IO_COUNT */ | ||
| 495 | #define OMAP4430_ISO_2_ON_TIME_SHIFT 0 | ||
| 496 | #define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) | ||
| 497 | |||
| 498 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
| 499 | #define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 | ||
| 500 | #define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) | ||
| 501 | |||
| 502 | /* Used by PM_L3INIT_PWRSTCTRL */ | ||
| 503 | #define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 | ||
| 504 | #define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) | ||
| 505 | |||
| 506 | /* Used by PM_L3INIT_PWRSTST */ | ||
| 507 | #define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 | ||
| 508 | #define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) | ||
| 509 | |||
| 510 | /* | ||
| 511 | * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, | ||
| 512 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
| 513 | */ | ||
| 514 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 | 43 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 |
| 515 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | 44 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
| 516 | |||
| 517 | /* | ||
| 518 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, | ||
| 519 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | ||
| 520 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
| 521 | */ | ||
| 522 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 | 45 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
| 523 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) | 46 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
| 524 | |||
| 525 | /* | ||
| 526 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
| 527 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
| 528 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
| 529 | */ | ||
| 530 | #define OMAP4430_LOGICSTATEST_SHIFT 2 | 47 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
| 531 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) | 48 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
| 532 | |||
| 533 | /* | ||
| 534 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, | ||
| 535 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, | ||
| 536 | * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, | ||
| 537 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, | ||
| 538 | * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, | ||
| 539 | * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, | ||
| 540 | * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, | ||
| 541 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, | ||
| 542 | * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, | ||
| 543 | * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, | ||
| 544 | * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, | ||
| 545 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
| 546 | * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, | ||
| 547 | * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, | ||
| 548 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, | ||
| 549 | * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, | ||
| 550 | * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, | ||
| 551 | * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, | ||
| 552 | * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, | ||
| 553 | * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, | ||
| 554 | * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, | ||
| 555 | * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, | ||
| 556 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, | ||
| 557 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, | ||
| 558 | * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, | ||
| 559 | * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, | ||
| 560 | * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, | ||
| 561 | * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, | ||
| 562 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | ||
| 563 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, | ||
| 564 | * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, | ||
| 565 | * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, | ||
| 566 | * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, | ||
| 567 | * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT | ||
| 568 | */ | ||
| 569 | #define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 | ||
| 570 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) | 49 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
| 571 | |||
| 572 | /* | ||
| 573 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, | ||
| 574 | * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, | ||
| 575 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
| 576 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, | ||
| 577 | * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, | ||
| 578 | * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, | ||
| 579 | * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, | ||
| 580 | * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, | ||
| 581 | * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, | ||
| 582 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, | ||
| 583 | * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, | ||
| 584 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | ||
| 585 | * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, | ||
| 586 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, | ||
| 587 | * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, | ||
| 588 | * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, | ||
| 589 | * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT | ||
| 590 | */ | ||
| 591 | #define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 | ||
| 592 | #define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) | ||
| 593 | |||
| 594 | /* Used by RM_ABE_AESS_CONTEXT */ | ||
| 595 | #define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 | ||
| 596 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) | 50 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
| 597 | |||
| 598 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ | ||
| 599 | #define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 | ||
| 600 | #define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) | ||
| 601 | |||
| 602 | /* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ | ||
| 603 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 | ||
| 604 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) | ||
| 605 | |||
| 606 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ | ||
| 607 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 | ||
| 608 | #define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) | ||
| 609 | |||
| 610 | /* Used by RM_L3_2_OCMC_RAM_CONTEXT */ | ||
| 611 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 | ||
| 612 | #define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) | ||
| 613 | |||
| 614 | /* | ||
| 615 | * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, | ||
| 616 | * RM_SDMA_SDMA_CONTEXT | ||
| 617 | */ | ||
| 618 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 | ||
| 619 | #define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) | ||
| 620 | |||
| 621 | /* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ | ||
| 622 | #define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 | ||
| 623 | #define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) | ||
| 624 | |||
| 625 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
| 626 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 | ||
| 627 | #define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) | ||
| 628 | |||
| 629 | /* Used by RM_DUCATI_DUCATI_CONTEXT */ | ||
| 630 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 | ||
| 631 | #define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) | ||
| 632 | |||
| 633 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ | ||
| 634 | #define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 | ||
| 635 | #define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) | ||
| 636 | |||
| 637 | /* Used by RM_GFX_GFX_CONTEXT */ | ||
| 638 | #define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 | ||
| 639 | #define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) | ||
| 640 | |||
| 641 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
| 642 | #define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 | ||
| 643 | #define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) | ||
| 644 | |||
| 645 | /* | ||
| 646 | * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, | ||
| 647 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, | ||
| 648 | * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, | ||
| 649 | * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, | ||
| 650 | * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT | ||
| 651 | */ | ||
| 652 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 | ||
| 653 | #define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) | ||
| 654 | |||
| 655 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
| 656 | #define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 | ||
| 657 | #define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) | ||
| 658 | |||
| 659 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
| 660 | #define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 | ||
| 661 | #define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) | ||
| 662 | |||
| 663 | /* Used by RM_MPU_MPU_CONTEXT */ | ||
| 664 | #define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 | ||
| 665 | #define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) | ||
| 666 | |||
| 667 | /* | ||
| 668 | * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, | ||
| 669 | * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, | ||
| 670 | * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT | ||
| 671 | */ | ||
| 672 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 | ||
| 673 | #define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) | ||
| 674 | |||
| 675 | /* | ||
| 676 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, | ||
| 677 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT | ||
| 678 | */ | ||
| 679 | #define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 | ||
| 680 | #define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) | ||
| 681 | |||
| 682 | /* | ||
| 683 | * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, | ||
| 684 | * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, | ||
| 685 | * RM_L4SEC_CRYPTODMA_CONTEXT | ||
| 686 | */ | ||
| 687 | #define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 | ||
| 688 | #define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) | ||
| 689 | |||
| 690 | /* Used by RM_IVAHD_SL2_CONTEXT */ | ||
| 691 | #define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 | ||
| 692 | #define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) | ||
| 693 | |||
| 694 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
| 695 | #define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 | ||
| 696 | #define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) | ||
| 697 | |||
| 698 | /* Used by RM_IVAHD_IVAHD_CONTEXT */ | ||
| 699 | #define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 | ||
| 700 | #define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) | ||
| 701 | |||
| 702 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
| 703 | #define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 | ||
| 704 | #define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) | ||
| 705 | |||
| 706 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
| 707 | #define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 | ||
| 708 | #define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) | ||
| 709 | |||
| 710 | /* Used by RM_TESLA_TESLA_CONTEXT */ | ||
| 711 | #define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 | ||
| 712 | #define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) | ||
| 713 | |||
| 714 | /* Used by RM_WKUP_SARRAM_CONTEXT */ | ||
| 715 | #define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 | ||
| 716 | #define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) | ||
| 717 | |||
| 718 | /* | ||
| 719 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | ||
| 720 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, | ||
| 721 | * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
| 722 | */ | ||
| 723 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 | 51 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
| 724 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) | 52 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 725 | |||
| 726 | /* Used by PRM_MODEM_IF_CTRL */ | ||
| 727 | #define OMAP4430_MODEM_READY_SHIFT 1 | ||
| 728 | #define OMAP4430_MODEM_READY_MASK (1 << 1) | ||
| 729 | |||
| 730 | /* Used by PRM_MODEM_IF_CTRL */ | ||
| 731 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 | ||
| 732 | #define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) | ||
| 733 | |||
| 734 | /* Used by PRM_MODEM_IF_CTRL */ | ||
| 735 | #define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 | ||
| 736 | #define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) | ||
| 737 | |||
| 738 | /* Used by PRM_MODEM_IF_CTRL */ | ||
| 739 | #define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 | ||
| 740 | #define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) | ||
| 741 | |||
| 742 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 743 | #define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 | ||
| 744 | #define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) | ||
| 745 | |||
| 746 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 747 | #define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 | ||
| 748 | #define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) | ||
| 749 | |||
| 750 | /* Used by PM_MPU_PWRSTST */ | ||
| 751 | #define OMAP4430_MPU_L1_STATEST_SHIFT 4 | ||
| 752 | #define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) | ||
| 753 | |||
| 754 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 755 | #define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 | ||
| 756 | #define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) | ||
| 757 | |||
| 758 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 759 | #define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 | ||
| 760 | #define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) | ||
| 761 | |||
| 762 | /* Used by PM_MPU_PWRSTST */ | ||
| 763 | #define OMAP4430_MPU_L2_STATEST_SHIFT 6 | ||
| 764 | #define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) | ||
| 765 | |||
| 766 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 767 | #define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 | ||
| 768 | #define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) | ||
| 769 | |||
| 770 | /* Used by PM_MPU_PWRSTCTRL */ | ||
| 771 | #define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 | ||
| 772 | #define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) | ||
| 773 | |||
| 774 | /* Used by PM_MPU_PWRSTST */ | ||
| 775 | #define OMAP4430_MPU_RAM_STATEST_SHIFT 8 | ||
| 776 | #define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) | ||
| 777 | |||
| 778 | /* Used by PRM_RSTST */ | ||
| 779 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 | 53 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 780 | #define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
| 781 | |||
| 782 | /* Used by PRM_RSTST */ | ||
| 783 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 | 54 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
| 784 | #define OMAP4430_MPU_WDT_RST_MASK (1 << 3) | ||
| 785 | |||
| 786 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
| 787 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 | ||
| 788 | #define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) | ||
| 789 | |||
| 790 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
| 791 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 | ||
| 792 | #define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) | ||
| 793 | |||
| 794 | /* Used by PM_L4PER_PWRSTST */ | ||
| 795 | #define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 | ||
| 796 | #define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) | ||
| 797 | |||
| 798 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 799 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 | ||
| 800 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) | 55 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
| 801 | |||
| 802 | /* Used by PM_CORE_PWRSTCTRL */ | ||
| 803 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 | ||
| 804 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) | 56 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
| 805 | |||
| 806 | /* Used by PM_CORE_PWRSTST */ | ||
| 807 | #define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 | ||
| 808 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) | 57 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
| 809 | |||
| 810 | /* | ||
| 811 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
| 812 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
| 813 | */ | ||
| 814 | #define OMAP4430_OFF_SHIFT 0 | 58 | #define OMAP4430_OFF_SHIFT 0 |
| 815 | #define OMAP4430_OFF_MASK (0xff << 0) | ||
| 816 | |||
| 817 | /* | ||
| 818 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
| 819 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
| 820 | */ | ||
| 821 | #define OMAP4430_ON_SHIFT 24 | 59 | #define OMAP4430_ON_SHIFT 24 |
| 822 | #define OMAP4430_ON_MASK (0xff << 24) | 60 | #define OMAP4430_ON_MASK (0xff << 24) |
| 823 | |||
| 824 | /* | ||
| 825 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
| 826 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
| 827 | */ | ||
| 828 | #define OMAP4430_ONLP_SHIFT 16 | 61 | #define OMAP4430_ONLP_SHIFT 16 |
| 829 | #define OMAP4430_ONLP_MASK (0xff << 16) | ||
| 830 | |||
| 831 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
| 832 | #define OMAP4430_OPP_CHANGE_SHIFT 2 | ||
| 833 | #define OMAP4430_OPP_CHANGE_MASK (1 << 2) | ||
| 834 | |||
| 835 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
| 836 | #define OMAP4430_OPP_SEL_SHIFT 0 | ||
| 837 | #define OMAP4430_OPP_SEL_MASK (0x3 << 0) | ||
| 838 | |||
| 839 | /* Used by PRM_SRAM_COUNT */ | ||
| 840 | #define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 | ||
| 841 | #define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
| 842 | |||
| 843 | /* Used by PRM_PSCON_COUNT */ | ||
| 844 | #define OMAP4430_PCHARGE_TIME_SHIFT 0 | ||
| 845 | #define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) | ||
| 846 | |||
| 847 | /* Used by PM_ABE_PWRSTCTRL */ | ||
| 848 | #define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 | ||
| 849 | #define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) | ||
| 850 | |||
| 851 | /* Used by PM_ABE_PWRSTCTRL */ | ||
| 852 | #define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 | ||
| 853 | #define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) | ||
| 854 | |||
| 855 | /* Used by PM_ABE_PWRSTST */ | ||
| 856 | #define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 | ||
| 857 | #define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) | ||
| 858 | |||
| 859 | /* Used by PRM_PHASE1_CNDP */ | ||
| 860 | #define OMAP4430_PHASE1_CNDP_SHIFT 0 | ||
| 861 | #define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) | ||
| 862 | |||
| 863 | /* Used by PRM_PHASE2A_CNDP */ | ||
| 864 | #define OMAP4430_PHASE2A_CNDP_SHIFT 0 | ||
| 865 | #define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) | ||
| 866 | |||
| 867 | /* Used by PRM_PHASE2B_CNDP */ | ||
| 868 | #define OMAP4430_PHASE2B_CNDP_SHIFT 0 | ||
| 869 | #define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) | ||
| 870 | |||
| 871 | /* Used by PRM_PSCON_COUNT */ | ||
| 872 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 | ||
| 873 | #define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) | ||
| 874 | |||
| 875 | /* | ||
| 876 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, | ||
| 877 | * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, | ||
| 878 | * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, | ||
| 879 | * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL | ||
| 880 | */ | ||
| 881 | #define OMAP4430_POWERSTATE_SHIFT 0 | ||
| 882 | #define OMAP4430_POWERSTATE_MASK (0x3 << 0) | ||
| 883 | |||
| 884 | /* | ||
| 885 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, | ||
| 886 | * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, | ||
| 887 | * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST | ||
| 888 | */ | ||
| 889 | #define OMAP4430_POWERSTATEST_SHIFT 0 | ||
| 890 | #define OMAP4430_POWERSTATEST_MASK (0x3 << 0) | ||
| 891 | |||
| 892 | /* Used by PRM_PWRREQCTRL */ | ||
| 893 | #define OMAP4430_PWRREQ_COND_SHIFT 0 | ||
| 894 | #define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) | ||
| 895 | |||
| 896 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 897 | #define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 | ||
| 898 | #define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) | ||
| 899 | |||
| 900 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 901 | #define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 | ||
| 902 | #define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) | ||
| 903 | |||
| 904 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 905 | #define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 | ||
| 906 | #define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) | ||
| 907 | |||
| 908 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 909 | #define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 | ||
| 910 | #define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) | ||
| 911 | |||
| 912 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 913 | #define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 | ||
| 914 | #define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) | ||
| 915 | |||
| 916 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 917 | #define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 | ||
| 918 | #define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) | ||
| 919 | |||
| 920 | /* | ||
| 921 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
| 922 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
| 923 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
| 924 | */ | ||
| 925 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 | 62 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
| 926 | #define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) | ||
| 927 | |||
| 928 | /* | ||
| 929 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
| 930 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
| 931 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
| 932 | */ | ||
| 933 | #define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 | ||
| 934 | #define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) | ||
| 935 | |||
| 936 | /* | ||
| 937 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
| 938 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
| 939 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
| 940 | */ | ||
| 941 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 | 63 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
| 942 | #define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) | ||
| 943 | |||
| 944 | /* | ||
| 945 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, | ||
| 946 | * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, | ||
| 947 | * PRM_VOLTSETUP_MPU_RET_SLEEP | ||
| 948 | */ | ||
| 949 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 | 64 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
| 950 | #define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) | ||
| 951 | |||
| 952 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 953 | #define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 | ||
| 954 | #define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) | ||
| 955 | |||
| 956 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 957 | #define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 | ||
| 958 | #define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) | ||
| 959 | |||
| 960 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 961 | #define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 | ||
| 962 | #define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) | ||
| 963 | |||
| 964 | /* Used by PRM_VC_VAL_BYPASS */ | ||
| 965 | #define OMAP4430_REGADDR_SHIFT 8 | 65 | #define OMAP4430_REGADDR_SHIFT 8 |
| 966 | #define OMAP4430_REGADDR_MASK (0xff << 8) | ||
| 967 | |||
| 968 | /* | ||
| 969 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, | ||
| 970 | * PRM_VC_VAL_CMD_VDD_MPU_L | ||
| 971 | */ | ||
| 972 | #define OMAP4430_RET_SHIFT 8 | 66 | #define OMAP4430_RET_SHIFT 8 |
| 973 | #define OMAP4430_RET_MASK (0xff << 8) | ||
| 974 | |||
| 975 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
| 976 | #define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 | ||
| 977 | #define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) | ||
| 978 | |||
| 979 | /* Used by PM_L4PER_PWRSTCTRL */ | ||
| 980 | #define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 | ||
| 981 | #define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) | ||
| 982 | |||
| 983 | /* Used by PM_L4PER_PWRSTST */ | ||
| 984 | #define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 | ||
| 985 | #define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) | ||
| 986 | |||
| 987 | /* | ||
| 988 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
| 989 | * PRM_LDO_SRAM_MPU_CTRL | ||
| 990 | */ | ||
| 991 | #define OMAP4430_RETMODE_ENABLE_SHIFT 0 | ||
| 992 | #define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) | ||
| 993 | |||
| 994 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ | ||
| 995 | #define OMAP4430_RST1_SHIFT 0 | ||
| 996 | #define OMAP4430_RST1_MASK (1 << 0) | ||
| 997 | |||
| 998 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ | ||
| 999 | #define OMAP4430_RST1ST_SHIFT 0 | ||
| 1000 | #define OMAP4430_RST1ST_MASK (1 << 0) | ||
| 1001 | |||
| 1002 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ | ||
| 1003 | #define OMAP4430_RST2_SHIFT 1 | ||
| 1004 | #define OMAP4430_RST2_MASK (1 << 1) | ||
| 1005 | |||
| 1006 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ | ||
| 1007 | #define OMAP4430_RST2ST_SHIFT 1 | ||
| 1008 | #define OMAP4430_RST2ST_MASK (1 << 1) | ||
| 1009 | |||
| 1010 | /* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ | ||
| 1011 | #define OMAP4430_RST3_SHIFT 2 | ||
| 1012 | #define OMAP4430_RST3_MASK (1 << 2) | ||
| 1013 | |||
| 1014 | /* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ | ||
| 1015 | #define OMAP4430_RST3ST_SHIFT 2 | ||
| 1016 | #define OMAP4430_RST3ST_MASK (1 << 2) | ||
| 1017 | |||
| 1018 | /* Used by PRM_RSTTIME */ | ||
| 1019 | #define OMAP4430_RSTTIME1_SHIFT 0 | ||
| 1020 | #define OMAP4430_RSTTIME1_MASK (0x3ff << 0) | ||
| 1021 | |||
| 1022 | /* Used by PRM_RSTTIME */ | ||
| 1023 | #define OMAP4430_RSTTIME2_SHIFT 10 | ||
| 1024 | #define OMAP4430_RSTTIME2_MASK (0x1f << 10) | ||
| 1025 | |||
| 1026 | /* Used by PRM_RSTCTRL */ | ||
| 1027 | #define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
| 1028 | #define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
| 1029 | |||
| 1030 | /* Used by PRM_RSTCTRL */ | ||
| 1031 | #define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
| 1032 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) | 67 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| 1033 | |||
| 1034 | /* Used by REVISION_PRM */ | ||
| 1035 | #define OMAP4430_R_RTL_SHIFT 11 | ||
| 1036 | #define OMAP4430_R_RTL_MASK (0x1f << 11) | ||
| 1037 | |||
| 1038 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 1039 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 | 68 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
| 1040 | #define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) | ||
| 1041 | |||
| 1042 | /* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ | ||
| 1043 | #define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 | ||
| 1044 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) | 69 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
| 1045 | |||
| 1046 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 1047 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 | 70 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
| 1048 | #define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) | ||
| 1049 | |||
| 1050 | /* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ | ||
| 1051 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 | ||
| 1052 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) | 71 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
| 1053 | |||
| 1054 | /* Used by PRM_VC_CFG_CHANNEL */ | ||
| 1055 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 | 72 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
| 1056 | #define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) | ||
| 1057 | |||
| 1058 | /* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ | ||
| 1059 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 | ||
| 1060 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) | 73 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
| 1061 | |||
| 1062 | /* Used by REVISION_PRM */ | ||
| 1063 | #define OMAP4430_SCHEME_SHIFT 30 | ||
| 1064 | #define OMAP4430_SCHEME_MASK (0x3 << 30) | ||
| 1065 | |||
| 1066 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
| 1067 | #define OMAP4430_SCLH_SHIFT 0 | 74 | #define OMAP4430_SCLH_SHIFT 0 |
| 1068 | #define OMAP4430_SCLH_MASK (0xff << 0) | ||
| 1069 | |||
| 1070 | /* Used by PRM_VC_CFG_I2C_CLK */ | ||
| 1071 | #define OMAP4430_SCLL_SHIFT 8 | 75 | #define OMAP4430_SCLL_SHIFT 8 |
| 1072 | #define OMAP4430_SCLL_MASK (0xff << 8) | ||
| 1073 | |||
| 1074 | /* Used by PRM_RSTST */ | ||
| 1075 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 | 76 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
| 1076 | #define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) | ||
| 1077 | |||
| 1078 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1079 | #define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 | ||
| 1080 | #define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) | ||
| 1081 | |||
| 1082 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1083 | #define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 | ||
| 1084 | #define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) | ||
| 1085 | |||
| 1086 | /* Used by PM_IVAHD_PWRSTST */ | ||
| 1087 | #define OMAP4430_SL2_MEM_STATEST_SHIFT 6 | ||
| 1088 | #define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) | ||
| 1089 | |||
| 1090 | /* Used by PRM_VC_VAL_BYPASS */ | ||
| 1091 | #define OMAP4430_SLAVEADDR_SHIFT 0 | 77 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
| 1092 | #define OMAP4430_SLAVEADDR_MASK (0x7f << 0) | ||
| 1093 | |||
| 1094 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
| 1095 | #define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 | ||
| 1096 | #define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) | ||
| 1097 | |||
| 1098 | /* Used by PRM_SRAM_COUNT */ | ||
| 1099 | #define OMAP4430_SLPCNT_VALUE_SHIFT 16 | ||
| 1100 | #define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) | ||
| 1101 | |||
| 1102 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
| 1103 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 | 78 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
| 1104 | #define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | ||
| 1105 | |||
| 1106 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
| 1107 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 | 79 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
| 1108 | #define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | ||
| 1109 | |||
| 1110 | /* Used by PRM_VC_ERRST */ | ||
| 1111 | #define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 | ||
| 1112 | #define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) | ||
| 1113 | |||
| 1114 | /* Used by PRM_VC_ERRST */ | ||
| 1115 | #define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 | ||
| 1116 | #define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) | ||
| 1117 | |||
| 1118 | /* Used by PRM_VC_ERRST */ | ||
| 1119 | #define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 | ||
| 1120 | #define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) | ||
| 1121 | |||
| 1122 | /* Used by PRM_VC_ERRST */ | ||
| 1123 | #define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 | ||
| 1124 | #define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) | ||
| 1125 | |||
| 1126 | /* Used by PRM_VC_ERRST */ | ||
| 1127 | #define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 | ||
| 1128 | #define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) | ||
| 1129 | |||
| 1130 | /* Used by PRM_VC_ERRST */ | ||
| 1131 | #define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 | ||
| 1132 | #define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) | ||
| 1133 | |||
| 1134 | /* Used by PRM_VC_ERRST */ | ||
| 1135 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 | ||
| 1136 | #define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) | ||
| 1137 | |||
| 1138 | /* Used by PRM_VC_ERRST */ | ||
| 1139 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 | ||
| 1140 | #define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) | ||
| 1141 | |||
| 1142 | /* Used by PRM_VC_ERRST */ | ||
| 1143 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 | ||
| 1144 | #define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) | ||
| 1145 | |||
| 1146 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
| 1147 | #define OMAP4430_SR2EN_SHIFT 0 | ||
| 1148 | #define OMAP4430_SR2EN_MASK (1 << 0) | ||
| 1149 | |||
| 1150 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
| 1151 | #define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 | ||
| 1152 | #define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) | ||
| 1153 | |||
| 1154 | /* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ | ||
| 1155 | #define OMAP4430_SR2_STATUS_SHIFT 3 | ||
| 1156 | #define OMAP4430_SR2_STATUS_MASK (0x3 << 3) | ||
| 1157 | |||
| 1158 | /* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ | ||
| 1159 | #define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 | ||
| 1160 | #define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) | ||
| 1161 | |||
| 1162 | /* | ||
| 1163 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
| 1164 | * PRM_LDO_SRAM_MPU_CTRL | ||
| 1165 | */ | ||
| 1166 | #define OMAP4430_SRAMLDO_STATUS_SHIFT 8 | ||
| 1167 | #define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) | ||
| 1168 | |||
| 1169 | /* | ||
| 1170 | * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, | ||
| 1171 | * PRM_LDO_SRAM_MPU_CTRL | ||
| 1172 | */ | ||
| 1173 | #define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 | ||
| 1174 | #define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
| 1175 | |||
| 1176 | /* Used by PRM_VC_CFG_I2C_MODE */ | ||
| 1177 | #define OMAP4430_SRMODEEN_SHIFT 4 | ||
| 1178 | #define OMAP4430_SRMODEEN_MASK (1 << 4) | ||
| 1179 | |||
| 1180 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
| 1181 | #define OMAP4430_STABLE_COUNT_SHIFT 0 | ||
| 1182 | #define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) | ||
| 1183 | |||
| 1184 | /* Used by PRM_VOLTSETUP_WARMRESET */ | ||
| 1185 | #define OMAP4430_STABLE_PRESCAL_SHIFT 8 | ||
| 1186 | #define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) | ||
| 1187 | |||
| 1188 | /* Used by PRM_LDO_BANDGAP_SETUP */ | ||
| 1189 | #define OMAP4430_STARTUP_COUNT_SHIFT 0 | ||
| 1190 | #define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) | ||
| 1191 | |||
| 1192 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ | ||
| 1193 | #define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 | ||
| 1194 | #define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) | ||
| 1195 | |||
| 1196 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1197 | #define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 | ||
| 1198 | #define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) | ||
| 1199 | |||
| 1200 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1201 | #define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 | ||
| 1202 | #define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) | ||
| 1203 | |||
| 1204 | /* Used by PM_IVAHD_PWRSTST */ | ||
| 1205 | #define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 | ||
| 1206 | #define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) | ||
| 1207 | |||
| 1208 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1209 | #define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 | ||
| 1210 | #define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) | ||
| 1211 | |||
| 1212 | /* Used by PM_IVAHD_PWRSTCTRL */ | ||
| 1213 | #define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 | ||
| 1214 | #define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) | ||
| 1215 | |||
| 1216 | /* Used by PM_IVAHD_PWRSTST */ | ||
| 1217 | #define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 | ||
| 1218 | #define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) | ||
| 1219 | |||
| 1220 | /* Used by RM_TESLA_RSTST */ | ||
| 1221 | #define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 | ||
| 1222 | #define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) | ||
| 1223 | |||
| 1224 | /* Used by RM_TESLA_RSTST */ | ||
| 1225 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 | ||
| 1226 | #define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) | ||
| 1227 | |||
| 1228 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1229 | #define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 | ||
| 1230 | #define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) | ||
| 1231 | |||
| 1232 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1233 | #define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 | ||
| 1234 | #define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) | ||
| 1235 | |||
| 1236 | /* Used by PM_TESLA_PWRSTST */ | ||
| 1237 | #define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 | ||
| 1238 | #define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) | ||
| 1239 | |||
| 1240 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1241 | #define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 | ||
| 1242 | #define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) | ||
| 1243 | |||
| 1244 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1245 | #define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 | ||
| 1246 | #define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) | ||
| 1247 | |||
| 1248 | /* Used by PM_TESLA_PWRSTST */ | ||
| 1249 | #define OMAP4430_TESLA_L1_STATEST_SHIFT 4 | ||
| 1250 | #define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) | ||
| 1251 | |||
| 1252 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1253 | #define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 | ||
| 1254 | #define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) | ||
| 1255 | |||
| 1256 | /* Used by PM_TESLA_PWRSTCTRL */ | ||
| 1257 | #define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 | ||
| 1258 | #define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) | ||
| 1259 | |||
| 1260 | /* Used by PM_TESLA_PWRSTST */ | ||
| 1261 | #define OMAP4430_TESLA_L2_STATEST_SHIFT 6 | ||
| 1262 | #define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) | ||
| 1263 | |||
| 1264 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
| 1265 | #define OMAP4430_TIMEOUT_SHIFT 0 | 80 | #define OMAP4430_TIMEOUT_SHIFT 0 |
| 1266 | #define OMAP4430_TIMEOUT_MASK (0xffff << 0) | ||
| 1267 | |||
| 1268 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 1269 | #define OMAP4430_TIMEOUTEN_SHIFT 3 | ||
| 1270 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) | 81 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
| 1271 | |||
| 1272 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1273 | #define OMAP4430_TRANSITION_EN_SHIFT 8 | ||
| 1274 | #define OMAP4430_TRANSITION_EN_MASK (1 << 8) | ||
| 1275 | |||
| 1276 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1277 | #define OMAP4430_TRANSITION_ST_SHIFT 8 | ||
| 1278 | #define OMAP4430_TRANSITION_ST_MASK (1 << 8) | ||
| 1279 | |||
| 1280 | /* Used by PRM_VC_VAL_BYPASS */ | ||
| 1281 | #define OMAP4430_VALID_SHIFT 24 | ||
| 1282 | #define OMAP4430_VALID_MASK (1 << 24) | 82 | #define OMAP4430_VALID_MASK (1 << 24) |
| 1283 | |||
| 1284 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1285 | #define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 | ||
| 1286 | #define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) | ||
| 1287 | |||
| 1288 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1289 | #define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 | ||
| 1290 | #define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) | ||
| 1291 | |||
| 1292 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1293 | #define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 | ||
| 1294 | #define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) | ||
| 1295 | |||
| 1296 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1297 | #define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 | ||
| 1298 | #define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) | ||
| 1299 | |||
| 1300 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1301 | #define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 | ||
| 1302 | #define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) | ||
| 1303 | |||
| 1304 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1305 | #define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 | ||
| 1306 | #define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) | ||
| 1307 | |||
| 1308 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1309 | #define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 | ||
| 1310 | #define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) | ||
| 1311 | |||
| 1312 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1313 | #define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 | ||
| 1314 | #define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) | ||
| 1315 | |||
| 1316 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1317 | #define OMAP4430_VC_RAERR_EN_SHIFT 12 | ||
| 1318 | #define OMAP4430_VC_RAERR_EN_MASK (1 << 12) | ||
| 1319 | |||
| 1320 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1321 | #define OMAP4430_VC_RAERR_ST_SHIFT 12 | ||
| 1322 | #define OMAP4430_VC_RAERR_ST_MASK (1 << 12) | ||
| 1323 | |||
| 1324 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1325 | #define OMAP4430_VC_SAERR_EN_SHIFT 11 | ||
| 1326 | #define OMAP4430_VC_SAERR_EN_MASK (1 << 11) | ||
| 1327 | |||
| 1328 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1329 | #define OMAP4430_VC_SAERR_ST_SHIFT 11 | ||
| 1330 | #define OMAP4430_VC_SAERR_ST_MASK (1 << 11) | ||
| 1331 | |||
| 1332 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1333 | #define OMAP4430_VC_TOERR_EN_SHIFT 13 | ||
| 1334 | #define OMAP4430_VC_TOERR_EN_MASK (1 << 13) | ||
| 1335 | |||
| 1336 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1337 | #define OMAP4430_VC_TOERR_ST_SHIFT 13 | ||
| 1338 | #define OMAP4430_VC_TOERR_ST_MASK (1 << 13) | ||
| 1339 | |||
| 1340 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
| 1341 | #define OMAP4430_VDDMAX_SHIFT 24 | 83 | #define OMAP4430_VDDMAX_SHIFT 24 |
| 1342 | #define OMAP4430_VDDMAX_MASK (0xff << 24) | ||
| 1343 | |||
| 1344 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ | ||
| 1345 | #define OMAP4430_VDDMIN_SHIFT 16 | 84 | #define OMAP4430_VDDMIN_SHIFT 16 |
| 1346 | #define OMAP4430_VDDMIN_MASK (0xff << 16) | ||
| 1347 | |||
| 1348 | /* Used by PRM_VOLTCTRL */ | ||
| 1349 | #define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 | ||
| 1350 | #define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) | ||
| 1351 | |||
| 1352 | /* Used by PRM_RSTST */ | ||
| 1353 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 | 85 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 1354 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) | ||
| 1355 | |||
| 1356 | /* Used by PRM_VOLTCTRL */ | ||
| 1357 | #define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 | ||
| 1358 | #define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) | ||
| 1359 | |||
| 1360 | /* Used by PRM_VOLTCTRL */ | ||
| 1361 | #define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 | ||
| 1362 | #define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) | ||
| 1363 | |||
| 1364 | /* Used by PRM_RSTST */ | ||
| 1365 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 | 86 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
| 1366 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) | ||
| 1367 | |||
| 1368 | /* Used by PRM_VOLTCTRL */ | ||
| 1369 | #define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 | ||
| 1370 | #define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) | ||
| 1371 | |||
| 1372 | /* Used by PRM_VOLTCTRL */ | ||
| 1373 | #define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 | ||
| 1374 | #define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) | ||
| 1375 | |||
| 1376 | /* Used by PRM_RSTST */ | ||
| 1377 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 | 87 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 1378 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) | ||
| 1379 | |||
| 1380 | /* Used by PRM_VC_ERRST */ | ||
| 1381 | #define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 | ||
| 1382 | #define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) | ||
| 1383 | |||
| 1384 | /* Used by PRM_VC_ERRST */ | ||
| 1385 | #define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 | ||
| 1386 | #define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) | ||
| 1387 | |||
| 1388 | /* Used by PRM_VC_ERRST */ | ||
| 1389 | #define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 | ||
| 1390 | #define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) | ||
| 1391 | |||
| 1392 | /* Used by PRM_VC_ERRST */ | ||
| 1393 | #define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 | ||
| 1394 | #define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) | ||
| 1395 | |||
| 1396 | /* Used by PRM_VC_ERRST */ | ||
| 1397 | #define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 | ||
| 1398 | #define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) | ||
| 1399 | |||
| 1400 | /* Used by PRM_VC_ERRST */ | ||
| 1401 | #define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 | ||
| 1402 | #define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) | ||
| 1403 | |||
| 1404 | /* Used by PRM_VC_ERRST */ | ||
| 1405 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 | ||
| 1406 | #define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) | ||
| 1407 | |||
| 1408 | /* Used by PRM_VC_ERRST */ | ||
| 1409 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 | ||
| 1410 | #define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) | ||
| 1411 | |||
| 1412 | /* Used by PRM_VC_ERRST */ | ||
| 1413 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 | ||
| 1414 | #define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) | ||
| 1415 | |||
| 1416 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
| 1417 | #define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 | ||
| 1418 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) | 88 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
| 1419 | |||
| 1420 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
| 1421 | #define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 | ||
| 1422 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) | 89 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
| 1423 | |||
| 1424 | /* Used by PRM_VC_VAL_SMPS_RA_VOL */ | ||
| 1425 | #define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 | ||
| 1426 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) | 90 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
| 1427 | |||
| 1428 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ | ||
| 1429 | #define OMAP4430_VPENABLE_SHIFT 0 | ||
| 1430 | #define OMAP4430_VPENABLE_MASK (1 << 0) | 91 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
| 1431 | |||
| 1432 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ | ||
| 1433 | #define OMAP4430_VPINIDLE_SHIFT 0 | ||
| 1434 | #define OMAP4430_VPINIDLE_MASK (1 << 0) | ||
| 1435 | |||
| 1436 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ | ||
| 1437 | #define OMAP4430_VPVOLTAGE_SHIFT 0 | ||
| 1438 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) | 92 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
| 1439 | |||
| 1440 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1441 | #define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 | ||
| 1442 | #define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) | ||
| 1443 | |||
| 1444 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1445 | #define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 | ||
| 1446 | #define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) | ||
| 1447 | |||
| 1448 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1449 | #define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 | ||
| 1450 | #define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) | ||
| 1451 | |||
| 1452 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1453 | #define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 | ||
| 1454 | #define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) | ||
| 1455 | |||
| 1456 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1457 | #define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 | ||
| 1458 | #define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) | ||
| 1459 | |||
| 1460 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1461 | #define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 | ||
| 1462 | #define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) | ||
| 1463 | |||
| 1464 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1465 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 | ||
| 1466 | #define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) | ||
| 1467 | |||
| 1468 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1469 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 | ||
| 1470 | #define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) | ||
| 1471 | |||
| 1472 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1473 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 | ||
| 1474 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) | ||
| 1475 | |||
| 1476 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1477 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 | ||
| 1478 | #define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) | ||
| 1479 | |||
| 1480 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1481 | #define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 | ||
| 1482 | #define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) | ||
| 1483 | |||
| 1484 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1485 | #define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 | ||
| 1486 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) | 93 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
| 1487 | |||
| 1488 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1489 | #define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 | ||
| 1490 | #define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) | ||
| 1491 | |||
| 1492 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1493 | #define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 | ||
| 1494 | #define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) | ||
| 1495 | |||
| 1496 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1497 | #define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 | ||
| 1498 | #define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) | ||
| 1499 | |||
| 1500 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1501 | #define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 | ||
| 1502 | #define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) | ||
| 1503 | |||
| 1504 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1505 | #define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 | ||
| 1506 | #define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) | ||
| 1507 | |||
| 1508 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1509 | #define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 | ||
| 1510 | #define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) | ||
| 1511 | |||
| 1512 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1513 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 | ||
| 1514 | #define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) | ||
| 1515 | |||
| 1516 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1517 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 | ||
| 1518 | #define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) | ||
| 1519 | |||
| 1520 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1521 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 | ||
| 1522 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) | ||
| 1523 | |||
| 1524 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1525 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 | ||
| 1526 | #define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) | ||
| 1527 | |||
| 1528 | /* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ | ||
| 1529 | #define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 | ||
| 1530 | #define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) | ||
| 1531 | |||
| 1532 | /* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ | ||
| 1533 | #define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 | ||
| 1534 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) | 94 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
| 1535 | |||
| 1536 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1537 | #define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 | ||
| 1538 | #define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) | ||
| 1539 | |||
| 1540 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1541 | #define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 | ||
| 1542 | #define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) | ||
| 1543 | |||
| 1544 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1545 | #define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 | ||
| 1546 | #define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) | ||
| 1547 | |||
| 1548 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1549 | #define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 | ||
| 1550 | #define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) | ||
| 1551 | |||
| 1552 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1553 | #define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 | ||
| 1554 | #define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) | ||
| 1555 | |||
| 1556 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1557 | #define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 | ||
| 1558 | #define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) | ||
| 1559 | |||
| 1560 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1561 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 | ||
| 1562 | #define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) | ||
| 1563 | |||
| 1564 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1565 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 | ||
| 1566 | #define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) | ||
| 1567 | |||
| 1568 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1569 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 | ||
| 1570 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) | ||
| 1571 | |||
| 1572 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1573 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 | ||
| 1574 | #define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) | ||
| 1575 | |||
| 1576 | /* Used by PRM_IRQENABLE_MPU_2 */ | ||
| 1577 | #define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 | ||
| 1578 | #define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) | ||
| 1579 | |||
| 1580 | /* Used by PRM_IRQSTATUS_MPU_2 */ | ||
| 1581 | #define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 | ||
| 1582 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) | 95 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
| 1583 | |||
| 1584 | /* Used by PRM_SRAM_COUNT */ | ||
| 1585 | #define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 | ||
| 1586 | #define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
| 1587 | |||
| 1588 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ | ||
| 1589 | #define OMAP4430_VSTEPMAX_SHIFT 0 | 96 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
| 1590 | #define OMAP4430_VSTEPMAX_MASK (0xff << 0) | ||
| 1591 | |||
| 1592 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ | ||
| 1593 | #define OMAP4430_VSTEPMIN_SHIFT 0 | 97 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
| 1594 | #define OMAP4430_VSTEPMIN_MASK (0xff << 0) | ||
| 1595 | |||
| 1596 | /* Used by PRM_MODEM_IF_CTRL */ | ||
| 1597 | #define OMAP4430_WAKE_MODEM_SHIFT 0 | ||
| 1598 | #define OMAP4430_WAKE_MODEM_MASK (1 << 0) | ||
| 1599 | |||
| 1600 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1601 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 | ||
| 1602 | #define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) | ||
| 1603 | |||
| 1604 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1605 | #define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 | ||
| 1606 | #define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) | ||
| 1607 | |||
| 1608 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1609 | #define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 | ||
| 1610 | #define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) | ||
| 1611 | |||
| 1612 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1613 | #define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 | ||
| 1614 | #define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) | ||
| 1615 | |||
| 1616 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
| 1617 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 | ||
| 1618 | #define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) | ||
| 1619 | |||
| 1620 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
| 1621 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 | ||
| 1622 | #define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) | ||
| 1623 | |||
| 1624 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
| 1625 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 | ||
| 1626 | #define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) | ||
| 1627 | |||
| 1628 | /* Used by PM_ABE_DMIC_WKDEP */ | ||
| 1629 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 | ||
| 1630 | #define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) | ||
| 1631 | |||
| 1632 | /* Used by PM_L4PER_DMTIMER10_WKDEP */ | ||
| 1633 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 | ||
| 1634 | #define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) | ||
| 1635 | |||
| 1636 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
| 1637 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 | ||
| 1638 | #define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) | ||
| 1639 | |||
| 1640 | /* Used by PM_L4PER_DMTIMER11_WKDEP */ | ||
| 1641 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 | ||
| 1642 | #define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) | ||
| 1643 | |||
| 1644 | /* Used by PM_L4PER_DMTIMER2_WKDEP */ | ||
| 1645 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 | ||
| 1646 | #define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) | ||
| 1647 | |||
| 1648 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
| 1649 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 | ||
| 1650 | #define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) | ||
| 1651 | |||
| 1652 | /* Used by PM_L4PER_DMTIMER3_WKDEP */ | ||
| 1653 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 | ||
| 1654 | #define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) | ||
| 1655 | |||
| 1656 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
| 1657 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 | ||
| 1658 | #define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) | ||
| 1659 | |||
| 1660 | /* Used by PM_L4PER_DMTIMER4_WKDEP */ | ||
| 1661 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 | ||
| 1662 | #define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) | ||
| 1663 | |||
| 1664 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
| 1665 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 | ||
| 1666 | #define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) | ||
| 1667 | |||
| 1668 | /* Used by PM_L4PER_DMTIMER9_WKDEP */ | ||
| 1669 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 | ||
| 1670 | #define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) | ||
| 1671 | |||
| 1672 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1673 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 | ||
| 1674 | #define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) | ||
| 1675 | |||
| 1676 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1677 | #define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 | ||
| 1678 | #define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) | ||
| 1679 | |||
| 1680 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1681 | #define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 | ||
| 1682 | #define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) | ||
| 1683 | |||
| 1684 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1685 | #define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 | ||
| 1686 | #define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) | ||
| 1687 | |||
| 1688 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1689 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 | ||
| 1690 | #define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) | ||
| 1691 | |||
| 1692 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1693 | #define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 | ||
| 1694 | #define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) | ||
| 1695 | |||
| 1696 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1697 | #define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 | ||
| 1698 | #define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) | ||
| 1699 | |||
| 1700 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1701 | #define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 | ||
| 1702 | #define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) | ||
| 1703 | |||
| 1704 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
| 1705 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 | ||
| 1706 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) | ||
| 1707 | |||
| 1708 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
| 1709 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 | ||
| 1710 | #define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) | ||
| 1711 | |||
| 1712 | /* Used by PM_WKUP_GPIO1_WKDEP */ | ||
| 1713 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 | ||
| 1714 | #define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) | ||
| 1715 | |||
| 1716 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
| 1717 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 | ||
| 1718 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) | ||
| 1719 | |||
| 1720 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
| 1721 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 | ||
| 1722 | #define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) | ||
| 1723 | |||
| 1724 | /* Used by PM_L4PER_GPIO2_WKDEP */ | ||
| 1725 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 | ||
| 1726 | #define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) | ||
| 1727 | |||
| 1728 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
| 1729 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 | ||
| 1730 | #define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) | ||
| 1731 | |||
| 1732 | /* Used by PM_L4PER_GPIO3_WKDEP */ | ||
| 1733 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 | ||
| 1734 | #define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) | ||
| 1735 | |||
| 1736 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
| 1737 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 | ||
| 1738 | #define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) | ||
| 1739 | |||
| 1740 | /* Used by PM_L4PER_GPIO4_WKDEP */ | ||
| 1741 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 | ||
| 1742 | #define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) | ||
| 1743 | |||
| 1744 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
| 1745 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 | ||
| 1746 | #define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) | ||
| 1747 | |||
| 1748 | /* Used by PM_L4PER_GPIO5_WKDEP */ | ||
| 1749 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 | ||
| 1750 | #define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) | ||
| 1751 | |||
| 1752 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
| 1753 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 | ||
| 1754 | #define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) | ||
| 1755 | |||
| 1756 | /* Used by PM_L4PER_GPIO6_WKDEP */ | ||
| 1757 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 | ||
| 1758 | #define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) | ||
| 1759 | |||
| 1760 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1761 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 | ||
| 1762 | #define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) | ||
| 1763 | |||
| 1764 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1765 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 | ||
| 1766 | #define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) | ||
| 1767 | |||
| 1768 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1769 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 | ||
| 1770 | #define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) | ||
| 1771 | |||
| 1772 | /* Used by PM_DSS_DSS_WKDEP */ | ||
| 1773 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 | ||
| 1774 | #define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) | ||
| 1775 | |||
| 1776 | /* Used by PM_L4PER_HECC1_WKDEP */ | ||
| 1777 | #define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 | ||
| 1778 | #define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) | ||
| 1779 | |||
| 1780 | /* Used by PM_L4PER_HECC2_WKDEP */ | ||
| 1781 | #define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 | ||
| 1782 | #define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) | ||
| 1783 | |||
| 1784 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
| 1785 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 | ||
| 1786 | #define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) | ||
| 1787 | |||
| 1788 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
| 1789 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 | ||
| 1790 | #define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) | ||
| 1791 | |||
| 1792 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
| 1793 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 | ||
| 1794 | #define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) | ||
| 1795 | |||
| 1796 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
| 1797 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 | ||
| 1798 | #define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) | ||
| 1799 | |||
| 1800 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
| 1801 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 | ||
| 1802 | #define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) | ||
| 1803 | |||
| 1804 | /* Used by PM_L4PER_I2C1_WKDEP */ | ||
| 1805 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 | ||
| 1806 | #define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) | ||
| 1807 | |||
| 1808 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
| 1809 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 | ||
| 1810 | #define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) | ||
| 1811 | |||
| 1812 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
| 1813 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 | ||
| 1814 | #define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) | ||
| 1815 | |||
| 1816 | /* Used by PM_L4PER_I2C2_WKDEP */ | ||
| 1817 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 | ||
| 1818 | #define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) | ||
| 1819 | |||
| 1820 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
| 1821 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 | ||
| 1822 | #define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) | ||
| 1823 | |||
| 1824 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
| 1825 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 | ||
| 1826 | #define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) | ||
| 1827 | |||
| 1828 | /* Used by PM_L4PER_I2C3_WKDEP */ | ||
| 1829 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 | ||
| 1830 | #define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) | ||
| 1831 | |||
| 1832 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
| 1833 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 | ||
| 1834 | #define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) | ||
| 1835 | |||
| 1836 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
| 1837 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 | ||
| 1838 | #define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) | ||
| 1839 | |||
| 1840 | /* Used by PM_L4PER_I2C4_WKDEP */ | ||
| 1841 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 | ||
| 1842 | #define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) | ||
| 1843 | |||
| 1844 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
| 1845 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 | ||
| 1846 | #define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) | ||
| 1847 | |||
| 1848 | /* Used by PM_L4PER_I2C5_WKDEP */ | ||
| 1849 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 | ||
| 1850 | #define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) | ||
| 1851 | |||
| 1852 | /* Used by PM_WKUP_KEYBOARD_WKDEP */ | ||
| 1853 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 | ||
| 1854 | #define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) | ||
| 1855 | |||
| 1856 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
| 1857 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 | ||
| 1858 | #define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) | ||
| 1859 | |||
| 1860 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
| 1861 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 | ||
| 1862 | #define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) | ||
| 1863 | |||
| 1864 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
| 1865 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 | ||
| 1866 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) | ||
| 1867 | |||
| 1868 | /* Used by PM_ABE_MCASP_WKDEP */ | ||
| 1869 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 | ||
| 1870 | #define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) | ||
| 1871 | |||
| 1872 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
| 1873 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 | ||
| 1874 | #define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) | ||
| 1875 | |||
| 1876 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
| 1877 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 | ||
| 1878 | #define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) | ||
| 1879 | |||
| 1880 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
| 1881 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 | ||
| 1882 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) | ||
| 1883 | |||
| 1884 | /* Used by PM_L4PER_MCASP2_WKDEP */ | ||
| 1885 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 | ||
| 1886 | #define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) | ||
| 1887 | |||
| 1888 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
| 1889 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 | ||
| 1890 | #define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) | ||
| 1891 | |||
| 1892 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
| 1893 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 | ||
| 1894 | #define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) | ||
| 1895 | |||
| 1896 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
| 1897 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 | ||
| 1898 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) | ||
| 1899 | |||
| 1900 | /* Used by PM_L4PER_MCASP3_WKDEP */ | ||
| 1901 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 | ||
| 1902 | #define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) | ||
| 1903 | |||
| 1904 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
| 1905 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 | ||
| 1906 | #define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) | ||
| 1907 | |||
| 1908 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
| 1909 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 | ||
| 1910 | #define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) | ||
| 1911 | |||
| 1912 | /* Used by PM_ABE_MCBSP1_WKDEP */ | ||
| 1913 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 | ||
| 1914 | #define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) | ||
| 1915 | |||
| 1916 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
| 1917 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 | ||
| 1918 | #define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) | ||
| 1919 | |||
| 1920 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
| 1921 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 | ||
| 1922 | #define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) | ||
| 1923 | |||
| 1924 | /* Used by PM_ABE_MCBSP2_WKDEP */ | ||
| 1925 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 | ||
| 1926 | #define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) | ||
| 1927 | |||
| 1928 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
| 1929 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 | ||
| 1930 | #define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) | ||
| 1931 | |||
| 1932 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
| 1933 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 | ||
| 1934 | #define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) | ||
| 1935 | |||
| 1936 | /* Used by PM_ABE_MCBSP3_WKDEP */ | ||
| 1937 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 | ||
| 1938 | #define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) | ||
| 1939 | |||
| 1940 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
| 1941 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 | ||
| 1942 | #define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) | ||
| 1943 | |||
| 1944 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
| 1945 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 | ||
| 1946 | #define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) | ||
| 1947 | |||
| 1948 | /* Used by PM_L4PER_MCBSP4_WKDEP */ | ||
| 1949 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 | ||
| 1950 | #define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) | ||
| 1951 | |||
| 1952 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
| 1953 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 | ||
| 1954 | #define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) | ||
| 1955 | |||
| 1956 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
| 1957 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 | ||
| 1958 | #define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) | ||
| 1959 | |||
| 1960 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
| 1961 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 | ||
| 1962 | #define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) | ||
| 1963 | |||
| 1964 | /* Used by PM_L4PER_MCSPI1_WKDEP */ | ||
| 1965 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 | ||
| 1966 | #define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) | ||
| 1967 | |||
| 1968 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
| 1969 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 | ||
| 1970 | #define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) | ||
| 1971 | |||
| 1972 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
| 1973 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 | ||
| 1974 | #define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) | ||
| 1975 | |||
| 1976 | /* Used by PM_L4PER_MCSPI2_WKDEP */ | ||
| 1977 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 | ||
| 1978 | #define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) | ||
| 1979 | |||
| 1980 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
| 1981 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 | ||
| 1982 | #define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) | ||
| 1983 | |||
| 1984 | /* Used by PM_L4PER_MCSPI3_WKDEP */ | ||
| 1985 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 | ||
| 1986 | #define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) | ||
| 1987 | |||
| 1988 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
| 1989 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 | ||
| 1990 | #define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) | ||
| 1991 | |||
| 1992 | /* Used by PM_L4PER_MCSPI4_WKDEP */ | ||
| 1993 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 | ||
| 1994 | #define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) | ||
| 1995 | |||
| 1996 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
| 1997 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 | ||
| 1998 | #define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) | ||
| 1999 | |||
| 2000 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
| 2001 | #define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 | ||
| 2002 | #define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) | ||
| 2003 | |||
| 2004 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
| 2005 | #define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 | ||
| 2006 | #define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) | ||
| 2007 | |||
| 2008 | /* Used by PM_L3INIT_MMC1_WKDEP */ | ||
| 2009 | #define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 | ||
| 2010 | #define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) | ||
| 2011 | |||
| 2012 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
| 2013 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 | ||
| 2014 | #define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) | ||
| 2015 | |||
| 2016 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
| 2017 | #define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 | ||
| 2018 | #define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) | ||
| 2019 | |||
| 2020 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
| 2021 | #define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 | ||
| 2022 | #define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) | ||
| 2023 | |||
| 2024 | /* Used by PM_L3INIT_MMC2_WKDEP */ | ||
| 2025 | #define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 | ||
| 2026 | #define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) | ||
| 2027 | |||
| 2028 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
| 2029 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 | ||
| 2030 | #define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) | ||
| 2031 | |||
| 2032 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
| 2033 | #define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 | ||
| 2034 | #define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) | ||
| 2035 | |||
| 2036 | /* Used by PM_L3INIT_MMC6_WKDEP */ | ||
| 2037 | #define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 | ||
| 2038 | #define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) | ||
| 2039 | |||
| 2040 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
| 2041 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 | ||
| 2042 | #define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) | ||
| 2043 | |||
| 2044 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
| 2045 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 | ||
| 2046 | #define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) | ||
| 2047 | |||
| 2048 | /* Used by PM_L4PER_MMCSD3_WKDEP */ | ||
| 2049 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 | ||
| 2050 | #define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) | ||
| 2051 | |||
| 2052 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
| 2053 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 | ||
| 2054 | #define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) | ||
| 2055 | |||
| 2056 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
| 2057 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 | ||
| 2058 | #define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) | ||
| 2059 | |||
| 2060 | /* Used by PM_L4PER_MMCSD4_WKDEP */ | ||
| 2061 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 | ||
| 2062 | #define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) | ||
| 2063 | |||
| 2064 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
| 2065 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 | ||
| 2066 | #define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) | ||
| 2067 | |||
| 2068 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
| 2069 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 | ||
| 2070 | #define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) | ||
| 2071 | |||
| 2072 | /* Used by PM_L4PER_MMCSD5_WKDEP */ | ||
| 2073 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 | ||
| 2074 | #define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) | ||
| 2075 | |||
| 2076 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
| 2077 | #define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 | ||
| 2078 | #define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) | ||
| 2079 | |||
| 2080 | /* Used by PM_L3INIT_PCIESS_WKDEP */ | ||
| 2081 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 | ||
| 2082 | #define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) | ||
| 2083 | |||
| 2084 | /* Used by PM_ABE_PDM_WKDEP */ | ||
| 2085 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 | ||
| 2086 | #define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) | ||
| 2087 | |||
| 2088 | /* Used by PM_ABE_PDM_WKDEP */ | ||
| 2089 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 | ||
| 2090 | #define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) | ||
| 2091 | |||
| 2092 | /* Used by PM_ABE_PDM_WKDEP */ | ||
| 2093 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 | ||
| 2094 | #define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) | ||
| 2095 | |||
| 2096 | /* Used by PM_ABE_PDM_WKDEP */ | ||
| 2097 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 | ||
| 2098 | #define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) | ||
| 2099 | |||
| 2100 | /* Used by PM_WKUP_RTC_WKDEP */ | ||
| 2101 | #define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 | ||
| 2102 | #define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) | ||
| 2103 | |||
| 2104 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
| 2105 | #define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 | ||
| 2106 | #define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) | ||
| 2107 | |||
| 2108 | /* Used by PM_L3INIT_SATA_WKDEP */ | ||
| 2109 | #define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 | ||
| 2110 | #define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) | ||
| 2111 | |||
| 2112 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
| 2113 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 | ||
| 2114 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) | ||
| 2115 | |||
| 2116 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
| 2117 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 | ||
| 2118 | #define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) | ||
| 2119 | |||
| 2120 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
| 2121 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 | ||
| 2122 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) | ||
| 2123 | |||
| 2124 | /* Used by PM_ABE_SLIMBUS_WKDEP */ | ||
| 2125 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 | ||
| 2126 | #define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) | ||
| 2127 | |||
| 2128 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
| 2129 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 | ||
| 2130 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) | ||
| 2131 | |||
| 2132 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
| 2133 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 | ||
| 2134 | #define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) | ||
| 2135 | |||
| 2136 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
| 2137 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 | ||
| 2138 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) | ||
| 2139 | |||
| 2140 | /* Used by PM_L4PER_SLIMBUS2_WKDEP */ | ||
| 2141 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 | ||
| 2142 | #define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) | ||
| 2143 | |||
| 2144 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
| 2145 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 | ||
| 2146 | #define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) | ||
| 2147 | |||
| 2148 | /* Used by PM_ALWON_SR_CORE_WKDEP */ | ||
| 2149 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 | ||
| 2150 | #define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) | ||
| 2151 | |||
| 2152 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
| 2153 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 | ||
| 2154 | #define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) | ||
| 2155 | |||
| 2156 | /* Used by PM_ALWON_SR_IVA_WKDEP */ | ||
| 2157 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 | ||
| 2158 | #define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) | ||
| 2159 | |||
| 2160 | /* Used by PM_ALWON_SR_MPU_WKDEP */ | ||
| 2161 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 | ||
| 2162 | #define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) | ||
| 2163 | |||
| 2164 | /* Used by PM_WKUP_TIMER12_WKDEP */ | ||
| 2165 | #define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 | ||
| 2166 | #define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) | ||
| 2167 | |||
| 2168 | /* Used by PM_WKUP_TIMER1_WKDEP */ | ||
| 2169 | #define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 | ||
| 2170 | #define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) | ||
| 2171 | |||
| 2172 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
| 2173 | #define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 | ||
| 2174 | #define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) | ||
| 2175 | |||
| 2176 | /* Used by PM_ABE_TIMER5_WKDEP */ | ||
| 2177 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 | ||
| 2178 | #define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) | ||
| 2179 | |||
| 2180 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
| 2181 | #define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 | ||
| 2182 | #define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) | ||
| 2183 | |||
| 2184 | /* Used by PM_ABE_TIMER6_WKDEP */ | ||
| 2185 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 | ||
| 2186 | #define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) | ||
| 2187 | |||
| 2188 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
| 2189 | #define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 | ||
| 2190 | #define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) | ||
| 2191 | |||
| 2192 | /* Used by PM_ABE_TIMER7_WKDEP */ | ||
| 2193 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 | ||
| 2194 | #define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) | ||
| 2195 | |||
| 2196 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
| 2197 | #define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 | ||
| 2198 | #define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) | ||
| 2199 | |||
| 2200 | /* Used by PM_ABE_TIMER8_WKDEP */ | ||
| 2201 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 | ||
| 2202 | #define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) | ||
| 2203 | |||
| 2204 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
| 2205 | #define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 | ||
| 2206 | #define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) | ||
| 2207 | |||
| 2208 | /* Used by PM_L4PER_UART1_WKDEP */ | ||
| 2209 | #define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 | ||
| 2210 | #define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) | ||
| 2211 | |||
| 2212 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
| 2213 | #define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 | ||
| 2214 | #define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) | ||
| 2215 | |||
| 2216 | /* Used by PM_L4PER_UART2_WKDEP */ | ||
| 2217 | #define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 | ||
| 2218 | #define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) | ||
| 2219 | |||
| 2220 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
| 2221 | #define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 | ||
| 2222 | #define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) | ||
| 2223 | |||
| 2224 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
| 2225 | #define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 | ||
| 2226 | #define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) | ||
| 2227 | |||
| 2228 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
| 2229 | #define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 | ||
| 2230 | #define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) | ||
| 2231 | |||
| 2232 | /* Used by PM_L4PER_UART3_WKDEP */ | ||
| 2233 | #define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 | ||
| 2234 | #define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) | ||
| 2235 | |||
| 2236 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
| 2237 | #define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 | ||
| 2238 | #define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) | ||
| 2239 | |||
| 2240 | /* Used by PM_L4PER_UART4_WKDEP */ | ||
| 2241 | #define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 | ||
| 2242 | #define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) | ||
| 2243 | |||
| 2244 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
| 2245 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 | ||
| 2246 | #define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) | ||
| 2247 | |||
| 2248 | /* Used by PM_L3INIT_UNIPRO1_WKDEP */ | ||
| 2249 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 | ||
| 2250 | #define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) | ||
| 2251 | |||
| 2252 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
| 2253 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 | ||
| 2254 | #define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) | ||
| 2255 | |||
| 2256 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
| 2257 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 | ||
| 2258 | #define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) | ||
| 2259 | |||
| 2260 | /* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ | ||
| 2261 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 | ||
| 2262 | #define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) | ||
| 2263 | |||
| 2264 | /* Used by PM_L3INIT_USB_HOST_WKDEP */ | ||
| 2265 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 | ||
| 2266 | #define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) | ||
| 2267 | |||
| 2268 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
| 2269 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 | ||
| 2270 | #define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) | ||
| 2271 | |||
| 2272 | /* Used by PM_L3INIT_USB_OTG_WKDEP */ | ||
| 2273 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 | ||
| 2274 | #define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) | ||
| 2275 | |||
| 2276 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
| 2277 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 | ||
| 2278 | #define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) | ||
| 2279 | |||
| 2280 | /* Used by PM_L3INIT_USB_TLL_WKDEP */ | ||
| 2281 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 | ||
| 2282 | #define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) | ||
| 2283 | |||
| 2284 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
| 2285 | #define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 | ||
| 2286 | #define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) | ||
| 2287 | |||
| 2288 | /* Used by PM_WKUP_USIM_WKDEP */ | ||
| 2289 | #define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 | ||
| 2290 | #define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) | ||
| 2291 | |||
| 2292 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
| 2293 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 | ||
| 2294 | #define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) | ||
| 2295 | |||
| 2296 | /* Used by PM_WKUP_WDT2_WKDEP */ | ||
| 2297 | #define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 | ||
| 2298 | #define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) | ||
| 2299 | |||
| 2300 | /* Used by PM_ABE_WDT3_WKDEP */ | ||
| 2301 | #define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 | ||
| 2302 | #define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) | ||
| 2303 | |||
| 2304 | /* Used by PM_L3INIT_HSI_WKDEP */ | ||
| 2305 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 | ||
| 2306 | #define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) | ||
| 2307 | |||
| 2308 | /* Used by PM_L3INIT_XHPI_WKDEP */ | ||
| 2309 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 | ||
| 2310 | #define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) | ||
| 2311 | |||
| 2312 | /* Used by PRM_IO_PMCTRL */ | ||
| 2313 | #define OMAP4430_WUCLK_CTRL_SHIFT 8 | ||
| 2314 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) | 98 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
| 2315 | |||
| 2316 | /* Used by PRM_IO_PMCTRL */ | ||
| 2317 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 | 99 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
| 2318 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) | 100 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
| 2319 | |||
| 2320 | /* Used by REVISION_PRM */ | ||
| 2321 | #define OMAP4430_X_MAJOR_SHIFT 8 | ||
| 2322 | #define OMAP4430_X_MAJOR_MASK (0x7 << 8) | ||
| 2323 | |||
| 2324 | /* Used by REVISION_PRM */ | ||
| 2325 | #define OMAP4430_Y_MINOR_SHIFT 0 | ||
| 2326 | #define OMAP4430_Y_MINOR_MASK (0x3f << 0) | ||
| 2327 | #endif | 101 | #endif |