Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "This weeks' round of MIPS bug fixes for 3.18:

   - wire up the bpf syscall
   - fix TLB dump output for R3000 class TLBs
   - fix strnlen_user return value if no NUL character was found.
   - fix build with binutils 2.24.51+.  While there is no binutils 2.25
     release yet, toolchains derived from binutils 2.24.51+ are already
     in common use.
   - the Octeon GPIO code forgot to offline GPIO IRQs.
   - fix build error for XLP.
   - fix possible BUG assertion with EVA for CMA"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Fix build with binutils 2.24.51+
  MIPS: R3000: Fix debug output for Virtual page number
  MIPS: Fix strnlen_user() return value in case of overlong strings.
  MIPS: CMA: Do not reserve memory if not required
  MIPS: Wire up bpf syscall.
  MIPS/Xlp: Remove the dead function destroy_irq() to fix build error
  MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware

24 files changed, 142 insertions, 31 deletions

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 23cb94806fbc..58076472bdd8 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE            += -mlong-calls
 KBUILD_CFLAGS_MODULE            += -mlong-calls
 
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+        cflags-y                += -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
+
 cflags-y += -ffreestanding
 
 #
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 741734049675..2bc4aa95944e 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -809,6 +809,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
         .irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
         .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
         .flags = IRQCHIP_SET_TYPE_MASKED,
 };
@@ -823,6 +824,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
         .irq_set_type = octeon_irq_ciu_gpio_set_type,
 #ifdef CONFIG_SMP
         .irq_set_affinity = octeon_irq_ciu_set_affinity,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
         .flags = IRQCHIP_SET_TYPE_MASKED,
 };
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index e38c2811d4e2..cdac7b3eeaf7 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
 #include <asm/mipsregs.h>
 
         .macro  fpu_save_single thread tmp=t0
+        .set push
+        SET_HARDFLOAT
         cfc1    \tmp,  fcr31
         swc1    $f0,  THREAD_FPR0_LS64(\thread)
         swc1    $f1,  THREAD_FPR1_LS64(\thread)
@@ -47,9 +49,12 @@
         swc1    $f30, THREAD_FPR30_LS64(\thread)
         swc1    $f31, THREAD_FPR31_LS64(\thread)
         sw      \tmp, THREAD_FCR31(\thread)
+        .set pop
         .endm
 
         .macro  fpu_restore_single thread tmp=t0
+        .set push
+        SET_HARDFLOAT
         lw      \tmp, THREAD_FCR31(\thread)
         lwc1    $f0,  THREAD_FPR0_LS64(\thread)
         lwc1    $f1,  THREAD_FPR1_LS64(\thread)
@@ -84,6 +89,7 @@
         lwc1    $f30, THREAD_FPR30_LS64(\thread)
         lwc1    $f31, THREAD_FPR31_LS64(\thread)
         ctc1    \tmp, fcr31
+        .set pop
         .endm
 
         .macro  cpu_save_nonscratch thread
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index cd9a98bc8f60..6caf8766b80f 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -57,6 +57,8 @@
 #endif /* CONFIG_CPU_MIPSR2 */
 
         .macro  fpu_save_16even thread tmp=t0
+        .set    push
+        SET_HARDFLOAT
         cfc1    \tmp, fcr31
         sdc1    $f0,  THREAD_FPR0_LS64(\thread)
         sdc1    $f2,  THREAD_FPR2_LS64(\thread)
@@ -75,11 +77,13 @@
         sdc1    $f28, THREAD_FPR28_LS64(\thread)
         sdc1    $f30, THREAD_FPR30_LS64(\thread)
         sw      \tmp, THREAD_FCR31(\thread)
+        .set    pop
         .endm
 
         .macro  fpu_save_16odd thread
         .set    push
         .set    mips64r2
+        SET_HARDFLOAT
         sdc1    $f1,  THREAD_FPR1_LS64(\thread)
         sdc1    $f3,  THREAD_FPR3_LS64(\thread)
         sdc1    $f5,  THREAD_FPR5_LS64(\thread)
@@ -110,6 +114,8 @@
         .endm
 
         .macro  fpu_restore_16even thread tmp=t0
+        .set    push
+        SET_HARDFLOAT
         lw      \tmp, THREAD_FCR31(\thread)
         ldc1    $f0,  THREAD_FPR0_LS64(\thread)
         ldc1    $f2,  THREAD_FPR2_LS64(\thread)
@@ -133,6 +139,7 @@
         .macro  fpu_restore_16odd thread
         .set    push
         .set    mips64r2
+        SET_HARDFLOAT
         ldc1    $f1,  THREAD_FPR1_LS64(\thread)
         ldc1    $f3,  THREAD_FPR3_LS64(\thread)
         ldc1    $f5,  THREAD_FPR5_LS64(\thread)
@@ -277,6 +284,7 @@
         .macro  cfcmsa  rd, cs
         .set    push
         .set    noat
+        SET_HARDFLOAT
         .insn
         .word   CFC_MSA_INSN | (\cs << 11)
         move    \rd, $1
@@ -286,6 +294,7 @@
         .macro  ctcmsa  cd, rs
         .set    push
         .set    noat
+        SET_HARDFLOAT
         move    $1, \rs
         .word   CTC_MSA_INSN | (\cd << 6)
         .set    pop
@@ -294,6 +303,7 @@
         .macro  ld_d    wd, off, base
         .set    push
         .set    noat
+        SET_HARDFLOAT
         add     $1, \base, \off
         .word   LDD_MSA_INSN | (\wd << 6)
         .set    pop
@@ -302,6 +312,7 @@
         .macro  st_d    wd, off, base
         .set    push
         .set    noat
+        SET_HARDFLOAT
         add     $1, \base, \off
         .word   STD_MSA_INSN | (\wd << 6)
         .set    pop
@@ -310,6 +321,7 @@
         .macro  copy_u_w        rd, ws, n
         .set    push
         .set    noat
+        SET_HARDFLOAT
         .insn
         .word   COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
         /* move triggers an assembler bug... */
@@ -320,6 +332,7 @@
         .macro  copy_u_d        rd, ws, n
         .set    push
         .set    noat
+        SET_HARDFLOAT
         .insn
         .word   COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
         /* move triggers an assembler bug... */
@@ -330,6 +343,7 @@
         .macro  insert_w        wd, n, rs
         .set    push
         .set    noat
+        SET_HARDFLOAT
         /* move triggers an assembler bug... */
         or      $1, \rs, zero
         .word   INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -339,6 +353,7 @@
         .macro  insert_d        wd, n, rs
         .set    push
         .set    noat
+        SET_HARDFLOAT
         /* move triggers an assembler bug... */
         or      $1, \rs, zero
         .word   INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -381,6 +396,7 @@
         st_d    31, THREAD_FPR31, \thread
         .set    push
         .set    noat
+        SET_HARDFLOAT
         cfcmsa  $1, MSA_CSR
         sw      $1, THREAD_MSA_CSR(\thread)
         .set    pop
@@ -389,6 +405,7 @@
         .macro  msa_restore_all thread
         .set    push
         .set    noat
+        SET_HARDFLOAT
         lw      $1, THREAD_MSA_CSR(\thread)
         ctcmsa  MSA_CSR, $1
         .set    pop
@@ -441,6 +458,7 @@
         .macro  msa_init_all_upper
         .set    push
         .set    noat
+        SET_HARDFLOAT
         not     $1, zero
         msa_init_upper  0
         .set    pop
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 429481f9028d..f184ba088532 100644
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
 
 #include <asm/sgidefs.h>
 
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 4d0aeda68397..dd562414cd5e 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -145,8 +145,8 @@ static inline void lose_fpu(int save)
         if (is_msa_enabled()) {
                 if (save) {
                         save_msa(current);
-                        asm volatile("cfc1 %0, $31"
-                                : "=r"(current->thread.fpu.fcr31));
+                        current->thread.fpu.fcr31 =
+                                        read_32bit_cp1_register(CP1_STATUS);
                 }
                 disable_msa();
                 clear_thread_flag(TIF_USEDMSA);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index cf3b580c3df6..b46cd220a018 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1324,7 +1324,7 @@ do {									\
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)                                 \
+#define _read_32bit_cp1_register(source, gas_hardfloat)                 \
 ({                                                                      \
         int __res;                                                      \
                                                                         \
@@ -1334,12 +1334,21 @@ do {									\
         "       # gas fails to assemble cfc1 for some archs,    \n"     \
         "       # like Octeon.                                  \n"     \
         "       .set    mips1                                   \n"     \
+        "       "STR(gas_hardfloat)"                            \n"     \
         "       cfc1    %0,"STR(source)"                        \n"     \
         "       .set    pop                                     \n"     \
         : "=r" (__res));                                                \
         __res;                                                          \
 })
 
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)                                 \
+        _read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)                                 \
+        _read_32bit_cp1_register(source, )
+#endif
+
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)                                                     \
 ({                                                                      \
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index fdb4923777d1..9dc58568f230 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -375,16 +375,17 @@
 #define __NR_seccomp                    (__NR_Linux + 352)
 #define __NR_getrandom                  (__NR_Linux + 353)
 #define __NR_memfd_create               (__NR_Linux + 354)
+#define __NR_bpf                        (__NR_Linux + 355)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             354
+#define __NR_Linux_syscalls             355
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         354
+#define __NR_O32_Linux_syscalls         355
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -707,16 +708,17 @@
 #define __NR_seccomp                    (__NR_Linux + 312)
 #define __NR_getrandom                  (__NR_Linux + 313)
 #define __NR_memfd_create               (__NR_Linux + 314)
+#define __NR_bpf                        (__NR_Linux + 315)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             314
+#define __NR_Linux_syscalls             315
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          314
+#define __NR_64_Linux_syscalls          315
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -1043,15 +1045,16 @@
 #define __NR_seccomp                    (__NR_Linux + 316)
 #define __NR_getrandom                  (__NR_Linux + 317)
 #define __NR_memfd_create               (__NR_Linux + 318)
+#define __NR_memfd_create               (__NR_Linux + 319)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             318
+#define __NR_Linux_syscalls             319
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         318
+#define __NR_N32_Linux_syscalls         319
 
 #endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df224f041..4d7d99d601cc 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                 case mm_bc1t_op:
                         preempt_disable();
                         if (is_fpu_owner())
-                                asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+                                fcr31 = read_32bit_cp1_register(CP1_STATUS);
                         else
                                 fcr31 = current->thread.fpu.fcr31;
                         preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
         case cop1_op:
                 preempt_disable();
                 if (is_fpu_owner())
-                        asm volatile(
-                                ".set push\n"
-                                "\t.set mips1\n"
-                                "\tcfc1\t%0,$31\n"
-                                "\t.set pop" : "=r" (fcr31));
+                        fcr31 = read_32bit_cp1_register(CP1_STATUS);
                 else
                         fcr31 = current->thread.fpu.fcr31;
                 preempt_enable();
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac35e12cb1f3..a5e26dd90592 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
         .set    push
         /* gas fails to assemble cfc1 for some archs (octeon).*/ \
         .set    mips1
+        SET_HARDFLOAT
         cfc1    a1, fcr31
         li      a2, ~(0x3f << 12)
         and     a2, a1
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index f31063dbdaeb..5ce3b746cedc 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
         .set    mips1
         /* Save floating point context */
 LEAF(_save_fp_context)
+        .set    push
+        SET_HARDFLOAT
         li      v0, 0                                   # assume success
         cfc1    t1,fcr31
         EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
         EX(sw   t1,(SC_FPC_CSR)(a0))
         cfc1    t0,$0                           # implementation/version
         jr      ra
+        .set    pop
         .set    nomacro
          EX(sw  t0,(SC_FPC_EIR)(a0))
         .set    macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
  * stack frame which might have been changed by the user.
  */
 LEAF(_restore_fp_context)
+        .set    push
+        SET_HARDFLOAT
         li      v0, 0                                   # assume success
         EX(lw t0,(SC_FPC_CSR)(a0))
         EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
         EX(lwc1 $f31,(SC_FPREGS+248)(a0))
         jr      ra
          ctc1   t0,fcr31
+        .set    pop
         END(_restore_fp_context)
         .set    reorder
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 20b7b040e76f..435ea652f5fa 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+        .set push
+        SET_HARDFLOAT
+
 LEAF(_init_fpu)
         mfc0    t0, CP0_STATUS
         li      t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
         mtc1    t0, $f31
         jr      ra
         END(_init_fpu)
+
+        .set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8352523568e6..6c160c67984c 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
         .macro  EX insn, reg, src
         .set    push
+        SET_HARDFLOAT
         .set    nomacro
 .ex\@:  \insn   \reg, \src
         .set    pop
@@ -33,12 +37,17 @@
         .set    arch=r4000
 
 LEAF(_save_fp_context)
+        .set    push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
+        .set    pop
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         .set    push
+        SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         mfc0    t0, CP0_STATUS
         sll     t0, t0, 5
         bgez    t0, 1f                  # skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
 1:      .set    pop
 #endif
 
+        .set push
+        SET_HARDFLOAT
         /* Store the 16 even double precision registers */
         EX      sdc1 $f0, SC_FPREGS+0(a0)
         EX      sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
         EX      sw t1, SC_FPC_CSR(a0)
         jr      ra
          li     v0, 0                                   # success
+        .set pop
         END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
         /* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
+        .set push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
 
         mfc0    t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
         EX      sw t1, SC32_FPC_CSR(a0)
         cfc1    t0, $0                          # implementation/version
         EX      sw t0, SC32_FPC_EIR(a0)
+        .set pop
 
         jr      ra
          li     v0, 0                                   # success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
         .set    push
+        SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         mfc0    t0, CP0_STATUS
         sll     t0, t0, 5
         bgez    t0, 1f                  # skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
         EX      ldc1 $f31, SC_FPREGS+248(a0)
 1:      .set pop
 #endif
+        .set push
+        SET_HARDFLOAT
         EX      ldc1 $f0, SC_FPREGS+0(a0)
         EX      ldc1 $f2, SC_FPREGS+16(a0)
         EX      ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
         EX      ldc1 $f28, SC_FPREGS+224(a0)
         EX      ldc1 $f30, SC_FPREGS+240(a0)
         ctc1    t1, fcr31
+        .set pop
         jr      ra
          li     v0, 0                                   # success
         END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 LEAF(_restore_fp_context32)
         /* Restore an o32 sigcontext.  */
+        .set push
+        SET_HARDFLOAT
         EX      lw t1, SC32_FPC_CSR(a0)
 
         mfc0    t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
         ctc1    t1, fcr31
         jr      ra
          li     v0, 0                                   # success
+        .set pop
         END(_restore_fp_context32)
 #endif
 
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 4c4ec1812420..64591e671878 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
 
 #include <asm/asmmacro.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
@@ -65,8 +68,12 @@
         bgtz    a3, 1f
 
         /* Save 128b MSA vector context + scalar FP control & status. */
+        .set push
+        SET_HARDFLOAT
         cfc1    t1, fcr31
         msa_save_all    a0
+        .set pop        /* SET_HARDFLOAT */
+
         sw      t1, THREAD_FCR31(a0)
         b       2f
 
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
 
 #define FPU_DEFAULT  0x00000000
 
+        .set push
+        SET_HARDFLOAT
+
 LEAF(_init_fpu)
         mfc0    t0, CP0_STATUS
         li      t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
 
 #ifdef CONFIG_CPU_MIPS32_R2
         .set    push
-        .set    mips64r2
+        .set    mips32r2
+        .set    fp=64
         sll     t0, t0, 5                       # is Status.FR set?
         bgez    t0, 1f                          # no: skip setting upper 32b
 
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
 #endif
         jr      ra
         END(_init_fpu)
+
+        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index da0fbe46d83b..47077380c15c 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
 
         .set    noreorder
         .set    mips2
+        .set    push
+        SET_HARDFLOAT
+
         /* Save floating point context */
         LEAF(_save_fp_context)
         mfc0    t0,CP0_STATUS
@@ -85,3 +88,5 @@
 1:      jr      ra
          nop
         END(_restore_fp_context)
+
+        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 744cd10ba599..00cad1005a16 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -579,3 +579,4 @@ EXPORT(sys_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 4355 */
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 002b1bc09c38..5251565e344b 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -434,4 +434,5 @@ EXPORT(sys_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 5315 */
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index ca6cbbe9805b..77e74398b828 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -427,4 +427,5 @@ EXPORT(sysn32_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 9e10d11fbb84..6f8db9f728e8 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -564,4 +564,5 @@ EXPORT(sys32_call_table)
         PTR     sys_seccomp
         PTR     sys_getrandom
         PTR     sys_memfd_create
+        PTR     sys_bpf                         /* 4355 */
         .size   sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b3b8f0d9d4a7..d21ec57b6e95 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -683,7 +683,8 @@ static void __init arch_mem_init(char **cmdline_p)
         dma_contiguous_reserve(PFN_PHYS(max_low_pfn));
         /* Tell bootmem about cma reserved memblock section */
         for_each_memblock(reserved, reg)
-                reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+                if (reg->size != 0)
+                        reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
 }
 
 static void __init resource_init(void)
diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 91615c2ef0cf..1ef365ab3cd3 100644
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -34,7 +34,7 @@ static void dump_tlb(int first, int last)
                 entrylo0 = read_c0_entrylo0();
 
                 /* Unused entries have a virtual address of KSEG0.  */
-                if ((entryhi & 0xffffe000) != 0x80000000
+                if ((entryhi & 0xfffff000) != 0x80000000
                     && (entryhi & 0xfc0) == asid) {
                         /*
                          * Only print entries in use
@@ -43,7 +43,7 @@ static void dump_tlb(int first, int last)
 
                         printk("va=%08lx asid=%08lx"
                                "  [pa=%06lx n=%d d=%d v=%d g=%d]",
-                               (entryhi & 0xffffe000),
+                               (entryhi & 0xfffff000),
                                entryhi & 0xfc0,
                                entrylo0 & PAGE_MASK,
                                (entrylo0 & (1 << 11)) ? 1 : 0,
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index f3af6995e2a6..7d12c0dded3d 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -40,9 +40,11 @@ FEXPORT(__strnlen_\func\()_nocheck_asm)
 .else
         EX(lbe, t0, (v0), .Lfault\@)
 .endif
-        PTR_ADDIU       v0, 1
+        .set            noreorder
         bnez            t0, 1b
-1:      PTR_SUBU        v0, a0
+1:       PTR_ADDIU      v0, 1
+        .set            reorder
+        PTR_SUBU        v0, a0
         jr              ra
         END(__strnlen_\func\()_asm)
 
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 51a0fde4bec1..cac529a405b8 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -584,11 +584,7 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                 if (insn.i_format.rs == bc_op) {
                         preempt_disable();
                         if (is_fpu_owner())
-                                asm volatile(
-                                        ".set push\n"
-                                        "\t.set mips1\n"
-                                        "\tcfc1\t%0,$31\n"
-                                        "\t.set pop" : "=r" (fcr31));
+                                fcr31 = read_32bit_cp1_register(CP1_STATUS);
                         else
                                 fcr31 = current->thread.fpu.fcr31;
                         preempt_enable();
diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c
index fa374fe3746b..f7ac3edda1b2 100644
--- a/arch/mips/pci/msi-xlp.c
+++ b/arch/mips/pci/msi-xlp.c
@@ -443,10 +443,8 @@ static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
         msg.data = 0xc00 | msixvec;
 
         ret = irq_set_msi_desc(xirq, desc);
-        if (ret < 0) {
-                destroy_irq(xirq);
+        if (ret < 0)
                 return ret;
-        }
 
         write_msi_msg(xirq, &msg);
         return 0;