Merge tag 'omap-for-v3.12/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/all

From Tony Lindgren:
OMAP PRCM and hwmod fixes and improvments via Paul Walmsley <paul@pwsan.com>:

Various OMAP PRCM & hwmod fixes and improvements.  Notable changes
include:

- a fix for OMAP4 PLL locking to avoid a bootloader dependency that
  causes nasty log spew on startup

- AM33xx DEBUGSS support fixes in hwmod data

- OMAP5 mailbox support in hwmod data

Basic test logs are here:

http://www.pwsan.com/omap/testlogs/prcm_a_for_v3.12/20130823125002/

Note that the 3530 failure is due to the mysterious transient serial
issue affecting 3530 for several releases now, which causes a log
parsing failure.  PM still seems to work.

* tag 'omap-for-v3.12/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP: AM33xx: clock: Add RNG clock data
  ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
  ARM: OMAP4: clock: Lock PLLs in the right sequence
  ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
  ARM: OMAP2+: Only write the sysconfig on idle when necessary
  ARM: OMAP5: hwmod data: Add mailbox data

Signed-off-by: Olof Johansson <olof@lixom.net>

7 files changed, 118 insertions, 31 deletions

diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ba6534d7f155..865d30ee812f 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -421,6 +421,10 @@ static struct clk aes0_fck;
 DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
 DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
 
+static struct clk rng_fck;
+DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
+DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
+
 /*
  * Modules clock nodes
  *
@@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
         CLK(NULL,       "sha0_fck",             &sha0_fck),
         CLK(NULL,       "aes0_fck",             &aes0_fck),
+        CLK(NULL,       "rng_fck",              &rng_fck),
         CLK(NULL,       "timer1_fck",           &timer1_fck),
         CLK(NULL,       "timer2_fck",           &timer2_fck),
         CLK(NULL,       "timer3_fck",           &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a474334..1d5b5290d2af 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void)
         omap2_clk_disable_autoidle_all();
 
         /*
+         * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
+         * when its in bypass. So always lock USB before ABE DPLL.
+         */
+        /*
+         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
+         * domain can transition to retention state when not in use.
+         */
+        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
+        if (rc)
+                pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+        /*
          * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
          * state when turning the ABE clock domain. Workaround this by
          * locking the ABE DPLL on boot.
@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
         if (rc)
                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
 
-        /*
-         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-         * domain can transition to retention state when not in use.
-         */
-        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
         return 0;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7f4db12b1459..03e9e2f5d9a7 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1405,7 +1405,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
             (sf & SYSC_HAS_CLOCKACTIVITY))
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
-        _write_sysconfig(v, oh);
+        /* If the cached value is the same as the new value, skip the write */
+        if (oh->_sysc_cache != v)
+                _write_sysconfig(v, oh);
 
         /*
          * Set the autoidle bit only after setting the smartidle bit
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b93b51c..215894f8910d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
  *
  *    - cEFUSE (doesn't fall under any ocp_if)
  *    - clkdiv32k
- *    - debugss
  *    - ocp watch point
  */
 #if 0
@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
         },
 };
 
-/*
- * 'debugss' class
- * debug sub system
- */
-static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
-        .name           = "debugss",
-};
-
-static struct omap_hwmod am33xx_debugss_hwmod = {
-        .name           = "debugss",
-        .class          = &am33xx_debugss_hwmod_class,
-        .clkdm_name     = "l3_aon_clkdm",
-        .main_clk       = "debugss_ick",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* ocpwp */
 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
         .name           = "ocpwp",
@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
         },
 };
 
+/*
+ * 'debugss' class
+ * debug sub system
+ */
+static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
+        { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
+        { .role = "dbg_clka", .clk = "dbg_clka_ck" },
+};
+
+static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
+        .name           = "debugss",
+};
+
+static struct omap_hwmod am33xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &am33xx_debugss_hwmod_class,
+        .clkdm_name     = "l3_aon_clkdm",
+        .main_clk       = "trace_clk_div_ck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = debugss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(debugss_opt_clks),
+};
+
 /* 'smartreflex' class */
 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
         .name           = "smartreflex",
@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l3_main -> debugss */
+static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
+        {
+                .pa_start       = 0x4b000000,
+                .pa_end         = 0x4b000000 + SZ_16M - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
+        .master         = &am33xx_l3_main_hwmod,
+        .slave          = &am33xx_debugss_hwmod,
+        .clk            = "dpll_core_m4_ck",
+        .addr           = am33xx_debugss_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 /* l4 wkup -> smartreflex0 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_pruss__l3_main,
         &am33xx_wkup_m3__l4_wkup,
         &am33xx_gfx__l3_main,
+        &am33xx_l3_main__debugss,
         &am33xx_l4_wkup__wkup_m3,
         &am33xx_l4_wkup__control,
         &am33xx_l4_wkup__smartreflex0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3c70f5c1860f..7996ca5538e5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -741,6 +741,39 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
+        .name   = "mailbox",
+        .sysc   = &omap54xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap54xx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap54xx_mailbox_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
  * 'mcbsp' class
  * multi channel buffered serial port controller
  */
@@ -1808,6 +1841,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mailbox_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l4_abe -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
         .master         = &omap54xx_l4_abe_hwmod,
@@ -2108,6 +2149,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__i2c4,
         &omap54xx_l4_per__i2c5,
         &omap54xx_l4_wkup__kbd,
+        &omap54xx_l4_cfg__mailbox,
         &omap54xx_l4_abe__mcbsp1,
         &omap54xx_l4_abe__mcbsp2,
         &omap54xx_l4_abe__mcbsp3,
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e2d4bd804523..328c1037cb60 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain alwon_81xx_pwrdm = {
+        .name             = "alwon_pwrdm",
+        .prcm_offs        = TI81XX_PRM_ALWON_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain device_81xx_pwrdm = {
         .name             = "device_pwrdm",
         .prcm_offs        = TI81XX_PRM_DEVICE_MOD,
@@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
 };
 
 static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+        &alwon_81xx_pwrdm,
         &device_81xx_pwrdm,
         &active_816x_pwrdm,
         &default_816x_pwrdm,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index ff1ac4a82a04..0e841fd9498a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -58,6 +58,7 @@
 #define TI816X_PRM_IVAHD1_MOD                   0x0d00
 #define TI816X_PRM_IVAHD2_MOD                   0x0e00
 #define TI816X_PRM_SGX_MOD                              0x0f00
+#define TI81XX_PRM_ALWON_MOD                    0x1800
 
 /* 24XX register bits shared between CM & PRM registers */