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Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_33xx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c69
1 files changed, 47 insertions, 22 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b93b51c..215894f8910d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
325 * 325 *
326 * - cEFUSE (doesn't fall under any ocp_if) 326 * - cEFUSE (doesn't fall under any ocp_if)
327 * - clkdiv32k 327 * - clkdiv32k
328 * - debugss
329 * - ocp watch point 328 * - ocp watch point
330 */ 329 */
331#if 0 330#if 0
@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
369 }, 368 },
370}; 369};
371 370
372/*
373 * 'debugss' class
374 * debug sub system
375 */
376static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
377 .name = "debugss",
378};
379
380static struct omap_hwmod am33xx_debugss_hwmod = {
381 .name = "debugss",
382 .class = &am33xx_debugss_hwmod_class,
383 .clkdm_name = "l3_aon_clkdm",
384 .main_clk = "debugss_ick",
385 .prcm = {
386 .omap4 = {
387 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
388 .modulemode = MODULEMODE_SWCTRL,
389 },
390 },
391};
392
393/* ocpwp */ 371/* ocpwp */
394static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 372static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
395 .name = "ocpwp", 373 .name = "ocpwp",
@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
482 }, 460 },
483}; 461};
484 462
463/*
464 * 'debugss' class
465 * debug sub system
466 */
467static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
468 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
469 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
470};
471
472static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
473 .name = "debugss",
474};
475
476static struct omap_hwmod am33xx_debugss_hwmod = {
477 .name = "debugss",
478 .class = &am33xx_debugss_hwmod_class,
479 .clkdm_name = "l3_aon_clkdm",
480 .main_clk = "trace_clk_div_ck",
481 .prcm = {
482 .omap4 = {
483 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
484 .modulemode = MODULEMODE_SWCTRL,
485 },
486 },
487 .opt_clks = debugss_opt_clks,
488 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
489};
490
485/* 'smartreflex' class */ 491/* 'smartreflex' class */
486static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 492static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
487 .name = "smartreflex", 493 .name = "smartreflex",
@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1796 .user = OCP_USER_MPU | OCP_USER_SDMA, 1802 .user = OCP_USER_MPU | OCP_USER_SDMA,
1797}; 1803};
1798 1804
1805/* l3_main -> debugss */
1806static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
1807 {
1808 .pa_start = 0x4b000000,
1809 .pa_end = 0x4b000000 + SZ_16M - 1,
1810 .flags = ADDR_TYPE_RT
1811 },
1812 { }
1813};
1814
1815static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
1816 .master = &am33xx_l3_main_hwmod,
1817 .slave = &am33xx_debugss_hwmod,
1818 .clk = "dpll_core_m4_ck",
1819 .addr = am33xx_debugss_addrs,
1820 .user = OCP_USER_MPU,
1821};
1822
1799/* l4 wkup -> smartreflex0 */ 1823/* l4 wkup -> smartreflex0 */
1800static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { 1824static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
1801 .master = &am33xx_l4_wkup_hwmod, 1825 .master = &am33xx_l4_wkup_hwmod,
@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2470 &am33xx_pruss__l3_main, 2494 &am33xx_pruss__l3_main,
2471 &am33xx_wkup_m3__l4_wkup, 2495 &am33xx_wkup_m3__l4_wkup,
2472 &am33xx_gfx__l3_main, 2496 &am33xx_gfx__l3_main,
2497 &am33xx_l3_main__debugss,
2473 &am33xx_l4_wkup__wkup_m3, 2498 &am33xx_l4_wkup__wkup_m3,
2474 &am33xx_l4_wkup__control, 2499 &am33xx_l4_wkup__control,
2475 &am33xx_l4_wkup__smartreflex0, 2500 &am33xx_l4_wkup__smartreflex0,