diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-02-22 16:51:30 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:44 -0400 |
commit | 65bda1a95d395c256818d1d8129487a4497b29d8 (patch) | |
tree | 57bea8a2593b17b987cbc188ecf07c341fda5dbc /arch | |
parent | 4912ba72d6e27d0f19ec062ffd00a8c0165a2f67 (diff) |
Switch SiByte drivers back to __raw_*() functions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/mm/pg-sb1.c | 28 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/bcm1250_tbprof.c | 130 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/bus_watcher.c | 2 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 88 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/setup.c | 4 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/smp.c | 18 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 26 | ||||
-rw-r--r-- | arch/mips/sibyte/swarm/rtc_m41t81.c | 47 | ||||
-rw-r--r-- | arch/mips/sibyte/swarm/rtc_xicor1241.c | 42 | ||||
-rw-r--r-- | arch/mips/sibyte/swarm/time.c | 44 |
10 files changed, 220 insertions, 209 deletions
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c index 1b6df7133c1e..7a90ea383845 100644 --- a/arch/mips/mm/pg-sb1.c +++ b/arch/mips/mm/pg-sb1.c | |||
@@ -214,12 +214,12 @@ void sb1_dma_init(void) | |||
214 | int cpu = smp_processor_id(); | 214 | int cpu = smp_processor_id(); |
215 | u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1); | 215 | u64 base_val = CPHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1); |
216 | 216 | ||
217 | bus_writeq(base_val, | 217 | __raw_writeq(base_val, |
218 | (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 218 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
219 | bus_writeq(base_val | M_DM_DSCR_BASE_RESET, | 219 | __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, |
220 | (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 220 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
221 | bus_writeq(base_val | M_DM_DSCR_BASE_ENABL, | 221 | __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, |
222 | (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 222 | IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
223 | } | 223 | } |
224 | 224 | ||
225 | void clear_page(void *page) | 225 | void clear_page(void *page) |
@@ -232,16 +232,16 @@ void clear_page(void *page) | |||
232 | 232 | ||
233 | page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; | 233 | page_descr[cpu].dscr_a = CPHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; |
234 | page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | 234 | page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); |
235 | bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | 235 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); |
236 | 236 | ||
237 | /* | 237 | /* |
238 | * Don't really want to do it this way, but there's no | 238 | * Don't really want to do it this way, but there's no |
239 | * reliable way to delay completion detection. | 239 | * reliable way to delay completion detection. |
240 | */ | 240 | */ |
241 | while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & | 241 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) |
242 | M_DM_DSCR_BASE_INTERRUPT)))) | 242 | M_DM_DSCR_BASE_INTERRUPT))) |
243 | ; | 243 | ; |
244 | bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 244 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
245 | } | 245 | } |
246 | 246 | ||
247 | void copy_page(void *to, void *from) | 247 | void copy_page(void *to, void *from) |
@@ -257,16 +257,16 @@ void copy_page(void *to, void *from) | |||
257 | 257 | ||
258 | page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; | 258 | page_descr[cpu].dscr_a = CPHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; |
259 | page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); | 259 | page_descr[cpu].dscr_b = CPHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); |
260 | bus_writeq(1, (void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); | 260 | __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); |
261 | 261 | ||
262 | /* | 262 | /* |
263 | * Don't really want to do it this way, but there's no | 263 | * Don't really want to do it this way, but there's no |
264 | * reliable way to delay completion detection. | 264 | * reliable way to delay completion detection. |
265 | */ | 265 | */ |
266 | while (!(bus_readq((void *)(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & | 266 | while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & |
267 | M_DM_DSCR_BASE_INTERRUPT)))) | 267 | M_DM_DSCR_BASE_INTERRUPT))) |
268 | ; | 268 | ; |
269 | bus_readq((void *)IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); | 269 | __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); |
270 | } | 270 | } |
271 | 271 | ||
272 | #else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ | 272 | #else /* !CONFIG_SIBYTE_DMA_PAGEOPS */ |
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c index dba3d0872e7e..e4dfeb52dcec 100644 --- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c +++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c | |||
@@ -65,24 +65,25 @@ static void arm_tb(void) | |||
65 | u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; | 65 | u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; |
66 | /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to | 66 | /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to |
67 | trigger start of trace. XXX vary sampling period */ | 67 | trigger start of trace. XXX vary sampling period */ |
68 | bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); | 68 | __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); |
69 | scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); | 69 | scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); |
70 | /* Unfortunately, in Pass 2 we must clear all counters to knock down | 70 | /* Unfortunately, in Pass 2 we must clear all counters to knock down |
71 | a previous interrupt request. This means that bus profiling | 71 | a previous interrupt request. This means that bus profiling |
72 | requires ALL of the SCD perf counters. */ | 72 | requires ALL of the SCD perf counters. */ |
73 | bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is | 73 | __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | |
74 | M_SPC_CFG_ENABLE | // enable counting | 74 | // keep counters 0,2,3 as is |
75 | M_SPC_CFG_CLEAR | // clear all counters | 75 | M_SPC_CFG_ENABLE | // enable counting |
76 | V_SPC_CFG_SRC1(1), // counter 1 counts cycles | 76 | M_SPC_CFG_CLEAR | // clear all counters |
77 | IOADDR(A_SCD_PERF_CNT_CFG)); | 77 | V_SPC_CFG_SRC1(1), // counter 1 counts cycles |
78 | bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); | 78 | IOADDR(A_SCD_PERF_CNT_CFG)); |
79 | __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); | ||
79 | /* Reset the trace buffer */ | 80 | /* Reset the trace buffer */ |
80 | bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); | 81 | __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); |
81 | #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) | 82 | #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) |
82 | /* XXXKW may want to expose control to the data-collector */ | 83 | /* XXXKW may want to expose control to the data-collector */ |
83 | tb_options |= M_SCD_TRACE_CFG_FORCECNT; | 84 | tb_options |= M_SCD_TRACE_CFG_FORCECNT; |
84 | #endif | 85 | #endif |
85 | bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); | 86 | __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG)); |
86 | sbp.tb_armed = 1; | 87 | sbp.tb_armed = 1; |
87 | } | 88 | } |
88 | 89 | ||
@@ -94,23 +95,30 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
94 | /* XXX should use XKPHYS to make writes bypass L2 */ | 95 | /* XXX should use XKPHYS to make writes bypass L2 */ |
95 | u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; | 96 | u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++]; |
96 | /* Read out trace */ | 97 | /* Read out trace */ |
97 | bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); | 98 | __raw_writeq(M_SCD_TRACE_CFG_START_READ, |
99 | IOADDR(A_SCD_TRACE_CFG)); | ||
98 | __asm__ __volatile__ ("sync" : : : "memory"); | 100 | __asm__ __volatile__ ("sync" : : : "memory"); |
99 | /* Loop runs backwards because bundles are read out in reverse order */ | 101 | /* Loop runs backwards because bundles are read out in reverse order */ |
100 | for (i = 256 * 6; i > 0; i -= 6) { | 102 | for (i = 256 * 6; i > 0; i -= 6) { |
101 | // Subscripts decrease to put bundle in the order | 103 | // Subscripts decrease to put bundle in the order |
102 | // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi | 104 | // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi |
103 | p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi | 105 | p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
104 | p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo | 106 | // read t2 hi |
105 | p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi | 107 | p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
106 | p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo | 108 | // read t2 lo |
107 | p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi | 109 | p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); |
108 | p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo | 110 | // read t1 hi |
111 | p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); | ||
112 | // read t1 lo | ||
113 | p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); | ||
114 | // read t0 hi | ||
115 | p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); | ||
116 | // read t0 lo | ||
109 | } | 117 | } |
110 | if (!sbp.tb_enable) { | 118 | if (!sbp.tb_enable) { |
111 | DBG(printk(DEVNAME ": tb_intr shutdown\n")); | 119 | DBG(printk(DEVNAME ": tb_intr shutdown\n")); |
112 | bus_writeq(M_SCD_TRACE_CFG_RESET, | 120 | __raw_writeq(M_SCD_TRACE_CFG_RESET, |
113 | IOADDR(A_SCD_TRACE_CFG)); | 121 | IOADDR(A_SCD_TRACE_CFG)); |
114 | sbp.tb_armed = 0; | 122 | sbp.tb_armed = 0; |
115 | wake_up(&sbp.tb_sync); | 123 | wake_up(&sbp.tb_sync); |
116 | } else { | 124 | } else { |
@@ -119,7 +127,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
119 | } else { | 127 | } else { |
120 | /* No more trace buffer samples */ | 128 | /* No more trace buffer samples */ |
121 | DBG(printk(DEVNAME ": tb_intr full\n")); | 129 | DBG(printk(DEVNAME ": tb_intr full\n")); |
122 | bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); | 130 | __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); |
123 | sbp.tb_armed = 0; | 131 | sbp.tb_armed = 0; |
124 | if (!sbp.tb_enable) { | 132 | if (!sbp.tb_enable) { |
125 | wake_up(&sbp.tb_sync); | 133 | wake_up(&sbp.tb_sync); |
@@ -153,13 +161,11 @@ int sbprof_zbprof_start(struct file *filp) | |||
153 | return -EBUSY; | 161 | return -EBUSY; |
154 | } | 162 | } |
155 | /* Make sure there isn't a perf-cnt interrupt waiting */ | 163 | /* Make sure there isn't a perf-cnt interrupt waiting */ |
156 | scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG)); | 164 | scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); |
157 | /* Disable and clear counters, override SRC_1 */ | 165 | /* Disable and clear counters, override SRC_1 */ |
158 | bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | | 166 | __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) | |
159 | M_SPC_CFG_ENABLE | | 167 | M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1), |
160 | M_SPC_CFG_CLEAR | | 168 | IOADDR(A_SCD_PERF_CNT_CFG)); |
161 | V_SPC_CFG_SRC1(1), | ||
162 | IOADDR(A_SCD_PERF_CNT_CFG)); | ||
163 | 169 | ||
164 | /* We grab this interrupt to prevent others from trying to use | 170 | /* We grab this interrupt to prevent others from trying to use |
165 | it, even though we don't want to service the interrupts | 171 | it, even though we don't want to service the interrupts |
@@ -173,55 +179,55 @@ int sbprof_zbprof_start(struct file *filp) | |||
173 | /* I need the core to mask these, but the interrupt mapper to | 179 | /* I need the core to mask these, but the interrupt mapper to |
174 | pass them through. I am exploiting my knowledge that | 180 | pass them through. I am exploiting my knowledge that |
175 | cp0_status masks out IP[5]. krw */ | 181 | cp0_status masks out IP[5]. krw */ |
176 | bus_writeq(K_INT_MAP_I3, | 182 | __raw_writeq(K_INT_MAP_I3, |
177 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | 183 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + |
178 | (K_INT_PERF_CNT << 3))); | 184 | (K_INT_PERF_CNT << 3))); |
179 | 185 | ||
180 | /* Initialize address traps */ | 186 | /* Initialize address traps */ |
181 | bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); | 187 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); |
182 | bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); | 188 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1)); |
183 | bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); | 189 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2)); |
184 | bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); | 190 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3)); |
185 | 191 | ||
186 | bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); | 192 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0)); |
187 | bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); | 193 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1)); |
188 | bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); | 194 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2)); |
189 | bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); | 195 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3)); |
190 | 196 | ||
191 | bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); | 197 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0)); |
192 | bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); | 198 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1)); |
193 | bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); | 199 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2)); |
194 | bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); | 200 | __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); |
195 | 201 | ||
196 | /* Initialize Trace Event 0-7 */ | 202 | /* Initialize Trace Event 0-7 */ |
197 | // when interrupt | 203 | // when interrupt |
198 | bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); | 204 | __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); |
199 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); | 205 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); |
200 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); | 206 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); |
201 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); | 207 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3)); |
202 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); | 208 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4)); |
203 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); | 209 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5)); |
204 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); | 210 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6)); |
205 | bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); | 211 | __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7)); |
206 | 212 | ||
207 | /* Initialize Trace Sequence 0-7 */ | 213 | /* Initialize Trace Sequence 0-7 */ |
208 | // Start on event 0 (interrupt) | 214 | // Start on event 0 (interrupt) |
209 | bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, | 215 | __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff, |
210 | IOADDR(A_SCD_TRACE_SEQUENCE_0)); | 216 | IOADDR(A_SCD_TRACE_SEQUENCE_0)); |
211 | // dsamp when d used | asamp when a used | 217 | // dsamp when d used | asamp when a used |
212 | bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | | 218 | __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | |
213 | K_SCD_TRSEQ_TRIGGER_ALL, | 219 | K_SCD_TRSEQ_TRIGGER_ALL, |
214 | IOADDR(A_SCD_TRACE_SEQUENCE_1)); | 220 | IOADDR(A_SCD_TRACE_SEQUENCE_1)); |
215 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); | 221 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2)); |
216 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); | 222 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3)); |
217 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); | 223 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4)); |
218 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); | 224 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); |
219 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); | 225 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6)); |
220 | bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); | 226 | __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); |
221 | 227 | ||
222 | /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ | 228 | /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ |
223 | bus_writeq((1ULL << K_INT_PERF_CNT), | 229 | __raw_writeq(1ULL << K_INT_PERF_CNT, |
224 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); | 230 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); |
225 | 231 | ||
226 | arm_tb(); | 232 | arm_tb(); |
227 | 233 | ||
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c index 1a97e3127aeb..482dee054e68 100644 --- a/arch/mips/sibyte/sb1250/bus_watcher.c +++ b/arch/mips/sibyte/sb1250/bus_watcher.c | |||
@@ -189,7 +189,7 @@ static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs) | |||
189 | 189 | ||
190 | for (i=0; i<256*6; i++) | 190 | for (i=0; i<256*6; i++) |
191 | printk("%016llx\n", | 191 | printk("%016llx\n", |
192 | (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ))); | 192 | (long long)__raw_readq(IOADDR(A_SCD_TRACE_READ))); |
193 | 193 | ||
194 | csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); | 194 | csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); |
195 | csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); | 195 | csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); |
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 2725b263cced..a62cba9f32ba 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c | |||
@@ -96,11 +96,11 @@ void sb1250_mask_irq(int cpu, int irq) | |||
96 | u64 cur_ints; | 96 | u64 cur_ints; |
97 | 97 | ||
98 | spin_lock_irqsave(&sb1250_imr_lock, flags); | 98 | spin_lock_irqsave(&sb1250_imr_lock, flags); |
99 | cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + | 99 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
100 | R_IMR_INTERRUPT_MASK)); | 100 | R_IMR_INTERRUPT_MASK)); |
101 | cur_ints |= (((u64) 1) << irq); | 101 | cur_ints |= (((u64) 1) << irq); |
102 | __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + | 102 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
103 | R_IMR_INTERRUPT_MASK)); | 103 | R_IMR_INTERRUPT_MASK)); |
104 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); | 104 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
105 | } | 105 | } |
106 | 106 | ||
@@ -110,11 +110,11 @@ void sb1250_unmask_irq(int cpu, int irq) | |||
110 | u64 cur_ints; | 110 | u64 cur_ints; |
111 | 111 | ||
112 | spin_lock_irqsave(&sb1250_imr_lock, flags); | 112 | spin_lock_irqsave(&sb1250_imr_lock, flags); |
113 | cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + | 113 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
114 | R_IMR_INTERRUPT_MASK)); | 114 | R_IMR_INTERRUPT_MASK)); |
115 | cur_ints &= ~(((u64) 1) << irq); | 115 | cur_ints &= ~(((u64) 1) << irq); |
116 | __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + | 116 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
117 | R_IMR_INTERRUPT_MASK)); | 117 | R_IMR_INTERRUPT_MASK)); |
118 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); | 118 | spin_unlock_irqrestore(&sb1250_imr_lock, flags); |
119 | } | 119 | } |
120 | 120 | ||
@@ -149,23 +149,23 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask) | |||
149 | 149 | ||
150 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ | 150 | /* Swizzle each CPU's IMR (but leave the IP selection alone) */ |
151 | old_cpu = sb1250_irq_owner[irq]; | 151 | old_cpu = sb1250_irq_owner[irq]; |
152 | cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + | 152 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + |
153 | R_IMR_INTERRUPT_MASK)); | 153 | R_IMR_INTERRUPT_MASK)); |
154 | int_on = !(cur_ints & (((u64) 1) << irq)); | 154 | int_on = !(cur_ints & (((u64) 1) << irq)); |
155 | if (int_on) { | 155 | if (int_on) { |
156 | /* If it was on, mask it */ | 156 | /* If it was on, mask it */ |
157 | cur_ints |= (((u64) 1) << irq); | 157 | cur_ints |= (((u64) 1) << irq); |
158 | __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + | 158 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + |
159 | R_IMR_INTERRUPT_MASK)); | 159 | R_IMR_INTERRUPT_MASK)); |
160 | } | 160 | } |
161 | sb1250_irq_owner[irq] = cpu; | 161 | sb1250_irq_owner[irq] = cpu; |
162 | if (int_on) { | 162 | if (int_on) { |
163 | /* unmask for the new CPU */ | 163 | /* unmask for the new CPU */ |
164 | cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + | 164 | cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + |
165 | R_IMR_INTERRUPT_MASK)); | 165 | R_IMR_INTERRUPT_MASK)); |
166 | cur_ints &= ~(((u64) 1) << irq); | 166 | cur_ints &= ~(((u64) 1) << irq); |
167 | __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + | 167 | ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + |
168 | R_IMR_INTERRUPT_MASK)); | 168 | R_IMR_INTERRUPT_MASK)); |
169 | } | 169 | } |
170 | spin_unlock(&sb1250_imr_lock); | 170 | spin_unlock(&sb1250_imr_lock); |
171 | spin_unlock_irqrestore(&desc->lock, flags); | 171 | spin_unlock_irqrestore(&desc->lock, flags); |
@@ -208,8 +208,8 @@ static void ack_sb1250_irq(unsigned int irq) | |||
208 | * deliver the interrupts to all CPUs (which makes affinity | 208 | * deliver the interrupts to all CPUs (which makes affinity |
209 | * changing easier for us) | 209 | * changing easier for us) |
210 | */ | 210 | */ |
211 | pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], | 211 | pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], |
212 | R_IMR_LDT_INTERRUPT))); | 212 | R_IMR_LDT_INTERRUPT))); |
213 | pending &= ((u64)1 << (irq)); | 213 | pending &= ((u64)1 << (irq)); |
214 | if (pending) { | 214 | if (pending) { |
215 | int i; | 215 | int i; |
@@ -224,8 +224,8 @@ static void ack_sb1250_irq(unsigned int irq) | |||
224 | * Clear for all CPUs so an affinity switch | 224 | * Clear for all CPUs so an affinity switch |
225 | * doesn't find an old status | 225 | * doesn't find an old status |
226 | */ | 226 | */ |
227 | bus_writeq(pending, | 227 | __raw_writeq(pending, |
228 | IOADDR(A_IMR_REGISTER(cpu, | 228 | IOADDR(A_IMR_REGISTER(cpu, |
229 | R_IMR_LDT_INTERRUPT_CLR))); | 229 | R_IMR_LDT_INTERRUPT_CLR))); |
230 | } | 230 | } |
231 | 231 | ||
@@ -340,12 +340,14 @@ void __init arch_init_irq(void) | |||
340 | 340 | ||
341 | /* Default everything to IP2 */ | 341 | /* Default everything to IP2 */ |
342 | for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ | 342 | for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ |
343 | bus_writeq(IMR_IP2_VAL, | 343 | __raw_writeq(IMR_IP2_VAL, |
344 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | 344 | IOADDR(A_IMR_REGISTER(0, |
345 | (i << 3))); | 345 | R_IMR_INTERRUPT_MAP_BASE) + |
346 | bus_writeq(IMR_IP2_VAL, | 346 | (i << 3))); |
347 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + | 347 | __raw_writeq(IMR_IP2_VAL, |
348 | (i << 3))); | 348 | IOADDR(A_IMR_REGISTER(1, |
349 | R_IMR_INTERRUPT_MAP_BASE) + | ||
350 | (i << 3))); | ||
349 | } | 351 | } |
350 | 352 | ||
351 | init_sb1250_irqs(); | 353 | init_sb1250_irqs(); |
@@ -355,23 +357,23 @@ void __init arch_init_irq(void) | |||
355 | * inter-cpu messages | 357 | * inter-cpu messages |
356 | */ | 358 | */ |
357 | /* Was I1 */ | 359 | /* Was I1 */ |
358 | bus_writeq(IMR_IP3_VAL, | 360 | __raw_writeq(IMR_IP3_VAL, |
359 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | 361 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + |
360 | (K_INT_MBOX_0 << 3))); | 362 | (K_INT_MBOX_0 << 3))); |
361 | bus_writeq(IMR_IP3_VAL, | 363 | __raw_writeq(IMR_IP3_VAL, |
362 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + | 364 | IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + |
363 | (K_INT_MBOX_0 << 3))); | 365 | (K_INT_MBOX_0 << 3))); |
364 | 366 | ||
365 | /* Clear the mailboxes. The firmware may leave them dirty */ | 367 | /* Clear the mailboxes. The firmware may leave them dirty */ |
366 | bus_writeq(0xffffffffffffffffULL, | 368 | __raw_writeq(0xffffffffffffffffULL, |
367 | IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); | 369 | IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); |
368 | bus_writeq(0xffffffffffffffffULL, | 370 | __raw_writeq(0xffffffffffffffffULL, |
369 | IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); | 371 | IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); |
370 | 372 | ||
371 | /* Mask everything except the mailbox registers for both cpus */ | 373 | /* Mask everything except the mailbox registers for both cpus */ |
372 | tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); | 374 | tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); |
373 | bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); | 375 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); |
374 | bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); | 376 | __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); |
375 | 377 | ||
376 | sb1250_steal_irq(K_INT_MBOX_0); | 378 | sb1250_steal_irq(K_INT_MBOX_0); |
377 | 379 | ||
@@ -396,12 +398,14 @@ void __init arch_init_irq(void) | |||
396 | sb1250_duart_present[kgdb_port] = 0; | 398 | sb1250_duart_present[kgdb_port] = 0; |
397 | #endif | 399 | #endif |
398 | /* Setup uart 1 settings, mapper */ | 400 | /* Setup uart 1 settings, mapper */ |
399 | bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); | 401 | __raw_writeq(M_DUART_IMR_BRK, |
402 | IOADDR(A_DUART_IMRREG(kgdb_port))); | ||
400 | 403 | ||
401 | sb1250_steal_irq(kgdb_irq); | 404 | sb1250_steal_irq(kgdb_irq); |
402 | bus_writeq(IMR_IP6_VAL, | 405 | __raw_writeq(IMR_IP6_VAL, |
403 | IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + | 406 | IOADDR(A_IMR_REGISTER(0, |
404 | (kgdb_irq<<3))); | 407 | R_IMR_INTERRUPT_MAP_BASE) + |
408 | (kgdb_irq << 3))); | ||
405 | sb1250_unmask_irq(0, kgdb_irq); | 409 | sb1250_unmask_irq(0, kgdb_irq); |
406 | } | 410 | } |
407 | #endif | 411 | #endif |
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index f8c605be96c7..df2e266c700c 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c | |||
@@ -153,7 +153,7 @@ void sb1250_setup(void) | |||
153 | int bad_config = 0; | 153 | int bad_config = 0; |
154 | 154 | ||
155 | sb1_pass = read_c0_prid() & 0xff; | 155 | sb1_pass = read_c0_prid() & 0xff; |
156 | sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION)); | 156 | sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); |
157 | soc_type = SYS_SOC_TYPE(sys_rev); | 157 | soc_type = SYS_SOC_TYPE(sys_rev); |
158 | soc_pass = G_SYS_REVISION(sys_rev); | 158 | soc_pass = G_SYS_REVISION(sys_rev); |
159 | 159 | ||
@@ -162,7 +162,7 @@ void sb1250_setup(void) | |||
162 | machine_restart(NULL); | 162 | machine_restart(NULL); |
163 | } | 163 | } |
164 | 164 | ||
165 | plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG))); | 165 | plldiv = G_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG))); |
166 | zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); | 166 | zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25); |
167 | 167 | ||
168 | prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", | 168 | prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n", |
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index be91b3990952..f859db02d3c9 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c | |||
@@ -29,18 +29,18 @@ | |||
29 | #include <asm/sibyte/sb1250_int.h> | 29 | #include <asm/sibyte/sb1250_int.h> |
30 | 30 | ||
31 | static void *mailbox_set_regs[] = { | 31 | static void *mailbox_set_regs[] = { |
32 | (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), | 32 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), |
33 | (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) | 33 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) |
34 | }; | 34 | }; |
35 | 35 | ||
36 | static void *mailbox_clear_regs[] = { | 36 | static void *mailbox_clear_regs[] = { |
37 | (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), | 37 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), |
38 | (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) | 38 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) |
39 | }; | 39 | }; |
40 | 40 | ||
41 | static void *mailbox_regs[] = { | 41 | static void *mailbox_regs[] = { |
42 | (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), | 42 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), |
43 | (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) | 43 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) |
44 | }; | 44 | }; |
45 | 45 | ||
46 | /* | 46 | /* |
@@ -73,7 +73,7 @@ void sb1250_smp_finish(void) | |||
73 | */ | 73 | */ |
74 | void core_send_ipi(int cpu, unsigned int action) | 74 | void core_send_ipi(int cpu, unsigned int action) |
75 | { | 75 | { |
76 | bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); | 76 | __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); |
77 | } | 77 | } |
78 | 78 | ||
79 | void sb1250_mailbox_interrupt(struct pt_regs *regs) | 79 | void sb1250_mailbox_interrupt(struct pt_regs *regs) |
@@ -83,10 +83,10 @@ void sb1250_mailbox_interrupt(struct pt_regs *regs) | |||
83 | 83 | ||
84 | kstat_this_cpu.irqs[K_INT_MBOX_0]++; | 84 | kstat_this_cpu.irqs[K_INT_MBOX_0]++; |
85 | /* Load the mailbox register to figure out what we're supposed to do */ | 85 | /* Load the mailbox register to figure out what we're supposed to do */ |
86 | action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff; | 86 | action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; |
87 | 87 | ||
88 | /* Clear the mailbox to clear the interrupt */ | 88 | /* Clear the mailbox to clear the interrupt */ |
89 | __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); | 89 | ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); |
90 | 90 | ||
91 | /* | 91 | /* |
92 | * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the | 92 | * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the |
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 8b4c848c907b..0ffbc835b116 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c | |||
@@ -67,24 +67,24 @@ void sb1250_time_init(void) | |||
67 | sb1250_mask_irq(cpu, irq); | 67 | sb1250_mask_irq(cpu, irq); |
68 | 68 | ||
69 | /* Map the timer interrupt to ip[4] of this cpu */ | 69 | /* Map the timer interrupt to ip[4] of this cpu */ |
70 | bus_writeq(IMR_IP4_VAL, | 70 | __raw_writeq(IMR_IP4_VAL, |
71 | IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + | 71 | IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + |
72 | (irq << 3))); | 72 | (irq << 3))); |
73 | 73 | ||
74 | /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ | 74 | /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ |
75 | /* Disable the timer and set up the count */ | 75 | /* Disable the timer and set up the count */ |
76 | bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 76 | __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
77 | #ifdef CONFIG_SIMULATION | 77 | #ifdef CONFIG_SIMULATION |
78 | bus_writeq(50000 / HZ, | 78 | __raw_writeq(50000 / HZ, |
79 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); | 79 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); |
80 | #else | 80 | #else |
81 | bus_writeq(1000000/HZ, | 81 | __raw_writeq(1000000 / HZ, |
82 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); | 82 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); |
83 | #endif | 83 | #endif |
84 | 84 | ||
85 | /* Set the timer running */ | 85 | /* Set the timer running */ |
86 | bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | 86 | __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, |
87 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 87 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
88 | 88 | ||
89 | sb1250_unmask_irq(cpu, irq); | 89 | sb1250_unmask_irq(cpu, irq); |
90 | sb1250_steal_irq(irq); | 90 | sb1250_steal_irq(irq); |
@@ -105,8 +105,8 @@ void sb1250_timer_interrupt(struct pt_regs *regs) | |||
105 | int irq = K_INT_TIMER_0 + cpu; | 105 | int irq = K_INT_TIMER_0 + cpu; |
106 | 106 | ||
107 | /* Reset the timer */ | 107 | /* Reset the timer */ |
108 | __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | 108 | ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, |
109 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 109 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
110 | 110 | ||
111 | /* | 111 | /* |
112 | * CPU 0 handles the global timer interrupt job | 112 | * CPU 0 handles the global timer interrupt job |
@@ -130,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs) | |||
130 | unsigned long sb1250_gettimeoffset(void) | 130 | unsigned long sb1250_gettimeoffset(void) |
131 | { | 131 | { |
132 | unsigned long count = | 132 | unsigned long count = |
133 | bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); | 133 | __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); |
134 | 134 | ||
135 | return 1000000/HZ - count; | 135 | return 1000000/HZ - count; |
136 | } | 136 | } |
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index a686bb716ec6..5b4fc26c1b36 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c | |||
@@ -82,59 +82,60 @@ | |||
82 | #define M41T81REG_SQW 0x13 /* square wave register */ | 82 | #define M41T81REG_SQW 0x13 /* square wave register */ |
83 | 83 | ||
84 | #define M41T81_CCR_ADDRESS 0x68 | 84 | #define M41T81_CCR_ADDRESS 0x68 |
85 | #define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) | 85 | |
86 | #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) | ||
86 | 87 | ||
87 | static int m41t81_read(uint8_t addr) | 88 | static int m41t81_read(uint8_t addr) |
88 | { | 89 | { |
89 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 90 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
90 | ; | 91 | ; |
91 | 92 | ||
92 | bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); | 93 | __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); |
93 | bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE), | 94 | __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE, |
94 | SMB_CSR(R_SMB_START)); | 95 | SMB_CSR(R_SMB_START)); |
95 | 96 | ||
96 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 97 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
97 | ; | 98 | ; |
98 | 99 | ||
99 | bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), | 100 | __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
100 | SMB_CSR(R_SMB_START)); | 101 | SMB_CSR(R_SMB_START)); |
101 | 102 | ||
102 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 103 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
103 | ; | 104 | ; |
104 | 105 | ||
105 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 106 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
106 | /* Clear error bit by writing a 1 */ | 107 | /* Clear error bit by writing a 1 */ |
107 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 108 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
108 | return -1; | 109 | return -1; |
109 | } | 110 | } |
110 | 111 | ||
111 | return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); | 112 | return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); |
112 | } | 113 | } |
113 | 114 | ||
114 | static int m41t81_write(uint8_t addr, int b) | 115 | static int m41t81_write(uint8_t addr, int b) |
115 | { | 116 | { |
116 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 117 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
117 | ; | 118 | ; |
118 | 119 | ||
119 | bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD)); | 120 | __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); |
120 | bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA)); | 121 | __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); |
121 | bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, | 122 | __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, |
122 | SMB_CSR(R_SMB_START)); | 123 | SMB_CSR(R_SMB_START)); |
123 | 124 | ||
124 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 125 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
125 | ; | 126 | ; |
126 | 127 | ||
127 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 128 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
128 | /* Clear error bit by writing a 1 */ | 129 | /* Clear error bit by writing a 1 */ |
129 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 130 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
130 | return -1; | 131 | return -1; |
131 | } | 132 | } |
132 | 133 | ||
133 | /* read the same byte again to make sure it is written */ | 134 | /* read the same byte again to make sure it is written */ |
134 | bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, | 135 | __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
135 | SMB_CSR(R_SMB_START)); | 136 | SMB_CSR(R_SMB_START)); |
136 | 137 | ||
137 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 138 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
138 | ; | 139 | ; |
139 | 140 | ||
140 | return 0; | 141 | return 0; |
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c index 981d21f16e64..d9ff9323f24e 100644 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c +++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c | |||
@@ -57,52 +57,52 @@ | |||
57 | 57 | ||
58 | #define X1241_CCR_ADDRESS 0x6F | 58 | #define X1241_CCR_ADDRESS 0x6F |
59 | 59 | ||
60 | #define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg)))) | 60 | #define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg)) |
61 | 61 | ||
62 | static int xicor_read(uint8_t addr) | 62 | static int xicor_read(uint8_t addr) |
63 | { | 63 | { |
64 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 64 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
65 | ; | 65 | ; |
66 | 66 | ||
67 | bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); | 67 | __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); |
68 | bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); | 68 | __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); |
69 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), | 69 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, |
70 | SMB_CSR(R_SMB_START)); | 70 | SMB_CSR(R_SMB_START)); |
71 | 71 | ||
72 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 72 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
73 | ; | 73 | ; |
74 | 74 | ||
75 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), | 75 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
76 | SMB_CSR(R_SMB_START)); | 76 | SMB_CSR(R_SMB_START)); |
77 | 77 | ||
78 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 78 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
79 | ; | 79 | ; |
80 | 80 | ||
81 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 81 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
82 | /* Clear error bit by writing a 1 */ | 82 | /* Clear error bit by writing a 1 */ |
83 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 83 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
84 | return -1; | 84 | return -1; |
85 | } | 85 | } |
86 | 86 | ||
87 | return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); | 87 | return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); |
88 | } | 88 | } |
89 | 89 | ||
90 | static int xicor_write(uint8_t addr, int b) | 90 | static int xicor_write(uint8_t addr, int b) |
91 | { | 91 | { |
92 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 92 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
93 | ; | 93 | ; |
94 | 94 | ||
95 | bus_writeq(addr, SMB_CSR(R_SMB_CMD)); | 95 | __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); |
96 | bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); | 96 | __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); |
97 | bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, | 97 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, |
98 | SMB_CSR(R_SMB_START)); | 98 | SMB_CSR(R_SMB_START)); |
99 | 99 | ||
100 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 100 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
101 | ; | 101 | ; |
102 | 102 | ||
103 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 103 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
104 | /* Clear error bit by writing a 1 */ | 104 | /* Clear error bit by writing a 1 */ |
105 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 105 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
106 | return -1; | 106 | return -1; |
107 | } else { | 107 | } else { |
108 | return 0; | 108 | return 0; |
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c index c1f1a9defeeb..97c73c793c35 100644 --- a/arch/mips/sibyte/swarm/time.c +++ b/arch/mips/sibyte/swarm/time.c | |||
@@ -79,48 +79,48 @@ static unsigned int usec_bias = 0; | |||
79 | 79 | ||
80 | static int xicor_read(uint8_t addr) | 80 | static int xicor_read(uint8_t addr) |
81 | { | 81 | { |
82 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 82 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
83 | ; | 83 | ; |
84 | 84 | ||
85 | bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); | 85 | __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); |
86 | bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); | 86 | __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); |
87 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), | 87 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, |
88 | SMB_CSR(R_SMB_START)); | 88 | SMB_CSR(R_SMB_START)); |
89 | 89 | ||
90 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 90 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
91 | ; | 91 | ; |
92 | 92 | ||
93 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), | 93 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
94 | SMB_CSR(R_SMB_START)); | 94 | SMB_CSR(R_SMB_START)); |
95 | 95 | ||
96 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 96 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
97 | ; | 97 | ; |
98 | 98 | ||
99 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 99 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
100 | /* Clear error bit by writing a 1 */ | 100 | /* Clear error bit by writing a 1 */ |
101 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 101 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
102 | return -1; | 102 | return -1; |
103 | } | 103 | } |
104 | 104 | ||
105 | return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); | 105 | return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); |
106 | } | 106 | } |
107 | 107 | ||
108 | static int xicor_write(uint8_t addr, int b) | 108 | static int xicor_write(uint8_t addr, int b) |
109 | { | 109 | { |
110 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 110 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
111 | ; | 111 | ; |
112 | 112 | ||
113 | bus_writeq(addr, SMB_CSR(R_SMB_CMD)); | 113 | __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); |
114 | bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); | 114 | __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); |
115 | bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, | 115 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, |
116 | SMB_CSR(R_SMB_START)); | 116 | SMB_CSR(R_SMB_START)); |
117 | 117 | ||
118 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 118 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
119 | ; | 119 | ; |
120 | 120 | ||
121 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 121 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
122 | /* Clear error bit by writing a 1 */ | 122 | /* Clear error bit by writing a 1 */ |
123 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 123 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
124 | return -1; | 124 | return -1; |
125 | } else { | 125 | } else { |
126 | return 0; | 126 | return 0; |
@@ -228,8 +228,8 @@ void __init swarm_time_init(void) | |||
228 | /* Establish communication with the Xicor 1241 RTC */ | 228 | /* Establish communication with the Xicor 1241 RTC */ |
229 | /* XXXKW how do I share the SMBus with the I2C subsystem? */ | 229 | /* XXXKW how do I share the SMBus with the I2C subsystem? */ |
230 | 230 | ||
231 | bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); | 231 | __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); |
232 | bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); | 232 | __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); |
233 | 233 | ||
234 | if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { | 234 | if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { |
235 | printk("x1241: couldn't detect on SWARM SMBus 1\n"); | 235 | printk("x1241: couldn't detect on SWARM SMBus 1\n"); |