diff options
Diffstat (limited to 'arch/mips/sibyte/sb1250/time.c')
-rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 8b4c848c907b..0ffbc835b116 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c | |||
@@ -67,24 +67,24 @@ void sb1250_time_init(void) | |||
67 | sb1250_mask_irq(cpu, irq); | 67 | sb1250_mask_irq(cpu, irq); |
68 | 68 | ||
69 | /* Map the timer interrupt to ip[4] of this cpu */ | 69 | /* Map the timer interrupt to ip[4] of this cpu */ |
70 | bus_writeq(IMR_IP4_VAL, | 70 | __raw_writeq(IMR_IP4_VAL, |
71 | IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + | 71 | IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + |
72 | (irq << 3))); | 72 | (irq << 3))); |
73 | 73 | ||
74 | /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ | 74 | /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ |
75 | /* Disable the timer and set up the count */ | 75 | /* Disable the timer and set up the count */ |
76 | bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 76 | __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
77 | #ifdef CONFIG_SIMULATION | 77 | #ifdef CONFIG_SIMULATION |
78 | bus_writeq(50000 / HZ, | 78 | __raw_writeq(50000 / HZ, |
79 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); | 79 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); |
80 | #else | 80 | #else |
81 | bus_writeq(1000000/HZ, | 81 | __raw_writeq(1000000 / HZ, |
82 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); | 82 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); |
83 | #endif | 83 | #endif |
84 | 84 | ||
85 | /* Set the timer running */ | 85 | /* Set the timer running */ |
86 | bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | 86 | __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, |
87 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 87 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
88 | 88 | ||
89 | sb1250_unmask_irq(cpu, irq); | 89 | sb1250_unmask_irq(cpu, irq); |
90 | sb1250_steal_irq(irq); | 90 | sb1250_steal_irq(irq); |
@@ -105,8 +105,8 @@ void sb1250_timer_interrupt(struct pt_regs *regs) | |||
105 | int irq = K_INT_TIMER_0 + cpu; | 105 | int irq = K_INT_TIMER_0 + cpu; |
106 | 106 | ||
107 | /* Reset the timer */ | 107 | /* Reset the timer */ |
108 | __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | 108 | ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, |
109 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | 109 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); |
110 | 110 | ||
111 | /* | 111 | /* |
112 | * CPU 0 handles the global timer interrupt job | 112 | * CPU 0 handles the global timer interrupt job |
@@ -130,7 +130,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs) | |||
130 | unsigned long sb1250_gettimeoffset(void) | 130 | unsigned long sb1250_gettimeoffset(void) |
131 | { | 131 | { |
132 | unsigned long count = | 132 | unsigned long count = |
133 | bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); | 133 | __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); |
134 | 134 | ||
135 | return 1000000/HZ - count; | 135 | return 1000000/HZ - count; |
136 | } | 136 | } |