ARM: tegra: migrate to new clock code

Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>

8 files changed, 5 insertions, 128 deletions

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index e1f87dd314ef..0c11b8af3af3 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -42,7 +42,6 @@
 #include <asm/setup.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -104,37 +103,8 @@ static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
         {}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        216000000,      true },
-        { "uartd",      "pll_p",        216000000,      true },
-        { "usbd",       "clk_m",        12000000,       false },
-        { "usb2",       "clk_m",        12000000,       false },
-        { "usb3",       "clk_m",        12000000,       false },
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "blink",      "clk_32k",      32768,          true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "i2s2",       "pll_a_out0",   11289600,       false},
-        { "sdmmc1",     "pll_p",        48000000,       false},
-        { "sdmmc3",     "pll_p",        48000000,       false},
-        { "sdmmc4",     "pll_p",        48000000,       false},
-        { "spi",        "pll_p",        20000000,       false },
-        { "sbc1",       "pll_p",        100000000,      false },
-        { "sbc2",       "pll_p",        100000000,      false },
-        { "sbc3",       "pll_p",        100000000,      false },
-        { "sbc4",       "pll_p",        100000000,      false },
-        { "host1x",     "pll_c",        150000000,      false },
-        { "disp1",      "pll_p",        600000000,      false },
-        { "disp2",      "pll_p",        600000000,      false },
-        { NULL,         NULL,           0,              0},
-};
-
 static void __init tegra_dt_init(void)
 {
-        tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
         /*
          * Finished with the static registrations now; fill in the missing
          * devices
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index cfe5fc02be77..92f6014d22a1 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -35,7 +35,6 @@
 #include <asm/hardware/gic.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "iomap.h"
 
@@ -67,38 +66,8 @@ static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
         {}
 };
 
-static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uarta",      "pll_p",        408000000,      true },
-        { "pll_a",      "pll_p_out1",   564480000,      true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "extern1",    "pll_a_out0",   0,              true },
-        { "clk_out_1",  "extern1",      0,              true },
-        { "blink",      "clk_32k",      32768,          true },
-        { "i2s0",       "pll_a_out0",   11289600,       false},
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "i2s2",       "pll_a_out0",   11289600,       false},
-        { "i2s3",       "pll_a_out0",   11289600,       false},
-        { "i2s4",       "pll_a_out0",   11289600,       false},
-        { "sdmmc1",     "pll_p",        48000000,       false},
-        { "sdmmc3",     "pll_p",        48000000,       false},
-        { "sdmmc4",     "pll_p",        48000000,       false},
-        { "sbc1",       "pll_p",        100000000,      false},
-        { "sbc2",       "pll_p",        100000000,      false},
-        { "sbc3",       "pll_p",        100000000,      false},
-        { "sbc4",       "pll_p",        100000000,      false},
-        { "sbc5",       "pll_p",        100000000,      false},
-        { "sbc6",       "pll_p",        100000000,      false},
-        { "host1x",     "pll_c",        150000000,      false},
-        { "disp1",      "pll_p",        600000000,      false},
-        { "disp2",      "pll_p",        600000000,      false},
-        { NULL,         NULL,           0,              0},
-};
-
 static void __init tegra30_dt_init(void)
 {
-        tegra_clk_init_from_table(tegra_dt_clk_init_table);
-
         of_platform_populate(NULL, of_default_bus_match_table,
                                 tegra30_auxdata_lookup, NULL);
 }
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 8c0ff061f8cf..baa0c5b008f1 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -31,9 +31,6 @@
 #include "board.h"
 #include "clock.h"
 
-/* Global data of Tegra CPU CAR ops */
-struct tegra_cpu_car_ops *tegra_cpu_car_ops;
-
 /*
  * Locking:
  *
@@ -131,22 +128,6 @@ void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
                 tegra_clk_init_one_from_table(table);
 }
 
-void tegra_periph_reset_deassert(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        BUG_ON(!clk->reset);
-        clk->reset(__clk_get_hw(c), false);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-        struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
-        BUG_ON(!clk->reset);
-        clk->reset(__clk_get_hw(c), true);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
 /* Several extended clock configuration bits (e.g., clock routing, clock
  * phase control) are included in PLL and peripheral clock source
  * registers. */
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 3efe80b2af28..87dd69ccdf8e 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/of_irq.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -29,7 +30,6 @@
 #include <mach/powergate.h>
 
 #include "board.h"
-#include "clock.h"
 #include "common.h"
 #include "fuse.h"
 #include "iomap.h"
@@ -65,6 +65,7 @@ static const struct of_device_id tegra_dt_irq_match[] __initconst = {
 
 void __init tegra_dt_init_irq(void)
 {
+        tegra_clocks_init();
         tegra_init_irq();
         of_irq_init(tegra_dt_irq_match);
 }
@@ -80,43 +81,6 @@ void tegra_assert_system_reset(char mode, const char *cmd)
         writel_relaxed(reg, reset);
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "clk_m",      NULL,           0,              true },
-        { "pll_p",      "clk_m",        216000000,      true },
-        { "pll_p_out1", "pll_p",        28800000,       true },
-        { "pll_p_out2", "pll_p",        48000000,       true },
-        { "pll_p_out3", "pll_p",        72000000,       true },
-        { "pll_p_out4", "pll_p",        24000000,       true },
-        { "pll_c",      "clk_m",        600000000,      true },
-        { "pll_c_out1", "pll_c",        120000000,      true },
-        { "sclk",       "pll_c_out1",   120000000,      true },
-        { "hclk",       "sclk",         120000000,      true },
-        { "pclk",       "hclk",         60000000,       true },
-        { "csite",      NULL,           0,              true },
-        { "emc",        NULL,           0,              true },
-        { "cpu",        NULL,           0,              true },
-        { NULL,         NULL,           0,              0},
-};
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "clk_m",      NULL,           0,              true },
-        { "pll_p",      "pll_ref",      408000000,      true },
-        { "pll_p_out1", "pll_p",        9600000,        true },
-        { "pll_p_out4", "pll_p",        102000000,      true },
-        { "sclk",       "pll_p_out4",   102000000,      true },
-        { "hclk",       "sclk",         102000000,      true },
-        { "pclk",       "hclk",         51000000,       true },
-        { "csite",      NULL,           0,              true },
-        { NULL,         NULL,           0,              0},
-};
-#endif
-
-
 static void __init tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -141,8 +105,6 @@ void __init tegra20_init_early(void)
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
         tegra_init_fuse();
-        tegra2_init_clocks();
-        tegra_clk_init_from_table(tegra20_clk_init_table);
         tegra_init_cache();
         tegra_pmc_init();
         tegra_powergate_init();
@@ -155,8 +117,6 @@ void __init tegra30_init_early(void)
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
         tegra_init_fuse();
-        tegra30_init_clocks();
-        tegra_clk_init_from_table(tegra30_clk_init_table);
         tegra_init_cache();
         tegra_pmc_init();
         tegra_powergate_init();
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 85d4a23bba03..ebffed67e2f5 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -266,7 +266,7 @@ static int __init tegra_cpufreq_init(void)
         if (IS_ERR(pll_x_clk))
                 return PTR_ERR(pll_x_clk);
 
-        pll_p_clk = clk_get_sys(NULL, "pll_p");
+        pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
         if (IS_ERR(pll_p_clk))
                 return PTR_ERR(pll_p_clk);
 
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index 95f3a547c770..85bbf10a7d0d 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -31,9 +31,6 @@ enum tegra_clk_ex_param {
         TEGRA_CLK_PLLD_MIPI_MUX_SEL,
 };
 
-void tegra_periph_reset_deassert(struct clk *c);
-void tegra_periph_reset_assert(struct clk *c);
-
 #ifndef CONFIG_COMMON_CLK
 unsigned long clk_get_rate_all_locked(struct clk *c);
 #endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index bffcd643d7a3..b60165f1ca02 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -33,11 +33,11 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/export.h>
+#include <linux/clk/tegra.h>
 
 #include <asm/sizes.h>
 #include <asm/mach/pci.h>
 
-#include <mach/clk.h>
 #include <mach/powergate.h>
 
 #include "board.h"
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 2cc1185d902e..c6bc8f85759c 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -26,8 +26,8 @@
 #include <linux/io.h>
 #include <linux/seq_file.h>
 #include <linux/spinlock.h>
+#include <linux/clk/tegra.h>
 
-#include <mach/clk.h>
 #include <mach/powergate.h>
 
 #include "fuse.h"