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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:12:17 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:12:18 -0500
commit5ce7aba976ebdfbf467e3cbcd3a7536ebdec4b11 (patch)
treea31ceb4a167035aad73fd116ee8512fca905fd7b /arch
parent7ae1c76ee5b58fe5bd55a07f99a3359333270b86 (diff)
parentb6a03d0492dedb5c10b8a5708ee92e04b0590c07 (diff)
Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann: - Updates to the ux500 cpufreq code - Moving the u300 DMA controller driver to drivers/dma - Moving versatile express drivers out of arch/arm for sharing with arch/arm64 - Device tree bindings for the OMAP General Purpose Memory Controller * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits) ARM: OMAP2+: gpmc: Add device tree documentation for elm handle ARM: OMAP2+: gpmc: add DT bindings for OneNAND ARM: OMAP2+: gpmc-onenand: drop __init annotation mtd: omap-onenand: pass device_node in platform data ARM: OMAP2+: Prevent potential crash if GPMC probe fails ARM: OMAP2+: gpmc: Remove unneeded of_node_put() arm: Move sp810.h to include/linux/amba/ ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs ARM: OMAP: gpmc-nand: drop __init annotation mtd: omap-nand: pass device_node in platform data ARM: OMAP: gpmc: don't create devices from initcall on DT dma: coh901318: cut down on platform data abstraction dma: coh901318: merge header files dma: coh901318: push definitions into driver dma: coh901318: push header down into the DMA subsystem dma: coh901318: skip hard-coded addresses dma: coh901318: remove hardcoded target addresses dma: coh901318: push platform data into driver dma: coh901318: create a proper platform data file ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/hardware/sp810.h64
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c15
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c232
-rw-r--r--arch/arm/mach-u300/core.c1087
-rw-r--r--arch/arm/mach-u300/dma_channels.h60
-rw-r--r--arch/arm/mach-u300/include/mach/coh901318.h267
-rw-r--r--arch/arm/mach-u300/spi.c3
-rw-r--r--arch/arm/plat-spear/restart.c2
9 files changed, 243 insertions, 1489 deletions
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
deleted file mode 100644
index 6636430dd0e6..000000000000
--- a/arch/arm/include/asm/hardware/sp810.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/sp810.h
3 *
4 * ARM PrimeXsys System Controller SP810 header file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar <viresh.linux@gmail.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARM_SP810_H
15#define __ASM_ARM_SP810_H
16
17#include <linux/io.h>
18
19/* sysctl registers offset */
20#define SCCTRL 0x000
21#define SCSYSSTAT 0x004
22#define SCIMCTRL 0x008
23#define SCIMSTAT 0x00C
24#define SCXTALCTRL 0x010
25#define SCPLLCTRL 0x014
26#define SCPLLFCTRL 0x018
27#define SCPERCTRL0 0x01C
28#define SCPERCTRL1 0x020
29#define SCPEREN 0x024
30#define SCPERDIS 0x028
31#define SCPERCLKEN 0x02C
32#define SCPERSTAT 0x030
33#define SCSYSID0 0xEE0
34#define SCSYSID1 0xEE4
35#define SCSYSID2 0xEE8
36#define SCSYSID3 0xEEC
37#define SCITCR 0xF00
38#define SCITIR0 0xF04
39#define SCITIR1 0xF08
40#define SCITOR 0xF0C
41#define SCCNTCTRL 0xF10
42#define SCCNTDATA 0xF14
43#define SCCNTSTEP 0xF18
44#define SCPERIPHID0 0xFE0
45#define SCPERIPHID1 0xFE4
46#define SCPERIPHID2 0xFE8
47#define SCPERIPHID3 0xFEC
48#define SCPCELLID0 0xFF0
49#define SCPCELLID1 0xFF4
50#define SCPCELLID2 0xFF8
51#define SCPCELLID3 0xFFC
52
53#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
54
55static inline void sysctl_soft_reset(void __iomem *base)
56{
57 /* switch to slow mode */
58 writel(0x2, base + SCCTRL);
59
60 /* writing any value to SCSYSSTAT reg will reset system */
61 writel(0, base + SCSYSSTAT);
62}
63
64#endif /* __ASM_ARM_SP810_H */
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index db969a5c4998..afc1e8c32d6c 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
89 return 0; 89 return 0;
90} 90}
91 91
92static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 92static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
93{ 93{
94 /* support only OMAP3 class */ 94 /* support only OMAP3 class */
95 if (!cpu_is_omap34xx()) { 95 if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
96 pr_err("BCH ecc is not supported on this CPU\n"); 96 pr_err("BCH ecc is not supported on this CPU\n");
97 return 0; 97 return 0;
98 } 98 }
99 99
100 /* 100 /*
101 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. 101 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
102 * Other chips may be added if confirmed to work. 102 * and AM33xx derivates. Other chips may be added if confirmed to work.
103 */ 103 */
104 if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && 104 if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
105 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { 105 (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
106 (!soc_is_am33xx())) {
106 pr_err("BCH 4-bit mode is not supported on this CPU\n"); 107 pr_err("BCH 4-bit mode is not supported on this CPU\n");
107 return 0; 108 return 0;
108 } 109 }
@@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
110 return 1; 111 return 1;
111} 112}
112 113
113int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, 114int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
114 struct gpmc_timings *gpmc_t) 115 struct gpmc_timings *gpmc_t)
115{ 116{
116 int err = 0; 117 int err = 0;
117 struct device *dev = &gpmc_nand_device.dev; 118 struct device *dev = &gpmc_nand_device.dev;
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 94a349e4dc96..fadd87435cd0 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
356 return ret; 356 return ret;
357} 357}
358 358
359void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data) 359void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
360{ 360{
361 int err; 361 int err;
362 362
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 64bac53da0e8..03d771349be6 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -25,6 +25,10 @@
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/of.h>
29#include <linux/of_mtd.h>
30#include <linux/of_device.h>
31#include <linux/mtd/nand.h>
28 32
29#include <linux/platform_data/mtd-nand-omap2.h> 33#include <linux/platform_data/mtd-nand-omap2.h>
30 34
@@ -34,6 +38,8 @@
34#include "common.h" 38#include "common.h"
35#include "omap_device.h" 39#include "omap_device.h"
36#include "gpmc.h" 40#include "gpmc.h"
41#include "gpmc-nand.h"
42#include "gpmc-onenand.h"
37 43
38#define DEVICE_NAME "omap-gpmc" 44#define DEVICE_NAME "omap-gpmc"
39 45
@@ -145,7 +151,8 @@ static unsigned gpmc_irq_start;
145static struct resource gpmc_mem_root; 151static struct resource gpmc_mem_root;
146static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 152static struct resource gpmc_cs_mem[GPMC_CS_NUM];
147static DEFINE_SPINLOCK(gpmc_mem_lock); 153static DEFINE_SPINLOCK(gpmc_mem_lock);
148static unsigned int gpmc_cs_map; /* flag for cs which are initialized */ 154/* Define chip-selects as reserved by default until probe completes */
155static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
149static struct device *gpmc_dev; 156static struct device *gpmc_dev;
150static int gpmc_irq; 157static int gpmc_irq;
151static resource_size_t phys_base, mem_size; 158static resource_size_t phys_base, mem_size;
@@ -1118,9 +1125,216 @@ int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1118 /* TODO: remove, see function definition */ 1125 /* TODO: remove, see function definition */
1119 gpmc_convert_ps_to_ns(gpmc_t); 1126 gpmc_convert_ps_to_ns(gpmc_t);
1120 1127
1128 /* Now the GPMC is initialised, unreserve the chip-selects */
1129 gpmc_cs_map = 0;
1130
1121 return 0; 1131 return 0;
1122} 1132}
1123 1133
1134#ifdef CONFIG_OF
1135static struct of_device_id gpmc_dt_ids[] = {
1136 { .compatible = "ti,omap2420-gpmc" },
1137 { .compatible = "ti,omap2430-gpmc" },
1138 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1139 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1140 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1141 { }
1142};
1143MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1144
1145static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1146 struct gpmc_timings *gpmc_t)
1147{
1148 u32 val;
1149
1150 memset(gpmc_t, 0, sizeof(*gpmc_t));
1151
1152 /* minimum clock period for syncronous mode */
1153 if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1154 gpmc_t->sync_clk = val;
1155
1156 /* chip select timtings */
1157 if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1158 gpmc_t->cs_on = val;
1159
1160 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1161 gpmc_t->cs_rd_off = val;
1162
1163 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1164 gpmc_t->cs_wr_off = val;
1165
1166 /* ADV signal timings */
1167 if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1168 gpmc_t->adv_on = val;
1169
1170 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1171 gpmc_t->adv_rd_off = val;
1172
1173 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1174 gpmc_t->adv_wr_off = val;
1175
1176 /* WE signal timings */
1177 if (!of_property_read_u32(np, "gpmc,we-on", &val))
1178 gpmc_t->we_on = val;
1179
1180 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1181 gpmc_t->we_off = val;
1182
1183 /* OE signal timings */
1184 if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1185 gpmc_t->oe_on = val;
1186
1187 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1188 gpmc_t->oe_off = val;
1189
1190 /* access and cycle timings */
1191 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1192 gpmc_t->page_burst_access = val;
1193
1194 if (!of_property_read_u32(np, "gpmc,access", &val))
1195 gpmc_t->access = val;
1196
1197 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1198 gpmc_t->rd_cycle = val;
1199
1200 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1201 gpmc_t->wr_cycle = val;
1202
1203 /* only for OMAP3430 */
1204 if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1205 gpmc_t->wr_access = val;
1206
1207 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1208 gpmc_t->wr_data_mux_bus = val;
1209}
1210
1211#ifdef CONFIG_MTD_NAND
1212
1213static const char * const nand_ecc_opts[] = {
1214 [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
1215 [OMAP_ECC_HAMMING_CODE_HW] = "hw",
1216 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
1217 [OMAP_ECC_BCH4_CODE_HW] = "bch4",
1218 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1219};
1220
1221static int gpmc_probe_nand_child(struct platform_device *pdev,
1222 struct device_node *child)
1223{
1224 u32 val;
1225 const char *s;
1226 struct gpmc_timings gpmc_t;
1227 struct omap_nand_platform_data *gpmc_nand_data;
1228
1229 if (of_property_read_u32(child, "reg", &val) < 0) {
1230 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1231 child->full_name);
1232 return -ENODEV;
1233 }
1234
1235 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1236 GFP_KERNEL);
1237 if (!gpmc_nand_data)
1238 return -ENOMEM;
1239
1240 gpmc_nand_data->cs = val;
1241 gpmc_nand_data->of_node = child;
1242
1243 if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1244 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1245 if (!strcasecmp(s, nand_ecc_opts[val])) {
1246 gpmc_nand_data->ecc_opt = val;
1247 break;
1248 }
1249
1250 val = of_get_nand_bus_width(child);
1251 if (val == 16)
1252 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1253
1254 gpmc_read_timings_dt(child, &gpmc_t);
1255 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1256
1257 return 0;
1258}
1259#else
1260static int gpmc_probe_nand_child(struct platform_device *pdev,
1261 struct device_node *child)
1262{
1263 return 0;
1264}
1265#endif
1266
1267#ifdef CONFIG_MTD_ONENAND
1268static int gpmc_probe_onenand_child(struct platform_device *pdev,
1269 struct device_node *child)
1270{
1271 u32 val;
1272 struct omap_onenand_platform_data *gpmc_onenand_data;
1273
1274 if (of_property_read_u32(child, "reg", &val) < 0) {
1275 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1276 child->full_name);
1277 return -ENODEV;
1278 }
1279
1280 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1281 GFP_KERNEL);
1282 if (!gpmc_onenand_data)
1283 return -ENOMEM;
1284
1285 gpmc_onenand_data->cs = val;
1286 gpmc_onenand_data->of_node = child;
1287 gpmc_onenand_data->dma_channel = -1;
1288
1289 if (!of_property_read_u32(child, "dma-channel", &val))
1290 gpmc_onenand_data->dma_channel = val;
1291
1292 gpmc_onenand_init(gpmc_onenand_data);
1293
1294 return 0;
1295}
1296#else
1297static int gpmc_probe_onenand_child(struct platform_device *pdev,
1298 struct device_node *child)
1299{
1300 return 0;
1301}
1302#endif
1303
1304static int gpmc_probe_dt(struct platform_device *pdev)
1305{
1306 int ret;
1307 struct device_node *child;
1308 const struct of_device_id *of_id =
1309 of_match_device(gpmc_dt_ids, &pdev->dev);
1310
1311 if (!of_id)
1312 return 0;
1313
1314 for_each_node_by_name(child, "nand") {
1315 ret = gpmc_probe_nand_child(pdev, child);
1316 if (ret < 0) {
1317 of_node_put(child);
1318 return ret;
1319 }
1320 }
1321
1322 for_each_node_by_name(child, "onenand") {
1323 ret = gpmc_probe_onenand_child(pdev, child);
1324 if (ret < 0) {
1325 of_node_put(child);
1326 return ret;
1327 }
1328 }
1329 return 0;
1330}
1331#else
1332static int gpmc_probe_dt(struct platform_device *pdev)
1333{
1334 return 0;
1335}
1336#endif
1337
1124static int gpmc_probe(struct platform_device *pdev) 1338static int gpmc_probe(struct platform_device *pdev)
1125{ 1339{
1126 int rc; 1340 int rc;
@@ -1172,6 +1386,14 @@ static int gpmc_probe(struct platform_device *pdev)
1172 if (IS_ERR_VALUE(gpmc_setup_irq())) 1386 if (IS_ERR_VALUE(gpmc_setup_irq()))
1173 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); 1387 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1174 1388
1389 rc = gpmc_probe_dt(pdev);
1390 if (rc < 0) {
1391 clk_disable_unprepare(gpmc_l3_clk);
1392 clk_put(gpmc_l3_clk);
1393 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1394 return rc;
1395 }
1396
1175 return 0; 1397 return 0;
1176} 1398}
1177 1399
@@ -1189,6 +1411,7 @@ static struct platform_driver gpmc_driver = {
1189 .driver = { 1411 .driver = {
1190 .name = DEVICE_NAME, 1412 .name = DEVICE_NAME,
1191 .owner = THIS_MODULE, 1413 .owner = THIS_MODULE,
1414 .of_match_table = of_match_ptr(gpmc_dt_ids),
1192 }, 1415 },
1193}; 1416};
1194 1417
@@ -1212,6 +1435,13 @@ static int __init omap_gpmc_init(void)
1212 struct platform_device *pdev; 1435 struct platform_device *pdev;
1213 char *oh_name = "gpmc"; 1436 char *oh_name = "gpmc";
1214 1437
1438 /*
1439 * if the board boots up with a populated DT, do not
1440 * manually add the device from this initcall
1441 */
1442 if (of_have_populated_dt())
1443 return -ENODEV;
1444
1215 oh = omap_hwmod_lookup(oh_name); 1445 oh = omap_hwmod_lookup(oh_name);
1216 if (!oh) { 1446 if (!oh) {
1217 pr_err("Could not look up %s\n", oh_name); 1447 pr_err("Could not look up %s\n", oh_name);
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 12060ae4e8f1..a683d17b2ce4 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -31,6 +31,7 @@
31#include <linux/dma-mapping.h> 31#include <linux/dma-mapping.h>
32#include <linux/platform_data/clk-u300.h> 32#include <linux/platform_data/clk-u300.h>
33#include <linux/platform_data/pinctrl-coh901.h> 33#include <linux/platform_data/pinctrl-coh901.h>
34#include <linux/platform_data/dma-coh901318.h>
34#include <linux/irqchip/arm-vic.h> 35#include <linux/irqchip/arm-vic.h>
35 36
36#include <asm/types.h> 37#include <asm/types.h>
@@ -40,7 +41,6 @@
40#include <asm/mach-types.h> 41#include <asm/mach-types.h>
41#include <asm/mach/arch.h> 42#include <asm/mach/arch.h>
42 43
43#include <mach/coh901318.h>
44#include <mach/hardware.h> 44#include <mach/hardware.h>
45#include <mach/syscon.h> 45#include <mach/syscon.h>
46#include <mach/irqs.h> 46#include <mach/irqs.h>
@@ -49,7 +49,6 @@
49#include "spi.h" 49#include "spi.h"
50#include "i2c.h" 50#include "i2c.h"
51#include "u300-gpio.h" 51#include "u300-gpio.h"
52#include "dma_channels.h"
53 52
54/* 53/*
55 * Static I/O mappings that are needed for booting the U300 platforms. The 54 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -327,1089 +326,6 @@ static struct resource dma_resource[] = {
327 } 326 }
328}; 327};
329 328
330/* points out all dma slave channels.
331 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
332 * Select all channels from A to B, end of list is marked with -1,-1
333 */
334static int dma_slave_channels[] = {
335 U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
336 U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
337
338/* points out all dma memcpy channels. */
339static int dma_memcpy_channels[] = {
340 U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
341
342/** register dma for memory access
343 *
344 * active 1 means dma intends to access memory
345 * 0 means dma wont access memory
346 */
347static void coh901318_access_memory_state(struct device *dev, bool active)
348{
349}
350
351#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
352 COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
353 COH901318_CX_CFG_LCR_DISABLE | \
354 COH901318_CX_CFG_TC_IRQ_ENABLE | \
355 COH901318_CX_CFG_BE_IRQ_ENABLE)
356#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
357 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
358 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
359 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
360 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
361 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
362 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
363 COH901318_CX_CTRL_TCP_DISABLE | \
364 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
365 COH901318_CX_CTRL_HSP_DISABLE | \
366 COH901318_CX_CTRL_HSS_DISABLE | \
367 COH901318_CX_CTRL_DDMA_LEGACY | \
368 COH901318_CX_CTRL_PRDD_SOURCE)
369#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
370 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
371 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
372 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
373 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
374 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
375 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
376 COH901318_CX_CTRL_TCP_DISABLE | \
377 COH901318_CX_CTRL_TC_IRQ_DISABLE | \
378 COH901318_CX_CTRL_HSP_DISABLE | \
379 COH901318_CX_CTRL_HSS_DISABLE | \
380 COH901318_CX_CTRL_DDMA_LEGACY | \
381 COH901318_CX_CTRL_PRDD_SOURCE)
382#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
383 COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
384 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
385 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
386 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
387 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
388 COH901318_CX_CTRL_MASTER_MODE_M1RW | \
389 COH901318_CX_CTRL_TCP_DISABLE | \
390 COH901318_CX_CTRL_TC_IRQ_ENABLE | \
391 COH901318_CX_CTRL_HSP_DISABLE | \
392 COH901318_CX_CTRL_HSS_DISABLE | \
393 COH901318_CX_CTRL_DDMA_LEGACY | \
394 COH901318_CX_CTRL_PRDD_SOURCE)
395
396const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
397 {
398 .number = U300_DMA_MSL_TX_0,
399 .name = "MSL TX 0",
400 .priority_high = 0,
401 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
402 },
403 {
404 .number = U300_DMA_MSL_TX_1,
405 .name = "MSL TX 1",
406 .priority_high = 0,
407 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
408 .param.config = COH901318_CX_CFG_CH_DISABLE |
409 COH901318_CX_CFG_LCR_DISABLE |
410 COH901318_CX_CFG_TC_IRQ_ENABLE |
411 COH901318_CX_CFG_BE_IRQ_ENABLE,
412 .param.ctrl_lli_chained = 0 |
413 COH901318_CX_CTRL_TC_ENABLE |
414 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
415 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
416 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
417 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
418 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
419 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
420 COH901318_CX_CTRL_TCP_DISABLE |
421 COH901318_CX_CTRL_TC_IRQ_DISABLE |
422 COH901318_CX_CTRL_HSP_ENABLE |
423 COH901318_CX_CTRL_HSS_DISABLE |
424 COH901318_CX_CTRL_DDMA_LEGACY |
425 COH901318_CX_CTRL_PRDD_SOURCE,
426 .param.ctrl_lli = 0 |
427 COH901318_CX_CTRL_TC_ENABLE |
428 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
429 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
430 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
431 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
432 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
433 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
434 COH901318_CX_CTRL_TCP_ENABLE |
435 COH901318_CX_CTRL_TC_IRQ_DISABLE |
436 COH901318_CX_CTRL_HSP_ENABLE |
437 COH901318_CX_CTRL_HSS_DISABLE |
438 COH901318_CX_CTRL_DDMA_LEGACY |
439 COH901318_CX_CTRL_PRDD_SOURCE,
440 .param.ctrl_lli_last = 0 |
441 COH901318_CX_CTRL_TC_ENABLE |
442 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
443 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
444 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
445 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
446 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
447 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
448 COH901318_CX_CTRL_TCP_ENABLE |
449 COH901318_CX_CTRL_TC_IRQ_ENABLE |
450 COH901318_CX_CTRL_HSP_ENABLE |
451 COH901318_CX_CTRL_HSS_DISABLE |
452 COH901318_CX_CTRL_DDMA_LEGACY |
453 COH901318_CX_CTRL_PRDD_SOURCE,
454 },
455 {
456 .number = U300_DMA_MSL_TX_2,
457 .name = "MSL TX 2",
458 .priority_high = 0,
459 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
460 .param.config = COH901318_CX_CFG_CH_DISABLE |
461 COH901318_CX_CFG_LCR_DISABLE |
462 COH901318_CX_CFG_TC_IRQ_ENABLE |
463 COH901318_CX_CFG_BE_IRQ_ENABLE,
464 .param.ctrl_lli_chained = 0 |
465 COH901318_CX_CTRL_TC_ENABLE |
466 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
467 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
468 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
469 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
470 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
471 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
472 COH901318_CX_CTRL_TCP_DISABLE |
473 COH901318_CX_CTRL_TC_IRQ_DISABLE |
474 COH901318_CX_CTRL_HSP_ENABLE |
475 COH901318_CX_CTRL_HSS_DISABLE |
476 COH901318_CX_CTRL_DDMA_LEGACY |
477 COH901318_CX_CTRL_PRDD_SOURCE,
478 .param.ctrl_lli = 0 |
479 COH901318_CX_CTRL_TC_ENABLE |
480 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
481 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
482 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
483 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
484 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
485 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
486 COH901318_CX_CTRL_TCP_ENABLE |
487 COH901318_CX_CTRL_TC_IRQ_DISABLE |
488 COH901318_CX_CTRL_HSP_ENABLE |
489 COH901318_CX_CTRL_HSS_DISABLE |
490 COH901318_CX_CTRL_DDMA_LEGACY |
491 COH901318_CX_CTRL_PRDD_SOURCE,
492 .param.ctrl_lli_last = 0 |
493 COH901318_CX_CTRL_TC_ENABLE |
494 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
495 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
496 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
497 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
498 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
499 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
500 COH901318_CX_CTRL_TCP_ENABLE |
501 COH901318_CX_CTRL_TC_IRQ_ENABLE |
502 COH901318_CX_CTRL_HSP_ENABLE |
503 COH901318_CX_CTRL_HSS_DISABLE |
504 COH901318_CX_CTRL_DDMA_LEGACY |
505 COH901318_CX_CTRL_PRDD_SOURCE,
506 .desc_nbr_max = 10,
507 },
508 {
509 .number = U300_DMA_MSL_TX_3,
510 .name = "MSL TX 3",
511 .priority_high = 0,
512 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
513 .param.config = COH901318_CX_CFG_CH_DISABLE |
514 COH901318_CX_CFG_LCR_DISABLE |
515 COH901318_CX_CFG_TC_IRQ_ENABLE |
516 COH901318_CX_CFG_BE_IRQ_ENABLE,
517 .param.ctrl_lli_chained = 0 |
518 COH901318_CX_CTRL_TC_ENABLE |
519 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
520 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
521 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
522 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
523 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
524 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
525 COH901318_CX_CTRL_TCP_DISABLE |
526 COH901318_CX_CTRL_TC_IRQ_DISABLE |
527 COH901318_CX_CTRL_HSP_ENABLE |
528 COH901318_CX_CTRL_HSS_DISABLE |
529 COH901318_CX_CTRL_DDMA_LEGACY |
530 COH901318_CX_CTRL_PRDD_SOURCE,
531 .param.ctrl_lli = 0 |
532 COH901318_CX_CTRL_TC_ENABLE |
533 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
534 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
535 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
536 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
537 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
538 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
539 COH901318_CX_CTRL_TCP_ENABLE |
540 COH901318_CX_CTRL_TC_IRQ_DISABLE |
541 COH901318_CX_CTRL_HSP_ENABLE |
542 COH901318_CX_CTRL_HSS_DISABLE |
543 COH901318_CX_CTRL_DDMA_LEGACY |
544 COH901318_CX_CTRL_PRDD_SOURCE,
545 .param.ctrl_lli_last = 0 |
546 COH901318_CX_CTRL_TC_ENABLE |
547 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
548 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
549 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
550 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
551 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
552 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
553 COH901318_CX_CTRL_TCP_ENABLE |
554 COH901318_CX_CTRL_TC_IRQ_ENABLE |
555 COH901318_CX_CTRL_HSP_ENABLE |
556 COH901318_CX_CTRL_HSS_DISABLE |
557 COH901318_CX_CTRL_DDMA_LEGACY |
558 COH901318_CX_CTRL_PRDD_SOURCE,
559 },
560 {
561 .number = U300_DMA_MSL_TX_4,
562 .name = "MSL TX 4",
563 .priority_high = 0,
564 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
565 .param.config = COH901318_CX_CFG_CH_DISABLE |
566 COH901318_CX_CFG_LCR_DISABLE |
567 COH901318_CX_CFG_TC_IRQ_ENABLE |
568 COH901318_CX_CFG_BE_IRQ_ENABLE,
569 .param.ctrl_lli_chained = 0 |
570 COH901318_CX_CTRL_TC_ENABLE |
571 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
572 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
573 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
574 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
575 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
576 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
577 COH901318_CX_CTRL_TCP_DISABLE |
578 COH901318_CX_CTRL_TC_IRQ_DISABLE |
579 COH901318_CX_CTRL_HSP_ENABLE |
580 COH901318_CX_CTRL_HSS_DISABLE |
581 COH901318_CX_CTRL_DDMA_LEGACY |
582 COH901318_CX_CTRL_PRDD_SOURCE,
583 .param.ctrl_lli = 0 |
584 COH901318_CX_CTRL_TC_ENABLE |
585 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
586 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
587 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
588 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
589 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
590 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
591 COH901318_CX_CTRL_TCP_ENABLE |
592 COH901318_CX_CTRL_TC_IRQ_DISABLE |
593 COH901318_CX_CTRL_HSP_ENABLE |
594 COH901318_CX_CTRL_HSS_DISABLE |
595 COH901318_CX_CTRL_DDMA_LEGACY |
596 COH901318_CX_CTRL_PRDD_SOURCE,
597 .param.ctrl_lli_last = 0 |
598 COH901318_CX_CTRL_TC_ENABLE |
599 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
600 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
601 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
602 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
603 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
604 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
605 COH901318_CX_CTRL_TCP_ENABLE |
606 COH901318_CX_CTRL_TC_IRQ_ENABLE |
607 COH901318_CX_CTRL_HSP_ENABLE |
608 COH901318_CX_CTRL_HSS_DISABLE |
609 COH901318_CX_CTRL_DDMA_LEGACY |
610 COH901318_CX_CTRL_PRDD_SOURCE,
611 },
612 {
613 .number = U300_DMA_MSL_TX_5,
614 .name = "MSL TX 5",
615 .priority_high = 0,
616 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
617 },
618 {
619 .number = U300_DMA_MSL_TX_6,
620 .name = "MSL TX 6",
621 .priority_high = 0,
622 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
623 },
624 {
625 .number = U300_DMA_MSL_RX_0,
626 .name = "MSL RX 0",
627 .priority_high = 0,
628 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
629 },
630 {
631 .number = U300_DMA_MSL_RX_1,
632 .name = "MSL RX 1",
633 .priority_high = 0,
634 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
635 .param.config = COH901318_CX_CFG_CH_DISABLE |
636 COH901318_CX_CFG_LCR_DISABLE |
637 COH901318_CX_CFG_TC_IRQ_ENABLE |
638 COH901318_CX_CFG_BE_IRQ_ENABLE,
639 .param.ctrl_lli_chained = 0 |
640 COH901318_CX_CTRL_TC_ENABLE |
641 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
642 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
643 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
644 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
645 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
646 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
647 COH901318_CX_CTRL_TCP_DISABLE |
648 COH901318_CX_CTRL_TC_IRQ_DISABLE |
649 COH901318_CX_CTRL_HSP_ENABLE |
650 COH901318_CX_CTRL_HSS_DISABLE |
651 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
652 COH901318_CX_CTRL_PRDD_DEST,
653 .param.ctrl_lli = 0,
654 .param.ctrl_lli_last = 0 |
655 COH901318_CX_CTRL_TC_ENABLE |
656 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
657 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
658 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
659 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
660 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
661 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
662 COH901318_CX_CTRL_TCP_DISABLE |
663 COH901318_CX_CTRL_TC_IRQ_ENABLE |
664 COH901318_CX_CTRL_HSP_ENABLE |
665 COH901318_CX_CTRL_HSS_DISABLE |
666 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
667 COH901318_CX_CTRL_PRDD_DEST,
668 },
669 {
670 .number = U300_DMA_MSL_RX_2,
671 .name = "MSL RX 2",
672 .priority_high = 0,
673 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
674 .param.config = COH901318_CX_CFG_CH_DISABLE |
675 COH901318_CX_CFG_LCR_DISABLE |
676 COH901318_CX_CFG_TC_IRQ_ENABLE |
677 COH901318_CX_CFG_BE_IRQ_ENABLE,
678 .param.ctrl_lli_chained = 0 |
679 COH901318_CX_CTRL_TC_ENABLE |
680 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
681 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
682 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
683 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
684 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
685 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
686 COH901318_CX_CTRL_TCP_DISABLE |
687 COH901318_CX_CTRL_TC_IRQ_DISABLE |
688 COH901318_CX_CTRL_HSP_ENABLE |
689 COH901318_CX_CTRL_HSS_DISABLE |
690 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
691 COH901318_CX_CTRL_PRDD_DEST,
692 .param.ctrl_lli = 0 |
693 COH901318_CX_CTRL_TC_ENABLE |
694 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
695 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
696 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
697 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
698 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
699 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
700 COH901318_CX_CTRL_TCP_DISABLE |
701 COH901318_CX_CTRL_TC_IRQ_ENABLE |
702 COH901318_CX_CTRL_HSP_ENABLE |
703 COH901318_CX_CTRL_HSS_DISABLE |
704 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
705 COH901318_CX_CTRL_PRDD_DEST,
706 .param.ctrl_lli_last = 0 |
707 COH901318_CX_CTRL_TC_ENABLE |
708 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
709 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
710 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
711 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
712 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
713 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
714 COH901318_CX_CTRL_TCP_DISABLE |
715 COH901318_CX_CTRL_TC_IRQ_ENABLE |
716 COH901318_CX_CTRL_HSP_ENABLE |
717 COH901318_CX_CTRL_HSS_DISABLE |
718 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
719 COH901318_CX_CTRL_PRDD_DEST,
720 },
721 {
722 .number = U300_DMA_MSL_RX_3,
723 .name = "MSL RX 3",
724 .priority_high = 0,
725 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
726 .param.config = COH901318_CX_CFG_CH_DISABLE |
727 COH901318_CX_CFG_LCR_DISABLE |
728 COH901318_CX_CFG_TC_IRQ_ENABLE |
729 COH901318_CX_CFG_BE_IRQ_ENABLE,
730 .param.ctrl_lli_chained = 0 |
731 COH901318_CX_CTRL_TC_ENABLE |
732 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
733 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
734 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
735 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
736 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
737 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
738 COH901318_CX_CTRL_TCP_DISABLE |
739 COH901318_CX_CTRL_TC_IRQ_DISABLE |
740 COH901318_CX_CTRL_HSP_ENABLE |
741 COH901318_CX_CTRL_HSS_DISABLE |
742 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
743 COH901318_CX_CTRL_PRDD_DEST,
744 .param.ctrl_lli = 0 |
745 COH901318_CX_CTRL_TC_ENABLE |
746 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
747 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
748 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
749 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
750 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
751 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
752 COH901318_CX_CTRL_TCP_DISABLE |
753 COH901318_CX_CTRL_TC_IRQ_ENABLE |
754 COH901318_CX_CTRL_HSP_ENABLE |
755 COH901318_CX_CTRL_HSS_DISABLE |
756 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
757 COH901318_CX_CTRL_PRDD_DEST,
758 .param.ctrl_lli_last = 0 |
759 COH901318_CX_CTRL_TC_ENABLE |
760 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
761 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
762 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
763 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
764 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
765 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
766 COH901318_CX_CTRL_TCP_DISABLE |
767 COH901318_CX_CTRL_TC_IRQ_ENABLE |
768 COH901318_CX_CTRL_HSP_ENABLE |
769 COH901318_CX_CTRL_HSS_DISABLE |
770 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
771 COH901318_CX_CTRL_PRDD_DEST,
772 },
773 {
774 .number = U300_DMA_MSL_RX_4,
775 .name = "MSL RX 4",
776 .priority_high = 0,
777 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
778 .param.config = COH901318_CX_CFG_CH_DISABLE |
779 COH901318_CX_CFG_LCR_DISABLE |
780 COH901318_CX_CFG_TC_IRQ_ENABLE |
781 COH901318_CX_CFG_BE_IRQ_ENABLE,
782 .param.ctrl_lli_chained = 0 |
783 COH901318_CX_CTRL_TC_ENABLE |
784 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
785 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
786 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
787 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
788 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
789 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
790 COH901318_CX_CTRL_TCP_DISABLE |
791 COH901318_CX_CTRL_TC_IRQ_DISABLE |
792 COH901318_CX_CTRL_HSP_ENABLE |
793 COH901318_CX_CTRL_HSS_DISABLE |
794 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
795 COH901318_CX_CTRL_PRDD_DEST,
796 .param.ctrl_lli = 0 |
797 COH901318_CX_CTRL_TC_ENABLE |
798 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
799 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
800 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
801 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
802 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
803 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
804 COH901318_CX_CTRL_TCP_DISABLE |
805 COH901318_CX_CTRL_TC_IRQ_ENABLE |
806 COH901318_CX_CTRL_HSP_ENABLE |
807 COH901318_CX_CTRL_HSS_DISABLE |
808 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
809 COH901318_CX_CTRL_PRDD_DEST,
810 .param.ctrl_lli_last = 0 |
811 COH901318_CX_CTRL_TC_ENABLE |
812 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
813 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
814 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
815 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
816 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
817 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
818 COH901318_CX_CTRL_TCP_DISABLE |
819 COH901318_CX_CTRL_TC_IRQ_ENABLE |
820 COH901318_CX_CTRL_HSP_ENABLE |
821 COH901318_CX_CTRL_HSS_DISABLE |
822 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
823 COH901318_CX_CTRL_PRDD_DEST,
824 },
825 {
826 .number = U300_DMA_MSL_RX_5,
827 .name = "MSL RX 5",
828 .priority_high = 0,
829 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
830 .param.config = COH901318_CX_CFG_CH_DISABLE |
831 COH901318_CX_CFG_LCR_DISABLE |
832 COH901318_CX_CFG_TC_IRQ_ENABLE |
833 COH901318_CX_CFG_BE_IRQ_ENABLE,
834 .param.ctrl_lli_chained = 0 |
835 COH901318_CX_CTRL_TC_ENABLE |
836 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
837 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
838 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
839 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
840 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
841 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
842 COH901318_CX_CTRL_TCP_DISABLE |
843 COH901318_CX_CTRL_TC_IRQ_DISABLE |
844 COH901318_CX_CTRL_HSP_ENABLE |
845 COH901318_CX_CTRL_HSS_DISABLE |
846 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
847 COH901318_CX_CTRL_PRDD_DEST,
848 .param.ctrl_lli = 0 |
849 COH901318_CX_CTRL_TC_ENABLE |
850 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
851 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
852 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
853 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
854 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
855 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
856 COH901318_CX_CTRL_TCP_DISABLE |
857 COH901318_CX_CTRL_TC_IRQ_ENABLE |
858 COH901318_CX_CTRL_HSP_ENABLE |
859 COH901318_CX_CTRL_HSS_DISABLE |
860 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
861 COH901318_CX_CTRL_PRDD_DEST,
862 .param.ctrl_lli_last = 0 |
863 COH901318_CX_CTRL_TC_ENABLE |
864 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
865 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
866 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
867 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
868 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
869 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
870 COH901318_CX_CTRL_TCP_DISABLE |
871 COH901318_CX_CTRL_TC_IRQ_ENABLE |
872 COH901318_CX_CTRL_HSP_ENABLE |
873 COH901318_CX_CTRL_HSS_DISABLE |
874 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
875 COH901318_CX_CTRL_PRDD_DEST,
876 },
877 {
878 .number = U300_DMA_MSL_RX_6,
879 .name = "MSL RX 6",
880 .priority_high = 0,
881 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
882 },
883 /*
884 * Don't set up device address, burst count or size of src
885 * or dst bus for this peripheral - handled by PrimeCell
886 * DMA extension.
887 */
888 {
889 .number = U300_DMA_MMCSD_RX_TX,
890 .name = "MMCSD RX TX",
891 .priority_high = 0,
892 .param.config = COH901318_CX_CFG_CH_DISABLE |
893 COH901318_CX_CFG_LCR_DISABLE |
894 COH901318_CX_CFG_TC_IRQ_ENABLE |
895 COH901318_CX_CFG_BE_IRQ_ENABLE,
896 .param.ctrl_lli_chained = 0 |
897 COH901318_CX_CTRL_TC_ENABLE |
898 COH901318_CX_CTRL_MASTER_MODE_M1RW |
899 COH901318_CX_CTRL_TCP_ENABLE |
900 COH901318_CX_CTRL_TC_IRQ_DISABLE |
901 COH901318_CX_CTRL_HSP_ENABLE |
902 COH901318_CX_CTRL_HSS_DISABLE |
903 COH901318_CX_CTRL_DDMA_LEGACY,
904 .param.ctrl_lli = 0 |
905 COH901318_CX_CTRL_TC_ENABLE |
906 COH901318_CX_CTRL_MASTER_MODE_M1RW |
907 COH901318_CX_CTRL_TCP_ENABLE |
908 COH901318_CX_CTRL_TC_IRQ_DISABLE |
909 COH901318_CX_CTRL_HSP_ENABLE |
910 COH901318_CX_CTRL_HSS_DISABLE |
911 COH901318_CX_CTRL_DDMA_LEGACY,
912 .param.ctrl_lli_last = 0 |
913 COH901318_CX_CTRL_TC_ENABLE |
914 COH901318_CX_CTRL_MASTER_MODE_M1RW |
915 COH901318_CX_CTRL_TCP_DISABLE |
916 COH901318_CX_CTRL_TC_IRQ_ENABLE |
917 COH901318_CX_CTRL_HSP_ENABLE |
918 COH901318_CX_CTRL_HSS_DISABLE |
919 COH901318_CX_CTRL_DDMA_LEGACY,
920
921 },
922 {
923 .number = U300_DMA_MSPRO_TX,
924 .name = "MSPRO TX",
925 .priority_high = 0,
926 },
927 {
928 .number = U300_DMA_MSPRO_RX,
929 .name = "MSPRO RX",
930 .priority_high = 0,
931 },
932 /*
933 * Don't set up device address, burst count or size of src
934 * or dst bus for this peripheral - handled by PrimeCell
935 * DMA extension.
936 */
937 {
938 .number = U300_DMA_UART0_TX,
939 .name = "UART0 TX",
940 .priority_high = 0,
941 .param.config = COH901318_CX_CFG_CH_DISABLE |
942 COH901318_CX_CFG_LCR_DISABLE |
943 COH901318_CX_CFG_TC_IRQ_ENABLE |
944 COH901318_CX_CFG_BE_IRQ_ENABLE,
945 .param.ctrl_lli_chained = 0 |
946 COH901318_CX_CTRL_TC_ENABLE |
947 COH901318_CX_CTRL_MASTER_MODE_M1RW |
948 COH901318_CX_CTRL_TCP_ENABLE |
949 COH901318_CX_CTRL_TC_IRQ_DISABLE |
950 COH901318_CX_CTRL_HSP_ENABLE |
951 COH901318_CX_CTRL_HSS_DISABLE |
952 COH901318_CX_CTRL_DDMA_LEGACY,
953 .param.ctrl_lli = 0 |
954 COH901318_CX_CTRL_TC_ENABLE |
955 COH901318_CX_CTRL_MASTER_MODE_M1RW |
956 COH901318_CX_CTRL_TCP_ENABLE |
957 COH901318_CX_CTRL_TC_IRQ_ENABLE |
958 COH901318_CX_CTRL_HSP_ENABLE |
959 COH901318_CX_CTRL_HSS_DISABLE |
960 COH901318_CX_CTRL_DDMA_LEGACY,
961 .param.ctrl_lli_last = 0 |
962 COH901318_CX_CTRL_TC_ENABLE |
963 COH901318_CX_CTRL_MASTER_MODE_M1RW |
964 COH901318_CX_CTRL_TCP_ENABLE |
965 COH901318_CX_CTRL_TC_IRQ_ENABLE |
966 COH901318_CX_CTRL_HSP_ENABLE |
967 COH901318_CX_CTRL_HSS_DISABLE |
968 COH901318_CX_CTRL_DDMA_LEGACY,
969 },
970 {
971 .number = U300_DMA_UART0_RX,
972 .name = "UART0 RX",
973 .priority_high = 0,
974 .param.config = COH901318_CX_CFG_CH_DISABLE |
975 COH901318_CX_CFG_LCR_DISABLE |
976 COH901318_CX_CFG_TC_IRQ_ENABLE |
977 COH901318_CX_CFG_BE_IRQ_ENABLE,
978 .param.ctrl_lli_chained = 0 |
979 COH901318_CX_CTRL_TC_ENABLE |
980 COH901318_CX_CTRL_MASTER_MODE_M1RW |
981 COH901318_CX_CTRL_TCP_ENABLE |
982 COH901318_CX_CTRL_TC_IRQ_DISABLE |
983 COH901318_CX_CTRL_HSP_ENABLE |
984 COH901318_CX_CTRL_HSS_DISABLE |
985 COH901318_CX_CTRL_DDMA_LEGACY,
986 .param.ctrl_lli = 0 |
987 COH901318_CX_CTRL_TC_ENABLE |
988 COH901318_CX_CTRL_MASTER_MODE_M1RW |
989 COH901318_CX_CTRL_TCP_ENABLE |
990 COH901318_CX_CTRL_TC_IRQ_ENABLE |
991 COH901318_CX_CTRL_HSP_ENABLE |
992 COH901318_CX_CTRL_HSS_DISABLE |
993 COH901318_CX_CTRL_DDMA_LEGACY,
994 .param.ctrl_lli_last = 0 |
995 COH901318_CX_CTRL_TC_ENABLE |
996 COH901318_CX_CTRL_MASTER_MODE_M1RW |
997 COH901318_CX_CTRL_TCP_ENABLE |
998 COH901318_CX_CTRL_TC_IRQ_ENABLE |
999 COH901318_CX_CTRL_HSP_ENABLE |
1000 COH901318_CX_CTRL_HSS_DISABLE |
1001 COH901318_CX_CTRL_DDMA_LEGACY,
1002 },
1003 {
1004 .number = U300_DMA_APEX_TX,
1005 .name = "APEX TX",
1006 .priority_high = 0,
1007 },
1008 {
1009 .number = U300_DMA_APEX_RX,
1010 .name = "APEX RX",
1011 .priority_high = 0,
1012 },
1013 {
1014 .number = U300_DMA_PCM_I2S0_TX,
1015 .name = "PCM I2S0 TX",
1016 .priority_high = 1,
1017 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1018 .param.config = COH901318_CX_CFG_CH_DISABLE |
1019 COH901318_CX_CFG_LCR_DISABLE |
1020 COH901318_CX_CFG_TC_IRQ_ENABLE |
1021 COH901318_CX_CFG_BE_IRQ_ENABLE,
1022 .param.ctrl_lli_chained = 0 |
1023 COH901318_CX_CTRL_TC_ENABLE |
1024 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1025 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1026 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1027 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1028 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1029 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1030 COH901318_CX_CTRL_TCP_DISABLE |
1031 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1032 COH901318_CX_CTRL_HSP_ENABLE |
1033 COH901318_CX_CTRL_HSS_DISABLE |
1034 COH901318_CX_CTRL_DDMA_LEGACY |
1035 COH901318_CX_CTRL_PRDD_SOURCE,
1036 .param.ctrl_lli = 0 |
1037 COH901318_CX_CTRL_TC_ENABLE |
1038 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1039 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1040 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1041 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1042 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1043 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1044 COH901318_CX_CTRL_TCP_ENABLE |
1045 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1046 COH901318_CX_CTRL_HSP_ENABLE |
1047 COH901318_CX_CTRL_HSS_DISABLE |
1048 COH901318_CX_CTRL_DDMA_LEGACY |
1049 COH901318_CX_CTRL_PRDD_SOURCE,
1050 .param.ctrl_lli_last = 0 |
1051 COH901318_CX_CTRL_TC_ENABLE |
1052 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1053 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1054 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1055 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1056 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1057 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1058 COH901318_CX_CTRL_TCP_ENABLE |
1059 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1060 COH901318_CX_CTRL_HSP_ENABLE |
1061 COH901318_CX_CTRL_HSS_DISABLE |
1062 COH901318_CX_CTRL_DDMA_LEGACY |
1063 COH901318_CX_CTRL_PRDD_SOURCE,
1064 },
1065 {
1066 .number = U300_DMA_PCM_I2S0_RX,
1067 .name = "PCM I2S0 RX",
1068 .priority_high = 1,
1069 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1070 .param.config = COH901318_CX_CFG_CH_DISABLE |
1071 COH901318_CX_CFG_LCR_DISABLE |
1072 COH901318_CX_CFG_TC_IRQ_ENABLE |
1073 COH901318_CX_CFG_BE_IRQ_ENABLE,
1074 .param.ctrl_lli_chained = 0 |
1075 COH901318_CX_CTRL_TC_ENABLE |
1076 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1077 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1078 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1079 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1080 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1081 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1082 COH901318_CX_CTRL_TCP_DISABLE |
1083 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1084 COH901318_CX_CTRL_HSP_ENABLE |
1085 COH901318_CX_CTRL_HSS_DISABLE |
1086 COH901318_CX_CTRL_DDMA_LEGACY |
1087 COH901318_CX_CTRL_PRDD_DEST,
1088 .param.ctrl_lli = 0 |
1089 COH901318_CX_CTRL_TC_ENABLE |
1090 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1091 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1092 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1093 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1094 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1095 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1096 COH901318_CX_CTRL_TCP_ENABLE |
1097 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1098 COH901318_CX_CTRL_HSP_ENABLE |
1099 COH901318_CX_CTRL_HSS_DISABLE |
1100 COH901318_CX_CTRL_DDMA_LEGACY |
1101 COH901318_CX_CTRL_PRDD_DEST,
1102 .param.ctrl_lli_last = 0 |
1103 COH901318_CX_CTRL_TC_ENABLE |
1104 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1105 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1106 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1107 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1108 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1109 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1110 COH901318_CX_CTRL_TCP_ENABLE |
1111 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1112 COH901318_CX_CTRL_HSP_ENABLE |
1113 COH901318_CX_CTRL_HSS_DISABLE |
1114 COH901318_CX_CTRL_DDMA_LEGACY |
1115 COH901318_CX_CTRL_PRDD_DEST,
1116 },
1117 {
1118 .number = U300_DMA_PCM_I2S1_TX,
1119 .name = "PCM I2S1 TX",
1120 .priority_high = 1,
1121 .dev_addr = U300_PCM_I2S1_BASE + 0x14,
1122 .param.config = COH901318_CX_CFG_CH_DISABLE |
1123 COH901318_CX_CFG_LCR_DISABLE |
1124 COH901318_CX_CFG_TC_IRQ_ENABLE |
1125 COH901318_CX_CFG_BE_IRQ_ENABLE,
1126 .param.ctrl_lli_chained = 0 |
1127 COH901318_CX_CTRL_TC_ENABLE |
1128 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1129 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1130 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1131 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1132 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1133 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1134 COH901318_CX_CTRL_TCP_DISABLE |
1135 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1136 COH901318_CX_CTRL_HSP_ENABLE |
1137 COH901318_CX_CTRL_HSS_DISABLE |
1138 COH901318_CX_CTRL_DDMA_LEGACY |
1139 COH901318_CX_CTRL_PRDD_SOURCE,
1140 .param.ctrl_lli = 0 |
1141 COH901318_CX_CTRL_TC_ENABLE |
1142 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1143 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1144 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1145 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1146 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1147 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1148 COH901318_CX_CTRL_TCP_ENABLE |
1149 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1150 COH901318_CX_CTRL_HSP_ENABLE |
1151 COH901318_CX_CTRL_HSS_DISABLE |
1152 COH901318_CX_CTRL_DDMA_LEGACY |
1153 COH901318_CX_CTRL_PRDD_SOURCE,
1154 .param.ctrl_lli_last = 0 |
1155 COH901318_CX_CTRL_TC_ENABLE |
1156 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1157 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1158 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1159 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1160 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1161 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1162 COH901318_CX_CTRL_TCP_ENABLE |
1163 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1164 COH901318_CX_CTRL_HSP_ENABLE |
1165 COH901318_CX_CTRL_HSS_DISABLE |
1166 COH901318_CX_CTRL_DDMA_LEGACY |
1167 COH901318_CX_CTRL_PRDD_SOURCE,
1168 },
1169 {
1170 .number = U300_DMA_PCM_I2S1_RX,
1171 .name = "PCM I2S1 RX",
1172 .priority_high = 1,
1173 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1174 .param.config = COH901318_CX_CFG_CH_DISABLE |
1175 COH901318_CX_CFG_LCR_DISABLE |
1176 COH901318_CX_CFG_TC_IRQ_ENABLE |
1177 COH901318_CX_CFG_BE_IRQ_ENABLE,
1178 .param.ctrl_lli_chained = 0 |
1179 COH901318_CX_CTRL_TC_ENABLE |
1180 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1181 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1182 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1183 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1184 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1185 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1186 COH901318_CX_CTRL_TCP_DISABLE |
1187 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1188 COH901318_CX_CTRL_HSP_ENABLE |
1189 COH901318_CX_CTRL_HSS_DISABLE |
1190 COH901318_CX_CTRL_DDMA_LEGACY |
1191 COH901318_CX_CTRL_PRDD_DEST,
1192 .param.ctrl_lli = 0 |
1193 COH901318_CX_CTRL_TC_ENABLE |
1194 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1195 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1196 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1197 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1198 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1199 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1200 COH901318_CX_CTRL_TCP_ENABLE |
1201 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1202 COH901318_CX_CTRL_HSP_ENABLE |
1203 COH901318_CX_CTRL_HSS_DISABLE |
1204 COH901318_CX_CTRL_DDMA_LEGACY |
1205 COH901318_CX_CTRL_PRDD_DEST,
1206 .param.ctrl_lli_last = 0 |
1207 COH901318_CX_CTRL_TC_ENABLE |
1208 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1209 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1210 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1211 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1212 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1213 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1214 COH901318_CX_CTRL_TCP_ENABLE |
1215 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1216 COH901318_CX_CTRL_HSP_ENABLE |
1217 COH901318_CX_CTRL_HSS_DISABLE |
1218 COH901318_CX_CTRL_DDMA_LEGACY |
1219 COH901318_CX_CTRL_PRDD_DEST,
1220 },
1221 {
1222 .number = U300_DMA_XGAM_CDI,
1223 .name = "XGAM CDI",
1224 .priority_high = 0,
1225 },
1226 {
1227 .number = U300_DMA_XGAM_PDI,
1228 .name = "XGAM PDI",
1229 .priority_high = 0,
1230 },
1231 /*
1232 * Don't set up device address, burst count or size of src
1233 * or dst bus for this peripheral - handled by PrimeCell
1234 * DMA extension.
1235 */
1236 {
1237 .number = U300_DMA_SPI_TX,
1238 .name = "SPI TX",
1239 .priority_high = 0,
1240 .param.config = COH901318_CX_CFG_CH_DISABLE |
1241 COH901318_CX_CFG_LCR_DISABLE |
1242 COH901318_CX_CFG_TC_IRQ_ENABLE |
1243 COH901318_CX_CFG_BE_IRQ_ENABLE,
1244 .param.ctrl_lli_chained = 0 |
1245 COH901318_CX_CTRL_TC_ENABLE |
1246 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1247 COH901318_CX_CTRL_TCP_DISABLE |
1248 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1249 COH901318_CX_CTRL_HSP_ENABLE |
1250 COH901318_CX_CTRL_HSS_DISABLE |
1251 COH901318_CX_CTRL_DDMA_LEGACY,
1252 .param.ctrl_lli = 0 |
1253 COH901318_CX_CTRL_TC_ENABLE |
1254 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1255 COH901318_CX_CTRL_TCP_DISABLE |
1256 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1257 COH901318_CX_CTRL_HSP_ENABLE |
1258 COH901318_CX_CTRL_HSS_DISABLE |
1259 COH901318_CX_CTRL_DDMA_LEGACY,
1260 .param.ctrl_lli_last = 0 |
1261 COH901318_CX_CTRL_TC_ENABLE |
1262 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1263 COH901318_CX_CTRL_TCP_DISABLE |
1264 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1265 COH901318_CX_CTRL_HSP_ENABLE |
1266 COH901318_CX_CTRL_HSS_DISABLE |
1267 COH901318_CX_CTRL_DDMA_LEGACY,
1268 },
1269 {
1270 .number = U300_DMA_SPI_RX,
1271 .name = "SPI RX",
1272 .priority_high = 0,
1273 .param.config = COH901318_CX_CFG_CH_DISABLE |
1274 COH901318_CX_CFG_LCR_DISABLE |
1275 COH901318_CX_CFG_TC_IRQ_ENABLE |
1276 COH901318_CX_CFG_BE_IRQ_ENABLE,
1277 .param.ctrl_lli_chained = 0 |
1278 COH901318_CX_CTRL_TC_ENABLE |
1279 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1280 COH901318_CX_CTRL_TCP_DISABLE |
1281 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1282 COH901318_CX_CTRL_HSP_ENABLE |
1283 COH901318_CX_CTRL_HSS_DISABLE |
1284 COH901318_CX_CTRL_DDMA_LEGACY,
1285 .param.ctrl_lli = 0 |
1286 COH901318_CX_CTRL_TC_ENABLE |
1287 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1288 COH901318_CX_CTRL_TCP_DISABLE |
1289 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1290 COH901318_CX_CTRL_HSP_ENABLE |
1291 COH901318_CX_CTRL_HSS_DISABLE |
1292 COH901318_CX_CTRL_DDMA_LEGACY,
1293 .param.ctrl_lli_last = 0 |
1294 COH901318_CX_CTRL_TC_ENABLE |
1295 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1296 COH901318_CX_CTRL_TCP_DISABLE |
1297 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1298 COH901318_CX_CTRL_HSP_ENABLE |
1299 COH901318_CX_CTRL_HSS_DISABLE |
1300 COH901318_CX_CTRL_DDMA_LEGACY,
1301
1302 },
1303 {
1304 .number = U300_DMA_GENERAL_PURPOSE_0,
1305 .name = "GENERAL 00",
1306 .priority_high = 0,
1307
1308 .param.config = flags_memcpy_config,
1309 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1310 .param.ctrl_lli = flags_memcpy_lli,
1311 .param.ctrl_lli_last = flags_memcpy_lli_last,
1312 },
1313 {
1314 .number = U300_DMA_GENERAL_PURPOSE_1,
1315 .name = "GENERAL 01",
1316 .priority_high = 0,
1317
1318 .param.config = flags_memcpy_config,
1319 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1320 .param.ctrl_lli = flags_memcpy_lli,
1321 .param.ctrl_lli_last = flags_memcpy_lli_last,
1322 },
1323 {
1324 .number = U300_DMA_GENERAL_PURPOSE_2,
1325 .name = "GENERAL 02",
1326 .priority_high = 0,
1327
1328 .param.config = flags_memcpy_config,
1329 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1330 .param.ctrl_lli = flags_memcpy_lli,
1331 .param.ctrl_lli_last = flags_memcpy_lli_last,
1332 },
1333 {
1334 .number = U300_DMA_GENERAL_PURPOSE_3,
1335 .name = "GENERAL 03",
1336 .priority_high = 0,
1337
1338 .param.config = flags_memcpy_config,
1339 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1340 .param.ctrl_lli = flags_memcpy_lli,
1341 .param.ctrl_lli_last = flags_memcpy_lli_last,
1342 },
1343 {
1344 .number = U300_DMA_GENERAL_PURPOSE_4,
1345 .name = "GENERAL 04",
1346 .priority_high = 0,
1347
1348 .param.config = flags_memcpy_config,
1349 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1350 .param.ctrl_lli = flags_memcpy_lli,
1351 .param.ctrl_lli_last = flags_memcpy_lli_last,
1352 },
1353 {
1354 .number = U300_DMA_GENERAL_PURPOSE_5,
1355 .name = "GENERAL 05",
1356 .priority_high = 0,
1357
1358 .param.config = flags_memcpy_config,
1359 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1360 .param.ctrl_lli = flags_memcpy_lli,
1361 .param.ctrl_lli_last = flags_memcpy_lli_last,
1362 },
1363 {
1364 .number = U300_DMA_GENERAL_PURPOSE_6,
1365 .name = "GENERAL 06",
1366 .priority_high = 0,
1367
1368 .param.config = flags_memcpy_config,
1369 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1370 .param.ctrl_lli = flags_memcpy_lli,
1371 .param.ctrl_lli_last = flags_memcpy_lli_last,
1372 },
1373 {
1374 .number = U300_DMA_GENERAL_PURPOSE_7,
1375 .name = "GENERAL 07",
1376 .priority_high = 0,
1377
1378 .param.config = flags_memcpy_config,
1379 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1380 .param.ctrl_lli = flags_memcpy_lli,
1381 .param.ctrl_lli_last = flags_memcpy_lli_last,
1382 },
1383 {
1384 .number = U300_DMA_GENERAL_PURPOSE_8,
1385 .name = "GENERAL 08",
1386 .priority_high = 0,
1387
1388 .param.config = flags_memcpy_config,
1389 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1390 .param.ctrl_lli = flags_memcpy_lli,
1391 .param.ctrl_lli_last = flags_memcpy_lli_last,
1392 },
1393 {
1394 .number = U300_DMA_UART1_TX,
1395 .name = "UART1 TX",
1396 .priority_high = 0,
1397 },
1398 {
1399 .number = U300_DMA_UART1_RX,
1400 .name = "UART1 RX",
1401 .priority_high = 0,
1402 }
1403};
1404
1405
1406static struct coh901318_platform coh901318_platform = {
1407 .chans_slave = dma_slave_channels,
1408 .chans_memcpy = dma_memcpy_channels,
1409 .access_memory_state = coh901318_access_memory_state,
1410 .chan_conf = chan_config,
1411 .max_channels = U300_DMA_CHANNELS,
1412};
1413 329
1414static struct resource pinctrl_resources[] = { 330static struct resource pinctrl_resources[] = {
1415 { 331 {
@@ -1521,7 +437,6 @@ static struct platform_device dma_device = {
1521 .resource = dma_resource, 437 .resource = dma_resource,
1522 .num_resources = ARRAY_SIZE(dma_resource), 438 .num_resources = ARRAY_SIZE(dma_resource),
1523 .dev = { 439 .dev = {
1524 .platform_data = &coh901318_platform,
1525 .coherent_dma_mask = ~0, 440 .coherent_dma_mask = ~0,
1526 }, 441 },
1527}; 442};
diff --git a/arch/arm/mach-u300/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
deleted file mode 100644
index 4e8a88fbca49..000000000000
--- a/arch/arm/mach-u300/dma_channels.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/dma_channels.h
4 *
5 *
6 * Copyright (C) 2007-2012 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * Map file for the U300 dma driver.
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef DMA_CHANNELS_H
13#define DMA_CHANNELS_H
14
15#define U300_DMA_MSL_TX_0 0
16#define U300_DMA_MSL_TX_1 1
17#define U300_DMA_MSL_TX_2 2
18#define U300_DMA_MSL_TX_3 3
19#define U300_DMA_MSL_TX_4 4
20#define U300_DMA_MSL_TX_5 5
21#define U300_DMA_MSL_TX_6 6
22#define U300_DMA_MSL_RX_0 7
23#define U300_DMA_MSL_RX_1 8
24#define U300_DMA_MSL_RX_2 9
25#define U300_DMA_MSL_RX_3 10
26#define U300_DMA_MSL_RX_4 11
27#define U300_DMA_MSL_RX_5 12
28#define U300_DMA_MSL_RX_6 13
29#define U300_DMA_MMCSD_RX_TX 14
30#define U300_DMA_MSPRO_TX 15
31#define U300_DMA_MSPRO_RX 16
32#define U300_DMA_UART0_TX 17
33#define U300_DMA_UART0_RX 18
34#define U300_DMA_APEX_TX 19
35#define U300_DMA_APEX_RX 20
36#define U300_DMA_PCM_I2S0_TX 21
37#define U300_DMA_PCM_I2S0_RX 22
38#define U300_DMA_PCM_I2S1_TX 23
39#define U300_DMA_PCM_I2S1_RX 24
40#define U300_DMA_XGAM_CDI 25
41#define U300_DMA_XGAM_PDI 26
42#define U300_DMA_SPI_TX 27
43#define U300_DMA_SPI_RX 28
44#define U300_DMA_GENERAL_PURPOSE_0 29
45#define U300_DMA_GENERAL_PURPOSE_1 30
46#define U300_DMA_GENERAL_PURPOSE_2 31
47#define U300_DMA_GENERAL_PURPOSE_3 32
48#define U300_DMA_GENERAL_PURPOSE_4 33
49#define U300_DMA_GENERAL_PURPOSE_5 34
50#define U300_DMA_GENERAL_PURPOSE_6 35
51#define U300_DMA_GENERAL_PURPOSE_7 36
52#define U300_DMA_GENERAL_PURPOSE_8 37
53#define U300_DMA_UART1_TX 38
54#define U300_DMA_UART1_RX 39
55
56#define U300_DMA_DEVICE_CHANNELS 32
57#define U300_DMA_CHANNELS 40
58
59
60#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/coh901318.h b/arch/arm/mach-u300/include/mach/coh901318.h
deleted file mode 100644
index 7c3b2b2d25b6..000000000000
--- a/arch/arm/mach-u300/include/mach/coh901318.h
+++ /dev/null
@@ -1,267 +0,0 @@
1/*
2 *
3 * include/linux/coh901318.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson
7 * License terms: GNU General Public License (GPL) version 2
8 * DMA driver for COH 901 318
9 * Author: Per Friden <per.friden@stericsson.com>
10 */
11
12#ifndef COH901318_H
13#define COH901318_H
14
15#include <linux/device.h>
16#include <linux/dmaengine.h>
17
18#define MAX_DMA_PACKET_SIZE_SHIFT 11
19#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
20
21/**
22 * struct coh901318_lli - linked list item for DMAC
23 * @control: control settings for DMAC
24 * @src_addr: transfer source address
25 * @dst_addr: transfer destination address
26 * @link_addr: physical address to next lli
27 * @virt_link_addr: virtual address of next lli (only used by pool_free)
28 * @phy_this: physical address of current lli (only used by pool_free)
29 */
30struct coh901318_lli {
31 u32 control;
32 dma_addr_t src_addr;
33 dma_addr_t dst_addr;
34 dma_addr_t link_addr;
35
36 void *virt_link_addr;
37 dma_addr_t phy_this;
38};
39/**
40 * struct coh901318_params - parameters for DMAC configuration
41 * @config: DMA config register
42 * @ctrl_lli_last: DMA control register for the last lli in the list
43 * @ctrl_lli: DMA control register for an lli
44 * @ctrl_lli_chained: DMA control register for a chained lli
45 */
46struct coh901318_params {
47 u32 config;
48 u32 ctrl_lli_last;
49 u32 ctrl_lli;
50 u32 ctrl_lli_chained;
51};
52/**
53 * struct coh_dma_channel - dma channel base
54 * @name: ascii name of dma channel
55 * @number: channel id number
56 * @desc_nbr_max: number of preallocated descriptors
57 * @priority_high: prio of channel, 0 low otherwise high.
58 * @param: configuration parameters
59 * @dev_addr: physical address of periphal connected to channel
60 */
61struct coh_dma_channel {
62 const char name[32];
63 const int number;
64 const int desc_nbr_max;
65 const int priority_high;
66 const struct coh901318_params param;
67 const dma_addr_t dev_addr;
68};
69
70/**
71 * dma_access_memory_state_t - register dma for memory access
72 *
73 * @dev: The dma device
74 * @active: 1 means dma intends to access memory
75 * 0 means dma wont access memory
76 */
77typedef void (*dma_access_memory_state_t)(struct device *dev,
78 bool active);
79
80/**
81 * struct powersave - DMA power save structure
82 * @lock: lock protecting data in this struct
83 * @started_channels: bit mask indicating active dma channels
84 */
85struct powersave {
86 spinlock_t lock;
87 u64 started_channels;
88};
89/**
90 * struct coh901318_platform - platform arch structure
91 * @chans_slave: specifying dma slave channels
92 * @chans_memcpy: specifying dma memcpy channels
93 * @access_memory_state: requesting DMA memory access (on / off)
94 * @chan_conf: dma channel configurations
95 * @max_channels: max number of dma chanenls
96 */
97struct coh901318_platform {
98 const int *chans_slave;
99 const int *chans_memcpy;
100 const dma_access_memory_state_t access_memory_state;
101 const struct coh_dma_channel *chan_conf;
102 const int max_channels;
103};
104
105#ifdef CONFIG_COH901318
106/**
107 * coh901318_filter_id() - DMA channel filter function
108 * @chan: dma channel handle
109 * @chan_id: id of dma channel to be filter out
110 *
111 * In dma_request_channel() it specifies what channel id to be requested
112 */
113bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
114#else
115static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
116{
117 return false;
118}
119#endif
120
121/*
122 * DMA Controller - this access the static mappings of the coh901318 dma.
123 *
124 */
125
126#define COH901318_MOD32_MASK (0x1F)
127#define COH901318_WORD_MASK (0xFFFFFFFF)
128/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
129#define COH901318_INT_STATUS1 (0x0000)
130#define COH901318_INT_STATUS2 (0x0004)
131/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
132#define COH901318_TC_INT_STATUS1 (0x0008)
133#define COH901318_TC_INT_STATUS2 (0x000C)
134/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
135#define COH901318_TC_INT_CLEAR1 (0x0010)
136#define COH901318_TC_INT_CLEAR2 (0x0014)
137/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
138#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
139#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
140/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
141#define COH901318_BE_INT_STATUS1 (0x0020)
142#define COH901318_BE_INT_STATUS2 (0x0024)
143/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
144#define COH901318_BE_INT_CLEAR1 (0x0028)
145#define COH901318_BE_INT_CLEAR2 (0x002C)
146/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
147#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
148#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
149
150/*
151 * CX_CFG - Channel Configuration Registers 32bit (R/W)
152 */
153#define COH901318_CX_CFG (0x0100)
154#define COH901318_CX_CFG_SPACING (0x04)
155/* Channel enable activates tha dma job */
156#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
157#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
158/* Request Mode */
159#define COH901318_CX_CFG_RM_MASK (0x00000006)
160#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
161#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
162#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
163#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
164#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
165/* Linked channel request field. RM must == 11 */
166#define COH901318_CX_CFG_LCRF_SHIFT 3
167#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
168#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
169/* Terminal Counter Interrupt Request Mask */
170#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
171#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
172/* Bus Error interrupt Mask */
173#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
174#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
175
176/*
177 * CX_STAT - Channel Status Registers 32bit (R/-)
178 */
179#define COH901318_CX_STAT (0x0200)
180#define COH901318_CX_STAT_SPACING (0x04)
181#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
182#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
183#define COH901318_CX_STAT_ACTIVE (0x00000002)
184#define COH901318_CX_STAT_ENABLED (0x00000001)
185
186/*
187 * CX_CTRL - Channel Control Registers 32bit (R/W)
188 */
189#define COH901318_CX_CTRL (0x0400)
190#define COH901318_CX_CTRL_SPACING (0x10)
191/* Transfer Count Enable */
192#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
193#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
194/* Transfer Count Value 0 - 4095 */
195#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
196/* Burst count */
197#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
198#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
199#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
200#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
201#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
202#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
203#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
204#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
205#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
206/* Source bus size */
207#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
208#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
209#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
210#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
211/* Source address increment */
212#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
213#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
214/* Destination Bus Size */
215#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
216#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
217#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
218#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
219/* Destination address increment */
220#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
221#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
222/* Master Mode (Master2 is only connected to MSL) */
223#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
224#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
225#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
226#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
227#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
228/* Terminal Count flag to PER enable */
229#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
230#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
231/* Terminal Count flags to CPU enable */
232#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
233#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
234/* Hand shake to peripheral */
235#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
236#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
237#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
238#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
239/* DMA mode */
240#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
241#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
242#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
243#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
244/* Primary Request Data Destination */
245#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
246#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
247#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
248
249/*
250 * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
251 */
252#define COH901318_CX_SRC_ADDR (0x0404)
253#define COH901318_CX_SRC_ADDR_SPACING (0x10)
254
255/*
256 * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
257 */
258#define COH901318_CX_DST_ADDR (0x0408)
259#define COH901318_CX_DST_ADDR_SPACING (0x10)
260
261/*
262 * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
263 */
264#define COH901318_CX_LNK_ADDR (0x040C)
265#define COH901318_CX_LNK_ADDR_SPACING (0x10)
266#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
267#endif /* COH901318_H */
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 02e6659286d5..910698293d64 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -10,9 +10,8 @@
10#include <linux/amba/bus.h> 10#include <linux/amba/bus.h>
11#include <linux/spi/spi.h> 11#include <linux/spi/spi.h>
12#include <linux/amba/pl022.h> 12#include <linux/amba/pl022.h>
13#include <linux/platform_data/dma-coh901318.h>
13#include <linux/err.h> 14#include <linux/err.h>
14#include <mach/coh901318.h>
15#include "dma_channels.h"
16 15
17/* 16/*
18 * The following is for the actual devices on the SSP/SPI bus 17 * The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 4f990115b1bd..7d4616d5df11 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -11,8 +11,8 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/amba/sp810.h>
14#include <asm/system_misc.h> 15#include <asm/system_misc.h>
15#include <asm/hardware/sp810.h>
16#include <mach/spear.h> 16#include <mach/spear.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18 18
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 17:02:45 -0500