1 files changed, 8 insertions, 7 deletions

diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index db969a5c4998..afc1e8c32d6c 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime(
         return 0;
 }
 
-static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
         /* support only OMAP3 class */
-        if (!cpu_is_omap34xx()) {
+        if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
                 pr_err("BCH ecc is not supported on this CPU\n");
                 return 0;
         }
 
         /*
-         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
-         * Other chips may be added if confirmed to work.
+         * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
+         * and AM33xx derivates. Other chips may be added if confirmed to work.
          */
         if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
-            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+            (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
+            (!soc_is_am33xx())) {
                 pr_err("BCH 4-bit mode is not supported on this CPU\n");
                 return 0;
         }
@@ -110,8 +111,8 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
         return 1;
 }
 
-int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
-                          struct gpmc_timings *gpmc_t)
+int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
+                   struct gpmc_timings *gpmc_t)
 {
         int err = 0;
         struct device *dev = &gpmc_nand_device.dev;