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authorPrashant Gaikwad <pgaikwad@nvidia.com>2013-01-11 02:46:27 -0500
committerStephen Warren <swarren@nvidia.com>2013-01-28 13:19:33 -0500
commit52dec4c9eacc339dbf1b2ab549248df1cc6eb030 (patch)
tree57d38133caf4e6f88f788eebde4452ed0fee727d /arch
parent61fd290d213e25d5a119b8ca25644001ed9f8f2d (diff)
ARM: tegra: remove legacy clock code
Remove all legacy clock code from mach-tegra. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-tegra/Makefile5
-rw-r--r--arch/arm/mach-tegra/clock.c147
-rw-r--r--arch/arm/mach-tegra/clock.h153
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h41
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.c1623
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks.h42
-rw-r--r--arch/arm/mach-tegra/tegra20_clocks_data.c1143
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c2506
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.h54
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks_data.c1425
10 files changed, 0 insertions, 7139 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f0520961bafe..6018a05e808c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,6 @@
1obj-y += common.o 1obj-y += common.o
2obj-y += io.o 2obj-y += io.o
3obj-y += irq.o 3obj-y += irq.o
4obj-y += clock.o
5obj-y += fuse.o 4obj-y += fuse.o
6obj-y += pmc.o 5obj-y += pmc.o
7obj-y += flowctrl.o 6obj-y += flowctrl.o
@@ -12,16 +11,12 @@ obj-y += reset.o
12obj-y += reset-handler.o 11obj-y += reset-handler.o
13obj-y += sleep.o 12obj-y += sleep.o
14obj-$(CONFIG_CPU_IDLE) += cpuidle.o 13obj-$(CONFIG_CPU_IDLE) += cpuidle.o
15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o 14obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 15obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
19obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o 16obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
20ifeq ($(CONFIG_CPU_IDLE),y) 17ifeq ($(CONFIG_CPU_IDLE),y)
21obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o 18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
22endif 19endif
23obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
24obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
25obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o 20obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
26obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o 21obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
27ifeq ($(CONFIG_CPU_IDLE),y) 22ifeq ($(CONFIG_CPU_IDLE),y)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
deleted file mode 100644
index baa0c5b008f1..000000000000
--- a/arch/arm/mach-tegra/clock.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/clk.h>
22#include <linux/clkdev.h>
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/module.h>
26#include <linux/sched.h>
27#include <linux/seq_file.h>
28#include <linux/slab.h>
29#include <linux/clk/tegra.h>
30
31#include "board.h"
32#include "clock.h"
33
34/*
35 * Locking:
36 *
37 * An additional mutex, clock_list_lock, is used to protect the list of all
38 * clocks.
39 *
40 */
41static DEFINE_MUTEX(clock_list_lock);
42static LIST_HEAD(clocks);
43
44void tegra_clk_add(struct clk *clk)
45{
46 struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
47
48 mutex_lock(&clock_list_lock);
49 list_add(&c->node, &clocks);
50 mutex_unlock(&clock_list_lock);
51}
52
53struct clk *tegra_get_clock_by_name(const char *name)
54{
55 struct clk_tegra *c;
56 struct clk *ret = NULL;
57 mutex_lock(&clock_list_lock);
58 list_for_each_entry(c, &clocks, node) {
59 if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
60 ret = c->hw.clk;
61 break;
62 }
63 }
64 mutex_unlock(&clock_list_lock);
65 return ret;
66}
67
68static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
69{
70 struct clk *c;
71 struct clk *p;
72 struct clk *parent;
73
74 int ret = 0;
75
76 c = tegra_get_clock_by_name(table->name);
77
78 if (!c) {
79 pr_warn("Unable to initialize clock %s\n",
80 table->name);
81 return -ENODEV;
82 }
83
84 parent = clk_get_parent(c);
85
86 if (table->parent) {
87 p = tegra_get_clock_by_name(table->parent);
88 if (!p) {
89 pr_warn("Unable to find parent %s of clock %s\n",
90 table->parent, table->name);
91 return -ENODEV;
92 }
93
94 if (parent != p) {
95 ret = clk_set_parent(c, p);
96 if (ret) {
97 pr_warn("Unable to set parent %s of clock %s: %d\n",
98 table->parent, table->name, ret);
99 return -EINVAL;
100 }
101 }
102 }
103
104 if (table->rate && table->rate != clk_get_rate(c)) {
105 ret = clk_set_rate(c, table->rate);
106 if (ret) {
107 pr_warn("Unable to set clock %s to rate %lu: %d\n",
108 table->name, table->rate, ret);
109 return -EINVAL;
110 }
111 }
112
113 if (table->enabled) {
114 ret = clk_prepare_enable(c);
115 if (ret) {
116 pr_warn("Unable to enable clock %s: %d\n",
117 table->name, ret);
118 return -EINVAL;
119 }
120 }
121
122 return 0;
123}
124
125void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
126{
127 for (; table->name; table++)
128 tegra_clk_init_one_from_table(table);
129}
130
131/* Several extended clock configuration bits (e.g., clock routing, clock
132 * phase control) are included in PLL and peripheral clock source
133 * registers. */
134int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
135{
136 int ret = 0;
137 struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
138
139 if (!clk->clk_cfg_ex) {
140 ret = -ENOSYS;
141 goto out;
142 }
143 ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
144
145out:
146 return ret;
147}
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
deleted file mode 100644
index 2aa37f5c44c0..000000000000
--- a/arch/arm/mach-tegra/clock.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/clock.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_CLOCK_H
22#define __MACH_TEGRA_CLOCK_H
23
24#include <linux/clk-provider.h>
25#include <linux/clkdev.h>
26#include <linux/list.h>
27
28#include <mach/clk.h>
29
30#define DIV_BUS (1 << 0)
31#define DIV_U71 (1 << 1)
32#define DIV_U71_FIXED (1 << 2)
33#define DIV_2 (1 << 3)
34#define DIV_U16 (1 << 4)
35#define PLL_FIXED (1 << 5)
36#define PLL_HAS_CPCON (1 << 6)
37#define MUX (1 << 7)
38#define PLLD (1 << 8)
39#define PERIPH_NO_RESET (1 << 9)
40#define PERIPH_NO_ENB (1 << 10)
41#define PERIPH_EMC_ENB (1 << 11)
42#define PERIPH_MANUAL_RESET (1 << 12)
43#define PLL_ALT_MISC_REG (1 << 13)
44#define PLLU (1 << 14)
45#define PLLX (1 << 15)
46#define MUX_PWM (1 << 16)
47#define MUX8 (1 << 17)
48#define DIV_U71_UART (1 << 18)
49#define MUX_CLK_OUT (1 << 19)
50#define PLLM (1 << 20)
51#define DIV_U71_INT (1 << 21)
52#define DIV_U71_IDLE (1 << 22)
53#define ENABLE_ON_INIT (1 << 28)
54#define PERIPH_ON_APB (1 << 29)
55
56struct clk_tegra;
57#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
58
59struct clk_mux_sel {
60 struct clk *input;
61 u32 value;
62};
63
64struct clk_pll_freq_table {
65 unsigned long input_rate;
66 unsigned long output_rate;
67 u16 n;
68 u16 m;
69 u8 p;
70 u8 cpcon;
71};
72
73enum clk_state {
74 UNINITIALIZED = 0,
75 ON,
76 OFF,
77};
78
79struct clk_tegra {
80 /* node for master clocks list */
81 struct list_head node; /* node for list of all clocks */
82 struct clk_lookup lookup;
83 struct clk_hw hw;
84
85 bool set;
86 unsigned long fixed_rate;
87 unsigned long max_rate;
88 unsigned long min_rate;
89 u32 flags;
90 const char *name;
91
92 enum clk_state state;
93 u32 div;
94 u32 mul;
95
96 u32 reg;
97 u32 reg_shift;
98
99 struct list_head shared_bus_list;
100
101 union {
102 struct {
103 unsigned int clk_num;
104 } periph;
105 struct {
106 unsigned long input_min;
107 unsigned long input_max;
108 unsigned long cf_min;
109 unsigned long cf_max;
110 unsigned long vco_min;
111 unsigned long vco_max;
112 const struct clk_pll_freq_table *freq_table;
113 int lock_delay;
114 unsigned long fixed_rate;
115 } pll;
116 struct {
117 u32 sel;
118 u32 reg_mask;
119 } mux;
120 struct {
121 struct clk *main;
122 struct clk *backup;
123 } cpu;
124 struct {
125 struct list_head node;
126 bool enabled;
127 unsigned long rate;
128 } shared_bus_user;
129 } u;
130
131 void (*reset)(struct clk_hw *, bool);
132 int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
133};
134
135struct clk_duplicate {
136 const char *name;
137 struct clk_lookup lookup;
138};
139
140struct tegra_clk_init_table {
141 const char *name;
142 const char *parent;
143 unsigned long rate;
144 bool enabled;
145};
146
147void tegra_clk_add(struct clk *c);
148void tegra2_init_clocks(void);
149void tegra30_init_clocks(void);
150struct clk *tegra_get_clock_by_name(const char *name);
151void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
152
153#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
deleted file mode 100644
index 85bbf10a7d0d..000000000000
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/clk.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#ifndef __MACH_CLK_H
21#define __MACH_CLK_H
22
23struct clk;
24
25enum tegra_clk_ex_param {
26 TEGRA_CLK_VI_INP_SEL,
27 TEGRA_CLK_DTV_INVERT,
28 TEGRA_CLK_NAND_PAD_DIV2_ENB,
29 TEGRA_CLK_PLLD_CSI_OUT_ENB,
30 TEGRA_CLK_PLLD_DSI_OUT_ENB,
31 TEGRA_CLK_PLLD_MIPI_MUX_SEL,
32};
33
34#ifndef CONFIG_COMMON_CLK
35unsigned long clk_get_rate_all_locked(struct clk *c);
36#endif
37
38void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
39int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
40
41#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
deleted file mode 100644
index 1a80ff65e5fc..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.c
+++ /dev/null
@@ -1,1623 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra20_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clkdev.h>
28#include <linux/clk.h>
29#include <linux/clk/tegra.h>
30
31#include "clock.h"
32#include "fuse.h"
33#include "iomap.h"
34#include "tegra2_emc.h"
35
36#define RST_DEVICES 0x004
37#define RST_DEVICES_SET 0x300
38#define RST_DEVICES_CLR 0x304
39#define RST_DEVICES_NUM 3
40
41#define CLK_OUT_ENB 0x010
42#define CLK_OUT_ENB_SET 0x320
43#define CLK_OUT_ENB_CLR 0x324
44#define CLK_OUT_ENB_NUM 3
45
46#define CLK_MASK_ARM 0x44
47#define MISC_CLK_ENB 0x48
48
49#define OSC_CTRL 0x50
50#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
51#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
52#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
53#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
54#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
55#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
56
57#define OSC_FREQ_DET 0x58
58#define OSC_FREQ_DET_TRIG (1<<31)
59
60#define OSC_FREQ_DET_STATUS 0x5C
61#define OSC_FREQ_DET_BUSY (1<<31)
62#define OSC_FREQ_DET_CNT_MASK 0xFFFF
63
64#define PERIPH_CLK_SOURCE_I2S1 0x100
65#define PERIPH_CLK_SOURCE_EMC 0x19c
66#define PERIPH_CLK_SOURCE_OSC 0x1fc
67#define PERIPH_CLK_SOURCE_NUM \
68 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
69
70#define PERIPH_CLK_SOURCE_MASK (3<<30)
71#define PERIPH_CLK_SOURCE_SHIFT 30
72#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
73#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
74#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
75#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
76#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
77#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
78
79#define SDMMC_CLK_INT_FB_SEL (1 << 23)
80#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
81#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
82
83#define PLL_BASE 0x0
84#define PLL_BASE_BYPASS (1<<31)
85#define PLL_BASE_ENABLE (1<<30)
86#define PLL_BASE_REF_ENABLE (1<<29)
87#define PLL_BASE_OVERRIDE (1<<28)
88#define PLL_BASE_DIVP_MASK (0x7<<20)
89#define PLL_BASE_DIVP_SHIFT 20
90#define PLL_BASE_DIVN_MASK (0x3FF<<8)
91#define PLL_BASE_DIVN_SHIFT 8
92#define PLL_BASE_DIVM_MASK (0x1F)
93#define PLL_BASE_DIVM_SHIFT 0
94
95#define PLL_OUT_RATIO_MASK (0xFF<<8)
96#define PLL_OUT_RATIO_SHIFT 8
97#define PLL_OUT_OVERRIDE (1<<2)
98#define PLL_OUT_CLKEN (1<<1)
99#define PLL_OUT_RESET_DISABLE (1<<0)
100
101#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
102
103#define PLL_MISC_DCCON_SHIFT 20
104#define PLL_MISC_CPCON_SHIFT 8
105#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
106#define PLL_MISC_LFCON_SHIFT 4
107#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
108#define PLL_MISC_VCOCON_SHIFT 0
109#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
110
111#define PLLU_BASE_POST_DIV (1<<20)
112
113#define PLLD_MISC_CLKENABLE (1<<30)
114#define PLLD_MISC_DIV_RST (1<<23)
115#define PLLD_MISC_DCCON_SHIFT 12
116
117#define PLLE_MISC_READY (1 << 15)
118
119#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
120#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
121#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
122
123#define SUPER_CLK_MUX 0x00
124#define SUPER_STATE_SHIFT 28
125#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
126#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
127#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
128#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
129#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
130#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
131#define SUPER_SOURCE_MASK 0xF
132#define SUPER_FIQ_SOURCE_SHIFT 12
133#define SUPER_IRQ_SOURCE_SHIFT 8
134#define SUPER_RUN_SOURCE_SHIFT 4
135#define SUPER_IDLE_SOURCE_SHIFT 0
136
137#define SUPER_CLK_DIVIDER 0x04
138
139#define BUS_CLK_DISABLE (1<<3)
140#define BUS_CLK_DIV_MASK 0x3
141
142#define PMC_CTRL 0x0
143 #define PMC_CTRL_BLINK_ENB (1 << 7)
144
145#define PMC_DPD_PADS_ORIDE 0x1c
146 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
147
148#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
149#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
150#define PMC_BLINK_TIMER_ENB (1 << 15)
151#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
152#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
153
154/* Tegra CPU clock and reset control regs */
155#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
156#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
157#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
158
159#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
160#define CPU_RESET(cpu) (0x1111ul << (cpu))
161
162static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
163static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
164
165/*
166 * Some clocks share a register with other clocks. Any clock op that
167 * non-atomically modifies a register used by another clock must lock
168 * clock_register_lock first.
169 */
170static DEFINE_SPINLOCK(clock_register_lock);
171
172/*
173 * Some peripheral clocks share an enable bit, so refcount the enable bits
174 * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
175 */
176static int tegra_periph_clk_enable_refcount[3 * 32];
177
178#define clk_writel(value, reg) \
179 __raw_writel(value, reg_clk_base + (reg))
180#define clk_readl(reg) \
181 __raw_readl(reg_clk_base + (reg))
182#define pmc_writel(value, reg) \
183 __raw_writel(value, reg_pmc_base + (reg))
184#define pmc_readl(reg) \
185 __raw_readl(reg_pmc_base + (reg))
186
187static unsigned long clk_measure_input_freq(void)
188{
189 u32 clock_autodetect;
190 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
191 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
192 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
193 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
194 return 12000000;
195 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
196 return 13000000;
197 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
198 return 19200000;
199 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
200 return 26000000;
201 } else {
202 pr_err("%s: Unexpected clock autodetect value %d",
203 __func__, clock_autodetect);
204 BUG();
205 return 0;
206 }
207}
208
209static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
210{
211 s64 divider_u71 = parent_rate * 2;
212 divider_u71 += rate - 1;
213 do_div(divider_u71, rate);
214
215 if (divider_u71 - 2 < 0)
216 return 0;
217
218 if (divider_u71 - 2 > 255)
219 return -EINVAL;
220
221 return divider_u71 - 2;
222}
223
224static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
225{
226 s64 divider_u16;
227
228 divider_u16 = parent_rate;
229 divider_u16 += rate - 1;
230 do_div(divider_u16, rate);
231
232 if (divider_u16 - 1 < 0)
233 return 0;
234
235 if (divider_u16 - 1 > 0xFFFF)
236 return -EINVAL;
237
238 return divider_u16 - 1;
239}
240
241static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
242 unsigned long parent_rate)
243{
244 return to_clk_tegra(hw)->fixed_rate;
245}
246
247struct clk_ops tegra_clk_32k_ops = {
248 .recalc_rate = tegra_clk_fixed_recalc_rate,
249};
250
251/* clk_m functions */
252static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
253 unsigned long prate)
254{
255 if (!to_clk_tegra(hw)->fixed_rate)
256 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
257 return to_clk_tegra(hw)->fixed_rate;
258}
259
260static void tegra20_clk_m_init(struct clk_hw *hw)
261{
262 struct clk_tegra *c = to_clk_tegra(hw);
263 u32 osc_ctrl = clk_readl(OSC_CTRL);
264 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
265
266 switch (c->fixed_rate) {
267 case 12000000:
268 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
269 break;
270 case 13000000:
271 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
272 break;
273 case 19200000:
274 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
275 break;
276 case 26000000:
277 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
278 break;
279 default:
280 BUG();
281 }
282 clk_writel(auto_clock_control, OSC_CTRL);
283}
284
285struct clk_ops tegra_clk_m_ops = {
286 .init = tegra20_clk_m_init,
287 .recalc_rate = tegra20_clk_m_recalc_rate,
288};
289
290/* super clock functions */
291/* "super clocks" on tegra have two-stage muxes and a clock skipping
292 * super divider. We will ignore the clock skipping divider, since we
293 * can't lower the voltage when using the clock skip, but we can if we
294 * lower the PLL frequency.
295 */
296static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
297{
298 struct clk_tegra *c = to_clk_tegra(hw);
299 u32 val;
300
301 val = clk_readl(c->reg + SUPER_CLK_MUX);
302 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
303 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
304 c->state = ON;
305 return c->state;
306}
307
308static int tegra20_super_clk_enable(struct clk_hw *hw)
309{
310 struct clk_tegra *c = to_clk_tegra(hw);
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
312 return 0;
313}
314
315static void tegra20_super_clk_disable(struct clk_hw *hw)
316{
317 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
318
319 /* oops - don't disable the CPU clock! */
320 BUG();
321}
322
323static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
324{
325 struct clk_tegra *c = to_clk_tegra(hw);
326 int val = clk_readl(c->reg + SUPER_CLK_MUX);
327 int source;
328 int shift;
329
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 source = (val >> shift) & SUPER_SOURCE_MASK;
335 return source;
336}
337
338static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
339{
340 struct clk_tegra *c = to_clk_tegra(hw);
341 u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
342 int shift;
343
344 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
345 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
346 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
347 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
348 val &= ~(SUPER_SOURCE_MASK << shift);
349 val |= index << shift;
350
351 clk_writel(val, c->reg);
352
353 return 0;
354}
355
356/* FIX ME: Need to switch parents to change the source PLL rate */
357static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
358 unsigned long prate)
359{
360 return prate;
361}
362
363static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
364 unsigned long *prate)
365{
366 return *prate;
367}
368
369static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long parent_rate)
371{
372 return 0;
373}
374
375struct clk_ops tegra_super_ops = {
376 .is_enabled = tegra20_super_clk_is_enabled,
377 .enable = tegra20_super_clk_enable,
378 .disable = tegra20_super_clk_disable,
379 .set_parent = tegra20_super_clk_set_parent,
380 .get_parent = tegra20_super_clk_get_parent,
381 .set_rate = tegra20_super_clk_set_rate,
382 .round_rate = tegra20_super_clk_round_rate,
383 .recalc_rate = tegra20_super_clk_recalc_rate,
384};
385
386static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
387 unsigned long parent_rate)
388{
389 struct clk_tegra *c = to_clk_tegra(hw);
390 u64 rate = parent_rate;
391
392 if (c->mul != 0 && c->div != 0) {
393 rate *= c->mul;
394 rate += c->div - 1; /* round up */
395 do_div(rate, c->div);
396 }
397
398 return rate;
399}
400
401struct clk_ops tegra_twd_ops = {
402 .recalc_rate = tegra20_twd_clk_recalc_rate,
403};
404
405static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
406{
407 return 0;
408}
409
410struct clk_ops tegra_cop_ops = {
411 .get_parent = tegra20_cop_clk_get_parent,
412};
413
414/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
415 * reset the COP block (i.e. AVP) */
416void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
417{
418 unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
419
420 pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
421 clk_writel(1 << 1, reg);
422}
423
424/* bus clock functions */
425static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
426{
427 struct clk_tegra *c = to_clk_tegra(hw);
428 u32 val = clk_readl(c->reg);
429
430 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
431 return c->state;
432}
433
434static int tegra20_bus_clk_enable(struct clk_hw *hw)
435{
436 struct clk_tegra *c = to_clk_tegra(hw);
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&clock_register_lock, flags);
441
442 val = clk_readl(c->reg);
443 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
444 clk_writel(val, c->reg);
445
446 spin_unlock_irqrestore(&clock_register_lock, flags);
447
448 return 0;
449}
450
451static void tegra20_bus_clk_disable(struct clk_hw *hw)
452{
453 struct clk_tegra *c = to_clk_tegra(hw);
454 unsigned long flags;
455 u32 val;
456
457 spin_lock_irqsave(&clock_register_lock, flags);
458
459 val = clk_readl(c->reg);
460 val |= BUS_CLK_DISABLE << c->reg_shift;
461 clk_writel(val, c->reg);
462
463 spin_unlock_irqrestore(&clock_register_lock, flags);
464}
465
466static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
467 unsigned long prate)
468{
469 struct clk_tegra *c = to_clk_tegra(hw);
470 u32 val = clk_readl(c->reg);
471 u64 rate = prate;
472
473 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
474 c->mul = 1;
475
476 if (c->mul != 0 && c->div != 0) {
477 rate *= c->mul;
478 rate += c->div - 1; /* round up */
479 do_div(rate, c->div);
480 }
481 return rate;
482}
483
484static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
485 unsigned long parent_rate)
486{
487 struct clk_tegra *c = to_clk_tegra(hw);
488 int ret = -EINVAL;
489 unsigned long flags;
490 u32 val;
491 int i;
492
493 spin_lock_irqsave(&clock_register_lock, flags);
494
495 val = clk_readl(c->reg);
496 for (i = 1; i <= 4; i++) {
497 if (rate == parent_rate / i) {
498 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
499 val |= (i - 1) << c->reg_shift;
500 clk_writel(val, c->reg);
501 c->div = i;
502 c->mul = 1;
503 ret = 0;
504 break;
505 }
506 }
507
508 spin_unlock_irqrestore(&clock_register_lock, flags);
509
510 return ret;
511}
512
513static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
514 unsigned long *prate)
515{
516 unsigned long parent_rate = *prate;
517 s64 divider;
518
519 if (rate >= parent_rate)
520 return rate;
521
522 divider = parent_rate;
523 divider += rate - 1;
524 do_div(divider, rate);
525
526 if (divider < 0)
527 return divider;
528
529 if (divider > 4)
530 divider = 4;
531 do_div(parent_rate, divider);
532
533 return parent_rate;
534}
535
536struct clk_ops tegra_bus_ops = {
537 .is_enabled = tegra20_bus_clk_is_enabled,
538 .enable = tegra20_bus_clk_enable,
539 .disable = tegra20_bus_clk_disable,
540 .set_rate = tegra20_bus_clk_set_rate,
541 .round_rate = tegra20_bus_clk_round_rate,
542 .recalc_rate = tegra20_bus_clk_recalc_rate,
543};
544
545/* Blink output functions */
546static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
547{
548 struct clk_tegra *c = to_clk_tegra(hw);
549 u32 val;
550
551 val = pmc_readl(PMC_CTRL);
552 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
553 return c->state;
554}
555
556static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
557 unsigned long prate)
558{
559 struct clk_tegra *c = to_clk_tegra(hw);
560 u64 rate = prate;
561 u32 val;
562
563 c->mul = 1;
564 val = pmc_readl(c->reg);
565
566 if (val & PMC_BLINK_TIMER_ENB) {
567 unsigned int on_off;
568
569 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
570 PMC_BLINK_TIMER_DATA_ON_MASK;
571 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
572 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
573 on_off += val;
574 /* each tick in the blink timer is 4 32KHz clocks */
575 c->div = on_off * 4;
576 } else {
577 c->div = 1;
578 }
579
580 if (c->mul != 0 && c->div != 0) {
581 rate *= c->mul;
582 rate += c->div - 1; /* round up */
583 do_div(rate, c->div);
584 }
585 return rate;
586}
587
588static int tegra20_blink_clk_enable(struct clk_hw *hw)
589{
590 u32 val;
591
592 val = pmc_readl(PMC_DPD_PADS_ORIDE);
593 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
594
595 val = pmc_readl(PMC_CTRL);
596 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
597
598 return 0;
599}
600
601static void tegra20_blink_clk_disable(struct clk_hw *hw)
602{
603 u32 val;
604
605 val = pmc_readl(PMC_CTRL);
606 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
607
608 val = pmc_readl(PMC_DPD_PADS_ORIDE);
609 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
610}
611
612static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
613 unsigned long parent_rate)
614{
615 struct clk_tegra *c = to_clk_tegra(hw);
616
617 if (rate >= parent_rate) {
618 c->div = 1;
619 pmc_writel(0, c->reg);
620 } else {
621 unsigned int on_off;
622 u32 val;
623
624 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
625 c->div = on_off * 8;
626
627 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
628 PMC_BLINK_TIMER_DATA_ON_SHIFT;
629 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
630 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
631 val |= on_off;
632 val |= PMC_BLINK_TIMER_ENB;
633 pmc_writel(val, c->reg);
634 }
635
636 return 0;
637}
638
639static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
640 unsigned long *prate)
641{
642 int div;
643 int mul;
644 long round_rate = *prate;
645
646 mul = 1;
647
648 if (rate >= *prate) {
649 div = 1;
650 } else {
651 div = DIV_ROUND_UP(*prate / 8, rate);
652 div *= 8;
653 }
654
655 round_rate *= mul;
656 round_rate += div - 1;
657 do_div(round_rate, div);
658
659 return round_rate;
660}
661
662struct clk_ops tegra_blink_clk_ops = {
663 .is_enabled = tegra20_blink_clk_is_enabled,
664 .enable = tegra20_blink_clk_enable,
665 .disable = tegra20_blink_clk_disable,
666 .set_rate = tegra20_blink_clk_set_rate,
667 .round_rate = tegra20_blink_clk_round_rate,
668 .recalc_rate = tegra20_blink_clk_recalc_rate,
669};
670
671/* PLL Functions */
672static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
673{
674 udelay(c->u.pll.lock_delay);
675 return 0;
676}
677
678static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
679{
680 struct clk_tegra *c = to_clk_tegra(hw);
681 u32 val = clk_readl(c->reg + PLL_BASE);
682
683 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
684 return c->state;
685}
686
687static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
688 unsigned long prate)
689{
690 struct clk_tegra *c = to_clk_tegra(hw);
691 u32 val = clk_readl(c->reg + PLL_BASE);
692 u64 rate = prate;
693
694 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
695 const struct clk_pll_freq_table *sel;
696 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
697 if (sel->input_rate == prate &&
698 sel->output_rate == c->u.pll.fixed_rate) {
699 c->mul = sel->n;
700 c->div = sel->m * sel->p;
701 break;
702 }
703 }
704 pr_err("Clock %s has unknown fixed frequency\n",
705 __clk_get_name(hw->clk));
706 BUG();
707 } else if (val & PLL_BASE_BYPASS) {
708 c->mul = 1;
709 c->div = 1;
710 } else {
711 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
712 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
713 if (c->flags & PLLU)
714 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
715 else
716 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
717 }
718
719 if (c->mul != 0 && c->div != 0) {
720 rate *= c->mul;
721 rate += c->div - 1; /* round up */
722 do_div(rate, c->div);
723 }
724 return rate;
725}
726
727static int tegra20_pll_clk_enable(struct clk_hw *hw)
728{
729 struct clk_tegra *c = to_clk_tegra(hw);
730 u32 val;
731 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
732
733 val = clk_readl(c->reg + PLL_BASE);
734 val &= ~PLL_BASE_BYPASS;
735 val |= PLL_BASE_ENABLE;
736 clk_writel(val, c->reg + PLL_BASE);
737
738 tegra20_pll_clk_wait_for_lock(c);
739
740 return 0;
741}
742
743static void tegra20_pll_clk_disable(struct clk_hw *hw)
744{
745 struct clk_tegra *c = to_clk_tegra(hw);
746 u32 val;
747 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
748
749 val = clk_readl(c->reg);
750 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
751 clk_writel(val, c->reg);
752}
753
754static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
755 unsigned long parent_rate)
756{
757 struct clk_tegra *c = to_clk_tegra(hw);
758 unsigned long input_rate = parent_rate;
759 const struct clk_pll_freq_table *sel;
760 u32 val;
761
762 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
763
764 if (c->flags & PLL_FIXED) {
765 int ret = 0;
766 if (rate != c->u.pll.fixed_rate) {
767 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
768 __func__, __clk_get_name(hw->clk),
769 c->u.pll.fixed_rate, rate);
770 ret = -EINVAL;
771 }
772 return ret;
773 }
774
775 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
776 if (sel->input_rate == input_rate && sel->output_rate == rate) {
777 c->mul = sel->n;
778 c->div = sel->m * sel->p;
779
780 val = clk_readl(c->reg + PLL_BASE);
781 if (c->flags & PLL_FIXED)
782 val |= PLL_BASE_OVERRIDE;
783 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
784 PLL_BASE_DIVM_MASK);
785 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
786 (sel->n << PLL_BASE_DIVN_SHIFT);
787 BUG_ON(sel->p < 1 || sel->p > 2);
788 if (c->flags & PLLU) {
789 if (sel->p == 1)
790 val |= PLLU_BASE_POST_DIV;
791 } else {
792 if (sel->p == 2)
793 val |= 1 << PLL_BASE_DIVP_SHIFT;
794 }
795 clk_writel(val, c->reg + PLL_BASE);
796
797 if (c->flags & PLL_HAS_CPCON) {
798 val = clk_readl(c->reg + PLL_MISC(c));
799 val &= ~PLL_MISC_CPCON_MASK;
800 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
801 clk_writel(val, c->reg + PLL_MISC(c));
802 }
803
804 if (c->state == ON)
805 tegra20_pll_clk_enable(hw);
806 return 0;
807 }
808 }
809 return -EINVAL;
810}
811
812static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
813 unsigned long *prate)
814{
815 struct clk_tegra *c = to_clk_tegra(hw);
816 const struct clk_pll_freq_table *sel;
817 unsigned long input_rate = *prate;
818 u64 output_rate = *prate;
819 int mul;
820 int div;
821
822 if (c->flags & PLL_FIXED)
823 return c->u.pll.fixed_rate;
824
825 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
826 if (sel->input_rate == input_rate && sel->output_rate == rate) {
827 mul = sel->n;
828 div = sel->m * sel->p;
829 break;
830 }
831
832 if (sel->input_rate == 0)
833 return -EINVAL;
834
835 output_rate *= mul;
836 output_rate += div - 1; /* round up */
837 do_div(output_rate, div);
838
839 return output_rate;
840}
841
842struct clk_ops tegra_pll_ops = {
843 .is_enabled = tegra20_pll_clk_is_enabled,
844 .enable = tegra20_pll_clk_enable,
845 .disable = tegra20_pll_clk_disable,
846 .set_rate = tegra20_pll_clk_set_rate,
847 .recalc_rate = tegra20_pll_clk_recalc_rate,
848 .round_rate = tegra20_pll_clk_round_rate,
849};
850
851static void tegra20_pllx_clk_init(struct clk_hw *hw)
852{
853 struct clk_tegra *c = to_clk_tegra(hw);
854
855 if (tegra_sku_id == 7)
856 c->max_rate = 750000000;
857}
858
859struct clk_ops tegra_pllx_ops = {
860 .init = tegra20_pllx_clk_init,
861 .is_enabled = tegra20_pll_clk_is_enabled,
862 .enable = tegra20_pll_clk_enable,
863 .disable = tegra20_pll_clk_disable,
864 .set_rate = tegra20_pll_clk_set_rate,
865 .recalc_rate = tegra20_pll_clk_recalc_rate,
866 .round_rate = tegra20_pll_clk_round_rate,
867};
868
869static int tegra20_plle_clk_enable(struct clk_hw *hw)
870{
871 struct clk_tegra *c = to_clk_tegra(hw);
872 u32 val;
873
874 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
875
876 mdelay(1);
877
878 val = clk_readl(c->reg + PLL_BASE);
879 if (!(val & PLLE_MISC_READY))
880 return -EBUSY;
881
882 val = clk_readl(c->reg + PLL_BASE);
883 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
884 clk_writel(val, c->reg + PLL_BASE);
885
886 return 0;
887}
888
889struct clk_ops tegra_plle_ops = {
890 .is_enabled = tegra20_pll_clk_is_enabled,
891 .enable = tegra20_plle_clk_enable,
892 .set_rate = tegra20_pll_clk_set_rate,
893 .recalc_rate = tegra20_pll_clk_recalc_rate,
894 .round_rate = tegra20_pll_clk_round_rate,
895};
896
897/* Clock divider ops */
898static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
899{
900 struct clk_tegra *c = to_clk_tegra(hw);
901 u32 val = clk_readl(c->reg);
902
903 val >>= c->reg_shift;
904 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
905 if (!(val & PLL_OUT_RESET_DISABLE))
906 c->state = OFF;
907 return c->state;
908}
909
910static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
911 unsigned long prate)
912{
913 struct clk_tegra *c = to_clk_tegra(hw);
914 u64 rate = prate;
915 u32 val = clk_readl(c->reg);
916 u32 divu71;
917
918 val >>= c->reg_shift;
919
920 if (c->flags & DIV_U71) {
921 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
922 c->div = (divu71 + 2);
923 c->mul = 2;
924 } else if (c->flags & DIV_2) {
925 c->div = 2;
926 c->mul = 1;
927 } else {
928 c->div = 1;
929 c->mul = 1;
930 }
931
932 rate *= c->mul;
933 rate += c->div - 1; /* round up */
934 do_div(rate, c->div);
935
936 return rate;
937}
938
939static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
940{
941 struct clk_tegra *c = to_clk_tegra(hw);
942 unsigned long flags;
943 u32 new_val;
944 u32 val;
945
946 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
947
948 if (c->flags & DIV_U71) {
949 spin_lock_irqsave(&clock_register_lock, flags);
950 val = clk_readl(c->reg);
951 new_val = val >> c->reg_shift;
952 new_val &= 0xFFFF;
953
954 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
955
956 val &= ~(0xFFFF << c->reg_shift);
957 val |= new_val << c->reg_shift;
958 clk_writel(val, c->reg);
959 spin_unlock_irqrestore(&clock_register_lock, flags);
960 return 0;
961 } else if (c->flags & DIV_2) {
962 BUG_ON(!(c->flags & PLLD));
963 spin_lock_irqsave(&clock_register_lock, flags);
964 val = clk_readl(c->reg);
965 val &= ~PLLD_MISC_DIV_RST;
966 clk_writel(val, c->reg);
967 spin_unlock_irqrestore(&clock_register_lock, flags);
968 return 0;
969 }
970 return -EINVAL;
971}
972
973static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
974{
975 struct clk_tegra *c = to_clk_tegra(hw);
976 unsigned long flags;
977 u32 new_val;
978 u32 val;
979
980 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
981
982 if (c->flags & DIV_U71) {
983 spin_lock_irqsave(&clock_register_lock, flags);
984 val = clk_readl(c->reg);
985 new_val = val >> c->reg_shift;
986 new_val &= 0xFFFF;
987
988 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
989
990 val &= ~(0xFFFF << c->reg_shift);
991 val |= new_val << c->reg_shift;
992 clk_writel(val, c->reg);
993 spin_unlock_irqrestore(&clock_register_lock, flags);
994 } else if (c->flags & DIV_2) {
995 BUG_ON(!(c->flags & PLLD));
996 spin_lock_irqsave(&clock_register_lock, flags);
997 val = clk_readl(c->reg);
998 val |= PLLD_MISC_DIV_RST;
999 clk_writel(val, c->reg);
1000 spin_unlock_irqrestore(&clock_register_lock, flags);
1001 }
1002}
1003
1004static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1005 unsigned long parent_rate)
1006{
1007 struct clk_tegra *c = to_clk_tegra(hw);
1008 unsigned long flags;
1009 int divider_u71;
1010 u32 new_val;
1011 u32 val;
1012
1013 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1014
1015 if (c->flags & DIV_U71) {
1016 divider_u71 = clk_div71_get_divider(parent_rate, rate);
1017 if (divider_u71 >= 0) {
1018 spin_lock_irqsave(&clock_register_lock, flags);
1019 val = clk_readl(c->reg);
1020 new_val = val >> c->reg_shift;
1021 new_val &= 0xFFFF;
1022 if (c->flags & DIV_U71_FIXED)
1023 new_val |= PLL_OUT_OVERRIDE;
1024 new_val &= ~PLL_OUT_RATIO_MASK;
1025 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1026
1027 val &= ~(0xFFFF << c->reg_shift);
1028 val |= new_val << c->reg_shift;
1029 clk_writel(val, c->reg);
1030 c->div = divider_u71 + 2;
1031 c->mul = 2;
1032 spin_unlock_irqrestore(&clock_register_lock, flags);
1033 return 0;
1034 }
1035 } else if (c->flags & DIV_2) {
1036 if (parent_rate == rate * 2)
1037 return 0;
1038 }
1039 return -EINVAL;
1040}
1041
1042static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1043 unsigned long *prate)
1044{
1045 struct clk_tegra *c = to_clk_tegra(hw);
1046 unsigned long parent_rate = *prate;
1047 int divider;
1048
1049 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1050
1051 if (c->flags & DIV_U71) {
1052 divider = clk_div71_get_divider(parent_rate, rate);
1053 if (divider < 0)
1054 return divider;
1055 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1056 } else if (c->flags & DIV_2) {
1057 return DIV_ROUND_UP(parent_rate, 2);
1058 }
1059 return -EINVAL;
1060}
1061
1062struct clk_ops tegra_pll_div_ops = {
1063 .is_enabled = tegra20_pll_div_clk_is_enabled,
1064 .enable = tegra20_pll_div_clk_enable,
1065 .disable = tegra20_pll_div_clk_disable,
1066 .set_rate = tegra20_pll_div_clk_set_rate,
1067 .round_rate = tegra20_pll_div_clk_round_rate,
1068 .recalc_rate = tegra20_pll_div_clk_recalc_rate,
1069};
1070
1071/* Periph clk ops */
1072
1073static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
1074{
1075 struct clk_tegra *c = to_clk_tegra(hw);
1076
1077 c->state = ON;
1078
1079 if (!c->u.periph.clk_num)
1080 goto out;
1081
1082 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1083 PERIPH_CLK_TO_ENB_BIT(c)))
1084 c->state = OFF;
1085
1086 if (!(c->flags & PERIPH_NO_RESET))
1087 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
1088 PERIPH_CLK_TO_ENB_BIT(c))
1089 c->state = OFF;
1090
1091out:
1092 return c->state;
1093}
1094
1095static int tegra20_periph_clk_enable(struct clk_hw *hw)
1096{
1097 struct clk_tegra *c = to_clk_tegra(hw);
1098 unsigned long flags;
1099 u32 val;
1100
1101 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1102
1103 if (!c->u.periph.clk_num)
1104 return 0;
1105
1106 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1107 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1108 return 0;
1109
1110 spin_lock_irqsave(&clock_register_lock, flags);
1111
1112 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1113 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1114 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
1115 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1116 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1117 if (c->flags & PERIPH_EMC_ENB) {
1118 /* The EMC peripheral clock has 2 extra enable bits */
1119 /* FIXME: Do they need to be disabled? */
1120 val = clk_readl(c->reg);
1121 val |= 0x3 << 24;
1122 clk_writel(val, c->reg);
1123 }
1124
1125 spin_unlock_irqrestore(&clock_register_lock, flags);
1126
1127 return 0;
1128}
1129
1130static void tegra20_periph_clk_disable(struct clk_hw *hw)
1131{
1132 struct clk_tegra *c = to_clk_tegra(hw);
1133 unsigned long flags;
1134
1135 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1136
1137 if (!c->u.periph.clk_num)
1138 return;
1139
1140 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1141
1142 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1143 return;
1144
1145 spin_lock_irqsave(&clock_register_lock, flags);
1146
1147 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1148 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1149
1150 spin_unlock_irqrestore(&clock_register_lock, flags);
1151}
1152
1153void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
1154{
1155 struct clk_tegra *c = to_clk_tegra(hw);
1156 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
1157
1158 pr_debug("%s %s on clock %s\n", __func__,
1159 assert ? "assert" : "deassert", __clk_get_name(hw->clk));
1160
1161 BUG_ON(!c->u.periph.clk_num);
1162
1163 if (!(c->flags & PERIPH_NO_RESET))
1164 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1165 base + PERIPH_CLK_TO_ENB_SET_REG(c));
1166}
1167
1168static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1169{
1170 struct clk_tegra *c = to_clk_tegra(hw);
1171 u32 val;
1172 u32 mask;
1173 u32 shift;
1174
1175 pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
1176
1177 if (c->flags & MUX_PWM) {
1178 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1179 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1180 } else {
1181 shift = PERIPH_CLK_SOURCE_SHIFT;
1182 mask = PERIPH_CLK_SOURCE_MASK;
1183 }
1184
1185 val = clk_readl(c->reg);
1186 val &= ~mask;
1187 val |= (index) << shift;
1188
1189 clk_writel(val, c->reg);
1190
1191 return 0;
1192}
1193
1194static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
1195{
1196 struct clk_tegra *c = to_clk_tegra(hw);
1197 u32 val = clk_readl(c->reg);
1198 u32 mask;
1199 u32 shift;
1200
1201 if (c->flags & MUX_PWM) {
1202 shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
1203 mask = PERIPH_CLK_SOURCE_PWM_MASK;
1204 } else {
1205 shift = PERIPH_CLK_SOURCE_SHIFT;
1206 mask = PERIPH_CLK_SOURCE_MASK;
1207 }
1208
1209 if (c->flags & MUX)
1210 return (val & mask) >> shift;
1211 else
1212 return 0;
1213}
1214
1215static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
1216 unsigned long prate)
1217{
1218 struct clk_tegra *c = to_clk_tegra(hw);
1219 unsigned long rate = prate;
1220 u32 val = clk_readl(c->reg);
1221
1222 if (c->flags & DIV_U71) {
1223 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
1224 c->div = divu71 + 2;
1225 c->mul = 2;
1226 } else if (c->flags & DIV_U16) {
1227 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
1228 c->div = divu16 + 1;
1229 c->mul = 1;
1230 } else {
1231 c->div = 1;
1232 c->mul = 1;
1233 return rate;
1234 }
1235
1236 if (c->mul != 0 && c->div != 0) {
1237 rate *= c->mul;
1238 rate += c->div - 1; /* round up */
1239 do_div(rate, c->div);
1240 }
1241
1242 return rate;
1243}
1244
1245static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1246 unsigned long parent_rate)
1247{
1248 struct clk_tegra *c = to_clk_tegra(hw);
1249 u32 val;
1250 int divider;
1251
1252 val = clk_readl(c->reg);
1253
1254 if (c->flags & DIV_U71) {
1255 divider = clk_div71_get_divider(parent_rate, rate);
1256
1257 if (divider >= 0) {
1258 val = clk_readl(c->reg);
1259 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1260 val |= divider;
1261 clk_writel(val, c->reg);
1262 c->div = divider + 2;
1263 c->mul = 2;
1264 return 0;
1265 }
1266 } else if (c->flags & DIV_U16) {
1267 divider = clk_div16_get_divider(parent_rate, rate);
1268 if (divider >= 0) {
1269 val = clk_readl(c->reg);
1270 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1271 val |= divider;
1272 clk_writel(val, c->reg);
1273 c->div = divider + 1;
1274 c->mul = 1;
1275 return 0;
1276 }
1277 } else if (parent_rate <= rate) {
1278 c->div = 1;
1279 c->mul = 1;
1280 return 0;
1281 }
1282
1283 return -EINVAL;
1284}
1285
1286static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
1287 unsigned long rate, unsigned long *prate)
1288{
1289 struct clk_tegra *c = to_clk_tegra(hw);
1290 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1291 int divider;
1292
1293 pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
1294
1295 if (prate)
1296 parent_rate = *prate;
1297
1298 if (c->flags & DIV_U71) {
1299 divider = clk_div71_get_divider(parent_rate, rate);
1300 if (divider < 0)
1301 return divider;
1302
1303 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1304 } else if (c->flags & DIV_U16) {
1305 divider = clk_div16_get_divider(parent_rate, rate);
1306 if (divider < 0)
1307 return divider;
1308 return DIV_ROUND_UP(parent_rate, divider + 1);
1309 }
1310 return -EINVAL;
1311}
1312
1313struct clk_ops tegra_periph_clk_ops = {
1314 .is_enabled = tegra20_periph_clk_is_enabled,
1315 .enable = tegra20_periph_clk_enable,
1316 .disable = tegra20_periph_clk_disable,
1317 .set_parent = tegra20_periph_clk_set_parent,
1318 .get_parent = tegra20_periph_clk_get_parent,
1319 .set_rate = tegra20_periph_clk_set_rate,
1320 .round_rate = tegra20_periph_clk_round_rate,
1321 .recalc_rate = tegra20_periph_clk_recalc_rate,
1322};
1323
1324/* External memory controller clock ops */
1325static void tegra20_emc_clk_init(struct clk_hw *hw)
1326{
1327 struct clk_tegra *c = to_clk_tegra(hw);
1328 c->max_rate = __clk_get_rate(hw->clk);
1329}
1330
1331static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1332 unsigned long *prate)
1333{
1334 struct clk_tegra *c = to_clk_tegra(hw);
1335 long emc_rate;
1336 long clk_rate;
1337
1338 /*
1339 * The slowest entry in the EMC clock table that is at least as
1340 * fast as rate.
1341 */
1342 emc_rate = tegra_emc_round_rate(rate);
1343 if (emc_rate < 0)
1344 return c->max_rate;
1345
1346 /*
1347 * The fastest rate the PLL will generate that is at most the
1348 * requested rate.
1349 */
1350 clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
1351
1352 /*
1353 * If this fails, and emc_rate > clk_rate, it's because the maximum
1354 * rate in the EMC tables is larger than the maximum rate of the EMC
1355 * clock. The EMC clock's max rate is the rate it was running when the
1356 * kernel booted. Such a mismatch is probably due to using the wrong
1357 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
1358 */
1359 WARN_ONCE(emc_rate != clk_rate,
1360 "emc_rate %ld != clk_rate %ld",
1361 emc_rate, clk_rate);
1362
1363 return emc_rate;
1364}
1365
1366static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1367 unsigned long parent_rate)
1368{
1369 int ret;
1370
1371 /*
1372 * The Tegra2 memory controller has an interlock with the clock
1373 * block that allows memory shadowed registers to be updated,
1374 * and then transfer them to the main registers at the same
1375 * time as the clock update without glitches.
1376 */
1377 ret = tegra_emc_set_rate(rate);
1378 if (ret < 0)
1379 return ret;
1380
1381 ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
1382 udelay(1);
1383
1384 return ret;
1385}
1386
1387struct clk_ops tegra_emc_clk_ops = {
1388 .init = tegra20_emc_clk_init,
1389 .is_enabled = tegra20_periph_clk_is_enabled,
1390 .enable = tegra20_periph_clk_enable,
1391 .disable = tegra20_periph_clk_disable,
1392 .set_parent = tegra20_periph_clk_set_parent,
1393 .get_parent = tegra20_periph_clk_get_parent,
1394 .set_rate = tegra20_emc_clk_set_rate,
1395 .round_rate = tegra20_emc_clk_round_rate,
1396 .recalc_rate = tegra20_periph_clk_recalc_rate,
1397};
1398
1399/* Clock doubler ops */
1400static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
1401{
1402 struct clk_tegra *c = to_clk_tegra(hw);
1403
1404 c->state = ON;
1405
1406 if (!c->u.periph.clk_num)
1407 goto out;
1408
1409 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1410 PERIPH_CLK_TO_ENB_BIT(c)))
1411 c->state = OFF;
1412
1413out:
1414 return c->state;
1415};
1416
1417static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
1418 unsigned long prate)
1419{
1420 struct clk_tegra *c = to_clk_tegra(hw);
1421 u64 rate = prate;
1422
1423 c->mul = 2;
1424 c->div = 1;
1425
1426 rate *= c->mul;
1427 rate += c->div - 1; /* round up */
1428 do_div(rate, c->div);
1429
1430 return rate;
1431}
1432
1433static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
1434 unsigned long *prate)
1435{
1436 unsigned long output_rate = *prate;
1437
1438 do_div(output_rate, 2);
1439 return output_rate;
1440}
1441
1442static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
1443 unsigned long parent_rate)
1444{
1445 if (rate != 2 * parent_rate)
1446 return -EINVAL;
1447 return 0;
1448}
1449
1450struct clk_ops tegra_clk_double_ops = {
1451 .is_enabled = tegra20_clk_double_is_enabled,
1452 .enable = tegra20_periph_clk_enable,
1453 .disable = tegra20_periph_clk_disable,
1454 .set_rate = tegra20_clk_double_set_rate,
1455 .recalc_rate = tegra20_clk_double_recalc_rate,
1456 .round_rate = tegra20_clk_double_round_rate,
1457};
1458
1459/* Audio sync clock ops */
1460static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
1461{
1462 struct clk_tegra *c = to_clk_tegra(hw);
1463 u32 val = clk_readl(c->reg);
1464
1465 c->state = (val & (1<<4)) ? OFF : ON;
1466 return c->state;
1467}
1468
1469static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
1470{
1471 struct clk_tegra *c = to_clk_tegra(hw);
1472
1473 clk_writel(0, c->reg);
1474 return 0;
1475}
1476
1477static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
1478{
1479 struct clk_tegra *c = to_clk_tegra(hw);
1480 clk_writel(1, c->reg);
1481}
1482
1483static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
1484{
1485 struct clk_tegra *c = to_clk_tegra(hw);
1486 u32 val = clk_readl(c->reg);
1487 int source;
1488
1489 source = val & 0xf;
1490 return source;
1491}
1492
1493static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
1494{
1495 struct clk_tegra *c = to_clk_tegra(hw);
1496 u32 val;
1497
1498 val = clk_readl(c->reg);
1499 val &= ~0xf;
1500 val |= index;
1501
1502 clk_writel(val, c->reg);
1503
1504 return 0;
1505}
1506
1507struct clk_ops tegra_audio_sync_clk_ops = {
1508 .is_enabled = tegra20_audio_sync_clk_is_enabled,
1509 .enable = tegra20_audio_sync_clk_enable,
1510 .disable = tegra20_audio_sync_clk_disable,
1511 .set_parent = tegra20_audio_sync_clk_set_parent,
1512 .get_parent = tegra20_audio_sync_clk_get_parent,
1513};
1514
1515/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1516
1517static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
1518{
1519 struct clk_tegra *c = to_clk_tegra(hw);
1520 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1521 * currently done in the pinmux code. */
1522 c->state = ON;
1523
1524 BUG_ON(!c->u.periph.clk_num);
1525
1526 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1527 PERIPH_CLK_TO_ENB_BIT(c)))
1528 c->state = OFF;
1529 return c->state;
1530}
1531
1532static int tegra20_cdev_clk_enable(struct clk_hw *hw)
1533{
1534 struct clk_tegra *c = to_clk_tegra(hw);
1535 BUG_ON(!c->u.periph.clk_num);
1536
1537 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1538 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1539 return 0;
1540}
1541
1542static void tegra20_cdev_clk_disable(struct clk_hw *hw)
1543{
1544 struct clk_tegra *c = to_clk_tegra(hw);
1545 BUG_ON(!c->u.periph.clk_num);
1546
1547 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1548 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1549}
1550
1551static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
1552 unsigned long prate)
1553{
1554 return to_clk_tegra(hw)->fixed_rate;
1555}
1556
1557struct clk_ops tegra_cdev_clk_ops = {
1558 .is_enabled = tegra20_cdev_clk_is_enabled,
1559 .enable = tegra20_cdev_clk_enable,
1560 .disable = tegra20_cdev_clk_disable,
1561 .recalc_rate = tegra20_cdev_recalc_rate,
1562};
1563
1564/* Tegra20 CPU clock and reset control functions */
1565static void tegra20_wait_cpu_in_reset(u32 cpu)
1566{
1567 unsigned int reg;
1568
1569 do {
1570 reg = readl(reg_clk_base +
1571 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1572 cpu_relax();
1573 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
1574
1575 return;
1576}
1577
1578static void tegra20_put_cpu_in_reset(u32 cpu)
1579{
1580 writel(CPU_RESET(cpu),
1581 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1582 dmb();
1583}
1584
1585static void tegra20_cpu_out_of_reset(u32 cpu)
1586{
1587 writel(CPU_RESET(cpu),
1588 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1589 wmb();
1590}
1591
1592static void tegra20_enable_cpu_clock(u32 cpu)
1593{
1594 unsigned int reg;
1595
1596 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1597 writel(reg & ~CPU_CLOCK(cpu),
1598 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1599 barrier();
1600 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1601}
1602
1603static void tegra20_disable_cpu_clock(u32 cpu)
1604{
1605 unsigned int reg;
1606
1607 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1608 writel(reg | CPU_CLOCK(cpu),
1609 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1610}
1611
1612static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1613 .wait_for_reset = tegra20_wait_cpu_in_reset,
1614 .put_in_reset = tegra20_put_cpu_in_reset,
1615 .out_of_reset = tegra20_cpu_out_of_reset,
1616 .enable_clock = tegra20_enable_cpu_clock,
1617 .disable_clock = tegra20_disable_cpu_clock,
1618};
1619
1620void __init tegra20_cpu_car_ops_init(void)
1621{
1622 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1623}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
deleted file mode 100644
index 8bfd31bcc490..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA20_CLOCK_H
18#define __MACH_TEGRA20_CLOCK_H
19
20extern struct clk_ops tegra_clk_32k_ops;
21extern struct clk_ops tegra_pll_ops;
22extern struct clk_ops tegra_clk_m_ops;
23extern struct clk_ops tegra_pll_div_ops;
24extern struct clk_ops tegra_pllx_ops;
25extern struct clk_ops tegra_plle_ops;
26extern struct clk_ops tegra_clk_double_ops;
27extern struct clk_ops tegra_cdev_clk_ops;
28extern struct clk_ops tegra_audio_sync_clk_ops;
29extern struct clk_ops tegra_super_ops;
30extern struct clk_ops tegra_cpu_ops;
31extern struct clk_ops tegra_twd_ops;
32extern struct clk_ops tegra_cop_ops;
33extern struct clk_ops tegra_bus_ops;
34extern struct clk_ops tegra_blink_clk_ops;
35extern struct clk_ops tegra_emc_clk_ops;
36extern struct clk_ops tegra_periph_clk_ops;
37extern struct clk_ops tegra_clk_shared_bus_ops;
38
39void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
40void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
41
42#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
deleted file mode 100644
index 022cdaef7ca5..000000000000
--- a/arch/arm/mach-tegra/tegra20_clocks_data.c
+++ /dev/null
@@ -1,1143 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29#include <linux/clk/tegra.h>
30
31#include "clock.h"
32#include "fuse.h"
33#include "tegra2_emc.h"
34#include "tegra20_clocks.h"
35
36/* Clock definitions */
37
38#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
39 _parent_names, _parents, _parent) \
40 static struct clk tegra_##_name = { \
41 .hw = &tegra_##_name##_hw.hw, \
42 .name = #_name, \
43 .rate = _rate, \
44 .ops = _ops, \
45 .flags = _flags, \
46 .parent_names = _parent_names, \
47 .parents = _parents, \
48 .num_parents = ARRAY_SIZE(_parent_names), \
49 .parent = _parent, \
50 };
51
52static struct clk tegra_clk_32k;
53static struct clk_tegra tegra_clk_32k_hw = {
54 .hw = {
55 .clk = &tegra_clk_32k,
56 },
57 .fixed_rate = 32768,
58};
59
60static struct clk tegra_clk_32k = {
61 .name = "clk_32k",
62 .rate = 32768,
63 .ops = &tegra_clk_32k_ops,
64 .hw = &tegra_clk_32k_hw.hw,
65 .flags = CLK_IS_ROOT,
66};
67
68static struct clk tegra_clk_m;
69static struct clk_tegra tegra_clk_m_hw = {
70 .hw = {
71 .clk = &tegra_clk_m,
72 },
73 .flags = ENABLE_ON_INIT,
74 .reg = 0x1fc,
75 .reg_shift = 28,
76 .max_rate = 26000000,
77 .fixed_rate = 0,
78};
79
80static struct clk tegra_clk_m = {
81 .name = "clk_m",
82 .ops = &tegra_clk_m_ops,
83 .hw = &tegra_clk_m_hw.hw,
84 .flags = CLK_IS_ROOT,
85};
86
87#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
88 _input_max, _cf_min, _cf_max, _vco_min, \
89 _vco_max, _freq_table, _lock_delay, _ops, \
90 _fixed_rate, _parent) \
91 static const char *tegra_##_name##_parent_names[] = { \
92 #_parent, \
93 }; \
94 static struct clk *tegra_##_name##_parents[] = { \
95 &tegra_##_parent, \
96 }; \
97 static struct clk tegra_##_name; \
98 static struct clk_tegra tegra_##_name##_hw = { \
99 .hw = { \
100 .clk = &tegra_##_name, \
101 }, \
102 .flags = _flags, \
103 .reg = _reg, \
104 .max_rate = _max_rate, \
105 .u.pll = { \
106 .input_min = _input_min, \
107 .input_max = _input_max, \
108 .cf_min = _cf_min, \
109 .cf_max = _cf_max, \
110 .vco_min = _vco_min, \
111 .vco_max = _vco_max, \
112 .freq_table = _freq_table, \
113 .lock_delay = _lock_delay, \
114 .fixed_rate = _fixed_rate, \
115 }, \
116 }; \
117 static struct clk tegra_##_name = { \
118 .name = #_name, \
119 .ops = &_ops, \
120 .hw = &tegra_##_name##_hw.hw, \
121 .parent = &tegra_##_parent, \
122 .parent_names = tegra_##_name##_parent_names, \
123 .parents = tegra_##_name##_parents, \
124 .num_parents = 1, \
125 };
126
127#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
128 _max_rate, _ops, _parent, _clk_flags) \
129 static const char *tegra_##_name##_parent_names[] = { \
130 #_parent, \
131 }; \
132 static struct clk *tegra_##_name##_parents[] = { \
133 &tegra_##_parent, \
134 }; \
135 static struct clk tegra_##_name; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .reg_shift = _reg_shift, \
144 }; \
145 static struct clk tegra_##_name = { \
146 .name = #_name, \
147 .ops = &tegra_pll_div_ops, \
148 .hw = &tegra_##_name##_hw.hw, \
149 .parent = &tegra_##_parent, \
150 .parent_names = tegra_##_name##_parent_names, \
151 .parents = tegra_##_name##_parents, \
152 .num_parents = 1, \
153 .flags = _clk_flags, \
154 };
155
156
157static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
158 {32768, 12000000, 366, 1, 1, 0},
159 {32768, 13000000, 397, 1, 1, 0},
160 {32768, 19200000, 586, 1, 1, 0},
161 {32768, 26000000, 793, 1, 1, 0},
162 {0, 0, 0, 0, 0, 0},
163};
164
165DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
166 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
167 tegra_pll_ops, 0, clk_32k);
168
169static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
170 { 12000000, 600000000, 600, 12, 1, 8 },
171 { 13000000, 600000000, 600, 13, 1, 8 },
172 { 19200000, 600000000, 500, 16, 1, 6 },
173 { 26000000, 600000000, 600, 26, 1, 8 },
174 { 0, 0, 0, 0, 0, 0 },
175};
176
177DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
178 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
179 tegra_pll_ops, 0, clk_m);
180
181DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
182 tegra_pll_div_ops, pll_c, 0);
183
184static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
185 { 12000000, 666000000, 666, 12, 1, 8},
186 { 13000000, 666000000, 666, 13, 1, 8},
187 { 19200000, 666000000, 555, 16, 1, 8},
188 { 26000000, 666000000, 666, 26, 1, 8},
189 { 12000000, 600000000, 600, 12, 1, 8},
190 { 13000000, 600000000, 600, 13, 1, 8},
191 { 19200000, 600000000, 375, 12, 1, 6},
192 { 26000000, 600000000, 600, 26, 1, 8},
193 { 0, 0, 0, 0, 0, 0 },
194};
195
196DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
197 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
198 tegra_pll_ops, 0, clk_m);
199
200DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
201 tegra_pll_div_ops, pll_m, 0);
202
203static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
204 { 12000000, 216000000, 432, 12, 2, 8},
205 { 13000000, 216000000, 432, 13, 2, 8},
206 { 19200000, 216000000, 90, 4, 2, 1},
207 { 26000000, 216000000, 432, 26, 2, 8},
208 { 12000000, 432000000, 432, 12, 1, 8},
209 { 13000000, 432000000, 432, 13, 1, 8},
210 { 19200000, 432000000, 90, 4, 1, 1},
211 { 26000000, 432000000, 432, 26, 1, 8},
212 { 0, 0, 0, 0, 0, 0 },
213};
214
215
216DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
217 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
218 tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
219
220DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
221 432000000, tegra_pll_div_ops, pll_p, 0);
222DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
223 432000000, tegra_pll_div_ops, pll_p, 0);
224DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
225 432000000, tegra_pll_div_ops, pll_p, 0);
226DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
227 432000000, tegra_pll_div_ops, pll_p, 0);
228
229static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
230 { 28800000, 56448000, 49, 25, 1, 1},
231 { 28800000, 73728000, 64, 25, 1, 1},
232 { 28800000, 24000000, 5, 6, 1, 1},
233 { 0, 0, 0, 0, 0, 0 },
234};
235
236DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
237 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
238 tegra_pll_ops, 0, pll_p_out1);
239
240DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
241 tegra_pll_div_ops, pll_a, 0);
242
243static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
244 { 12000000, 216000000, 216, 12, 1, 4},
245 { 13000000, 216000000, 216, 13, 1, 4},
246 { 19200000, 216000000, 135, 12, 1, 3},
247 { 26000000, 216000000, 216, 26, 1, 4},
248
249 { 12000000, 297000000, 99, 4, 1, 4 },
250 { 12000000, 339000000, 113, 4, 1, 4 },
251
252 { 12000000, 594000000, 594, 12, 1, 8},
253 { 13000000, 594000000, 594, 13, 1, 8},
254 { 19200000, 594000000, 495, 16, 1, 8},
255 { 26000000, 594000000, 594, 26, 1, 8},
256
257 { 12000000, 616000000, 616, 12, 1, 8},
258
259 { 12000000, 1000000000, 1000, 12, 1, 12},
260 { 13000000, 1000000000, 1000, 13, 1, 12},
261 { 19200000, 1000000000, 625, 12, 1, 8},
262 { 26000000, 1000000000, 1000, 26, 1, 12},
263
264 { 0, 0, 0, 0, 0, 0 },
265};
266
267DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
268 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
269 1000, tegra_pll_ops, 0, clk_m);
270
271DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
272 tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
273
274static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
275 { 12000000, 480000000, 960, 12, 2, 0},
276 { 13000000, 480000000, 960, 13, 2, 0},
277 { 19200000, 480000000, 200, 4, 2, 0},
278 { 26000000, 480000000, 960, 26, 2, 0},
279 { 0, 0, 0, 0, 0, 0 },
280};
281
282DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
283 48000000, 960000000, tegra_pll_u_freq_table, 1000,
284 tegra_pll_ops, 0, clk_m);
285
286static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
287 /* 1 GHz */
288 { 12000000, 1000000000, 1000, 12, 1, 12},
289 { 13000000, 1000000000, 1000, 13, 1, 12},
290 { 19200000, 1000000000, 625, 12, 1, 8},
291 { 26000000, 1000000000, 1000, 26, 1, 12},
292
293 /* 912 MHz */
294 { 12000000, 912000000, 912, 12, 1, 12},
295 { 13000000, 912000000, 912, 13, 1, 12},
296 { 19200000, 912000000, 760, 16, 1, 8},
297 { 26000000, 912000000, 912, 26, 1, 12},
298
299 /* 816 MHz */
300 { 12000000, 816000000, 816, 12, 1, 12},
301 { 13000000, 816000000, 816, 13, 1, 12},
302 { 19200000, 816000000, 680, 16, 1, 8},
303 { 26000000, 816000000, 816, 26, 1, 12},
304
305 /* 760 MHz */
306 { 12000000, 760000000, 760, 12, 1, 12},
307 { 13000000, 760000000, 760, 13, 1, 12},
308 { 19200000, 760000000, 950, 24, 1, 8},
309 { 26000000, 760000000, 760, 26, 1, 12},
310
311 /* 750 MHz */
312 { 12000000, 750000000, 750, 12, 1, 12},
313 { 13000000, 750000000, 750, 13, 1, 12},
314 { 19200000, 750000000, 625, 16, 1, 8},
315 { 26000000, 750000000, 750, 26, 1, 12},
316
317 /* 608 MHz */
318 { 12000000, 608000000, 608, 12, 1, 12},
319 { 13000000, 608000000, 608, 13, 1, 12},
320 { 19200000, 608000000, 380, 12, 1, 8},
321 { 26000000, 608000000, 608, 26, 1, 12},
322
323 /* 456 MHz */
324 { 12000000, 456000000, 456, 12, 1, 12},
325 { 13000000, 456000000, 456, 13, 1, 12},
326 { 19200000, 456000000, 380, 16, 1, 8},
327 { 26000000, 456000000, 456, 26, 1, 12},
328
329 /* 312 MHz */
330 { 12000000, 312000000, 312, 12, 1, 12},
331 { 13000000, 312000000, 312, 13, 1, 12},
332 { 19200000, 312000000, 260, 16, 1, 8},
333 { 26000000, 312000000, 312, 26, 1, 12},
334
335 { 0, 0, 0, 0, 0, 0 },
336};
337
338DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
339 31000000, 1000000, 6000000, 20000000, 1200000000,
340 tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
341
342static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
343 { 12000000, 100000000, 200, 24, 1, 0 },
344 { 0, 0, 0, 0, 0, 0 },
345};
346
347DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
348 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
349
350static const char *tegra_common_parent_names[] = {
351 "clk_m",
352};
353
354static struct clk *tegra_common_parents[] = {
355 &tegra_clk_m,
356};
357
358static struct clk tegra_clk_d;
359static struct clk_tegra tegra_clk_d_hw = {
360 .hw = {
361 .clk = &tegra_clk_d,
362 },
363 .flags = PERIPH_NO_RESET,
364 .reg = 0x34,
365 .reg_shift = 12,
366 .max_rate = 52000000,
367 .u.periph = {
368 .clk_num = 90,
369 },
370};
371
372static struct clk tegra_clk_d = {
373 .name = "clk_d",
374 .hw = &tegra_clk_d_hw.hw,
375 .ops = &tegra_clk_double_ops,
376 .parent = &tegra_clk_m,
377 .parent_names = tegra_common_parent_names,
378 .parents = tegra_common_parents,
379 .num_parents = ARRAY_SIZE(tegra_common_parent_names),
380};
381
382static struct clk tegra_cdev1;
383static struct clk_tegra tegra_cdev1_hw = {
384 .hw = {
385 .clk = &tegra_cdev1,
386 },
387 .fixed_rate = 26000000,
388 .u.periph = {
389 .clk_num = 94,
390 },
391};
392static struct clk tegra_cdev1 = {
393 .name = "cdev1",
394 .hw = &tegra_cdev1_hw.hw,
395 .ops = &tegra_cdev_clk_ops,
396 .flags = CLK_IS_ROOT,
397};
398
399/* dap_mclk2, belongs to the cdev2 pingroup. */
400static struct clk tegra_cdev2;
401static struct clk_tegra tegra_cdev2_hw = {
402 .hw = {
403 .clk = &tegra_cdev2,
404 },
405 .fixed_rate = 26000000,
406 .u.periph = {
407 .clk_num = 93,
408 },
409};
410static struct clk tegra_cdev2 = {
411 .name = "cdev2",
412 .hw = &tegra_cdev2_hw.hw,
413 .ops = &tegra_cdev_clk_ops,
414 .flags = CLK_IS_ROOT,
415};
416
417/* initialized before peripheral clocks */
418static struct clk_mux_sel mux_audio_sync_clk[8+1];
419static const struct audio_sources {
420 const char *name;
421 int value;
422} mux_audio_sync_clk_sources[] = {
423 { .name = "spdif_in", .value = 0 },
424 { .name = "i2s1", .value = 1 },
425 { .name = "i2s2", .value = 2 },
426 { .name = "pll_a_out0", .value = 4 },
427#if 0 /* FIXME: not implemented */
428 { .name = "ac97", .value = 3 },
429 { .name = "ext_audio_clk2", .value = 5 },
430 { .name = "ext_audio_clk1", .value = 6 },
431 { .name = "ext_vimclk", .value = 7 },
432#endif
433 { NULL, 0 }
434};
435
436static const char *audio_parent_names[] = {
437 "spdif_in",
438 "i2s1",
439 "i2s2",
440 "dummy",
441 "pll_a_out0",
442 "dummy",
443 "dummy",
444 "dummy",
445};
446
447static struct clk *audio_parents[] = {
448 NULL,
449 NULL,
450 NULL,
451 NULL,
452 NULL,
453 NULL,
454 NULL,
455 NULL,
456};
457
458static struct clk tegra_audio;
459static struct clk_tegra tegra_audio_hw = {
460 .hw = {
461 .clk = &tegra_audio,
462 },
463 .reg = 0x38,
464 .max_rate = 73728000,
465};
466DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
467 audio_parents, NULL);
468
469static const char *audio_2x_parent_names[] = {
470 "audio",
471};
472
473static struct clk *audio_2x_parents[] = {
474 &tegra_audio,
475};
476
477static struct clk tegra_audio_2x;
478static struct clk_tegra tegra_audio_2x_hw = {
479 .hw = {
480 .clk = &tegra_audio_2x,
481 },
482 .flags = PERIPH_NO_RESET,
483 .max_rate = 48000000,
484 .reg = 0x34,
485 .reg_shift = 8,
486 .u.periph = {
487 .clk_num = 89,
488 },
489};
490DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
491 audio_2x_parents, &tegra_audio);
492
493static struct clk_lookup tegra_audio_clk_lookups[] = {
494 { .con_id = "audio", .clk = &tegra_audio },
495 { .con_id = "audio_2x", .clk = &tegra_audio_2x }
496};
497
498/* This is called after peripheral clocks are initialized, as the
499 * audio_sync clock depends on some of the peripheral clocks.
500 */
501
502static void init_audio_sync_clock_mux(void)
503{
504 int i;
505 struct clk_mux_sel *sel = mux_audio_sync_clk;
506 const struct audio_sources *src = mux_audio_sync_clk_sources;
507 struct clk_lookup *lookup;
508
509 for (i = 0; src->name; i++, sel++, src++) {
510 sel->input = tegra_get_clock_by_name(src->name);
511 if (!sel->input)
512 pr_err("%s: could not find clk %s\n", __func__,
513 src->name);
514 audio_parents[src->value] = sel->input;
515 sel->value = src->value;
516 }
517
518 lookup = tegra_audio_clk_lookups;
519 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
520 struct clk *c = lookup->clk;
521 struct clk_tegra *clk = to_clk_tegra(c->hw);
522 __clk_init(NULL, c);
523 INIT_LIST_HEAD(&clk->shared_bus_list);
524 clk->lookup.con_id = lookup->con_id;
525 clk->lookup.clk = c;
526 clkdev_add(&clk->lookup);
527 tegra_clk_add(c);
528 }
529}
530
531static const char *mux_cclk[] = {
532 "clk_m",
533 "pll_c",
534 "clk_32k",
535 "pll_m",
536 "pll_p",
537 "pll_p_out4",
538 "pll_p_out3",
539 "clk_d",
540 "pll_x",
541};
542
543
544static struct clk *mux_cclk_p[] = {
545 &tegra_clk_m,
546 &tegra_pll_c,
547 &tegra_clk_32k,
548 &tegra_pll_m,
549 &tegra_pll_p,
550 &tegra_pll_p_out4,
551 &tegra_pll_p_out3,
552 &tegra_clk_d,
553 &tegra_pll_x,
554};
555
556static const char *mux_sclk[] = {
557 "clk_m",
558 "pll_c_out1",
559 "pll_p_out4",
560 "pllp_p_out3",
561 "pll_p_out2",
562 "clk_d",
563 "clk_32k",
564 "pll_m_out1",
565};
566
567static struct clk *mux_sclk_p[] = {
568 &tegra_clk_m,
569 &tegra_pll_c_out1,
570 &tegra_pll_p_out4,
571 &tegra_pll_p_out3,
572 &tegra_pll_p_out2,
573 &tegra_clk_d,
574 &tegra_clk_32k,
575 &tegra_pll_m_out1,
576};
577
578static struct clk tegra_cclk;
579static struct clk_tegra tegra_cclk_hw = {
580 .hw = {
581 .clk = &tegra_cclk,
582 },
583 .reg = 0x20,
584 .max_rate = 1000000000,
585};
586DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
587 mux_cclk_p, NULL);
588
589static const char *mux_twd[] = {
590 "cclk",
591};
592
593static struct clk *mux_twd_p[] = {
594 &tegra_cclk,
595};
596
597static struct clk tegra_clk_twd;
598static struct clk_tegra tegra_clk_twd_hw = {
599 .hw = {
600 .clk = &tegra_clk_twd,
601 },
602 .max_rate = 1000000000,
603 .mul = 1,
604 .div = 4,
605};
606
607static struct clk tegra_clk_twd = {
608 .name = "twd",
609 .ops = &tegra_twd_ops,
610 .hw = &tegra_clk_twd_hw.hw,
611 .parent = &tegra_cclk,
612 .parent_names = mux_twd,
613 .parents = mux_twd_p,
614 .num_parents = ARRAY_SIZE(mux_twd),
615};
616
617static struct clk tegra_sclk;
618static struct clk_tegra tegra_sclk_hw = {
619 .hw = {
620 .clk = &tegra_sclk,
621 },
622 .reg = 0x28,
623 .max_rate = 240000000,
624 .min_rate = 120000000,
625};
626DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
627 mux_sclk_p, NULL);
628
629static const char *tegra_cop_parent_names[] = {
630 "tegra_sclk",
631};
632
633static struct clk *tegra_cop_parents[] = {
634 &tegra_sclk,
635};
636
637static struct clk tegra_cop;
638static struct clk_tegra tegra_cop_hw = {
639 .hw = {
640 .clk = &tegra_cop,
641 },
642 .max_rate = 240000000,
643 .reset = &tegra2_cop_clk_reset,
644};
645DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
646 tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
647
648static const char *tegra_hclk_parent_names[] = {
649 "tegra_sclk",
650};
651
652static struct clk *tegra_hclk_parents[] = {
653 &tegra_sclk,
654};
655
656static struct clk tegra_hclk;
657static struct clk_tegra tegra_hclk_hw = {
658 .hw = {
659 .clk = &tegra_hclk,
660 },
661 .flags = DIV_BUS,
662 .reg = 0x30,
663 .reg_shift = 4,
664 .max_rate = 240000000,
665};
666DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
667 tegra_hclk_parents, &tegra_sclk);
668
669static const char *tegra_pclk_parent_names[] = {
670 "tegra_hclk",
671};
672
673static struct clk *tegra_pclk_parents[] = {
674 &tegra_hclk,
675};
676
677static struct clk tegra_pclk;
678static struct clk_tegra tegra_pclk_hw = {
679 .hw = {
680 .clk = &tegra_pclk,
681 },
682 .flags = DIV_BUS,
683 .reg = 0x30,
684 .reg_shift = 0,
685 .max_rate = 120000000,
686};
687DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
688 tegra_pclk_parents, &tegra_hclk);
689
690static const char *tegra_blink_parent_names[] = {
691 "clk_32k",
692};
693
694static struct clk *tegra_blink_parents[] = {
695 &tegra_clk_32k,
696};
697
698static struct clk tegra_blink;
699static struct clk_tegra tegra_blink_hw = {
700 .hw = {
701 .clk = &tegra_blink,
702 },
703 .reg = 0x40,
704 .max_rate = 32768,
705};
706DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
707 tegra_blink_parents, &tegra_clk_32k);
708
709static const char *mux_pllm_pllc_pllp_plla[] = {
710 "pll_m",
711 "pll_c",
712 "pll_p",
713 "pll_a_out0",
714};
715
716static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
717 &tegra_pll_m,
718 &tegra_pll_c,
719 &tegra_pll_p,
720 &tegra_pll_a_out0,
721};
722
723static const char *mux_pllm_pllc_pllp_clkm[] = {
724 "pll_m",
725 "pll_c",
726 "pll_p",
727 "clk_m",
728};
729
730static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
731 &tegra_pll_m,
732 &tegra_pll_c,
733 &tegra_pll_p,
734 &tegra_clk_m,
735};
736
737static const char *mux_pllp_pllc_pllm_clkm[] = {
738 "pll_p",
739 "pll_c",
740 "pll_m",
741 "clk_m",
742};
743
744static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
745 &tegra_pll_p,
746 &tegra_pll_c,
747 &tegra_pll_m,
748 &tegra_clk_m,
749};
750
751static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
752 "pll_a_out0",
753 "audio_2x",
754 "pll_p",
755 "clk_m",
756};
757
758static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
759 &tegra_pll_a_out0,
760 &tegra_audio_2x,
761 &tegra_pll_p,
762 &tegra_clk_m,
763};
764
765static const char *mux_pllp_plld_pllc_clkm[] = {
766 "pllp",
767 "pll_d_out0",
768 "pll_c",
769 "clk_m",
770};
771
772static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
773 &tegra_pll_p,
774 &tegra_pll_d_out0,
775 &tegra_pll_c,
776 &tegra_clk_m,
777};
778
779static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
780 "pll_p",
781 "pll_c",
782 "audio",
783 "clk_m",
784 "clk_32k",
785};
786
787static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
788 &tegra_pll_p,
789 &tegra_pll_c,
790 &tegra_audio,
791 &tegra_clk_m,
792 &tegra_clk_32k,
793};
794
795static const char *mux_pllp_pllc_pllm[] = {
796 "pll_p",
797 "pll_c",
798 "pll_m"
799};
800
801static struct clk *mux_pllp_pllc_pllm_p[] = {
802 &tegra_pll_p,
803 &tegra_pll_c,
804 &tegra_pll_m,
805};
806
807static const char *mux_clk_m[] = {
808 "clk_m",
809};
810
811static struct clk *mux_clk_m_p[] = {
812 &tegra_clk_m,
813};
814
815static const char *mux_pllp_out3[] = {
816 "pll_p_out3",
817};
818
819static struct clk *mux_pllp_out3_p[] = {
820 &tegra_pll_p_out3,
821};
822
823static const char *mux_plld[] = {
824 "pll_d",
825};
826
827static struct clk *mux_plld_p[] = {
828 &tegra_pll_d,
829};
830
831static const char *mux_clk_32k[] = {
832 "clk_32k",
833};
834
835static struct clk *mux_clk_32k_p[] = {
836 &tegra_clk_32k,
837};
838
839static const char *mux_pclk[] = {
840 "pclk",
841};
842
843static struct clk *mux_pclk_p[] = {
844 &tegra_pclk,
845};
846
847static struct clk tegra_emc;
848static struct clk_tegra tegra_emc_hw = {
849 .hw = {
850 .clk = &tegra_emc,
851 },
852 .reg = 0x19c,
853 .max_rate = 800000000,
854 .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
855 .reset = &tegra2_periph_clk_reset,
856 .u.periph = {
857 .clk_num = 57,
858 },
859};
860DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
861 mux_pllm_pllc_pllp_clkm_p, NULL);
862
863#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
864 _max, _inputs, _flags) \
865 static struct clk tegra_##_name; \
866 static struct clk_tegra tegra_##_name##_hw = { \
867 .hw = { \
868 .clk = &tegra_##_name, \
869 }, \
870 .lookup = { \
871 .dev_id = _dev, \
872 .con_id = _con, \
873 }, \
874 .reg = _reg, \
875 .flags = _flags, \
876 .max_rate = _max, \
877 .u.periph = { \
878 .clk_num = _clk_num, \
879 }, \
880 .reset = tegra2_periph_clk_reset, \
881 }; \
882 static struct clk tegra_##_name = { \
883 .name = #_name, \
884 .ops = &tegra_periph_clk_ops, \
885 .hw = &tegra_##_name##_hw.hw, \
886 .parent_names = _inputs, \
887 .parents = _inputs##_p, \
888 .num_parents = ARRAY_SIZE(_inputs), \
889 };
890
891PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
892PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
893PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
894PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
895PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
896PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
897PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
898PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
899PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
900PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
901PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
902PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
903PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
904PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
905PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
906PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
907PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
908PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
909PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
910PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
911PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
912PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
913PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
914PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
915PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
916PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
917PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
918/* FIXME: what is la? */
919PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
920PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
921PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
922PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
923PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
924PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
925PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
926PERIPH_CLK(dvc, "tegra-i2c.3", "div-clk", 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
927PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
928PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
929PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
930PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
931PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
932PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
933PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
934PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
935PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
936PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
937PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
938PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
939PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
940PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
941PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
942PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
943PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
944PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
945PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
946PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
947PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
948PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
949PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
950PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
951PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
952PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
953PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
954PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
955
956static struct clk *tegra_list_clks[] = {
957 &tegra_apbdma,
958 &tegra_rtc,
959 &tegra_timer,
960 &tegra_i2s1,
961 &tegra_i2s2,
962 &tegra_spdif_out,
963 &tegra_spdif_in,
964 &tegra_pwm,
965 &tegra_spi,
966 &tegra_xio,
967 &tegra_twc,
968 &tegra_sbc1,
969 &tegra_sbc2,
970 &tegra_sbc3,
971 &tegra_sbc4,
972 &tegra_ide,
973 &tegra_ndflash,
974 &tegra_vfir,
975 &tegra_sdmmc1,
976 &tegra_sdmmc2,
977 &tegra_sdmmc3,
978 &tegra_sdmmc4,
979 &tegra_vcp,
980 &tegra_bsea,
981 &tegra_bsev,
982 &tegra_vde,
983 &tegra_csite,
984 &tegra_la,
985 &tegra_owr,
986 &tegra_nor,
987 &tegra_mipi,
988 &tegra_i2c1,
989 &tegra_i2c2,
990 &tegra_i2c3,
991 &tegra_dvc,
992 &tegra_uarta,
993 &tegra_uartb,
994 &tegra_uartc,
995 &tegra_uartd,
996 &tegra_uarte,
997 &tegra_3d,
998 &tegra_2d,
999 &tegra_vi,
1000 &tegra_vi_sensor,
1001 &tegra_epp,
1002 &tegra_mpe,
1003 &tegra_host1x,
1004 &tegra_cve,
1005 &tegra_tvo,
1006 &tegra_hdmi,
1007 &tegra_tvdac,
1008 &tegra_disp1,
1009 &tegra_disp2,
1010 &tegra_usbd,
1011 &tegra_usb2,
1012 &tegra_usb3,
1013 &tegra_dsi,
1014 &tegra_csi,
1015 &tegra_isp,
1016 &tegra_csus,
1017 &tegra_pex,
1018 &tegra_afi,
1019 &tegra_pcie_xclk,
1020};
1021
1022#define CLK_DUPLICATE(_name, _dev, _con) \
1023 { \
1024 .name = _name, \
1025 .lookup = { \
1026 .dev_id = _dev, \
1027 .con_id = _con, \
1028 }, \
1029 }
1030
1031/* Some clocks may be used by different drivers depending on the board
1032 * configuration. List those here to register them twice in the clock lookup
1033 * table under two names.
1034 */
1035static struct clk_duplicate tegra_clk_duplicates[] = {
1036 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1037 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1038 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1039 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1040 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1041 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1042 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1043 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1044 CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
1045 CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
1046 CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
1047 CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
1048 CLK_DUPLICATE("cop", "tegra-avp", "cop"),
1049 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1050 CLK_DUPLICATE("cclk", NULL, "cpu"),
1051 CLK_DUPLICATE("twd", "smp_twd", NULL),
1052 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1053 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1054 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1055 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1056 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1057 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1058 CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
1059};
1060
1061#define CLK(dev, con, ck) \
1062 { \
1063 .dev_id = dev, \
1064 .con_id = con, \
1065 .clk = ck, \
1066 }
1067
1068static struct clk *tegra_ptr_clks[] = {
1069 &tegra_clk_32k,
1070 &tegra_pll_s,
1071 &tegra_clk_m,
1072 &tegra_pll_m,
1073 &tegra_pll_m_out1,
1074 &tegra_pll_c,
1075 &tegra_pll_c_out1,
1076 &tegra_pll_p,
1077 &tegra_pll_p_out1,
1078 &tegra_pll_p_out2,
1079 &tegra_pll_p_out3,
1080 &tegra_pll_p_out4,
1081 &tegra_pll_a,
1082 &tegra_pll_a_out0,
1083 &tegra_pll_d,
1084 &tegra_pll_d_out0,
1085 &tegra_pll_u,
1086 &tegra_pll_x,
1087 &tegra_pll_e,
1088 &tegra_cclk,
1089 &tegra_clk_twd,
1090 &tegra_sclk,
1091 &tegra_hclk,
1092 &tegra_pclk,
1093 &tegra_clk_d,
1094 &tegra_cdev1,
1095 &tegra_cdev2,
1096 &tegra_blink,
1097 &tegra_cop,
1098 &tegra_emc,
1099};
1100
1101static void tegra2_init_one_clock(struct clk *c)
1102{
1103 struct clk_tegra *clk = to_clk_tegra(c->hw);
1104 int ret;
1105
1106 ret = __clk_init(NULL, c);
1107 if (ret)
1108 pr_err("clk init failed %s\n", __clk_get_name(c));
1109
1110 INIT_LIST_HEAD(&clk->shared_bus_list);
1111 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1112 clk->lookup.con_id = c->name;
1113 clk->lookup.clk = c;
1114 clkdev_add(&clk->lookup);
1115 tegra_clk_add(c);
1116}
1117
1118void __init tegra2_init_clocks(void)
1119{
1120 int i;
1121 struct clk *c;
1122
1123 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1124 tegra2_init_one_clock(tegra_ptr_clks[i]);
1125
1126 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1127 tegra2_init_one_clock(tegra_list_clks[i]);
1128
1129 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1130 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1131 if (!c) {
1132 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1133 tegra_clk_duplicates[i].name);
1134 continue;
1135 }
1136
1137 tegra_clk_duplicates[i].lookup.clk = c;
1138 clkdev_add(&tegra_clk_duplicates[i].lookup);
1139 }
1140
1141 init_audio_sync_clock_mux();
1142 tegra20_cpu_car_ops_init();
1143}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
deleted file mode 100644
index 4330787fe5cb..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ /dev/null
@@ -1,2506 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/list.h>
24#include <linux/spinlock.h>
25#include <linux/delay.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/clk.h>
29#include <linux/cpufreq.h>
30#include <linux/syscore_ops.h>
31#include <linux/clk/tegra.h>
32
33#include <asm/clkdev.h>
34
35#include <mach/powergate.h>
36
37#include "clock.h"
38#include "fuse.h"
39#include "iomap.h"
40
41#define USE_PLL_LOCK_BITS 0
42
43#define RST_DEVICES_L 0x004
44#define RST_DEVICES_H 0x008
45#define RST_DEVICES_U 0x00C
46#define RST_DEVICES_V 0x358
47#define RST_DEVICES_W 0x35C
48#define RST_DEVICES_SET_L 0x300
49#define RST_DEVICES_CLR_L 0x304
50#define RST_DEVICES_SET_V 0x430
51#define RST_DEVICES_CLR_V 0x434
52#define RST_DEVICES_NUM 5
53
54#define CLK_OUT_ENB_L 0x010
55#define CLK_OUT_ENB_H 0x014
56#define CLK_OUT_ENB_U 0x018
57#define CLK_OUT_ENB_V 0x360
58#define CLK_OUT_ENB_W 0x364
59#define CLK_OUT_ENB_SET_L 0x320
60#define CLK_OUT_ENB_CLR_L 0x324
61#define CLK_OUT_ENB_SET_V 0x440
62#define CLK_OUT_ENB_CLR_V 0x444
63#define CLK_OUT_ENB_NUM 5
64
65#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)
66#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)
67
68#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))
69#define PERIPH_CLK_TO_RST_REG(c) \
70 periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)
71#define PERIPH_CLK_TO_RST_SET_REG(c) \
72 periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)
73#define PERIPH_CLK_TO_RST_CLR_REG(c) \
74 periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)
75
76#define PERIPH_CLK_TO_ENB_REG(c) \
77 periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)
78#define PERIPH_CLK_TO_ENB_SET_REG(c) \
79 periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)
80#define PERIPH_CLK_TO_ENB_CLR_REG(c) \
81 periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)
82
83#define CLK_MASK_ARM 0x44
84#define MISC_CLK_ENB 0x48
85
86#define OSC_CTRL 0x50
87#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
88#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)
89#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)
90#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)
91#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)
92#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)
93#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)
94#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)
95#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
96
97#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
98#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
99#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
100#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
101
102#define OSC_FREQ_DET 0x58
103#define OSC_FREQ_DET_TRIG (1<<31)
104
105#define OSC_FREQ_DET_STATUS 0x5C
106#define OSC_FREQ_DET_BUSY (1<<31)
107#define OSC_FREQ_DET_CNT_MASK 0xFFFF
108
109#define PERIPH_CLK_SOURCE_I2S1 0x100
110#define PERIPH_CLK_SOURCE_EMC 0x19c
111#define PERIPH_CLK_SOURCE_OSC 0x1fc
112#define PERIPH_CLK_SOURCE_NUM1 \
113 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
114
115#define PERIPH_CLK_SOURCE_G3D2 0x3b0
116#define PERIPH_CLK_SOURCE_SE 0x42c
117#define PERIPH_CLK_SOURCE_NUM2 \
118 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)
119
120#define AUDIO_DLY_CLK 0x49c
121#define AUDIO_SYNC_CLK_SPDIF 0x4b4
122#define PERIPH_CLK_SOURCE_NUM3 \
123 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)
124
125#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \
126 PERIPH_CLK_SOURCE_NUM2 + \
127 PERIPH_CLK_SOURCE_NUM3)
128
129#define CPU_SOFTRST_CTRL 0x380
130
131#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
132#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
133#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
134#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8
135#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50
136#define PERIPH_CLK_UART_DIV_ENB (1<<24)
137#define PERIPH_CLK_VI_SEL_EX_SHIFT 24
138#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)
139#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)
140#define PERIPH_CLK_DTV_POLARITY_INV (1<<25)
141
142#define AUDIO_SYNC_SOURCE_MASK 0x0F
143#define AUDIO_SYNC_DISABLE_BIT 0x10
144#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)
145
146#define PLL_BASE 0x0
147#define PLL_BASE_BYPASS (1<<31)
148#define PLL_BASE_ENABLE (1<<30)
149#define PLL_BASE_REF_ENABLE (1<<29)
150#define PLL_BASE_OVERRIDE (1<<28)
151#define PLL_BASE_LOCK (1<<27)
152#define PLL_BASE_DIVP_MASK (0x7<<20)
153#define PLL_BASE_DIVP_SHIFT 20
154#define PLL_BASE_DIVN_MASK (0x3FF<<8)
155#define PLL_BASE_DIVN_SHIFT 8
156#define PLL_BASE_DIVM_MASK (0x1F)
157#define PLL_BASE_DIVM_SHIFT 0
158
159#define PLL_OUT_RATIO_MASK (0xFF<<8)
160#define PLL_OUT_RATIO_SHIFT 8
161#define PLL_OUT_OVERRIDE (1<<2)
162#define PLL_OUT_CLKEN (1<<1)
163#define PLL_OUT_RESET_DISABLE (1<<0)
164
165#define PLL_MISC(c) \
166 (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
167#define PLL_MISC_LOCK_ENABLE(c) \
168 (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))
169
170#define PLL_MISC_DCCON_SHIFT 20
171#define PLL_MISC_CPCON_SHIFT 8
172#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
173#define PLL_MISC_LFCON_SHIFT 4
174#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
175#define PLL_MISC_VCOCON_SHIFT 0
176#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
177#define PLLD_MISC_CLKENABLE (1<<30)
178
179#define PLLU_BASE_POST_DIV (1<<20)
180
181#define PLLD_BASE_DSIB_MUX_SHIFT 25
182#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)
183#define PLLD_BASE_CSI_CLKENABLE (1<<26)
184#define PLLD_MISC_DSI_CLKENABLE (1<<30)
185#define PLLD_MISC_DIV_RST (1<<23)
186#define PLLD_MISC_DCCON_SHIFT 12
187
188#define PLLDU_LFCON_SET_DIVN 600
189
190/* FIXME: OUT_OF_TABLE_CPCON per pll */
191#define OUT_OF_TABLE_CPCON 0x8
192
193#define SUPER_CLK_MUX 0x00
194#define SUPER_STATE_SHIFT 28
195#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
196#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
197#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
198#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
199#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
200#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
201#define SUPER_LP_DIV2_BYPASS (0x1 << 16)
202#define SUPER_SOURCE_MASK 0xF
203#define SUPER_FIQ_SOURCE_SHIFT 12
204#define SUPER_IRQ_SOURCE_SHIFT 8
205#define SUPER_RUN_SOURCE_SHIFT 4
206#define SUPER_IDLE_SOURCE_SHIFT 0
207
208#define SUPER_CLK_DIVIDER 0x04
209#define SUPER_CLOCK_DIV_U71_SHIFT 16
210#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)
211/* guarantees safe cpu backup */
212#define SUPER_CLOCK_DIV_U71_MIN 0x2
213
214#define BUS_CLK_DISABLE (1<<3)
215#define BUS_CLK_DIV_MASK 0x3
216
217#define PMC_CTRL 0x0
218 #define PMC_CTRL_BLINK_ENB (1 << 7)
219
220#define PMC_DPD_PADS_ORIDE 0x1c
221 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
222
223#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
224#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
225#define PMC_BLINK_TIMER_ENB (1 << 15)
226#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
227#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
228
229#define PMC_PLLP_WB0_OVERRIDE 0xf8
230#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)
231
232#define UTMIP_PLL_CFG2 0x488
233#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
234#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
235#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
236#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
237#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
238
239#define UTMIP_PLL_CFG1 0x484
240#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
241#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
242#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)
243#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)
244#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)
245
246#define PLLE_BASE_CML_ENABLE (1<<31)
247#define PLLE_BASE_ENABLE (1<<30)
248#define PLLE_BASE_DIVCML_SHIFT 24
249#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)
250#define PLLE_BASE_DIVP_SHIFT 16
251#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)
252#define PLLE_BASE_DIVN_SHIFT 8
253#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)
254#define PLLE_BASE_DIVM_SHIFT 0
255#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)
256#define PLLE_BASE_DIV_MASK \
257 (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \
258 PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)
259#define PLLE_BASE_DIV(m, n, p, cml) \
260 (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \
261 ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))
262
263#define PLLE_MISC_SETUP_BASE_SHIFT 16
264#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)
265#define PLLE_MISC_READY (1<<15)
266#define PLLE_MISC_LOCK (1<<11)
267#define PLLE_MISC_LOCK_ENABLE (1<<9)
268#define PLLE_MISC_SETUP_EX_SHIFT 2
269#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)
270#define PLLE_MISC_SETUP_MASK \
271 (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)
272#define PLLE_MISC_SETUP_VALUE \
273 ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))
274
275#define PLLE_SS_CTRL 0x68
276#define PLLE_SS_INCINTRV_SHIFT 24
277#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)
278#define PLLE_SS_INC_SHIFT 16
279#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)
280#define PLLE_SS_MAX_SHIFT 0
281#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)
282#define PLLE_SS_COEFFICIENTS_MASK \
283 (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)
284#define PLLE_SS_COEFFICIENTS_12MHZ \
285 ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \
286 (0x24<<PLLE_SS_MAX_SHIFT))
287#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))
288
289#define PLLE_AUX 0x48c
290#define PLLE_AUX_PLLP_SEL (1<<2)
291#define PLLE_AUX_CML_SATA_ENABLE (1<<1)
292#define PLLE_AUX_CML_PCIE_ENABLE (1<<0)
293
294#define PMC_SATA_PWRGT 0x1ac
295#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)
296#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)
297
298#define ROUND_DIVIDER_UP 0
299#define ROUND_DIVIDER_DOWN 1
300
301/* FIXME: recommended safety delay after lock is detected */
302#define PLL_POST_LOCK_DELAY 100
303
304/* Tegra CPU clock and reset control regs */
305#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
306#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
307#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
308#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
309#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
310
311#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
312#define CPU_RESET(cpu) (0x1111ul << (cpu))
313
314#define CLK_RESET_CCLK_BURST 0x20
315#define CLK_RESET_CCLK_DIVIDER 0x24
316#define CLK_RESET_PLLX_BASE 0xe0
317#define CLK_RESET_PLLX_MISC 0xe4
318
319#define CLK_RESET_SOURCE_CSITE 0x1d4
320
321#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
322#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
323#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
324#define CLK_RESET_CCLK_IDLE_POLICY 1
325#define CLK_RESET_CCLK_RUN_POLICY 2
326#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
327
328#ifdef CONFIG_PM_SLEEP
329static struct cpu_clk_suspend_context {
330 u32 pllx_misc;
331 u32 pllx_base;
332
333 u32 cpu_burst;
334 u32 clk_csite_src;
335 u32 cclk_divider;
336} tegra30_cpu_clk_sctx;
337#endif
338
339/**
340* Structure defining the fields for USB UTMI clocks Parameters.
341*/
342struct utmi_clk_param {
343 /* Oscillator Frequency in KHz */
344 u32 osc_frequency;
345 /* UTMIP PLL Enable Delay Count */
346 u8 enable_delay_count;
347 /* UTMIP PLL Stable count */
348 u8 stable_count;
349 /* UTMIP PLL Active delay count */
350 u8 active_delay_count;
351 /* UTMIP PLL Xtal frequency count */
352 u8 xtal_freq_count;
353};
354
355static const struct utmi_clk_param utmi_parameters[] = {
356 {
357 .osc_frequency = 13000000,
358 .enable_delay_count = 0x02,
359 .stable_count = 0x33,
360 .active_delay_count = 0x05,
361 .xtal_freq_count = 0x7F
362 },
363 {
364 .osc_frequency = 19200000,
365 .enable_delay_count = 0x03,
366 .stable_count = 0x4B,
367 .active_delay_count = 0x06,
368 .xtal_freq_count = 0xBB},
369 {
370 .osc_frequency = 12000000,
371 .enable_delay_count = 0x02,
372 .stable_count = 0x2F,
373 .active_delay_count = 0x04,
374 .xtal_freq_count = 0x76
375 },
376 {
377 .osc_frequency = 26000000,
378 .enable_delay_count = 0x04,
379 .stable_count = 0x66,
380 .active_delay_count = 0x09,
381 .xtal_freq_count = 0xFE
382 },
383 {
384 .osc_frequency = 16800000,
385 .enable_delay_count = 0x03,
386 .stable_count = 0x41,
387 .active_delay_count = 0x0A,
388 .xtal_freq_count = 0xA4
389 },
390};
391
392static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
393static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
394static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
395
396#define MISC_GP_HIDREV 0x804
397
398/*
399 * Some peripheral clocks share an enable bit, so refcount the enable bits
400 * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
401 */
402static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
403
404#define clk_writel(value, reg) \
405 __raw_writel(value, reg_clk_base + (reg))
406#define clk_readl(reg) \
407 __raw_readl(reg_clk_base + (reg))
408#define pmc_writel(value, reg) \
409 __raw_writel(value, reg_pmc_base + (reg))
410#define pmc_readl(reg) \
411 __raw_readl(reg_pmc_base + (reg))
412#define chipid_readl() \
413 __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
414
415#define clk_writel_delay(value, reg) \
416 do { \
417 __raw_writel((value), reg_clk_base + (reg)); \
418 udelay(2); \
419 } while (0)
420
421static inline int clk_set_div(struct clk_tegra *c, u32 n)
422{
423 struct clk *clk = c->hw.clk;
424
425 return clk_set_rate(clk,
426 (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
427}
428
429static inline u32 periph_clk_to_reg(
430 struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
431{
432 u32 reg = c->u.periph.clk_num / 32;
433 BUG_ON(reg >= RST_DEVICES_NUM);
434 if (reg < 3)
435 reg = reg_L + (reg * offs);
436 else
437 reg = reg_V + ((reg - 3) * offs);
438 return reg;
439}
440
441static unsigned long clk_measure_input_freq(void)
442{
443 u32 clock_autodetect;
444 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
445 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
446 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
447 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
448 return 12000000;
449 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
450 return 13000000;
451 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
452 return 19200000;
453 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
454 return 26000000;
455 } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) {
456 return 16800000;
457 } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) {
458 return 38400000;
459 } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) {
460 return 48000000;
461 } else {
462 pr_err("%s: Unexpected clock autodetect value %d", __func__,
463 clock_autodetect);
464 BUG();
465 return 0;
466 }
467}
468
469static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate,
470 u32 flags, u32 round_mode)
471{
472 s64 divider_u71 = parent_rate;
473 if (!rate)
474 return -EINVAL;
475
476 if (!(flags & DIV_U71_INT))
477 divider_u71 *= 2;
478 if (round_mode == ROUND_DIVIDER_UP)
479 divider_u71 += rate - 1;
480 do_div(divider_u71, rate);
481 if (flags & DIV_U71_INT)
482 divider_u71 *= 2;
483
484 if (divider_u71 - 2 < 0)
485 return 0;
486
487 if (divider_u71 - 2 > 255)
488 return -EINVAL;
489
490 return divider_u71 - 2;
491}
492
493static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
494{
495 s64 divider_u16;
496
497 divider_u16 = parent_rate;
498 if (!rate)
499 return -EINVAL;
500 divider_u16 += rate - 1;
501 do_div(divider_u16, rate);
502
503 if (divider_u16 - 1 < 0)
504 return 0;
505
506 if (divider_u16 - 1 > 0xFFFF)
507 return -EINVAL;
508
509 return divider_u16 - 1;
510}
511
512static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
513 unsigned long parent_rate)
514{
515 return to_clk_tegra(hw)->fixed_rate;
516}
517
518struct clk_ops tegra30_clk_32k_ops = {
519 .recalc_rate = tegra30_clk_fixed_recalc_rate,
520};
521
522/* clk_m functions */
523static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
524 unsigned long parent_rate)
525{
526 if (!to_clk_tegra(hw)->fixed_rate)
527 to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
528 return to_clk_tegra(hw)->fixed_rate;
529}
530
531static void tegra30_clk_m_init(struct clk_hw *hw)
532{
533 u32 osc_ctrl = clk_readl(OSC_CTRL);
534 u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
535 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
536
537 switch (to_clk_tegra(hw)->fixed_rate) {
538 case 12000000:
539 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
540 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
541 break;
542 case 13000000:
543 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
544 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
545 break;
546 case 19200000:
547 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
548 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
549 break;
550 case 26000000:
551 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
552 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
553 break;
554 case 16800000:
555 auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ;
556 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
557 break;
558 case 38400000:
559 auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ;
560 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2);
561 break;
562 case 48000000:
563 auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ;
564 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
565 break;
566 default:
567 pr_err("%s: Unexpected clock rate %ld", __func__,
568 to_clk_tegra(hw)->fixed_rate);
569 BUG();
570 }
571 clk_writel(auto_clock_control, OSC_CTRL);
572}
573
574struct clk_ops tegra30_clk_m_ops = {
575 .init = tegra30_clk_m_init,
576 .recalc_rate = tegra30_clk_m_recalc_rate,
577};
578
579static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
580 unsigned long parent_rate)
581{
582 struct clk_tegra *c = to_clk_tegra(hw);
583 u64 rate = parent_rate;
584
585 if (c->mul != 0 && c->div != 0) {
586 rate *= c->mul;
587 rate += c->div - 1; /* round up */
588 do_div(rate, c->div);
589 }
590
591 return rate;
592}
593
594struct clk_ops tegra_clk_m_div_ops = {
595 .recalc_rate = tegra30_clk_m_div_recalc_rate,
596};
597
598/* PLL reference divider functions */
599static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
600 unsigned long parent_rate)
601{
602 struct clk_tegra *c = to_clk_tegra(hw);
603 unsigned long rate = parent_rate;
604 u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
605
606 switch (pll_ref_div) {
607 case OSC_CTRL_PLL_REF_DIV_1:
608 c->div = 1;
609 break;
610 case OSC_CTRL_PLL_REF_DIV_2:
611 c->div = 2;
612 break;
613 case OSC_CTRL_PLL_REF_DIV_4:
614 c->div = 4;
615 break;
616 default:
617 pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div);
618 BUG();
619 }
620 c->mul = 1;
621
622 if (c->mul != 0 && c->div != 0) {
623 rate *= c->mul;
624 rate += c->div - 1; /* round up */
625 do_div(rate, c->div);
626 }
627
628 return rate;
629}
630
631struct clk_ops tegra_pll_ref_ops = {
632 .recalc_rate = tegra30_pll_ref_recalc_rate,
633};
634
635/* super clock functions */
636/* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and
637 * clock skipping super divider. We will ignore the clock skipping divider,
638 * since we can't lower the voltage when using the clock skip, but we can if
639 * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock
640 * only when its parent is a fixed rate PLL, since we can't change PLL rate
641 * in this case.
642 */
643static void tegra30_super_clk_init(struct clk_hw *hw)
644{
645 struct clk_tegra *c = to_clk_tegra(hw);
646 struct clk_tegra *p =
647 to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
648
649 c->state = ON;
650 if (c->flags & DIV_U71) {
651 /* Init safe 7.1 divider value (does not affect PLLX path) */
652 clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
653 c->reg + SUPER_CLK_DIVIDER);
654 c->mul = 2;
655 c->div = 2;
656 if (!(p->flags & PLLX))
657 c->div += SUPER_CLOCK_DIV_U71_MIN;
658 } else
659 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
660}
661
662static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
663{
664 struct clk_tegra *c = to_clk_tegra(hw);
665 u32 val;
666 int source;
667 int shift;
668
669 val = clk_readl(c->reg + SUPER_CLK_MUX);
670 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
671 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
672 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
673 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
674 source = (val >> shift) & SUPER_SOURCE_MASK;
675 if (c->flags & DIV_2)
676 source |= val & SUPER_LP_DIV2_BYPASS;
677
678 return source;
679}
680
681static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
682{
683 struct clk_tegra *c = to_clk_tegra(hw);
684 struct clk_tegra *p =
685 to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
686 u32 val;
687 int shift;
688
689 val = clk_readl(c->reg + SUPER_CLK_MUX);
690 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
691 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
692 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
693 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
694
695 /* For LP mode super-clock switch between PLLX direct
696 and divided-by-2 outputs is allowed only when other
697 than PLLX clock source is current parent */
698 if ((c->flags & DIV_2) && (p->flags & PLLX) &&
699 ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
700 if (p->flags & PLLX)
701 return -EINVAL;
702 val ^= SUPER_LP_DIV2_BYPASS;
703 clk_writel_delay(val, c->reg);
704 }
705 val &= ~(SUPER_SOURCE_MASK << shift);
706 val |= (index & SUPER_SOURCE_MASK) << shift;
707
708 /* 7.1 divider for CPU super-clock does not affect
709 PLLX path */
710 if (c->flags & DIV_U71) {
711 u32 div = 0;
712 if (!(p->flags & PLLX)) {
713 div = clk_readl(c->reg +
714 SUPER_CLK_DIVIDER);
715 div &= SUPER_CLOCK_DIV_U71_MASK;
716 div >>= SUPER_CLOCK_DIV_U71_SHIFT;
717 }
718 c->div = div + 2;
719 c->mul = 2;
720 }
721 clk_writel_delay(val, c->reg);
722
723 return 0;
724}
725
726/*
727 * Do not use super clocks "skippers", since dividing using a clock skipper
728 * does not allow the voltage to be scaled down. Instead adjust the rate of
729 * the parent clock. This requires that the parent of a super clock have no
730 * other children, otherwise the rate will change underneath the other
731 * children. Special case: if fixed rate PLL is CPU super clock parent the
732 * rate of this PLL can't be changed, and it has many other children. In
733 * this case use 7.1 fractional divider to adjust the super clock rate.
734 */
735static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
736 unsigned long parent_rate)
737{
738 struct clk_tegra *c = to_clk_tegra(hw);
739 struct clk *parent = __clk_get_parent(hw->clk);
740 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
741
742 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
743 int div = clk_div71_get_divider(parent_rate,
744 rate, c->flags, ROUND_DIVIDER_DOWN);
745 div = max(div, SUPER_CLOCK_DIV_U71_MIN);
746
747 clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT,
748 c->reg + SUPER_CLK_DIVIDER);
749 c->div = div + 2;
750 c->mul = 2;
751 return 0;
752 }
753 return 0;
754}
755
756static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
757 unsigned long parent_rate)
758{
759 struct clk_tegra *c = to_clk_tegra(hw);
760 u64 rate = parent_rate;
761
762 if (c->mul != 0 && c->div != 0) {
763 rate *= c->mul;
764 rate += c->div - 1; /* round up */
765 do_div(rate, c->div);
766 }
767
768 return rate;
769}
770
771static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
772 unsigned long *prate)
773{
774 struct clk_tegra *c = to_clk_tegra(hw);
775 struct clk *parent = __clk_get_parent(hw->clk);
776 struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
777 int mul = 2;
778 int div;
779
780 if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
781 div = clk_div71_get_divider(*prate,
782 rate, c->flags, ROUND_DIVIDER_DOWN);
783 div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
784 rate = *prate * mul;
785 rate += div - 1; /* round up */
786 do_div(rate, c->div);
787
788 return rate;
789 }
790 return *prate;
791}
792
793struct clk_ops tegra30_super_ops = {
794 .init = tegra30_super_clk_init,
795 .set_parent = tegra30_super_clk_set_parent,
796 .get_parent = tegra30_super_clk_get_parent,
797 .recalc_rate = tegra30_super_clk_recalc_rate,
798 .round_rate = tegra30_super_clk_round_rate,
799 .set_rate = tegra30_super_clk_set_rate,
800};
801
802static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
803 unsigned long parent_rate)
804{
805 struct clk_tegra *c = to_clk_tegra(hw);
806 u64 rate = parent_rate;
807
808 if (c->mul != 0 && c->div != 0) {
809 rate *= c->mul;
810 rate += c->div - 1; /* round up */
811 do_div(rate, c->div);
812 }
813
814 return rate;
815}
816
817struct clk_ops tegra30_twd_ops = {
818 .recalc_rate = tegra30_twd_clk_recalc_rate,
819};
820
821/* bus clock functions */
822static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
823{
824 struct clk_tegra *c = to_clk_tegra(hw);
825 u32 val = clk_readl(c->reg);
826
827 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
828 return c->state;
829}
830
831static int tegra30_bus_clk_enable(struct clk_hw *hw)
832{
833 struct clk_tegra *c = to_clk_tegra(hw);
834 u32 val;
835
836 val = clk_readl(c->reg);
837 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
838 clk_writel(val, c->reg);
839
840 return 0;
841}
842
843static void tegra30_bus_clk_disable(struct clk_hw *hw)
844{
845 struct clk_tegra *c = to_clk_tegra(hw);
846 u32 val;
847
848 val = clk_readl(c->reg);
849 val |= BUS_CLK_DISABLE << c->reg_shift;
850 clk_writel(val, c->reg);
851}
852
853static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
854 unsigned long prate)
855{
856 struct clk_tegra *c = to_clk_tegra(hw);
857 u32 val = clk_readl(c->reg);
858 u64 rate = prate;
859
860 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
861 c->mul = 1;
862
863 if (c->mul != 0 && c->div != 0) {
864 rate *= c->mul;
865 rate += c->div - 1; /* round up */
866 do_div(rate, c->div);
867 }
868 return rate;
869}
870
871static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
872 unsigned long parent_rate)
873{
874 struct clk_tegra *c = to_clk_tegra(hw);
875 int ret = -EINVAL;
876 u32 val;
877 int i;
878
879 val = clk_readl(c->reg);
880 for (i = 1; i <= 4; i++) {
881 if (rate == parent_rate / i) {
882 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
883 val |= (i - 1) << c->reg_shift;
884 clk_writel(val, c->reg);
885 c->div = i;
886 c->mul = 1;
887 ret = 0;
888 break;
889 }
890 }
891
892 return ret;
893}
894
895static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
896 unsigned long *prate)
897{
898 unsigned long parent_rate = *prate;
899 s64 divider;
900
901 if (rate >= parent_rate)
902 return parent_rate;
903
904 divider = parent_rate;
905 divider += rate - 1;
906 do_div(divider, rate);
907
908 if (divider < 0)
909 return divider;
910
911 if (divider > 4)
912 divider = 4;
913 do_div(parent_rate, divider);
914
915 return parent_rate;
916}
917
918struct clk_ops tegra30_bus_ops = {
919 .is_enabled = tegra30_bus_clk_is_enabled,
920 .enable = tegra30_bus_clk_enable,
921 .disable = tegra30_bus_clk_disable,
922 .set_rate = tegra30_bus_clk_set_rate,
923 .round_rate = tegra30_bus_clk_round_rate,
924 .recalc_rate = tegra30_bus_clk_recalc_rate,
925};
926
927/* Blink output functions */
928static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
929{
930 struct clk_tegra *c = to_clk_tegra(hw);
931 u32 val;
932
933 val = pmc_readl(PMC_CTRL);
934 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
935 return c->state;
936}
937
938static int tegra30_blink_clk_enable(struct clk_hw *hw)
939{
940 u32 val;
941
942 val = pmc_readl(PMC_DPD_PADS_ORIDE);
943 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
944
945 val = pmc_readl(PMC_CTRL);
946 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
947
948 return 0;
949}
950
951static void tegra30_blink_clk_disable(struct clk_hw *hw)
952{
953 u32 val;
954
955 val = pmc_readl(PMC_CTRL);
956 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
957
958 val = pmc_readl(PMC_DPD_PADS_ORIDE);
959 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
960}
961
962static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
963 unsigned long parent_rate)
964{
965 struct clk_tegra *c = to_clk_tegra(hw);
966
967 if (rate >= parent_rate) {
968 c->div = 1;
969 pmc_writel(0, c->reg);
970 } else {
971 unsigned int on_off;
972 u32 val;
973
974 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
975 c->div = on_off * 8;
976
977 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
978 PMC_BLINK_TIMER_DATA_ON_SHIFT;
979 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
980 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
981 val |= on_off;
982 val |= PMC_BLINK_TIMER_ENB;
983 pmc_writel(val, c->reg);
984 }
985
986 return 0;
987}
988
989static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
990 unsigned long parent_rate)
991{
992 struct clk_tegra *c = to_clk_tegra(hw);
993 u64 rate = parent_rate;
994 u32 val;
995 u32 mul;
996 u32 div;
997 u32 on_off;
998
999 mul = 1;
1000 val = pmc_readl(c->reg);
1001
1002 if (val & PMC_BLINK_TIMER_ENB) {
1003 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
1004 PMC_BLINK_TIMER_DATA_ON_MASK;
1005 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
1006 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
1007 on_off += val;
1008 /* each tick in the blink timer is 4 32KHz clocks */
1009 div = on_off * 4;
1010 } else {
1011 div = 1;
1012 }
1013
1014 if (mul != 0 && div != 0) {
1015 rate *= mul;
1016 rate += div - 1; /* round up */
1017 do_div(rate, div);
1018 }
1019 return rate;
1020}
1021
1022static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1023 unsigned long *prate)
1024{
1025 int div;
1026 int mul;
1027 long round_rate = *prate;
1028
1029 mul = 1;
1030
1031 if (rate >= *prate) {
1032 div = 1;
1033 } else {
1034 div = DIV_ROUND_UP(*prate / 8, rate);
1035 div *= 8;
1036 }
1037
1038 round_rate *= mul;
1039 round_rate += div - 1;
1040 do_div(round_rate, div);
1041
1042 return round_rate;
1043}
1044
1045struct clk_ops tegra30_blink_clk_ops = {
1046 .is_enabled = tegra30_blink_clk_is_enabled,
1047 .enable = tegra30_blink_clk_enable,
1048 .disable = tegra30_blink_clk_disable,
1049 .recalc_rate = tegra30_blink_clk_recalc_rate,
1050 .round_rate = tegra30_blink_clk_round_rate,
1051 .set_rate = tegra30_blink_clk_set_rate,
1052};
1053
1054static void tegra30_utmi_param_configure(struct clk_hw *hw)
1055{
1056 unsigned long main_rate =
1057 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
1058 u32 reg;
1059 int i;
1060
1061 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
1062 if (main_rate == utmi_parameters[i].osc_frequency)
1063 break;
1064 }
1065
1066 if (i >= ARRAY_SIZE(utmi_parameters)) {
1067 pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate);
1068 return;
1069 }
1070
1071 reg = clk_readl(UTMIP_PLL_CFG2);
1072
1073 /* Program UTMIP PLL stable and active counts */
1074 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
1075 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
1076 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
1077 utmi_parameters[i].stable_count);
1078
1079 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
1080
1081 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
1082 utmi_parameters[i].active_delay_count);
1083
1084 /* Remove power downs from UTMIP PLL control bits */
1085 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
1086 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
1087 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
1088
1089 clk_writel(reg, UTMIP_PLL_CFG2);
1090
1091 /* Program UTMIP PLL delay and oscillator frequency counts */
1092 reg = clk_readl(UTMIP_PLL_CFG1);
1093 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
1094
1095 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
1096 utmi_parameters[i].enable_delay_count);
1097
1098 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
1099 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
1100 utmi_parameters[i].xtal_freq_count);
1101
1102 /* Remove power downs from UTMIP PLL control bits */
1103 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
1104 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
1105 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
1106
1107 clk_writel(reg, UTMIP_PLL_CFG1);
1108}
1109
1110/* PLL Functions */
1111static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
1112 u32 lock_bit)
1113{
1114 int ret = 0;
1115
1116#if USE_PLL_LOCK_BITS
1117 int i;
1118 for (i = 0; i < c->u.pll.lock_delay; i++) {
1119 if (clk_readl(lock_reg) & lock_bit) {
1120 udelay(PLL_POST_LOCK_DELAY);
1121 return 0;
1122 }
1123 udelay(2); /* timeout = 2 * lock time */
1124 }
1125 pr_err("Timed out waiting for lock bit on pll %s",
1126 __clk_get_name(hw->clk));
1127 ret = -1;
1128#else
1129 udelay(c->u.pll.lock_delay);
1130#endif
1131 return ret;
1132}
1133
1134static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
1135{
1136 struct clk_tegra *c = to_clk_tegra(hw);
1137 u32 val = clk_readl(c->reg + PLL_BASE);
1138
1139 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
1140 return c->state;
1141}
1142
1143static void tegra30_pll_clk_init(struct clk_hw *hw)
1144{
1145 struct clk_tegra *c = to_clk_tegra(hw);
1146
1147 if (c->flags & PLLU)
1148 tegra30_utmi_param_configure(hw);
1149}
1150
1151static int tegra30_pll_clk_enable(struct clk_hw *hw)
1152{
1153 struct clk_tegra *c = to_clk_tegra(hw);
1154 u32 val;
1155 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1156
1157#if USE_PLL_LOCK_BITS
1158 val = clk_readl(c->reg + PLL_MISC(c));
1159 val |= PLL_MISC_LOCK_ENABLE(c);
1160 clk_writel(val, c->reg + PLL_MISC(c));
1161#endif
1162 val = clk_readl(c->reg + PLL_BASE);
1163 val &= ~PLL_BASE_BYPASS;
1164 val |= PLL_BASE_ENABLE;
1165 clk_writel(val, c->reg + PLL_BASE);
1166
1167 if (c->flags & PLLM) {
1168 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1169 val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1170 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1171 }
1172
1173 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
1174
1175 return 0;
1176}
1177
1178static void tegra30_pll_clk_disable(struct clk_hw *hw)
1179{
1180 struct clk_tegra *c = to_clk_tegra(hw);
1181 u32 val;
1182 pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
1183
1184 val = clk_readl(c->reg);
1185 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1186 clk_writel(val, c->reg);
1187
1188 if (c->flags & PLLM) {
1189 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE);
1190 val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
1191 pmc_writel(val, PMC_PLLP_WB0_OVERRIDE);
1192 }
1193}
1194
1195static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1196 unsigned long parent_rate)
1197{
1198 struct clk_tegra *c = to_clk_tegra(hw);
1199 u32 val, p_div, old_base;
1200 unsigned long input_rate;
1201 const struct clk_pll_freq_table *sel;
1202 struct clk_pll_freq_table cfg;
1203
1204 if (c->flags & PLL_FIXED) {
1205 int ret = 0;
1206 if (rate != c->u.pll.fixed_rate) {
1207 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
1208 __func__, __clk_get_name(hw->clk),
1209 c->u.pll.fixed_rate, rate);
1210 ret = -EINVAL;
1211 }
1212 return ret;
1213 }
1214
1215 if (c->flags & PLLM) {
1216 if (rate != __clk_get_rate(hw->clk)) {
1217 pr_err("%s: Can not change memory %s rate in flight\n",
1218 __func__, __clk_get_name(hw->clk));
1219 return -EINVAL;
1220 }
1221 }
1222
1223 p_div = 0;
1224 input_rate = parent_rate;
1225
1226 /* Check if the target rate is tabulated */
1227 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1228 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1229 if (c->flags & PLLU) {
1230 BUG_ON(sel->p < 1 || sel->p > 2);
1231 if (sel->p == 1)
1232 p_div = PLLU_BASE_POST_DIV;
1233 } else {
1234 BUG_ON(sel->p < 1);
1235 for (val = sel->p; val > 1; val >>= 1)
1236 p_div++;
1237 p_div <<= PLL_BASE_DIVP_SHIFT;
1238 }
1239 break;
1240 }
1241 }
1242
1243 /* Configure out-of-table rate */
1244 if (sel->input_rate == 0) {
1245 unsigned long cfreq;
1246 BUG_ON(c->flags & PLLU);
1247 sel = &cfg;
1248
1249 switch (input_rate) {
1250 case 12000000:
1251 case 26000000:
1252 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1253 break;
1254 case 13000000:
1255 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1256 break;
1257 case 16800000:
1258 case 19200000:
1259 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1260 break;
1261 default:
1262 pr_err("%s: Unexpected reference rate %lu\n",
1263 __func__, input_rate);
1264 BUG();
1265 }
1266
1267 /* Raise VCO to guarantee 0.5% accuracy */
1268 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1269 cfg.output_rate <<= 1)
1270 p_div++;
1271
1272 cfg.p = 0x1 << p_div;
1273 cfg.m = input_rate / cfreq;
1274 cfg.n = cfg.output_rate / cfreq;
1275 cfg.cpcon = OUT_OF_TABLE_CPCON;
1276
1277 if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) ||
1278 (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) ||
1279 (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
1280 (cfg.output_rate > c->u.pll.vco_max)) {
1281 pr_err("%s: Failed to set %s out-of-table rate %lu\n",
1282 __func__, __clk_get_name(hw->clk), rate);
1283 return -EINVAL;
1284 }
1285 p_div <<= PLL_BASE_DIVP_SHIFT;
1286 }
1287
1288 c->mul = sel->n;
1289 c->div = sel->m * sel->p;
1290
1291 old_base = val = clk_readl(c->reg + PLL_BASE);
1292 val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK |
1293 ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK));
1294 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
1295 (sel->n << PLL_BASE_DIVN_SHIFT) | p_div;
1296 if (val == old_base)
1297 return 0;
1298
1299 if (c->state == ON) {
1300 tegra30_pll_clk_disable(hw);
1301 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1302 }
1303 clk_writel(val, c->reg + PLL_BASE);
1304
1305 if (c->flags & PLL_HAS_CPCON) {
1306 val = clk_readl(c->reg + PLL_MISC(c));
1307 val &= ~PLL_MISC_CPCON_MASK;
1308 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
1309 if (c->flags & (PLLU | PLLD)) {
1310 val &= ~PLL_MISC_LFCON_MASK;
1311 if (sel->n >= PLLDU_LFCON_SET_DIVN)
1312 val |= 0x1 << PLL_MISC_LFCON_SHIFT;
1313 } else if (c->flags & (PLLX | PLLM)) {
1314 val &= ~(0x1 << PLL_MISC_DCCON_SHIFT);
1315 if (rate >= (c->u.pll.vco_max >> 1))
1316 val |= 0x1 << PLL_MISC_DCCON_SHIFT;
1317 }
1318 clk_writel(val, c->reg + PLL_MISC(c));
1319 }
1320
1321 if (c->state == ON)
1322 tegra30_pll_clk_enable(hw);
1323
1324 c->u.pll.fixed_rate = rate;
1325
1326 return 0;
1327}
1328
1329static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
1330 unsigned long *prate)
1331{
1332 struct clk_tegra *c = to_clk_tegra(hw);
1333 unsigned long input_rate = *prate;
1334 u64 output_rate = *prate;
1335 const struct clk_pll_freq_table *sel;
1336 struct clk_pll_freq_table cfg;
1337 int mul;
1338 int div;
1339 u32 p_div;
1340 u32 val;
1341
1342 if (c->flags & PLL_FIXED)
1343 return c->u.pll.fixed_rate;
1344
1345 if (c->flags & PLLM)
1346 return __clk_get_rate(hw->clk);
1347
1348 p_div = 0;
1349 /* Check if the target rate is tabulated */
1350 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1351 if (sel->input_rate == input_rate && sel->output_rate == rate) {
1352 if (c->flags & PLLU) {
1353 BUG_ON(sel->p < 1 || sel->p > 2);
1354 if (sel->p == 1)
1355 p_div = PLLU_BASE_POST_DIV;
1356 } else {
1357 BUG_ON(sel->p < 1);
1358 for (val = sel->p; val > 1; val >>= 1)
1359 p_div++;
1360 p_div <<= PLL_BASE_DIVP_SHIFT;
1361 }
1362 break;
1363 }
1364 }
1365
1366 if (sel->input_rate == 0) {
1367 unsigned long cfreq;
1368 BUG_ON(c->flags & PLLU);
1369 sel = &cfg;
1370
1371 switch (input_rate) {
1372 case 12000000:
1373 case 26000000:
1374 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
1375 break;
1376 case 13000000:
1377 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
1378 break;
1379 case 16800000:
1380 case 19200000:
1381 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
1382 break;
1383 default:
1384 pr_err("%s: Unexpected reference rate %lu\n",
1385 __func__, input_rate);
1386 BUG();
1387 }
1388
1389 /* Raise VCO to guarantee 0.5% accuracy */
1390 for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
1391 cfg.output_rate <<= 1)
1392 p_div++;
1393
1394 cfg.p = 0x1 << p_div;
1395 cfg.m = input_rate / cfreq;
1396 cfg.n = cfg.output_rate / cfreq;
1397 }
1398
1399 mul = sel->n;
1400 div = sel->m * sel->p;
1401
1402 output_rate *= mul;
1403 output_rate += div - 1; /* round up */
1404 do_div(output_rate, div);
1405
1406 return output_rate;
1407}
1408
1409static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
1410 unsigned long parent_rate)
1411{
1412 struct clk_tegra *c = to_clk_tegra(hw);
1413 u64 rate = parent_rate;
1414 u32 val = clk_readl(c->reg + PLL_BASE);
1415
1416 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
1417 const struct clk_pll_freq_table *sel;
1418 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1419 if (sel->input_rate == parent_rate &&
1420 sel->output_rate == c->u.pll.fixed_rate) {
1421 c->mul = sel->n;
1422 c->div = sel->m * sel->p;
1423 break;
1424 }
1425 }
1426 pr_err("Clock %s has unknown fixed frequency\n",
1427 __clk_get_name(hw->clk));
1428 BUG();
1429 } else if (val & PLL_BASE_BYPASS) {
1430 c->mul = 1;
1431 c->div = 1;
1432 } else {
1433 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
1434 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
1435 if (c->flags & PLLU)
1436 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
1437 else
1438 c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
1439 PLL_BASE_DIVP_SHIFT));
1440 }
1441
1442 if (c->mul != 0 && c->div != 0) {
1443 rate *= c->mul;
1444 rate += c->div - 1; /* round up */
1445 do_div(rate, c->div);
1446 }
1447
1448 return rate;
1449}
1450
1451struct clk_ops tegra30_pll_ops = {
1452 .is_enabled = tegra30_pll_clk_is_enabled,
1453 .init = tegra30_pll_clk_init,
1454 .enable = tegra30_pll_clk_enable,
1455 .disable = tegra30_pll_clk_disable,
1456 .recalc_rate = tegra30_pll_recalc_rate,
1457 .round_rate = tegra30_pll_round_rate,
1458 .set_rate = tegra30_pll_clk_set_rate,
1459};
1460
1461int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
1462 enum tegra_clk_ex_param p, u32 setting)
1463{
1464 struct clk_tegra *c = to_clk_tegra(hw);
1465 u32 val, mask, reg;
1466
1467 switch (p) {
1468 case TEGRA_CLK_PLLD_CSI_OUT_ENB:
1469 mask = PLLD_BASE_CSI_CLKENABLE;
1470 reg = c->reg + PLL_BASE;
1471 break;
1472 case TEGRA_CLK_PLLD_DSI_OUT_ENB:
1473 mask = PLLD_MISC_DSI_CLKENABLE;
1474 reg = c->reg + PLL_MISC(c);
1475 break;
1476 case TEGRA_CLK_PLLD_MIPI_MUX_SEL:
1477 if (!(c->flags & PLL_ALT_MISC_REG)) {
1478 mask = PLLD_BASE_DSIB_MUX_MASK;
1479 reg = c->reg + PLL_BASE;
1480 break;
1481 }
1482 /* fall through - error since PLLD2 does not have MUX_SEL control */
1483 default:
1484 return -EINVAL;
1485 }
1486
1487 val = clk_readl(reg);
1488 if (setting)
1489 val |= mask;
1490 else
1491 val &= ~mask;
1492 clk_writel(val, reg);
1493 return 0;
1494}
1495
1496static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
1497{
1498 struct clk_tegra *c = to_clk_tegra(hw);
1499 u32 val;
1500
1501 val = clk_readl(c->reg + PLL_BASE);
1502 c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
1503 return c->state;
1504}
1505
1506static void tegra30_plle_clk_disable(struct clk_hw *hw)
1507{
1508 struct clk_tegra *c = to_clk_tegra(hw);
1509 u32 val;
1510
1511 val = clk_readl(c->reg + PLL_BASE);
1512 val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1513 clk_writel(val, c->reg + PLL_BASE);
1514}
1515
1516static void tegra30_plle_training(struct clk_tegra *c)
1517{
1518 u32 val;
1519
1520 /* PLLE is already disabled, and setup cleared;
1521 * create falling edge on PLLE IDDQ input */
1522 val = pmc_readl(PMC_SATA_PWRGT);
1523 val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1524 pmc_writel(val, PMC_SATA_PWRGT);
1525
1526 val = pmc_readl(PMC_SATA_PWRGT);
1527 val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
1528 pmc_writel(val, PMC_SATA_PWRGT);
1529
1530 val = pmc_readl(PMC_SATA_PWRGT);
1531 val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
1532 pmc_writel(val, PMC_SATA_PWRGT);
1533
1534 do {
1535 val = clk_readl(c->reg + PLL_MISC(c));
1536 } while (!(val & PLLE_MISC_READY));
1537}
1538
1539static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
1540{
1541 struct clk_tegra *c = to_clk_tegra(hw);
1542 struct clk *parent = __clk_get_parent(hw->clk);
1543 const struct clk_pll_freq_table *sel;
1544 u32 val;
1545
1546 unsigned long rate = c->u.pll.fixed_rate;
1547 unsigned long input_rate = __clk_get_rate(parent);
1548
1549 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
1550 if (sel->input_rate == input_rate && sel->output_rate == rate)
1551 break;
1552 }
1553
1554 if (sel->input_rate == 0)
1555 return -ENOSYS;
1556
1557 /* disable PLLE, clear setup fiels */
1558 tegra30_plle_clk_disable(hw);
1559
1560 val = clk_readl(c->reg + PLL_MISC(c));
1561 val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
1562 clk_writel(val, c->reg + PLL_MISC(c));
1563
1564 /* training */
1565 val = clk_readl(c->reg + PLL_MISC(c));
1566 if (force_training || (!(val & PLLE_MISC_READY)))
1567 tegra30_plle_training(c);
1568
1569 /* configure dividers, setup, disable SS */
1570 val = clk_readl(c->reg + PLL_BASE);
1571 val &= ~PLLE_BASE_DIV_MASK;
1572 val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon);
1573 clk_writel(val, c->reg + PLL_BASE);
1574 c->mul = sel->n;
1575 c->div = sel->m * sel->p;
1576
1577 val = clk_readl(c->reg + PLL_MISC(c));
1578 val |= PLLE_MISC_SETUP_VALUE;
1579 val |= PLLE_MISC_LOCK_ENABLE;
1580 clk_writel(val, c->reg + PLL_MISC(c));
1581
1582 val = clk_readl(PLLE_SS_CTRL);
1583 val |= PLLE_SS_DISABLE;
1584 clk_writel(val, PLLE_SS_CTRL);
1585
1586 /* enable and lock PLLE*/
1587 val = clk_readl(c->reg + PLL_BASE);
1588 val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
1589 clk_writel(val, c->reg + PLL_BASE);
1590
1591 tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK);
1592
1593 return 0;
1594}
1595
1596static int tegra30_plle_clk_enable(struct clk_hw *hw)
1597{
1598 struct clk_tegra *c = to_clk_tegra(hw);
1599
1600 return tegra30_plle_configure(hw, !c->set);
1601}
1602
1603static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
1604 unsigned long parent_rate)
1605{
1606 struct clk_tegra *c = to_clk_tegra(hw);
1607 unsigned long rate = parent_rate;
1608 u32 val;
1609
1610 val = clk_readl(c->reg + PLL_BASE);
1611 c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
1612 c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
1613 c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
1614
1615 if (c->mul != 0 && c->div != 0) {
1616 rate *= c->mul;
1617 rate += c->div - 1; /* round up */
1618 do_div(rate, c->div);
1619 }
1620 return rate;
1621}
1622
1623struct clk_ops tegra30_plle_ops = {
1624 .is_enabled = tegra30_plle_clk_is_enabled,
1625 .enable = tegra30_plle_clk_enable,
1626 .disable = tegra30_plle_clk_disable,
1627 .recalc_rate = tegra30_plle_clk_recalc_rate,
1628};
1629
1630/* Clock divider ops */
1631static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
1632{
1633 struct clk_tegra *c = to_clk_tegra(hw);
1634
1635 if (c->flags & DIV_U71) {
1636 u32 val = clk_readl(c->reg);
1637 val >>= c->reg_shift;
1638 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
1639 if (!(val & PLL_OUT_RESET_DISABLE))
1640 c->state = OFF;
1641 } else {
1642 c->state = ON;
1643 }
1644 return c->state;
1645}
1646
1647static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
1648{
1649 struct clk_tegra *c = to_clk_tegra(hw);
1650 u32 val;
1651 u32 new_val;
1652
1653 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1654 if (c->flags & DIV_U71) {
1655 val = clk_readl(c->reg);
1656 new_val = val >> c->reg_shift;
1657 new_val &= 0xFFFF;
1658
1659 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
1660
1661 val &= ~(0xFFFF << c->reg_shift);
1662 val |= new_val << c->reg_shift;
1663 clk_writel_delay(val, c->reg);
1664 return 0;
1665 } else if (c->flags & DIV_2) {
1666 return 0;
1667 }
1668 return -EINVAL;
1669}
1670
1671static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
1672{
1673 struct clk_tegra *c = to_clk_tegra(hw);
1674 u32 val;
1675 u32 new_val;
1676
1677 pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
1678 if (c->flags & DIV_U71) {
1679 val = clk_readl(c->reg);
1680 new_val = val >> c->reg_shift;
1681 new_val &= 0xFFFF;
1682
1683 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
1684
1685 val &= ~(0xFFFF << c->reg_shift);
1686 val |= new_val << c->reg_shift;
1687 clk_writel_delay(val, c->reg);
1688 }
1689}
1690
1691static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1692 unsigned long parent_rate)
1693{
1694 struct clk_tegra *c = to_clk_tegra(hw);
1695 u32 val;
1696 u32 new_val;
1697 int divider_u71;
1698
1699 if (c->flags & DIV_U71) {
1700 divider_u71 = clk_div71_get_divider(
1701 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1702 if (divider_u71 >= 0) {
1703 val = clk_readl(c->reg);
1704 new_val = val >> c->reg_shift;
1705 new_val &= 0xFFFF;
1706 if (c->flags & DIV_U71_FIXED)
1707 new_val |= PLL_OUT_OVERRIDE;
1708 new_val &= ~PLL_OUT_RATIO_MASK;
1709 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
1710
1711 val &= ~(0xFFFF << c->reg_shift);
1712 val |= new_val << c->reg_shift;
1713 clk_writel_delay(val, c->reg);
1714 c->div = divider_u71 + 2;
1715 c->mul = 2;
1716 c->fixed_rate = rate;
1717 return 0;
1718 }
1719 } else if (c->flags & DIV_2) {
1720 c->fixed_rate = rate;
1721 return 0;
1722 }
1723
1724 return -EINVAL;
1725}
1726
1727static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
1728 unsigned long parent_rate)
1729{
1730 struct clk_tegra *c = to_clk_tegra(hw);
1731 u64 rate = parent_rate;
1732
1733 if (c->flags & DIV_U71) {
1734 u32 divu71;
1735 u32 val = clk_readl(c->reg);
1736 val >>= c->reg_shift;
1737
1738 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
1739 c->div = (divu71 + 2);
1740 c->mul = 2;
1741 } else if (c->flags & DIV_2) {
1742 if (c->flags & (PLLD | PLLX)) {
1743 c->div = 2;
1744 c->mul = 1;
1745 } else
1746 BUG();
1747 } else {
1748 c->div = 1;
1749 c->mul = 1;
1750 }
1751 if (c->mul != 0 && c->div != 0) {
1752 rate *= c->mul;
1753 rate += c->div - 1; /* round up */
1754 do_div(rate, c->div);
1755 }
1756
1757 return rate;
1758}
1759
1760static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
1761 unsigned long rate, unsigned long *prate)
1762{
1763 struct clk_tegra *c = to_clk_tegra(hw);
1764 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1765 int divider;
1766
1767 if (prate)
1768 parent_rate = *prate;
1769
1770 if (c->flags & DIV_U71) {
1771 divider = clk_div71_get_divider(
1772 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1773 if (divider < 0)
1774 return divider;
1775 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1776 } else if (c->flags & DIV_2) {
1777 *prate = rate * 2;
1778 return rate;
1779 }
1780
1781 return -EINVAL;
1782}
1783
1784struct clk_ops tegra30_pll_div_ops = {
1785 .is_enabled = tegra30_pll_div_clk_is_enabled,
1786 .enable = tegra30_pll_div_clk_enable,
1787 .disable = tegra30_pll_div_clk_disable,
1788 .set_rate = tegra30_pll_div_clk_set_rate,
1789 .recalc_rate = tegra30_pll_div_clk_recalc_rate,
1790 .round_rate = tegra30_pll_div_clk_round_rate,
1791};
1792
1793/* Periph clk ops */
1794static inline u32 periph_clk_source_mask(struct clk_tegra *c)
1795{
1796 if (c->flags & MUX8)
1797 return 7 << 29;
1798 else if (c->flags & MUX_PWM)
1799 return 3 << 28;
1800 else if (c->flags & MUX_CLK_OUT)
1801 return 3 << (c->u.periph.clk_num + 4);
1802 else if (c->flags & PLLD)
1803 return PLLD_BASE_DSIB_MUX_MASK;
1804 else
1805 return 3 << 30;
1806}
1807
1808static inline u32 periph_clk_source_shift(struct clk_tegra *c)
1809{
1810 if (c->flags & MUX8)
1811 return 29;
1812 else if (c->flags & MUX_PWM)
1813 return 28;
1814 else if (c->flags & MUX_CLK_OUT)
1815 return c->u.periph.clk_num + 4;
1816 else if (c->flags & PLLD)
1817 return PLLD_BASE_DSIB_MUX_SHIFT;
1818 else
1819 return 30;
1820}
1821
1822static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
1823{
1824 struct clk_tegra *c = to_clk_tegra(hw);
1825
1826 c->state = ON;
1827 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
1828 c->state = OFF;
1829 if (!(c->flags & PERIPH_NO_RESET))
1830 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
1831 c->state = OFF;
1832 return c->state;
1833}
1834
1835static int tegra30_periph_clk_enable(struct clk_hw *hw)
1836{
1837 struct clk_tegra *c = to_clk_tegra(hw);
1838
1839 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
1840 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
1841 return 0;
1842
1843 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c));
1844 if (!(c->flags & PERIPH_NO_RESET) &&
1845 !(c->flags & PERIPH_MANUAL_RESET)) {
1846 if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) &
1847 PERIPH_CLK_TO_BIT(c)) {
1848 udelay(5); /* reset propagation delay */
1849 clk_writel(PERIPH_CLK_TO_BIT(c),
1850 PERIPH_CLK_TO_RST_CLR_REG(c));
1851 }
1852 }
1853 return 0;
1854}
1855
1856static void tegra30_periph_clk_disable(struct clk_hw *hw)
1857{
1858 struct clk_tegra *c = to_clk_tegra(hw);
1859 unsigned long val;
1860
1861 tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
1862
1863 if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
1864 return;
1865
1866 /* If peripheral is in the APB bus then read the APB bus to
1867 * flush the write operation in apb bus. This will avoid the
1868 * peripheral access after disabling clock*/
1869 if (c->flags & PERIPH_ON_APB)
1870 val = chipid_readl();
1871
1872 clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
1873}
1874
1875void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
1876{
1877 struct clk_tegra *c = to_clk_tegra(hw);
1878 unsigned long val;
1879
1880 if (!(c->flags & PERIPH_NO_RESET)) {
1881 if (assert) {
1882 /* If peripheral is in the APB bus then read the APB
1883 * bus to flush the write operation in apb bus. This
1884 * will avoid the peripheral access after disabling
1885 * clock */
1886 if (c->flags & PERIPH_ON_APB)
1887 val = chipid_readl();
1888
1889 clk_writel(PERIPH_CLK_TO_BIT(c),
1890 PERIPH_CLK_TO_RST_SET_REG(c));
1891 } else
1892 clk_writel(PERIPH_CLK_TO_BIT(c),
1893 PERIPH_CLK_TO_RST_CLR_REG(c));
1894 }
1895}
1896
1897static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
1898{
1899 struct clk_tegra *c = to_clk_tegra(hw);
1900 u32 val;
1901
1902 if (!(c->flags & MUX))
1903 return (index == 0) ? 0 : (-EINVAL);
1904
1905 val = clk_readl(c->reg);
1906 val &= ~periph_clk_source_mask(c);
1907 val |= (index << periph_clk_source_shift(c));
1908 clk_writel_delay(val, c->reg);
1909 return 0;
1910}
1911
1912static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
1913{
1914 struct clk_tegra *c = to_clk_tegra(hw);
1915 u32 val = clk_readl(c->reg);
1916 int source = (val & periph_clk_source_mask(c)) >>
1917 periph_clk_source_shift(c);
1918
1919 if (!(c->flags & MUX))
1920 return 0;
1921
1922 return source;
1923}
1924
1925static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1926 unsigned long parent_rate)
1927{
1928 struct clk_tegra *c = to_clk_tegra(hw);
1929 u32 val;
1930 int divider;
1931
1932 if (c->flags & DIV_U71) {
1933 divider = clk_div71_get_divider(
1934 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1935 if (divider >= 0) {
1936 val = clk_readl(c->reg);
1937 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
1938 val |= divider;
1939 if (c->flags & DIV_U71_UART) {
1940 if (divider)
1941 val |= PERIPH_CLK_UART_DIV_ENB;
1942 else
1943 val &= ~PERIPH_CLK_UART_DIV_ENB;
1944 }
1945 clk_writel_delay(val, c->reg);
1946 c->div = divider + 2;
1947 c->mul = 2;
1948 return 0;
1949 }
1950 } else if (c->flags & DIV_U16) {
1951 divider = clk_div16_get_divider(parent_rate, rate);
1952 if (divider >= 0) {
1953 val = clk_readl(c->reg);
1954 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1955 val |= divider;
1956 clk_writel_delay(val, c->reg);
1957 c->div = divider + 1;
1958 c->mul = 1;
1959 return 0;
1960 }
1961 } else if (parent_rate <= rate) {
1962 c->div = 1;
1963 c->mul = 1;
1964 return 0;
1965 }
1966 return -EINVAL;
1967}
1968
1969static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1970 unsigned long *prate)
1971{
1972 struct clk_tegra *c = to_clk_tegra(hw);
1973 unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
1974 int divider;
1975
1976 if (prate)
1977 parent_rate = *prate;
1978
1979 if (c->flags & DIV_U71) {
1980 divider = clk_div71_get_divider(
1981 parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
1982 if (divider < 0)
1983 return divider;
1984
1985 return DIV_ROUND_UP(parent_rate * 2, divider + 2);
1986 } else if (c->flags & DIV_U16) {
1987 divider = clk_div16_get_divider(parent_rate, rate);
1988 if (divider < 0)
1989 return divider;
1990 return DIV_ROUND_UP(parent_rate, divider + 1);
1991 }
1992 return -EINVAL;
1993}
1994
1995static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
1996 unsigned long parent_rate)
1997{
1998 struct clk_tegra *c = to_clk_tegra(hw);
1999 u64 rate = parent_rate;
2000 u32 val = clk_readl(c->reg);
2001
2002 if (c->flags & DIV_U71) {
2003 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
2004 if ((c->flags & DIV_U71_UART) &&
2005 (!(val & PERIPH_CLK_UART_DIV_ENB))) {
2006 divu71 = 0;
2007 }
2008 if (c->flags & DIV_U71_IDLE) {
2009 val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
2010 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2011 val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
2012 PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
2013 clk_writel(val, c->reg);
2014 }
2015 c->div = divu71 + 2;
2016 c->mul = 2;
2017 } else if (c->flags & DIV_U16) {
2018 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
2019 c->div = divu16 + 1;
2020 c->mul = 1;
2021 } else {
2022 c->div = 1;
2023 c->mul = 1;
2024 }
2025
2026 if (c->mul != 0 && c->div != 0) {
2027 rate *= c->mul;
2028 rate += c->div - 1; /* round up */
2029 do_div(rate, c->div);
2030 }
2031 return rate;
2032}
2033
2034struct clk_ops tegra30_periph_clk_ops = {
2035 .is_enabled = tegra30_periph_clk_is_enabled,
2036 .enable = tegra30_periph_clk_enable,
2037 .disable = tegra30_periph_clk_disable,
2038 .set_parent = tegra30_periph_clk_set_parent,
2039 .get_parent = tegra30_periph_clk_get_parent,
2040 .set_rate = tegra30_periph_clk_set_rate,
2041 .round_rate = tegra30_periph_clk_round_rate,
2042 .recalc_rate = tegra30_periph_clk_recalc_rate,
2043};
2044
2045static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
2046{
2047 struct clk *d = clk_get_sys(NULL, "pll_d");
2048 /* The DSIB parent selection bit is in PLLD base register */
2049 tegra_clk_cfg_ex(
2050 d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
2051
2052 return 0;
2053}
2054
2055struct clk_ops tegra30_dsib_clk_ops = {
2056 .is_enabled = tegra30_periph_clk_is_enabled,
2057 .enable = &tegra30_periph_clk_enable,
2058 .disable = &tegra30_periph_clk_disable,
2059 .set_parent = &tegra30_dsib_clk_set_parent,
2060 .get_parent = &tegra30_periph_clk_get_parent,
2061 .set_rate = &tegra30_periph_clk_set_rate,
2062 .round_rate = &tegra30_periph_clk_round_rate,
2063 .recalc_rate = &tegra30_periph_clk_recalc_rate,
2064};
2065
2066/* Periph extended clock configuration ops */
2067int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
2068 enum tegra_clk_ex_param p, u32 setting)
2069{
2070 struct clk_tegra *c = to_clk_tegra(hw);
2071
2072 if (p == TEGRA_CLK_VI_INP_SEL) {
2073 u32 val = clk_readl(c->reg);
2074 val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
2075 val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) &
2076 PERIPH_CLK_VI_SEL_EX_MASK;
2077 clk_writel(val, c->reg);
2078 return 0;
2079 }
2080 return -EINVAL;
2081}
2082
2083int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
2084 enum tegra_clk_ex_param p, u32 setting)
2085{
2086 struct clk_tegra *c = to_clk_tegra(hw);
2087
2088 if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
2089 u32 val = clk_readl(c->reg);
2090 if (setting)
2091 val |= PERIPH_CLK_NAND_DIV_EX_ENB;
2092 else
2093 val &= ~PERIPH_CLK_NAND_DIV_EX_ENB;
2094 clk_writel(val, c->reg);
2095 return 0;
2096 }
2097 return -EINVAL;
2098}
2099
2100int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
2101 enum tegra_clk_ex_param p, u32 setting)
2102{
2103 struct clk_tegra *c = to_clk_tegra(hw);
2104
2105 if (p == TEGRA_CLK_DTV_INVERT) {
2106 u32 val = clk_readl(c->reg);
2107 if (setting)
2108 val |= PERIPH_CLK_DTV_POLARITY_INV;
2109 else
2110 val &= ~PERIPH_CLK_DTV_POLARITY_INV;
2111 clk_writel(val, c->reg);
2112 return 0;
2113 }
2114 return -EINVAL;
2115}
2116
2117/* Output clock ops */
2118
2119static DEFINE_SPINLOCK(clk_out_lock);
2120
2121static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
2122{
2123 struct clk_tegra *c = to_clk_tegra(hw);
2124 u32 val = pmc_readl(c->reg);
2125
2126 c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
2127 c->mul = 1;
2128 c->div = 1;
2129 return c->state;
2130}
2131
2132static int tegra30_clk_out_enable(struct clk_hw *hw)
2133{
2134 struct clk_tegra *c = to_clk_tegra(hw);
2135 u32 val;
2136 unsigned long flags;
2137
2138 spin_lock_irqsave(&clk_out_lock, flags);
2139 val = pmc_readl(c->reg);
2140 val |= (0x1 << c->u.periph.clk_num);
2141 pmc_writel(val, c->reg);
2142 spin_unlock_irqrestore(&clk_out_lock, flags);
2143
2144 return 0;
2145}
2146
2147static void tegra30_clk_out_disable(struct clk_hw *hw)
2148{
2149 struct clk_tegra *c = to_clk_tegra(hw);
2150 u32 val;
2151 unsigned long flags;
2152
2153 spin_lock_irqsave(&clk_out_lock, flags);
2154 val = pmc_readl(c->reg);
2155 val &= ~(0x1 << c->u.periph.clk_num);
2156 pmc_writel(val, c->reg);
2157 spin_unlock_irqrestore(&clk_out_lock, flags);
2158}
2159
2160static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
2161{
2162 struct clk_tegra *c = to_clk_tegra(hw);
2163 u32 val;
2164 unsigned long flags;
2165
2166 spin_lock_irqsave(&clk_out_lock, flags);
2167 val = pmc_readl(c->reg);
2168 val &= ~periph_clk_source_mask(c);
2169 val |= (index << periph_clk_source_shift(c));
2170 pmc_writel(val, c->reg);
2171 spin_unlock_irqrestore(&clk_out_lock, flags);
2172
2173 return 0;
2174}
2175
2176static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
2177{
2178 struct clk_tegra *c = to_clk_tegra(hw);
2179 u32 val = pmc_readl(c->reg);
2180 int source;
2181
2182 source = (val & periph_clk_source_mask(c)) >>
2183 periph_clk_source_shift(c);
2184 return source;
2185}
2186
2187struct clk_ops tegra_clk_out_ops = {
2188 .is_enabled = tegra30_clk_out_is_enabled,
2189 .enable = tegra30_clk_out_enable,
2190 .disable = tegra30_clk_out_disable,
2191 .set_parent = tegra30_clk_out_set_parent,
2192 .get_parent = tegra30_clk_out_get_parent,
2193 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2194};
2195
2196/* Clock doubler ops */
2197static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
2198{
2199 struct clk_tegra *c = to_clk_tegra(hw);
2200
2201 c->state = ON;
2202 if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
2203 c->state = OFF;
2204 return c->state;
2205};
2206
2207static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
2208 unsigned long parent_rate)
2209{
2210 struct clk_tegra *c = to_clk_tegra(hw);
2211 u32 val;
2212
2213 if (rate == parent_rate) {
2214 val = clk_readl(c->reg) | (0x1 << c->reg_shift);
2215 clk_writel(val, c->reg);
2216 c->mul = 1;
2217 c->div = 1;
2218 return 0;
2219 } else if (rate == 2 * parent_rate) {
2220 val = clk_readl(c->reg) & (~(0x1 << c->reg_shift));
2221 clk_writel(val, c->reg);
2222 c->mul = 2;
2223 c->div = 1;
2224 return 0;
2225 }
2226 return -EINVAL;
2227}
2228
2229static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
2230 unsigned long parent_rate)
2231{
2232 struct clk_tegra *c = to_clk_tegra(hw);
2233 u64 rate = parent_rate;
2234
2235 u32 val = clk_readl(c->reg);
2236 c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
2237 c->div = 1;
2238
2239 if (c->mul != 0 && c->div != 0) {
2240 rate *= c->mul;
2241 rate += c->div - 1; /* round up */
2242 do_div(rate, c->div);
2243 }
2244
2245 return rate;
2246}
2247
2248static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
2249 unsigned long *prate)
2250{
2251 unsigned long output_rate = *prate;
2252
2253 do_div(output_rate, 2);
2254 return output_rate;
2255}
2256
2257struct clk_ops tegra30_clk_double_ops = {
2258 .is_enabled = tegra30_clk_double_is_enabled,
2259 .enable = tegra30_periph_clk_enable,
2260 .disable = tegra30_periph_clk_disable,
2261 .recalc_rate = tegra30_clk_double_recalc_rate,
2262 .round_rate = tegra30_clk_double_round_rate,
2263 .set_rate = tegra30_clk_double_set_rate,
2264};
2265
2266/* Audio sync clock ops */
2267struct clk_ops tegra_sync_source_ops = {
2268 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2269};
2270
2271static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
2272{
2273 struct clk_tegra *c = to_clk_tegra(hw);
2274 u32 val = clk_readl(c->reg);
2275 c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
2276 return c->state;
2277}
2278
2279static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
2280{
2281 struct clk_tegra *c = to_clk_tegra(hw);
2282 u32 val = clk_readl(c->reg);
2283 clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
2284 return 0;
2285}
2286
2287static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
2288{
2289 struct clk_tegra *c = to_clk_tegra(hw);
2290 u32 val = clk_readl(c->reg);
2291 clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
2292}
2293
2294static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
2295{
2296 struct clk_tegra *c = to_clk_tegra(hw);
2297 u32 val;
2298
2299 val = clk_readl(c->reg);
2300 val &= ~AUDIO_SYNC_SOURCE_MASK;
2301 val |= index;
2302
2303 clk_writel(val, c->reg);
2304 return 0;
2305}
2306
2307static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
2308{
2309 struct clk_tegra *c = to_clk_tegra(hw);
2310 u32 val = clk_readl(c->reg);
2311 int source;
2312
2313 source = val & AUDIO_SYNC_SOURCE_MASK;
2314 return source;
2315}
2316
2317struct clk_ops tegra30_audio_sync_clk_ops = {
2318 .is_enabled = tegra30_audio_sync_clk_is_enabled,
2319 .enable = tegra30_audio_sync_clk_enable,
2320 .disable = tegra30_audio_sync_clk_disable,
2321 .set_parent = tegra30_audio_sync_clk_set_parent,
2322 .get_parent = tegra30_audio_sync_clk_get_parent,
2323 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2324};
2325
2326/* cml0 (pcie), and cml1 (sata) clock ops */
2327static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
2328{
2329 struct clk_tegra *c = to_clk_tegra(hw);
2330 u32 val = clk_readl(c->reg);
2331 c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
2332 return c->state;
2333}
2334
2335static int tegra30_cml_clk_enable(struct clk_hw *hw)
2336{
2337 struct clk_tegra *c = to_clk_tegra(hw);
2338
2339 u32 val = clk_readl(c->reg);
2340 val |= (0x1 << c->u.periph.clk_num);
2341 clk_writel(val, c->reg);
2342
2343 return 0;
2344}
2345
2346static void tegra30_cml_clk_disable(struct clk_hw *hw)
2347{
2348 struct clk_tegra *c = to_clk_tegra(hw);
2349
2350 u32 val = clk_readl(c->reg);
2351 val &= ~(0x1 << c->u.periph.clk_num);
2352 clk_writel(val, c->reg);
2353}
2354
2355struct clk_ops tegra_cml_clk_ops = {
2356 .is_enabled = tegra30_cml_clk_is_enabled,
2357 .enable = tegra30_cml_clk_enable,
2358 .disable = tegra30_cml_clk_disable,
2359 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2360};
2361
2362struct clk_ops tegra_pciex_clk_ops = {
2363 .recalc_rate = tegra30_clk_fixed_recalc_rate,
2364};
2365
2366/* Tegra30 CPU clock and reset control functions */
2367static void tegra30_wait_cpu_in_reset(u32 cpu)
2368{
2369 unsigned int reg;
2370
2371 do {
2372 reg = readl(reg_clk_base +
2373 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2374 cpu_relax();
2375 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
2376
2377 return;
2378}
2379
2380static void tegra30_put_cpu_in_reset(u32 cpu)
2381{
2382 writel(CPU_RESET(cpu),
2383 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
2384 dmb();
2385}
2386
2387static void tegra30_cpu_out_of_reset(u32 cpu)
2388{
2389 writel(CPU_RESET(cpu),
2390 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
2391 wmb();
2392}
2393
2394static void tegra30_enable_cpu_clock(u32 cpu)
2395{
2396 unsigned int reg;
2397
2398 writel(CPU_CLOCK(cpu),
2399 reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2400 reg = readl(reg_clk_base +
2401 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
2402}
2403
2404static void tegra30_disable_cpu_clock(u32 cpu)
2405{
2406
2407 unsigned int reg;
2408
2409 reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2410 writel(reg | CPU_CLOCK(cpu),
2411 reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
2412}
2413
2414#ifdef CONFIG_PM_SLEEP
2415static bool tegra30_cpu_rail_off_ready(void)
2416{
2417 unsigned int cpu_rst_status;
2418 int cpu_pwr_status;
2419
2420 cpu_rst_status = readl(reg_clk_base +
2421 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
2422 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
2423 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
2424 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
2425
2426 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
2427 return false;
2428
2429 return true;
2430}
2431
2432static void tegra30_cpu_clock_suspend(void)
2433{
2434 /* switch coresite to clk_m, save off original source */
2435 tegra30_cpu_clk_sctx.clk_csite_src =
2436 readl(reg_clk_base + CLK_RESET_SOURCE_CSITE);
2437 writel(3<<30, reg_clk_base + CLK_RESET_SOURCE_CSITE);
2438
2439 tegra30_cpu_clk_sctx.cpu_burst =
2440 readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2441 tegra30_cpu_clk_sctx.pllx_base =
2442 readl(reg_clk_base + CLK_RESET_PLLX_BASE);
2443 tegra30_cpu_clk_sctx.pllx_misc =
2444 readl(reg_clk_base + CLK_RESET_PLLX_MISC);
2445 tegra30_cpu_clk_sctx.cclk_divider =
2446 readl(reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2447}
2448
2449static void tegra30_cpu_clock_resume(void)
2450{
2451 unsigned int reg, policy;
2452
2453 /* Is CPU complex already running on PLLX? */
2454 reg = readl(reg_clk_base + CLK_RESET_CCLK_BURST);
2455 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
2456
2457 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
2458 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
2459 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
2460 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
2461 else
2462 BUG();
2463
2464 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
2465 /* restore PLLX settings if CPU is on different PLL */
2466 writel(tegra30_cpu_clk_sctx.pllx_misc,
2467 reg_clk_base + CLK_RESET_PLLX_MISC);
2468 writel(tegra30_cpu_clk_sctx.pllx_base,
2469 reg_clk_base + CLK_RESET_PLLX_BASE);
2470
2471 /* wait for PLL stabilization if PLLX was enabled */
2472 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
2473 udelay(300);
2474 }
2475
2476 /*
2477 * Restore original burst policy setting for calls resulting from CPU
2478 * LP2 in idle or system suspend.
2479 */
2480 writel(tegra30_cpu_clk_sctx.cclk_divider,
2481 reg_clk_base + CLK_RESET_CCLK_DIVIDER);
2482 writel(tegra30_cpu_clk_sctx.cpu_burst,
2483 reg_clk_base + CLK_RESET_CCLK_BURST);
2484
2485 writel(tegra30_cpu_clk_sctx.clk_csite_src,
2486 reg_clk_base + CLK_RESET_SOURCE_CSITE);
2487}
2488#endif
2489
2490static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
2491 .wait_for_reset = tegra30_wait_cpu_in_reset,
2492 .put_in_reset = tegra30_put_cpu_in_reset,
2493 .out_of_reset = tegra30_cpu_out_of_reset,
2494 .enable_clock = tegra30_enable_cpu_clock,
2495 .disable_clock = tegra30_disable_cpu_clock,
2496#ifdef CONFIG_PM_SLEEP
2497 .rail_off_ready = tegra30_cpu_rail_off_ready,
2498 .suspend = tegra30_cpu_clock_suspend,
2499 .resume = tegra30_cpu_clock_resume,
2500#endif
2501};
2502
2503void __init tegra30_cpu_car_ops_init(void)
2504{
2505 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
2506}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
deleted file mode 100644
index 7a34adb2f72d..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA30_CLOCK_H
18#define __MACH_TEGRA30_CLOCK_H
19
20extern struct clk_ops tegra30_clk_32k_ops;
21extern struct clk_ops tegra30_clk_m_ops;
22extern struct clk_ops tegra_clk_m_div_ops;
23extern struct clk_ops tegra_pll_ref_ops;
24extern struct clk_ops tegra30_pll_ops;
25extern struct clk_ops tegra30_pll_div_ops;
26extern struct clk_ops tegra_plld_ops;
27extern struct clk_ops tegra30_plle_ops;
28extern struct clk_ops tegra_cml_clk_ops;
29extern struct clk_ops tegra_pciex_clk_ops;
30extern struct clk_ops tegra_sync_source_ops;
31extern struct clk_ops tegra30_audio_sync_clk_ops;
32extern struct clk_ops tegra30_clk_double_ops;
33extern struct clk_ops tegra_clk_out_ops;
34extern struct clk_ops tegra30_super_ops;
35extern struct clk_ops tegra30_blink_clk_ops;
36extern struct clk_ops tegra30_twd_ops;
37extern struct clk_ops tegra30_bus_ops;
38extern struct clk_ops tegra30_periph_clk_ops;
39extern struct clk_ops tegra30_dsib_clk_ops;
40extern struct clk_ops tegra_nand_clk_ops;
41extern struct clk_ops tegra_vi_clk_ops;
42extern struct clk_ops tegra_dtv_clk_ops;
43extern struct clk_ops tegra_clk_shared_bus_ops;
44
45int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
46 enum tegra_clk_ex_param p, u32 setting);
47void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
48int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
49 enum tegra_clk_ex_param p, u32 setting);
50int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
51 enum tegra_clk_ex_param p, u32 setting);
52int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
53 enum tegra_clk_ex_param p, u32 setting);
54#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
deleted file mode 100644
index 9bfaa490cff6..000000000000
--- a/arch/arm/mach-tegra/tegra30_clocks_data.c
+++ /dev/null
@@ -1,1425 +0,0 @@
1/*
2 * arch/arm/mach-tegra/tegra30_clocks.c
3 *
4 * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21#include <linux/clk-private.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26#include <linux/delay.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/clk.h>
30#include <linux/cpufreq.h>
31#include <linux/clk/tegra.h>
32
33#include "clock.h"
34#include "fuse.h"
35#include "tegra30_clocks.h"
36
37#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
38 _parent_names, _parents, _parent) \
39 static struct clk tegra_##_name = { \
40 .hw = &tegra_##_name##_hw.hw, \
41 .name = #_name, \
42 .rate = _rate, \
43 .ops = _ops, \
44 .flags = _flags, \
45 .parent_names = _parent_names, \
46 .parents = _parents, \
47 .num_parents = ARRAY_SIZE(_parent_names), \
48 .parent = _parent, \
49 };
50
51static struct clk tegra_clk_32k;
52static struct clk_tegra tegra_clk_32k_hw = {
53 .hw = {
54 .clk = &tegra_clk_32k,
55 },
56 .fixed_rate = 32768,
57};
58static struct clk tegra_clk_32k = {
59 .name = "clk_32k",
60 .hw = &tegra_clk_32k_hw.hw,
61 .ops = &tegra30_clk_32k_ops,
62 .flags = CLK_IS_ROOT,
63};
64
65static struct clk tegra_clk_m;
66static struct clk_tegra tegra_clk_m_hw = {
67 .hw = {
68 .clk = &tegra_clk_m,
69 },
70 .flags = ENABLE_ON_INIT,
71 .reg = 0x1fc,
72 .reg_shift = 28,
73 .max_rate = 48000000,
74};
75static struct clk tegra_clk_m = {
76 .name = "clk_m",
77 .hw = &tegra_clk_m_hw.hw,
78 .ops = &tegra30_clk_m_ops,
79 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
80};
81
82static const char *clk_m_div_parent_names[] = {
83 "clk_m",
84};
85
86static struct clk *clk_m_div_parents[] = {
87 &tegra_clk_m,
88};
89
90static struct clk tegra_clk_m_div2;
91static struct clk_tegra tegra_clk_m_div2_hw = {
92 .hw = {
93 .clk = &tegra_clk_m_div2,
94 },
95 .mul = 1,
96 .div = 2,
97 .max_rate = 24000000,
98};
99DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
100 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
101
102static struct clk tegra_clk_m_div4;
103static struct clk_tegra tegra_clk_m_div4_hw = {
104 .hw = {
105 .clk = &tegra_clk_m_div4,
106 },
107 .mul = 1,
108 .div = 4,
109 .max_rate = 12000000,
110};
111DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
112 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
113
114static struct clk tegra_pll_ref;
115static struct clk_tegra tegra_pll_ref_hw = {
116 .hw = {
117 .clk = &tegra_pll_ref,
118 },
119 .flags = ENABLE_ON_INIT,
120 .max_rate = 26000000,
121};
122DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
123 clk_m_div_parents, &tegra_clk_m);
124
125#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
126 _input_max, _cf_min, _cf_max, _vco_min, \
127 _vco_max, _freq_table, _lock_delay, _ops, \
128 _fixed_rate, _clk_cfg_ex, _parent) \
129 static struct clk tegra_##_name; \
130 static const char *_name##_parent_names[] = { \
131 #_parent, \
132 }; \
133 static struct clk *_name##_parents[] = { \
134 &tegra_##_parent, \
135 }; \
136 static struct clk_tegra tegra_##_name##_hw = { \
137 .hw = { \
138 .clk = &tegra_##_name, \
139 }, \
140 .flags = _flags, \
141 .reg = _reg, \
142 .max_rate = _max_rate, \
143 .u.pll = { \
144 .input_min = _input_min, \
145 .input_max = _input_max, \
146 .cf_min = _cf_min, \
147 .cf_max = _cf_max, \
148 .vco_min = _vco_min, \
149 .vco_max = _vco_max, \
150 .freq_table = _freq_table, \
151 .lock_delay = _lock_delay, \
152 .fixed_rate = _fixed_rate, \
153 }, \
154 .clk_cfg_ex = _clk_cfg_ex, \
155 }; \
156 DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
157 _name##_parent_names, _name##_parents, \
158 &tegra_##_parent);
159
160#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
161 _max_rate, _ops, _parent, _clk_flags) \
162 static const char *_name##_parent_names[] = { \
163 #_parent, \
164 }; \
165 static struct clk *_name##_parents[] = { \
166 &tegra_##_parent, \
167 }; \
168 static struct clk tegra_##_name; \
169 static struct clk_tegra tegra_##_name##_hw = { \
170 .hw = { \
171 .clk = &tegra_##_name, \
172 }, \
173 .flags = _flags, \
174 .reg = _reg, \
175 .max_rate = _max_rate, \
176 .reg_shift = _reg_shift, \
177 }; \
178 DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
179 _clk_flags, _name##_parent_names, \
180 _name##_parents, &tegra_##_parent);
181
182static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
183 { 12000000, 1040000000, 520, 6, 1, 8},
184 { 13000000, 1040000000, 480, 6, 1, 8},
185 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
186 { 19200000, 1040000000, 325, 6, 1, 6},
187 { 26000000, 1040000000, 520, 13, 1, 8},
188
189 { 12000000, 832000000, 416, 6, 1, 8},
190 { 13000000, 832000000, 832, 13, 1, 8},
191 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
192 { 19200000, 832000000, 260, 6, 1, 8},
193 { 26000000, 832000000, 416, 13, 1, 8},
194
195 { 12000000, 624000000, 624, 12, 1, 8},
196 { 13000000, 624000000, 624, 13, 1, 8},
197 { 16800000, 600000000, 520, 14, 1, 8},
198 { 19200000, 624000000, 520, 16, 1, 8},
199 { 26000000, 624000000, 624, 26, 1, 8},
200
201 { 12000000, 600000000, 600, 12, 1, 8},
202 { 13000000, 600000000, 600, 13, 1, 8},
203 { 16800000, 600000000, 500, 14, 1, 8},
204 { 19200000, 600000000, 375, 12, 1, 6},
205 { 26000000, 600000000, 600, 26, 1, 8},
206
207 { 12000000, 520000000, 520, 12, 1, 8},
208 { 13000000, 520000000, 520, 13, 1, 8},
209 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
210 { 19200000, 520000000, 325, 12, 1, 6},
211 { 26000000, 520000000, 520, 26, 1, 8},
212
213 { 12000000, 416000000, 416, 12, 1, 8},
214 { 13000000, 416000000, 416, 13, 1, 8},
215 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
216 { 19200000, 416000000, 260, 12, 1, 6},
217 { 26000000, 416000000, 416, 26, 1, 8},
218 { 0, 0, 0, 0, 0, 0 },
219};
220
221DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
222 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
223 tegra30_pll_ops, 0, NULL, pll_ref);
224
225DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
226 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
227
228static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
229 { 12000000, 666000000, 666, 12, 1, 8},
230 { 13000000, 666000000, 666, 13, 1, 8},
231 { 16800000, 666000000, 555, 14, 1, 8},
232 { 19200000, 666000000, 555, 16, 1, 8},
233 { 26000000, 666000000, 666, 26, 1, 8},
234 { 12000000, 600000000, 600, 12, 1, 8},
235 { 13000000, 600000000, 600, 13, 1, 8},
236 { 16800000, 600000000, 500, 14, 1, 8},
237 { 19200000, 600000000, 375, 12, 1, 6},
238 { 26000000, 600000000, 600, 26, 1, 8},
239 { 0, 0, 0, 0, 0, 0 },
240};
241
242DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
243 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
244 300, tegra30_pll_ops, 0, NULL, pll_ref);
245
246DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
247 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
248
249static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
250 { 12000000, 216000000, 432, 12, 2, 8},
251 { 13000000, 216000000, 432, 13, 2, 8},
252 { 16800000, 216000000, 360, 14, 2, 8},
253 { 19200000, 216000000, 360, 16, 2, 8},
254 { 26000000, 216000000, 432, 26, 2, 8},
255 { 0, 0, 0, 0, 0, 0 },
256};
257
258DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
259 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
260 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
261 pll_ref);
262
263DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
264 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
265DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
266 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
267DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
268 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
269DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
270 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
271
272static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
273 { 9600000, 564480000, 294, 5, 1, 4},
274 { 9600000, 552960000, 288, 5, 1, 4},
275 { 9600000, 24000000, 5, 2, 1, 1},
276
277 { 28800000, 56448000, 49, 25, 1, 1},
278 { 28800000, 73728000, 64, 25, 1, 1},
279 { 28800000, 24000000, 5, 6, 1, 1},
280 { 0, 0, 0, 0, 0, 0 },
281};
282
283DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
284 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
285 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
286
287DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
288 pll_a, CLK_IGNORE_UNUSED);
289
290static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
291 { 12000000, 216000000, 216, 12, 1, 4},
292 { 13000000, 216000000, 216, 13, 1, 4},
293 { 16800000, 216000000, 180, 14, 1, 4},
294 { 19200000, 216000000, 180, 16, 1, 4},
295 { 26000000, 216000000, 216, 26, 1, 4},
296
297 { 12000000, 594000000, 594, 12, 1, 8},
298 { 13000000, 594000000, 594, 13, 1, 8},
299 { 16800000, 594000000, 495, 14, 1, 8},
300 { 19200000, 594000000, 495, 16, 1, 8},
301 { 26000000, 594000000, 594, 26, 1, 8},
302
303 { 12000000, 1000000000, 1000, 12, 1, 12},
304 { 13000000, 1000000000, 1000, 13, 1, 12},
305 { 19200000, 1000000000, 625, 12, 1, 8},
306 { 26000000, 1000000000, 1000, 26, 1, 12},
307
308 { 0, 0, 0, 0, 0, 0 },
309};
310
311DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
312 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
313 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
314
315DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
316 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
317
318DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
319 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
320 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
321 pll_ref);
322
323DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
324 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
325
326static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
327 { 12000000, 480000000, 960, 12, 2, 12},
328 { 13000000, 480000000, 960, 13, 2, 12},
329 { 16800000, 480000000, 400, 7, 2, 5},
330 { 19200000, 480000000, 200, 4, 2, 3},
331 { 26000000, 480000000, 960, 26, 2, 12},
332 { 0, 0, 0, 0, 0, 0 },
333};
334
335DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
336 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
337 1000, tegra30_pll_ops, 0, NULL, pll_ref);
338
339static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
340 /* 1.7 GHz */
341 { 12000000, 1700000000, 850, 6, 1, 8},
342 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
343 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
344 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
345 { 26000000, 1700000000, 850, 13, 1, 8},
346
347 /* 1.6 GHz */
348 { 12000000, 1600000000, 800, 6, 1, 8},
349 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
350 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
351 { 19200000, 1600000000, 500, 6, 1, 8},
352 { 26000000, 1600000000, 800, 13, 1, 8},
353
354 /* 1.5 GHz */
355 { 12000000, 1500000000, 750, 6, 1, 8},
356 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
357 { 16800000, 1500000000, 625, 7, 1, 8},
358 { 19200000, 1500000000, 625, 8, 1, 8},
359 { 26000000, 1500000000, 750, 13, 1, 8},
360
361 /* 1.4 GHz */
362 { 12000000, 1400000000, 700, 6, 1, 8},
363 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
364 { 16800000, 1400000000, 1000, 12, 1, 8},
365 { 19200000, 1400000000, 875, 12, 1, 8},
366 { 26000000, 1400000000, 700, 13, 1, 8},
367
368 /* 1.3 GHz */
369 { 12000000, 1300000000, 975, 9, 1, 8},
370 { 13000000, 1300000000, 1000, 10, 1, 8},
371 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
372 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
373 { 26000000, 1300000000, 650, 13, 1, 8},
374
375 /* 1.2 GHz */
376 { 12000000, 1200000000, 1000, 10, 1, 8},
377 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
378 { 16800000, 1200000000, 1000, 14, 1, 8},
379 { 19200000, 1200000000, 1000, 16, 1, 8},
380 { 26000000, 1200000000, 600, 13, 1, 8},
381
382 /* 1.1 GHz */
383 { 12000000, 1100000000, 825, 9, 1, 8},
384 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
385 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
386 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
387 { 26000000, 1100000000, 550, 13, 1, 8},
388
389 /* 1 GHz */
390 { 12000000, 1000000000, 1000, 12, 1, 8},
391 { 13000000, 1000000000, 1000, 13, 1, 8},
392 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
393 { 19200000, 1000000000, 625, 12, 1, 8},
394 { 26000000, 1000000000, 1000, 26, 1, 8},
395
396 { 0, 0, 0, 0, 0, 0 },
397};
398
399DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
400 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
401 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
402
403DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
404 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
405
406static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
407 /* PLLE special case: use cpcon field to store cml divider value */
408 { 12000000, 100000000, 150, 1, 18, 11},
409 { 216000000, 100000000, 200, 18, 24, 13},
410 { 0, 0, 0, 0, 0, 0 },
411};
412
413DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
414 12000000, 12000000, 1200000000, 2400000000U,
415 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
416 pll_ref);
417
418static const char *mux_plle[] = {
419 "pll_e",
420};
421
422static struct clk *mux_plle_p[] = {
423 &tegra_pll_e,
424};
425
426static struct clk tegra_cml0;
427static struct clk_tegra tegra_cml0_hw = {
428 .hw = {
429 .clk = &tegra_cml0,
430 },
431 .reg = 0x48c,
432 .fixed_rate = 100000000,
433 .u.periph = {
434 .clk_num = 0,
435 },
436};
437DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
438 mux_plle_p, &tegra_pll_e);
439
440static struct clk tegra_cml1;
441static struct clk_tegra tegra_cml1_hw = {
442 .hw = {
443 .clk = &tegra_cml1,
444 },
445 .reg = 0x48c,
446 .fixed_rate = 100000000,
447 .u.periph = {
448 .clk_num = 1,
449 },
450};
451DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
452 mux_plle_p, &tegra_pll_e);
453
454static struct clk tegra_pciex;
455static struct clk_tegra tegra_pciex_hw = {
456 .hw = {
457 .clk = &tegra_pciex,
458 },
459 .reg = 0x48c,
460 .fixed_rate = 100000000,
461 .reset = tegra30_periph_clk_reset,
462 .u.periph = {
463 .clk_num = 74,
464 },
465};
466DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
467 mux_plle_p, &tegra_pll_e);
468
469#define SYNC_SOURCE(_name) \
470 static struct clk tegra_##_name##_sync; \
471 static struct clk_tegra tegra_##_name##_sync_hw = { \
472 .hw = { \
473 .clk = &tegra_##_name##_sync, \
474 }, \
475 .max_rate = 24000000, \
476 .fixed_rate = 24000000, \
477 }; \
478 static struct clk tegra_##_name##_sync = { \
479 .name = #_name "_sync", \
480 .hw = &tegra_##_name##_sync_hw.hw, \
481 .ops = &tegra_sync_source_ops, \
482 .flags = CLK_IS_ROOT, \
483 };
484
485SYNC_SOURCE(spdif_in);
486SYNC_SOURCE(i2s0);
487SYNC_SOURCE(i2s1);
488SYNC_SOURCE(i2s2);
489SYNC_SOURCE(i2s3);
490SYNC_SOURCE(i2s4);
491SYNC_SOURCE(vimclk);
492
493static struct clk *tegra_sync_source_list[] = {
494 &tegra_spdif_in_sync,
495 &tegra_i2s0_sync,
496 &tegra_i2s1_sync,
497 &tegra_i2s2_sync,
498 &tegra_i2s3_sync,
499 &tegra_i2s4_sync,
500 &tegra_vimclk_sync,
501};
502
503static const char *mux_audio_sync_clk[] = {
504 "spdif_in_sync",
505 "i2s0_sync",
506 "i2s1_sync",
507 "i2s2_sync",
508 "i2s3_sync",
509 "i2s4_sync",
510 "vimclk_sync",
511};
512
513#define AUDIO_SYNC_CLK(_name, _index) \
514 static struct clk tegra_##_name; \
515 static struct clk_tegra tegra_##_name##_hw = { \
516 .hw = { \
517 .clk = &tegra_##_name, \
518 }, \
519 .max_rate = 24000000, \
520 .reg = 0x4A0 + (_index) * 4, \
521 }; \
522 static struct clk tegra_##_name = { \
523 .name = #_name, \
524 .ops = &tegra30_audio_sync_clk_ops, \
525 .hw = &tegra_##_name##_hw.hw, \
526 .parent_names = mux_audio_sync_clk, \
527 .parents = tegra_sync_source_list, \
528 .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
529 };
530
531AUDIO_SYNC_CLK(audio0, 0);
532AUDIO_SYNC_CLK(audio1, 1);
533AUDIO_SYNC_CLK(audio2, 2);
534AUDIO_SYNC_CLK(audio3, 3);
535AUDIO_SYNC_CLK(audio4, 4);
536AUDIO_SYNC_CLK(audio5, 5);
537
538static struct clk *tegra_clk_audio_list[] = {
539 &tegra_audio0,
540 &tegra_audio1,
541 &tegra_audio2,
542 &tegra_audio3,
543 &tegra_audio4,
544 &tegra_audio5, /* SPDIF */
545};
546
547#define AUDIO_SYNC_2X_CLK(_name, _index) \
548 static const char *_name##_parent_names[] = { \
549 "tegra_" #_name, \
550 }; \
551 static struct clk *_name##_parents[] = { \
552 &tegra_##_name, \
553 }; \
554 static struct clk tegra_##_name##_2x; \
555 static struct clk_tegra tegra_##_name##_2x_hw = { \
556 .hw = { \
557 .clk = &tegra_##_name##_2x, \
558 }, \
559 .flags = PERIPH_NO_RESET, \
560 .max_rate = 48000000, \
561 .reg = 0x49C, \
562 .reg_shift = 24 + (_index), \
563 .u.periph = { \
564 .clk_num = 113 + (_index), \
565 }, \
566 }; \
567 static struct clk tegra_##_name##_2x = { \
568 .name = #_name "_2x", \
569 .ops = &tegra30_clk_double_ops, \
570 .hw = &tegra_##_name##_2x_hw.hw, \
571 .parent_names = _name##_parent_names, \
572 .parents = _name##_parents, \
573 .parent = &tegra_##_name, \
574 .num_parents = 1, \
575 };
576
577AUDIO_SYNC_2X_CLK(audio0, 0);
578AUDIO_SYNC_2X_CLK(audio1, 1);
579AUDIO_SYNC_2X_CLK(audio2, 2);
580AUDIO_SYNC_2X_CLK(audio3, 3);
581AUDIO_SYNC_2X_CLK(audio4, 4);
582AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
583
584static struct clk *tegra_clk_audio_2x_list[] = {
585 &tegra_audio0_2x,
586 &tegra_audio1_2x,
587 &tegra_audio2_2x,
588 &tegra_audio3_2x,
589 &tegra_audio4_2x,
590 &tegra_audio5_2x, /* SPDIF */
591};
592
593#define MUX_I2S_SPDIF(_id) \
594static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
595 "pll_a_out0", \
596 #_id "_2x", \
597 "pll_p", \
598 "clk_m", \
599}; \
600static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
601 &tegra_pll_a_out0, \
602 &tegra_##_id##_2x, \
603 &tegra_pll_p, \
604 &tegra_clk_m, \
605};
606
607MUX_I2S_SPDIF(audio0);
608MUX_I2S_SPDIF(audio1);
609MUX_I2S_SPDIF(audio2);
610MUX_I2S_SPDIF(audio3);
611MUX_I2S_SPDIF(audio4);
612MUX_I2S_SPDIF(audio5); /* SPDIF */
613
614static struct clk tegra_extern1;
615static struct clk tegra_extern2;
616static struct clk tegra_extern3;
617
618/* External clock outputs (through PMC) */
619#define MUX_EXTERN_OUT(_id) \
620static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
621 "clk_m", \
622 "clk_m_div2", \
623 "clk_m_div4", \
624 "extern" #_id, \
625}; \
626static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
627 &tegra_clk_m, \
628 &tegra_clk_m_div2, \
629 &tegra_clk_m_div4, \
630 &tegra_extern##_id, \
631};
632
633MUX_EXTERN_OUT(1);
634MUX_EXTERN_OUT(2);
635MUX_EXTERN_OUT(3);
636
637#define CLK_OUT_CLK(_name, _index) \
638 static struct clk tegra_##_name; \
639 static struct clk_tegra tegra_##_name##_hw = { \
640 .hw = { \
641 .clk = &tegra_##_name, \
642 }, \
643 .lookup = { \
644 .dev_id = #_name, \
645 .con_id = "extern" #_index, \
646 }, \
647 .flags = MUX_CLK_OUT, \
648 .fixed_rate = 216000000, \
649 .reg = 0x1a8, \
650 .u.periph = { \
651 .clk_num = (_index - 1) * 8 + 2, \
652 }, \
653 }; \
654 static struct clk tegra_##_name = { \
655 .name = #_name, \
656 .ops = &tegra_clk_out_ops, \
657 .hw = &tegra_##_name##_hw.hw, \
658 .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
659 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
660 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
661 };
662
663CLK_OUT_CLK(clk_out_1, 1);
664CLK_OUT_CLK(clk_out_2, 2);
665CLK_OUT_CLK(clk_out_3, 3);
666
667static struct clk *tegra_clk_out_list[] = {
668 &tegra_clk_out_1,
669 &tegra_clk_out_2,
670 &tegra_clk_out_3,
671};
672
673static const char *mux_sclk[] = {
674 "clk_m",
675 "pll_c_out1",
676 "pll_p_out4",
677 "pll_p_out3",
678 "pll_p_out2",
679 "dummy",
680 "clk_32k",
681 "pll_m_out1",
682};
683
684static struct clk *mux_sclk_p[] = {
685 &tegra_clk_m,
686 &tegra_pll_c_out1,
687 &tegra_pll_p_out4,
688 &tegra_pll_p_out3,
689 &tegra_pll_p_out2,
690 NULL,
691 &tegra_clk_32k,
692 &tegra_pll_m_out1,
693};
694
695static struct clk tegra_clk_sclk;
696static struct clk_tegra tegra_clk_sclk_hw = {
697 .hw = {
698 .clk = &tegra_clk_sclk,
699 },
700 .reg = 0x28,
701 .max_rate = 334000000,
702 .min_rate = 40000000,
703};
704
705static struct clk tegra_clk_sclk = {
706 .name = "sclk",
707 .ops = &tegra30_super_ops,
708 .hw = &tegra_clk_sclk_hw.hw,
709 .parent_names = mux_sclk,
710 .parents = mux_sclk_p,
711 .num_parents = ARRAY_SIZE(mux_sclk),
712};
713
714static const char *tegra_hclk_parent_names[] = {
715 "tegra_sclk",
716};
717
718static struct clk *tegra_hclk_parents[] = {
719 &tegra_clk_sclk,
720};
721
722static struct clk tegra_hclk;
723static struct clk_tegra tegra_hclk_hw = {
724 .hw = {
725 .clk = &tegra_hclk,
726 },
727 .flags = DIV_BUS,
728 .reg = 0x30,
729 .reg_shift = 4,
730 .max_rate = 378000000,
731 .min_rate = 12000000,
732};
733DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
734 tegra_hclk_parents, &tegra_clk_sclk);
735
736static const char *tegra_pclk_parent_names[] = {
737 "tegra_hclk",
738};
739
740static struct clk *tegra_pclk_parents[] = {
741 &tegra_hclk,
742};
743
744static struct clk tegra_pclk;
745static struct clk_tegra tegra_pclk_hw = {
746 .hw = {
747 .clk = &tegra_pclk,
748 },
749 .flags = DIV_BUS,
750 .reg = 0x30,
751 .reg_shift = 0,
752 .max_rate = 167000000,
753 .min_rate = 12000000,
754};
755DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
756 tegra_pclk_parents, &tegra_hclk);
757
758static const char *mux_blink[] = {
759 "clk_32k",
760};
761
762static struct clk *mux_blink_p[] = {
763 &tegra_clk_32k,
764};
765
766static struct clk tegra_clk_blink;
767static struct clk_tegra tegra_clk_blink_hw = {
768 .hw = {
769 .clk = &tegra_clk_blink,
770 },
771 .reg = 0x40,
772 .max_rate = 32768,
773};
774static struct clk tegra_clk_blink = {
775 .name = "blink",
776 .ops = &tegra30_blink_clk_ops,
777 .hw = &tegra_clk_blink_hw.hw,
778 .parent = &tegra_clk_32k,
779 .parent_names = mux_blink,
780 .parents = mux_blink_p,
781 .num_parents = ARRAY_SIZE(mux_blink),
782};
783
784static const char *mux_pllm_pllc_pllp_plla[] = {
785 "pll_m",
786 "pll_c",
787 "pll_p",
788 "pll_a_out0",
789};
790
791static const char *mux_pllp_pllc_pllm_clkm[] = {
792 "pll_p",
793 "pll_c",
794 "pll_m",
795 "clk_m",
796};
797
798static const char *mux_pllp_clkm[] = {
799 "pll_p",
800 "dummy",
801 "dummy",
802 "clk_m",
803};
804
805static const char *mux_pllp_plld_pllc_clkm[] = {
806 "pll_p",
807 "pll_d_out0",
808 "pll_c",
809 "clk_m",
810};
811
812static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
813 "pll_p",
814 "pll_m",
815 "pll_d_out0",
816 "pll_a_out0",
817 "pll_c",
818 "pll_d2_out0",
819 "clk_m",
820};
821
822static const char *mux_plla_pllc_pllp_clkm[] = {
823 "pll_a_out0",
824 "dummy",
825 "pll_p",
826 "clk_m"
827};
828
829static const char *mux_pllp_pllc_clk32_clkm[] = {
830 "pll_p",
831 "pll_c",
832 "clk_32k",
833 "clk_m",
834};
835
836static const char *mux_pllp_pllc_clkm_clk32[] = {
837 "pll_p",
838 "pll_c",
839 "clk_m",
840 "clk_32k",
841};
842
843static const char *mux_pllp_pllc_pllm[] = {
844 "pll_p",
845 "pll_c",
846 "pll_m",
847};
848
849static const char *mux_clk_m[] = {
850 "clk_m",
851};
852
853static const char *mux_pllp_out3[] = {
854 "pll_p_out3",
855};
856
857static const char *mux_plld_out0[] = {
858 "pll_d_out0",
859};
860
861static const char *mux_plld_out0_plld2_out0[] = {
862 "pll_d_out0",
863 "pll_d2_out0",
864};
865
866static const char *mux_clk_32k[] = {
867 "clk_32k",
868};
869
870static const char *mux_plla_clk32_pllp_clkm_plle[] = {
871 "pll_a_out0",
872 "clk_32k",
873 "pll_p",
874 "clk_m",
875 "pll_e",
876};
877
878static const char *mux_cclk_g[] = {
879 "clk_m",
880 "pll_c",
881 "clk_32k",
882 "pll_m",
883 "pll_p",
884 "pll_p_out4",
885 "pll_p_out3",
886 "dummy",
887 "pll_x",
888};
889
890static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
891 &tegra_pll_m,
892 &tegra_pll_c,
893 &tegra_pll_p,
894 &tegra_pll_a_out0,
895};
896
897static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
898 &tegra_pll_p,
899 &tegra_pll_c,
900 &tegra_pll_m,
901 &tegra_clk_m,
902};
903
904static struct clk *mux_pllp_clkm_p[] = {
905 &tegra_pll_p,
906 NULL,
907 NULL,
908 &tegra_clk_m,
909};
910
911static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
912 &tegra_pll_p,
913 &tegra_pll_d_out0,
914 &tegra_pll_c,
915 &tegra_clk_m,
916};
917
918static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
919 &tegra_pll_p,
920 &tegra_pll_m,
921 &tegra_pll_d_out0,
922 &tegra_pll_a_out0,
923 &tegra_pll_c,
924 &tegra_pll_d2_out0,
925 &tegra_clk_m,
926};
927
928static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
929 &tegra_pll_a_out0,
930 NULL,
931 &tegra_pll_p,
932 &tegra_clk_m,
933};
934
935static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
936 &tegra_pll_p,
937 &tegra_pll_c,
938 &tegra_clk_32k,
939 &tegra_clk_m,
940};
941
942static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
943 &tegra_pll_p,
944 &tegra_pll_c,
945 &tegra_clk_m,
946 &tegra_clk_32k,
947};
948
949static struct clk *mux_pllp_pllc_pllm_p[] = {
950 &tegra_pll_p,
951 &tegra_pll_c,
952 &tegra_pll_m,
953};
954
955static struct clk *mux_clk_m_p[] = {
956 &tegra_clk_m,
957};
958
959static struct clk *mux_pllp_out3_p[] = {
960 &tegra_pll_p_out3,
961};
962
963static struct clk *mux_plld_out0_p[] = {
964 &tegra_pll_d_out0,
965};
966
967static struct clk *mux_plld_out0_plld2_out0_p[] = {
968 &tegra_pll_d_out0,
969 &tegra_pll_d2_out0,
970};
971
972static struct clk *mux_clk_32k_p[] = {
973 &tegra_clk_32k,
974};
975
976static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
977 &tegra_pll_a_out0,
978 &tegra_clk_32k,
979 &tegra_pll_p,
980 &tegra_clk_m,
981 &tegra_pll_e,
982};
983
984static struct clk *mux_cclk_g_p[] = {
985 &tegra_clk_m,
986 &tegra_pll_c,
987 &tegra_clk_32k,
988 &tegra_pll_m,
989 &tegra_pll_p,
990 &tegra_pll_p_out4,
991 &tegra_pll_p_out3,
992 NULL,
993 &tegra_pll_x,
994};
995
996static struct clk tegra_clk_cclk_g;
997static struct clk_tegra tegra_clk_cclk_g_hw = {
998 .hw = {
999 .clk = &tegra_clk_cclk_g,
1000 },
1001 .flags = DIV_U71 | DIV_U71_INT,
1002 .reg = 0x368,
1003 .max_rate = 1700000000,
1004};
1005static struct clk tegra_clk_cclk_g = {
1006 .name = "cclk_g",
1007 .ops = &tegra30_super_ops,
1008 .hw = &tegra_clk_cclk_g_hw.hw,
1009 .parent_names = mux_cclk_g,
1010 .parents = mux_cclk_g_p,
1011 .num_parents = ARRAY_SIZE(mux_cclk_g),
1012};
1013
1014static const char *mux_twd[] = {
1015 "cclk_g",
1016};
1017
1018static struct clk *mux_twd_p[] = {
1019 &tegra_clk_cclk_g,
1020};
1021
1022static struct clk tegra30_clk_twd;
1023static struct clk_tegra tegra30_clk_twd_hw = {
1024 .hw = {
1025 .clk = &tegra30_clk_twd,
1026 },
1027 .max_rate = 1400000000,
1028 .mul = 1,
1029 .div = 2,
1030};
1031
1032static struct clk tegra30_clk_twd = {
1033 .name = "twd",
1034 .ops = &tegra30_twd_ops,
1035 .hw = &tegra30_clk_twd_hw.hw,
1036 .parent = &tegra_clk_cclk_g,
1037 .parent_names = mux_twd,
1038 .parents = mux_twd_p,
1039 .num_parents = ARRAY_SIZE(mux_twd),
1040};
1041
1042#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
1043 _max, _inputs, _flags) \
1044 static struct clk tegra_##_name; \
1045 static struct clk_tegra tegra_##_name##_hw = { \
1046 .hw = { \
1047 .clk = &tegra_##_name, \
1048 }, \
1049 .lookup = { \
1050 .dev_id = _dev, \
1051 .con_id = _con, \
1052 }, \
1053 .reg = _reg, \
1054 .flags = _flags, \
1055 .max_rate = _max, \
1056 .u.periph = { \
1057 .clk_num = _clk_num, \
1058 }, \
1059 .reset = &tegra30_periph_clk_reset, \
1060 }; \
1061 static struct clk tegra_##_name = { \
1062 .name = #_name, \
1063 .ops = &tegra30_periph_clk_ops, \
1064 .hw = &tegra_##_name##_hw.hw, \
1065 .parent_names = _inputs, \
1066 .parents = _inputs##_p, \
1067 .num_parents = ARRAY_SIZE(_inputs), \
1068 };
1069
1070PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
1071PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1072PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
1073PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
1074PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
1075PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1076PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
1077PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
1078PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1079PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1080PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1081PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1082PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1083PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1084PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
1085PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1086PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1087PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1088PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1089PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
1090PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1091PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1092PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
1093PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1094PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1095PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1096PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1097PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1098PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1099PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1100PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1101PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
1102PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1103PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1104PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1105PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1106PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1107PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1108PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
1109PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
1110PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
1111PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
1112PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1113PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
1114PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
1115PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1116PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
1117PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1118PERIPH_CLK(i2c1, "tegra-i2c.0", "div-clk", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1119PERIPH_CLK(i2c2, "tegra-i2c.1", "div-clk", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1120PERIPH_CLK(i2c3, "tegra-i2c.2", "div-clk", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1121PERIPH_CLK(i2c4, "tegra-i2c.3", "div-clk", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1122PERIPH_CLK(i2c5, "tegra-i2c.4", "div-clk", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
1123PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1124PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1125PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1126PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1127PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1128PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1129PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1130PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1131PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1132PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
1133PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1134PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1135PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
1136PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1137PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1138PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
1139PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
1140PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
1141PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1142PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
1143PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1144PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1145PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
1146PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
1147PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
1148PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
1149PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
1150PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
1151PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
1152PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1153PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1154PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
1155PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
1156PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
1157PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
1158PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
1159
1160static struct clk tegra_dsib;
1161static struct clk_tegra tegra_dsib_hw = {
1162 .hw = {
1163 .clk = &tegra_dsib,
1164 },
1165 .lookup = {
1166 .dev_id = "tegradc.1",
1167 .con_id = "dsib",
1168 },
1169 .reg = 0xd0,
1170 .flags = MUX | PLLD,
1171 .max_rate = 500000000,
1172 .u.periph = {
1173 .clk_num = 82,
1174 },
1175 .reset = &tegra30_periph_clk_reset,
1176};
1177static struct clk tegra_dsib = {
1178 .name = "dsib",
1179 .ops = &tegra30_dsib_clk_ops,
1180 .hw = &tegra_dsib_hw.hw,
1181 .parent_names = mux_plld_out0_plld2_out0,
1182 .parents = mux_plld_out0_plld2_out0_p,
1183 .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1184};
1185
1186static struct clk *tegra_list_clks[] = {
1187 &tegra_apbdma,
1188 &tegra_rtc,
1189 &tegra_kbc,
1190 &tegra_timer,
1191 &tegra_kfuse,
1192 &tegra_fuse,
1193 &tegra_fuse_burn,
1194 &tegra_apbif,
1195 &tegra_i2s0,
1196 &tegra_i2s1,
1197 &tegra_i2s2,
1198 &tegra_i2s3,
1199 &tegra_i2s4,
1200 &tegra_spdif_out,
1201 &tegra_spdif_in,
1202 &tegra_pwm,
1203 &tegra_d_audio,
1204 &tegra_dam0,
1205 &tegra_dam1,
1206 &tegra_dam2,
1207 &tegra_hda,
1208 &tegra_hda2codec_2x,
1209 &tegra_hda2hdmi,
1210 &tegra_sbc1,
1211 &tegra_sbc2,
1212 &tegra_sbc3,
1213 &tegra_sbc4,
1214 &tegra_sbc5,
1215 &tegra_sbc6,
1216 &tegra_sata_oob,
1217 &tegra_sata,
1218 &tegra_sata_cold,
1219 &tegra_ndflash,
1220 &tegra_ndspeed,
1221 &tegra_vfir,
1222 &tegra_sdmmc1,
1223 &tegra_sdmmc2,
1224 &tegra_sdmmc3,
1225 &tegra_sdmmc4,
1226 &tegra_vcp,
1227 &tegra_bsea,
1228 &tegra_bsev,
1229 &tegra_vde,
1230 &tegra_csite,
1231 &tegra_la,
1232 &tegra_owr,
1233 &tegra_nor,
1234 &tegra_mipi,
1235 &tegra_i2c1,
1236 &tegra_i2c2,
1237 &tegra_i2c3,
1238 &tegra_i2c4,
1239 &tegra_i2c5,
1240 &tegra_uarta,
1241 &tegra_uartb,
1242 &tegra_uartc,
1243 &tegra_uartd,
1244 &tegra_uarte,
1245 &tegra_vi,
1246 &tegra_3d,
1247 &tegra_3d2,
1248 &tegra_2d,
1249 &tegra_vi_sensor,
1250 &tegra_epp,
1251 &tegra_mpe,
1252 &tegra_host1x,
1253 &tegra_cve,
1254 &tegra_tvo,
1255 &tegra_dtv,
1256 &tegra_hdmi,
1257 &tegra_tvdac,
1258 &tegra_disp1,
1259 &tegra_disp2,
1260 &tegra_usbd,
1261 &tegra_usb2,
1262 &tegra_usb3,
1263 &tegra_dsia,
1264 &tegra_dsib,
1265 &tegra_csi,
1266 &tegra_isp,
1267 &tegra_csus,
1268 &tegra_tsensor,
1269 &tegra_actmon,
1270 &tegra_extern1,
1271 &tegra_extern2,
1272 &tegra_extern3,
1273 &tegra_i2cslow,
1274 &tegra_pcie,
1275 &tegra_afi,
1276 &tegra_se,
1277};
1278
1279#define CLK_DUPLICATE(_name, _dev, _con) \
1280 { \
1281 .name = _name, \
1282 .lookup = { \
1283 .dev_id = _dev, \
1284 .con_id = _con, \
1285 }, \
1286 }
1287
1288/* Some clocks may be used by different drivers depending on the board
1289 * configuration. List those here to register them twice in the clock lookup
1290 * table under two names.
1291 */
1292static struct clk_duplicate tegra_clk_duplicates[] = {
1293 CLK_DUPLICATE("uarta", "serial8250.0", NULL),
1294 CLK_DUPLICATE("uartb", "serial8250.1", NULL),
1295 CLK_DUPLICATE("uartc", "serial8250.2", NULL),
1296 CLK_DUPLICATE("uartd", "serial8250.3", NULL),
1297 CLK_DUPLICATE("uarte", "serial8250.4", NULL),
1298 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1299 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1300 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1301 CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1302 CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1303 CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1304 CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1305 CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1306 CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1307 CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1308 CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1309 CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1310 CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1311 CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1312 CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1313 CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1314 CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1315 CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1316 CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1317 CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1318 CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1319 CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1320 CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1321 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1322 CLK_DUPLICATE("twd", "smp_twd", NULL),
1323 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1324 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1325 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1326 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1327 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1328 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1329 CLK_DUPLICATE("dam0", NULL, "dam0"),
1330 CLK_DUPLICATE("dam1", NULL, "dam1"),
1331 CLK_DUPLICATE("dam2", NULL, "dam2"),
1332 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1333 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1334 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1335 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1336 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1337 CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
1338 CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1339 CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1340 CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
1341};
1342
1343static struct clk *tegra_ptr_clks[] = {
1344 &tegra_clk_32k,
1345 &tegra_clk_m,
1346 &tegra_clk_m_div2,
1347 &tegra_clk_m_div4,
1348 &tegra_pll_ref,
1349 &tegra_pll_m,
1350 &tegra_pll_m_out1,
1351 &tegra_pll_c,
1352 &tegra_pll_c_out1,
1353 &tegra_pll_p,
1354 &tegra_pll_p_out1,
1355 &tegra_pll_p_out2,
1356 &tegra_pll_p_out3,
1357 &tegra_pll_p_out4,
1358 &tegra_pll_a,
1359 &tegra_pll_a_out0,
1360 &tegra_pll_d,
1361 &tegra_pll_d_out0,
1362 &tegra_pll_d2,
1363 &tegra_pll_d2_out0,
1364 &tegra_pll_u,
1365 &tegra_pll_x,
1366 &tegra_pll_x_out0,
1367 &tegra_pll_e,
1368 &tegra_clk_cclk_g,
1369 &tegra_cml0,
1370 &tegra_cml1,
1371 &tegra_pciex,
1372 &tegra_clk_sclk,
1373 &tegra_hclk,
1374 &tegra_pclk,
1375 &tegra_clk_blink,
1376 &tegra30_clk_twd,
1377};
1378
1379static void tegra30_init_one_clock(struct clk *c)
1380{
1381 struct clk_tegra *clk = to_clk_tegra(c->hw);
1382 __clk_init(NULL, c);
1383 INIT_LIST_HEAD(&clk->shared_bus_list);
1384 if (!clk->lookup.dev_id && !clk->lookup.con_id)
1385 clk->lookup.con_id = c->name;
1386 clk->lookup.clk = c;
1387 clkdev_add(&clk->lookup);
1388 tegra_clk_add(c);
1389}
1390
1391void __init tegra30_init_clocks(void)
1392{
1393 int i;
1394 struct clk *c;
1395
1396 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1397 tegra30_init_one_clock(tegra_ptr_clks[i]);
1398
1399 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1400 tegra30_init_one_clock(tegra_list_clks[i]);
1401
1402 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1403 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1404 if (!c) {
1405 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1406 tegra_clk_duplicates[i].name);
1407 continue;
1408 }
1409
1410 tegra_clk_duplicates[i].lookup.clk = c;
1411 clkdev_add(&tegra_clk_duplicates[i].lookup);
1412 }
1413
1414 for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1415 tegra30_init_one_clock(tegra_sync_source_list[i]);
1416 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1417 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1418 for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1419 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1420
1421 for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1422 tegra30_init_one_clock(tegra_clk_out_list[i]);
1423
1424 tegra30_cpu_car_ops_init();
1425}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 00:05:29 -0500