Merge tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here's the big char/misc driver patchset for 4.1-rc1.

  Lots of different driver subsystem updates here, nothing major, full
  details are in the shortlog.

  All of this has been in linux-next for a while"

* tag 'char-misc-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (133 commits)
  mei: trace: remove unused TRACE_SYSTEM_STRING
  DTS: ARM: OMAP3-N900: Add lis3lv02d support
  Documentation: DT: lis302: update wakeup binding
  lis3lv02d: DT: add wakeup unit 2 and wakeup threshold
  lis3lv02d: DT: use s32 to support negative values
  Drivers: hv: hv_balloon: correctly handle num_pages>INT_MAX case
  Drivers: hv: hv_balloon: correctly handle val.freeram<num_pages case
  mei: replace check for connection instead of transitioning
  mei: use mei_cl_is_connected consistently
  mei: fix mei_poll operation
  hv_vmbus: Add gradually increased delay for retries in vmbus_post_msg()
  Drivers: hv: hv_balloon: survive ballooning request with num_pages=0
  Drivers: hv: hv_balloon: eliminate jumps in piecewiese linear floor function
  Drivers: hv: hv_balloon: do not online pages in offline blocks
  hv: remove the per-channel workqueue
  hv: don't schedule new works in vmbus_onoffer()/vmbus_onoffer_rescind()
  hv: run non-blocking message handlers in the dispatch tasklet
  coresight: moving to new "hwtracing" directory
  coresight-tmc: Adding a status interface to sysfs
  coresight: remove the unnecessary configuration coresight-default-sink
  ...

9 files changed, 58 insertions, 58 deletions

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de7518341..8b0183a9a300 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1610,59 +1610,6 @@ config DEBUG_SET_MODULE_RONX
           against certain classes of kernel exploits.
           If in doubt, say "N".
 
-menuconfig CORESIGHT
-        bool "CoreSight Tracing Support"
-        select ARM_AMBA
-        help
-          This framework provides a kernel interface for the CoreSight debug
-          and trace drivers to register themselves with. It's intended to build
-          a topological view of the CoreSight components based on a DT
-          specification and configure the right serie of components when a
-          trace source gets enabled.
-
-if CORESIGHT
-config CORESIGHT_LINKS_AND_SINKS
-        bool "CoreSight Link and Sink drivers"
-        help
-          This enables support for CoreSight link and sink drivers that are
-          responsible for transporting and collecting the trace data
-          respectively.  Link and sinks are dynamically aggregated with a trace
-          entity at run time to form a complete trace path.
-
-config CORESIGHT_LINK_AND_SINK_TMC
-        bool "Coresight generic TMC driver"
-        depends on CORESIGHT_LINKS_AND_SINKS
-        help
-          This enables support for the Trace Memory Controller driver.  Depending
-          on its configuration the device can act as a link (embedded trace router
-          - ETR) or sink (embedded trace FIFO).  The driver complies with the
-          generic implementation of the component without special enhancement or
-          added features.
-
-config CORESIGHT_SINK_TPIU
-        bool "Coresight generic TPIU driver"
-        depends on CORESIGHT_LINKS_AND_SINKS
-        help
-          This enables support for the Trace Port Interface Unit driver, responsible
-          for bridging the gap between the on-chip coresight components and a trace
-          port collection engine, typically connected to an external host for use
-          case capturing more traces than the on-board coresight memory can handle.
-
-config CORESIGHT_SINK_ETBV10
-        bool "Coresight ETBv1.0 driver"
-        depends on CORESIGHT_LINKS_AND_SINKS
-        help
-          This enables support for the Embedded Trace Buffer version 1.0 driver
-          that complies with the generic implementation of the component without
-          special enhancement or added features.
+source "drivers/hwtracing/coresight/Kconfig"
 
-config CORESIGHT_SOURCE_ETM3X
-        bool "CoreSight Embedded Trace Macrocell 3.x driver"
-        select CORESIGHT_LINKS_AND_SINKS
-        help
-          This driver provides support for processor ETM3.x and PTM1.x modules,
-          which allows tracing the instructions that a processor is executing
-          This is primarily useful for instruction level tracing.  Depending
-          the ETM version data tracing may also be available.
-endif
 endmenu
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 238814596a87..44044f275115 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -275,7 +275,6 @@
                 compatible = "arm,coresight-etb10", "arm,primecell";
                 reg = <0 0xe3c42000 0 0x1000>;
 
-                coresight-default-sink;
                 clocks = <&clk_375m>;
                 clock-names = "apb_pclk";
                 port {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 25f7b0a22114..8cdca51b6984 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -150,7 +150,6 @@
                 compatible = "arm,coresight-etb10", "arm,primecell";
                 reg = <0x5401b000 0x1000>;
 
-                coresight-default-sink;
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
                 port {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index c792391ef090..6d4c46be8c39 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -145,7 +145,6 @@
                 compatible = "arm,coresight-etb10", "arm,primecell";
                 reg = <0x5401b000 0x1000>;
 
-                coresight-default-sink;
                 clocks = <&emu_src_ck>;
                 clock-names = "apb_pclk";
                 port {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index db80f9d376fa..2cab149b191c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -609,6 +609,58 @@
         pinctrl-0 = <&i2c3_pins>;
 
         clock-frequency = <400000>;
+
+        lis302dl: lis3lv02d@1d {
+                compatible = "st,lis3lv02d";
+                reg = <0x1d>;
+
+                Vdd-supply = <&vaux1>;
+                Vdd_IO-supply = <&vio>;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <21 20>; /* 181 and 180 */
+
+                /* click flags */
+                st,click-single-x;
+                st,click-single-y;
+                st,click-single-z;
+
+                /* Limits are 0.5g * value */
+                st,click-threshold-x = <8>;
+                st,click-threshold-y = <8>;
+                st,click-threshold-z = <10>;
+
+                /* Click must be longer than time limit */
+                st,click-time-limit = <9>;
+
+                /* Kind of debounce filter */
+                st,click-latency = <50>;
+
+                /* Interrupt line 2 for click detection */
+                st,irq2-click;
+
+                st,wakeup-x-hi;
+                st,wakeup-y-hi;
+                st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
+
+                st,wakeup2-z-hi;
+                st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */
+
+                st,hipass1-disable;
+                st,hipass2-disable;
+
+                st,axis-x = <1>;    /* LIS3_DEV_X */
+                st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
+                st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
+
+                st,min-limit-x = <(-32)>;
+                st,min-limit-y = <3>;
+                st,min-limit-z = <3>;
+
+                st,max-limit-x = <(-3)>;
+                st,max-limit-y = <32>;
+                st,max-limit-z = <32>;
+        };
 };
 
 &mmc1 {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 33920df03640..7a2aeacd62c0 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -362,7 +362,6 @@
                 compatible = "arm,coresight-etb10", "arm,primecell";
                 reg = <0 0x20010000 0 0x1000>;
 
-                coresight-default-sink;
                 clocks = <&oscclk6a>;
                 clock-names = "apb_pclk";
                 port {
diff --git a/arch/arm64/Kconfig.debug b/arch/arm64/Kconfig.debug
index 4a8741073c90..d6285ef9b5f9 100644
--- a/arch/arm64/Kconfig.debug
+++ b/arch/arm64/Kconfig.debug
@@ -89,4 +89,6 @@ config DEBUG_ALIGN_RODATA
 
           If in doubt, say N
 
+source "drivers/hwtracing/coresight/Kconfig"
+
 endmenu
diff --git a/arch/m32r/include/asm/io.h b/arch/m32r/include/asm/io.h
index 6e7787f3dac7..9cc00dbd59ce 100644
--- a/arch/m32r/include/asm/io.h
+++ b/arch/m32r/include/asm/io.h
@@ -67,6 +67,7 @@ static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
 
 extern void iounmap(volatile void __iomem *addr);
 #define ioremap_nocache(off,size) ioremap(off,size)
+#define ioremap_wc ioremap_nocache
 
 /*
  * IO bus memory addresses are also 1:1 with the physical address
diff --git a/arch/x86/include/uapi/asm/hyperv.h b/arch/x86/include/uapi/asm/hyperv.h
index 90c458e66e13..ce6068dbcfbc 100644
--- a/arch/x86/include/uapi/asm/hyperv.h
+++ b/arch/x86/include/uapi/asm/hyperv.h
@@ -225,6 +225,8 @@
 #define HV_STATUS_INVALID_HYPERCALL_CODE        2
 #define HV_STATUS_INVALID_HYPERCALL_INPUT       3
 #define HV_STATUS_INVALID_ALIGNMENT             4
+#define HV_STATUS_INSUFFICIENT_MEMORY           11
+#define HV_STATUS_INVALID_CONNECTION_ID         18
 #define HV_STATUS_INSUFFICIENT_BUFFERS          19
 
 typedef struct _HV_REFERENCE_TSC_PAGE {