Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf updates from Ingo Molnar:
 "As a first remark I'd like to note that the way to build perf tooling
  has been simplified and sped up, in the future it should be enough for
  you to build perf via:

        cd tools/perf/
        make install

  (ie without the -j option.) The build system will figure out the
  number of CPUs and will do a parallel build+install.

  The various build system inefficiencies and breakages Linus reported
  against the v3.12 pull request should now be resolved - please
  (re-)report any remaining annoyances or bugs.

  Main changes on the perf kernel side:

   * Performance optimizations:
      . perf ring-buffer code optimizations,          by Peter Zijlstra
      . perf ring-buffer code optimizations,          by Oleg Nesterov
      . x86 NMI call-stack processing optimizations,  by Peter Zijlstra
      . perf context-switch optimizations,            by Peter Zijlstra
      . perf sampling speedups,                       by Peter Zijlstra
      . x86 Intel PEBS processing speedups,           by Peter Zijlstra

   * Enhanced hardware support:
      . for Intel Ivy Bridge-EP uncore PMUs,          by Zheng Yan
      . for Haswell transactions,                     by Andi Kleen, Peter Zijlstra

   * Core perf events code enhancements and fixes by Oleg Nesterov:
      . for uprobes, if fork() is called with pending ret-probes
      . for uprobes platform support code

   * New ABI details by Andi Kleen:
      . Report x86 Haswell TSX transaction abort cost as weight

  Main changes on the perf tooling side (some of these tooling changes
  utilize the above kernel side changes):

   * 'perf report/top' enhancements:

      . Convert callchain children list to rbtree, greatly reducing the
        time taken for callchain processing, from Namhyung Kim.

      . Add new COMM infrastructure, further improving histogram
        processing, from Frédéric Weisbecker, one fix from Namhyung Kim.

      . Add /proc/kcore based live-annotation improvements, including
        build-id cache support, multi map 'call' instruction navigation
        fixes, kcore address validation, objdump workarounds.  From
        Adrian Hunter.

      . Show progress on histogram collapsing, that can take a long
        time, from Namhyung Kim.

      . Add --max-stack option to limit callchain stack scan in 'top'
        and 'report', improving callchain processing when reducing the
        stack depth is an option, from Waiman Long.

      . Add new option --ignore-vmlinux for perf top, from Willy
        Tarreau.

   * 'perf trace' enhancements:

      . 'perf trace' now can can use a 'perf probe' dynamic tracepoints
        to hook into the userspace -> kernel pathname copy so that it
        can map fds to pathnames without reading /proc/pid/fd/ symlinks.
        From Arnaldo Carvalho de Melo.

      . Show VFS path associated with fd in live sessions, using a
        'vfs_getname' 'perf probe' created dynamic tracepoint or by
        looking at /proc/pid/fd, from Arnaldo Carvalho de Melo.

      . Add 'trace' beautifiers for lots of syscall arguments, from
        Arnaldo Carvalho de Melo.

      . Implement more compact 'trace' output by suppressing zeroed
        args, from Arnaldo Carvalho de Melo.

      . Show thread COMM by default in 'trace', from Arnaldo Carvalho de
        Melo.

      . Add option to show full timestamp in 'trace', from David Ahern.

      . Add 'record' command in 'trace', to record raw_syscalls:*, from
        David Ahern.

      . Add summary option to dump syscall statistics in 'trace', from
        David Ahern.

      . Improve error messages in 'trace', providing hints about system
        configuration steps needed for using it, from Ramkumar
        Ramachandra.

      . 'perf trace' now emits hints as to why tracing is not possible,
        helping the user to setup the system to allow tracing in the
        desired permission granularity, telling if the problem is due to
        debugfs not being mounted or with not enough permission for
        !root, /proc/sys/kernel/perf_event_paranoit value, etc.  From
        Arnaldo Carvalho de Melo.

   * 'perf record' enhancements:

      . Check maximum frequency rate for record/top, emitting better
        error messages, from Jiri Olsa.

      . 'perf record' code cleanups, from David Ahern.

      . Improve write_output error message in 'perf record', from Adrian
        Hunter.

      . Allow specifying B/K/M/G unit to the --mmap-pages arguments,
        from Jiri Olsa.

      . Fix command line callchain attribute tests to handle the new
        -g/--call-chain semantics, from Arnaldo Carvalho de Melo.

   * 'perf kvm' enhancements:

      . Disable live kvm command if timerfd is not supported, from David
        Ahern.

      . Fix detection of non-core features, from David Ahern.

   * 'perf list' enhancements:

      . Add usage to 'perf list', from David Ahern.

      . Show error in 'perf list' if tracepoints not available, from
        Pekka Enberg.

   * 'perf probe' enhancements:

      . Support "$vars" meta argument syntax for local variables,
        allowing asking for all possible variables at a given probe
        point to be collected when it hits, from Masami Hiramatsu.

   * 'perf sched' enhancements:

      . Address the root cause of that 'perf sched' stack initialization
        build slowdown, by programmatically setting a big array after
        moving the global variable back to the stack.  Fix from Adrian
        Hunter.

   * 'perf script' enhancements:

      . Set up output options for in-stream attributes, from Adrian
        Hunter.

      . Print addr by default for BTS in 'perf script', from Adrian
        Juntmer

   * 'perf stat' enhancements:

      . Improved messages when doing profiling in all or a subset of
        CPUs using a workload as the session delimitator, as in:

         'perf stat --cpu 0,2 sleep 10s'

        from Arnaldo Carvalho de Melo.

      . Add units to nanosec-based counters in 'perf stat', from David
        Ahern.

      . Remove bogus info when using 'perf stat' -e cycles/instructions,
        from Ramkumar Ramachandra.

   * 'perf lock' enhancements:

      . 'perf lock' fixes and cleanups, from Davidlohr Bueso.

   * 'perf test' enhancements:

      . Fixup PERF_SAMPLE_TRANSACTION handling in sample synthesizing
        and 'perf test', from Adrian Hunter.

      . Clarify the "sample parsing" test entry, from Arnaldo Carvalho
        de Melo.

      . Consider PERF_SAMPLE_TRANSACTION in the "sample parsing" test,
        from Arnaldo Carvalho de Melo.

      . Memory leak fixes in 'perf test', from Felipe Pena.

   * 'perf bench' enhancements:

      . Change the procps visible command-name of invididual benchmark
        tests plus cleanups, from Ingo Molnar.

   * Generic perf tooling infrastructure/plumbing changes:

      . Separating data file properties from session, code
        reorganization from Jiri Olsa.

      . Fix version when building out of tree, as when using one of
        these:

        $ make help | grep perf
          perf-tar-src-pkg    - Build perf-3.12.0.tar source tarball
          perf-targz-src-pkg  - Build perf-3.12.0.tar.gz source tarball
          perf-tarbz2-src-pkg - Build perf-3.12.0.tar.bz2 source tarball
          perf-tarxz-src-pkg  - Build perf-3.12.0.tar.xz source tarball
        $

        from David Ahern.

      . Enhance option parse error message, showing just the help lines
        of the options affected, from Namhyung Kim.

      . libtraceevent updates from upstream trace-cmd repo, from Steven
        Rostedt.

      . Always use perf_evsel__set_sample_bit to set sample_type, from
        Adrian Hunter.

      . Memory and mmap leak fixes from Chenggang Qin.

      . Assorted build fixes for from David Ahern and Jiri Olsa.

      . Speed up and prettify the build system, from Ingo Molnar.

      . Implement addr2line directly using libbfd, from Roberto Vitillo.

      . Separate the GTK support in a separate libperf-gtk.so DSO, that
        is only loaded when --gtk is specified, from Namhyung Kim.

      . perf bash completion fixes and improvements from Ramkumar
        Ramachandra.

      . Support for Openembedded/Yocto -dbg packages, from Ricardo
        Ribalda Delgado.

  And lots and lots of other fixes and code reorganizations that did not
  make it into the list, see the shortlog, diffstat and the Git log for
  details!"

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (300 commits)
  uprobes: Fix the memory out of bound overwrite in copy_insn()
  uprobes: Fix the wrong usage of current->utask in uprobe_copy_process()
  perf tools: Remove unneeded include
  perf record: Remove post_processing_offset variable
  perf record: Remove advance_output function
  perf record: Refactor feature handling into a separate function
  perf trace: Don't relookup fields by name in each sample
  perf tools: Fix version when building out of tree
  perf evsel: Ditch evsel->handler.data field
  uprobes: Export write_opcode() as uprobe_write_opcode()
  uprobes: Introduce arch_uprobe->ixol
  uprobes: Kill module_init() and module_exit()
  uprobes: Move function declarations out of arch
  perf/x86/intel: Add Ivy Bridge-EP uncore IRP box support
  perf/x86/intel/uncore: Add filter support for IvyBridge-EP QPI boxes
  perf: Factor out strncpy() in perf_event_mmap_event()
  tools/perf: Add required memory barriers
  perf: Fix arch_perf_out_copy_user default
  perf: Update a stale comment
  perf: Optimize perf_output_begin() -- address calculation
  ...

6 files changed, 342 insertions, 114 deletions

diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 8a87a3224121..8e132931614d 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -1989,7 +1989,7 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
                 frame.return_address = 0;
 
                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
-                if (bytes != sizeof(frame))
+                if (bytes != 0)
                         break;
 
                 if (!valid_user_frame(fp, sizeof(frame)))
@@ -2041,7 +2041,7 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                 frame.return_address = 0;
 
                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
-                if (bytes != sizeof(frame))
+                if (bytes != 0)
                         break;
 
                 if (!valid_user_frame(fp, sizeof(frame)))
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index cc16faae0538..fd00bb29425d 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -164,6 +164,11 @@ struct cpu_hw_events {
         struct perf_guest_switch_msr    guest_switch_msrs[X86_PMC_IDX_MAX];
 
         /*
+         * Intel checkpoint mask
+         */
+        u64                             intel_cp_status;
+
+        /*
          * manage shared (per-core, per-cpu) registers
          * used on Intel NHM/WSM/SNB
          */
@@ -440,6 +445,7 @@ struct x86_pmu {
         int             lbr_nr;                    /* hardware stack size */
         u64             lbr_sel_mask;              /* LBR_SELECT valid bits */
         const int       *lbr_sel_map;              /* lbr_select mappings */
+        bool            lbr_double_abort;          /* duplicated lbr aborts */
 
         /*
          * Extra registers for events
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f31a1655d1ff..0fa4f242f050 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -190,9 +190,9 @@ static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
         EVENT_EXTRA_END
 };
 
-EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
-EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
+EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
+EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 
 struct attribute *nhm_events_attrs[] = {
         EVENT_PTR(mem_ld_nhm),
@@ -1184,6 +1184,11 @@ static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
         wrmsrl(hwc->config_base, ctrl_val);
 }
 
+static inline bool event_is_checkpointed(struct perf_event *event)
+{
+        return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
+}
+
 static void intel_pmu_disable_event(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
@@ -1197,6 +1202,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
 
         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
+        cpuc->intel_cp_status &= ~(1ull << hwc->idx);
 
         /*
          * must disable before any actual event
@@ -1271,6 +1277,9 @@ static void intel_pmu_enable_event(struct perf_event *event)
         if (event->attr.exclude_guest)
                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
 
+        if (unlikely(event_is_checkpointed(event)))
+                cpuc->intel_cp_status |= (1ull << hwc->idx);
+
         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                 intel_pmu_enable_fixed(hwc);
                 return;
@@ -1289,6 +1298,17 @@ static void intel_pmu_enable_event(struct perf_event *event)
 int intel_pmu_save_and_restart(struct perf_event *event)
 {
         x86_perf_event_update(event);
+        /*
+         * For a checkpointed counter always reset back to 0.  This
+         * avoids a situation where the counter overflows, aborts the
+         * transaction and is then set back to shortly before the
+         * overflow, and overflows and aborts again.
+         */
+        if (unlikely(event_is_checkpointed(event))) {
+                /* No race with NMIs because the counter should not be armed */
+                wrmsrl(event->hw.event_base, 0);
+                local64_set(&event->hw.prev_count, 0);
+        }
         return x86_perf_event_set_period(event);
 }
 
@@ -1372,6 +1392,13 @@ again:
                 x86_pmu.drain_pebs(regs);
         }
 
+        /*
+         * Checkpointed counters can lead to 'spurious' PMIs because the
+         * rollback caused by the PMI will have cleared the overflow status
+         * bit. Therefore always force probe these counters.
+         */
+        status |= cpuc->intel_cp_status;
+
         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
                 struct perf_event *event = cpuc->events[bit];
 
@@ -1837,6 +1864,20 @@ static int hsw_hw_config(struct perf_event *event)
               event->attr.precise_ip > 0))
                 return -EOPNOTSUPP;
 
+        if (event_is_checkpointed(event)) {
+                /*
+                 * Sampling of checkpointed events can cause situations where
+                 * the CPU constantly aborts because of a overflow, which is
+                 * then checkpointed back and ignored. Forbid checkpointing
+                 * for sampling.
+                 *
+                 * But still allow a long sampling period, so that perf stat
+                 * from KVM works.
+                 */
+                if (event->attr.sample_period > 0 &&
+                    event->attr.sample_period < 0x7fffffff)
+                        return -EOPNOTSUPP;
+        }
         return 0;
 }
 
@@ -2182,10 +2223,36 @@ static __init void intel_nehalem_quirk(void)
         }
 }
 
-EVENT_ATTR_STR(mem-loads,      mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores,     mem_st_hsw,     "event=0xd0,umask=0x82")
+EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
+
+/* Haswell special events */
+EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
+EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
+EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
+EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
+EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
+EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
+EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
+EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
+EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
+EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
+EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
+EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
 
 static struct attribute *hsw_events_attrs[] = {
+        EVENT_PTR(tx_start),
+        EVENT_PTR(tx_commit),
+        EVENT_PTR(tx_abort),
+        EVENT_PTR(tx_capacity),
+        EVENT_PTR(tx_conflict),
+        EVENT_PTR(el_start),
+        EVENT_PTR(el_commit),
+        EVENT_PTR(el_abort),
+        EVENT_PTR(el_capacity),
+        EVENT_PTR(el_conflict),
+        EVENT_PTR(cycles_t),
+        EVENT_PTR(cycles_ct),
         EVENT_PTR(mem_ld_hsw),
         EVENT_PTR(mem_st_hsw),
         NULL
@@ -2452,6 +2519,7 @@ __init int intel_pmu_init(void)
                 x86_pmu.hw_config = hsw_hw_config;
                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
                 x86_pmu.cpu_events = hsw_events_attrs;
+                x86_pmu.lbr_double_abort = true;
                 pr_cont("Haswell events, ");
                 break;
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index ab3ba1c1b7dd..ae96cfa5eddd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -12,6 +12,7 @@
 
 #define BTS_BUFFER_SIZE         (PAGE_SIZE << 4)
 #define PEBS_BUFFER_SIZE        PAGE_SIZE
+#define PEBS_FIXUP_SIZE         PAGE_SIZE
 
 /*
  * pebs_record_32 for p4 and core not supported
@@ -182,18 +183,32 @@ struct pebs_record_nhm {
  * Same as pebs_record_nhm, with two additional fields.
  */
 struct pebs_record_hsw {
-        struct pebs_record_nhm nhm;
-        /*
-         * Real IP of the event. In the Intel documentation this
-         * is called eventingrip.
-         */
-        u64 real_ip;
-        /*
-         * TSX tuning information field: abort cycles and abort flags.
-         */
-        u64 tsx_tuning;
+        u64 flags, ip;
+        u64 ax, bx, cx, dx;
+        u64 si, di, bp, sp;
+        u64 r8,  r9,  r10, r11;
+        u64 r12, r13, r14, r15;
+        u64 status, dla, dse, lat;
+        u64 real_ip, tsx_tuning;
+};
+
+union hsw_tsx_tuning {
+        struct {
+                u32 cycles_last_block     : 32,
+                    hle_abort             : 1,
+                    rtm_abort             : 1,
+                    instruction_abort     : 1,
+                    non_instruction_abort : 1,
+                    retry                 : 1,
+                    data_conflict         : 1,
+                    capacity_writes       : 1,
+                    capacity_reads        : 1;
+        };
+        u64         value;
 };
 
+#define PEBS_HSW_TSX_FLAGS      0xff00000000ULL
+
 void init_debug_store_on_cpu(int cpu)
 {
         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
@@ -214,12 +229,14 @@ void fini_debug_store_on_cpu(int cpu)
         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
 }
 
+static DEFINE_PER_CPU(void *, insn_buffer);
+
 static int alloc_pebs_buffer(int cpu)
 {
         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
         int node = cpu_to_node(cpu);
         int max, thresh = 1; /* always use a single PEBS record */
-        void *buffer;
+        void *buffer, *ibuffer;
 
         if (!x86_pmu.pebs)
                 return 0;
@@ -228,6 +245,19 @@ static int alloc_pebs_buffer(int cpu)
         if (unlikely(!buffer))
                 return -ENOMEM;
 
+        /*
+         * HSW+ already provides us the eventing ip; no need to allocate this
+         * buffer then.
+         */
+        if (x86_pmu.intel_cap.pebs_format < 2) {
+                ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
+                if (!ibuffer) {
+                        kfree(buffer);
+                        return -ENOMEM;
+                }
+                per_cpu(insn_buffer, cpu) = ibuffer;
+        }
+
         max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size;
 
         ds->pebs_buffer_base = (u64)(unsigned long)buffer;
@@ -248,6 +278,9 @@ static void release_pebs_buffer(int cpu)
         if (!ds || !x86_pmu.pebs)
                 return;
 
+        kfree(per_cpu(insn_buffer, cpu));
+        per_cpu(insn_buffer, cpu) = NULL;
+
         kfree((void *)(unsigned long)ds->pebs_buffer_base);
         ds->pebs_buffer_base = 0;
 }
@@ -715,6 +748,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
         unsigned long old_to, to = cpuc->lbr_entries[0].to;
         unsigned long ip = regs->ip;
         int is_64bit = 0;
+        void *kaddr;
 
         /*
          * We don't need to fixup if the PEBS assist is fault like
@@ -738,7 +772,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
          * unsigned math, either ip is before the start (impossible) or
          * the basic block is larger than 1 page (sanity)
          */
-        if ((ip - to) > PAGE_SIZE)
+        if ((ip - to) > PEBS_FIXUP_SIZE)
                 return 0;
 
         /*
@@ -749,29 +783,33 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
                 return 1;
         }
 
+        if (!kernel_ip(ip)) {
+                int size, bytes;
+                u8 *buf = this_cpu_read(insn_buffer);
+
+                size = ip - to; /* Must fit our buffer, see above */
+                bytes = copy_from_user_nmi(buf, (void __user *)to, size);
+                if (bytes != 0)
+                        return 0;
+
+                kaddr = buf;
+        } else {
+                kaddr = (void *)to;
+        }
+
         do {
                 struct insn insn;
-                u8 buf[MAX_INSN_SIZE];
-                void *kaddr;
 
                 old_to = to;
-                if (!kernel_ip(ip)) {
-                        int bytes, size = MAX_INSN_SIZE;
-
-                        bytes = copy_from_user_nmi(buf, (void __user *)to, size);
-                        if (bytes != size)
-                                return 0;
-
-                        kaddr = buf;
-                } else
-                        kaddr = (void *)to;
 
 #ifdef CONFIG_X86_64
                 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
 #endif
                 insn_init(&insn, kaddr, is_64bit);
                 insn_get_length(&insn);
+
                 to += insn.length;
+                kaddr += insn.length;
         } while (to < ip);
 
         if (to == ip) {
@@ -786,16 +824,34 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
         return 0;
 }
 
+static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)
+{
+        if (pebs->tsx_tuning) {
+                union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
+                return tsx.cycles_last_block;
+        }
+        return 0;
+}
+
+static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)
+{
+        u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
+
+        /* For RTM XABORTs also log the abort code from AX */
+        if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
+                txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
+        return txn;
+}
+
 static void __intel_pmu_pebs_event(struct perf_event *event,
                                    struct pt_regs *iregs, void *__pebs)
 {
         /*
-         * We cast to pebs_record_nhm to get the load latency data
-         * if extra_reg MSR_PEBS_LD_LAT_THRESHOLD used
+         * We cast to the biggest pebs_record but are careful not to
+         * unconditionally access the 'extra' entries.
          */
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct pebs_record_nhm *pebs = __pebs;
-        struct pebs_record_hsw *pebs_hsw = __pebs;
+        struct pebs_record_hsw *pebs = __pebs;
         struct perf_sample_data data;
         struct pt_regs regs;
         u64 sample_type;
@@ -854,7 +910,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
         regs.sp = pebs->sp;
 
         if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
-                regs.ip = pebs_hsw->real_ip;
+                regs.ip = pebs->real_ip;
                 regs.flags |= PERF_EFLAGS_EXACT;
         } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
                 regs.flags |= PERF_EFLAGS_EXACT;
@@ -862,9 +918,18 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
                 regs.flags &= ~PERF_EFLAGS_EXACT;
 
         if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
-                x86_pmu.intel_cap.pebs_format >= 1)
+            x86_pmu.intel_cap.pebs_format >= 1)
                 data.addr = pebs->dla;
 
+        if (x86_pmu.intel_cap.pebs_format >= 2) {
+                /* Only set the TSX weight when no memory weight. */
+                if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) && !fll)
+                        data.weight = intel_hsw_weight(pebs);
+
+                if (event->attr.sample_type & PERF_SAMPLE_TRANSACTION)
+                        data.txn = intel_hsw_transaction(pebs);
+        }
+
         if (has_branch_stack(event))
                 data.br_stack = &cpuc->lbr_stack;
 
@@ -913,17 +978,34 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
         __intel_pmu_pebs_event(event, iregs, at);
 }
 
-static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
-                                        void *top)
+static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct debug_store *ds = cpuc->ds;
         struct perf_event *event = NULL;
+        void *at, *top;
         u64 status = 0;
         int bit;
 
+        if (!x86_pmu.pebs_active)
+                return;
+
+        at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
+        top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
+
         ds->pebs_index = ds->pebs_buffer_base;
 
+        if (unlikely(at > top))
+                return;
+
+        /*
+         * Should not happen, we program the threshold at 1 and do not
+         * set a reset value.
+         */
+        WARN_ONCE(top - at > x86_pmu.max_pebs_events * x86_pmu.pebs_record_size,
+                  "Unexpected number of pebs records %ld\n",
+                  (long)(top - at) / x86_pmu.pebs_record_size);
+
         for (; at < top; at += x86_pmu.pebs_record_size) {
                 struct pebs_record_nhm *p = at;
 
@@ -951,61 +1033,6 @@ static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
         }
 }
 
-static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct debug_store *ds = cpuc->ds;
-        struct pebs_record_nhm *at, *top;
-        int n;
-
-        if (!x86_pmu.pebs_active)
-                return;
-
-        at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
-        top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
-
-        ds->pebs_index = ds->pebs_buffer_base;
-
-        n = top - at;
-        if (n <= 0)
-                return;
-
-        /*
-         * Should not happen, we program the threshold at 1 and do not
-         * set a reset value.
-         */
-        WARN_ONCE(n > x86_pmu.max_pebs_events,
-                  "Unexpected number of pebs records %d\n", n);
-
-        return __intel_pmu_drain_pebs_nhm(iregs, at, top);
-}
-
-static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        struct debug_store *ds = cpuc->ds;
-        struct pebs_record_hsw *at, *top;
-        int n;
-
-        if (!x86_pmu.pebs_active)
-                return;
-
-        at  = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
-        top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
-
-        n = top - at;
-        if (n <= 0)
-                return;
-        /*
-         * Should not happen, we program the threshold at 1 and do not
-         * set a reset value.
-         */
-        WARN_ONCE(n > x86_pmu.max_pebs_events,
-                  "Unexpected number of pebs records %d\n", n);
-
-        return __intel_pmu_drain_pebs_nhm(iregs, at, top);
-}
-
 /*
  * BTS, PEBS probe and setup
  */
@@ -1040,7 +1067,7 @@ void intel_ds_init(void)
                 case 2:
                         pr_cont("PEBS fmt2%c, ", pebs_type);
                         x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
-                        x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
+                        x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
                         break;
 
                 default:
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index d5be06a5005e..d82d155aca8c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -284,6 +284,7 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
         int lbr_format = x86_pmu.intel_cap.lbr_format;
         u64 tos = intel_pmu_lbr_tos();
         int i;
+        int out = 0;
 
         for (i = 0; i < x86_pmu.lbr_nr; i++) {
                 unsigned long lbr_idx = (tos - i) & mask;
@@ -306,15 +307,27 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
                 }
                 from = (u64)((((s64)from) << skip) >> skip);
 
-                cpuc->lbr_entries[i].from       = from;
-                cpuc->lbr_entries[i].to         = to;
-                cpuc->lbr_entries[i].mispred    = mis;
-                cpuc->lbr_entries[i].predicted  = pred;
-                cpuc->lbr_entries[i].in_tx      = in_tx;
-                cpuc->lbr_entries[i].abort      = abort;
-                cpuc->lbr_entries[i].reserved   = 0;
+                /*
+                 * Some CPUs report duplicated abort records,
+                 * with the second entry not having an abort bit set.
+                 * Skip them here. This loop runs backwards,
+                 * so we need to undo the previous record.
+                 * If the abort just happened outside the window
+                 * the extra entry cannot be removed.
+                 */
+                if (abort && x86_pmu.lbr_double_abort && out > 0)
+                        out--;
+
+                cpuc->lbr_entries[out].from      = from;
+                cpuc->lbr_entries[out].to        = to;
+                cpuc->lbr_entries[out].mispred   = mis;
+                cpuc->lbr_entries[out].predicted = pred;
+                cpuc->lbr_entries[out].in_tx     = in_tx;
+                cpuc->lbr_entries[out].abort     = abort;
+                cpuc->lbr_entries[out].reserved  = 0;
+                out++;
         }
-        cpuc->lbr_stack.nr = i;
+        cpuc->lbr_stack.nr = out;
 }
 
 void intel_pmu_lbr_read(void)
@@ -478,7 +491,7 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
 
                 /* may fail if text not present */
                 bytes = copy_from_user_nmi(buf, (void __user *)from, size);
-                if (bytes != size)
+                if (bytes != 0)
                         return X86_BR_NONE;
 
                 addr = buf;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 4118f9f68315..29c248799ced 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -997,6 +997,20 @@ static int snbep_pci2phy_map_init(int devid)
                 }
         }
 
+        if (!err) {
+                /*
+                 * For PCI bus with no UBOX device, find the next bus
+                 * that has UBOX device and use its mapping.
+                 */
+                i = -1;
+                for (bus = 255; bus >= 0; bus--) {
+                        if (pcibus_to_physid[bus] >= 0)
+                                i = pcibus_to_physid[bus];
+                        else
+                                pcibus_to_physid[bus] = i;
+                }
+        }
+
         if (ubox_dev)
                 pci_dev_put(ubox_dev);
 
@@ -1099,6 +1113,24 @@ static struct attribute *ivt_uncore_qpi_formats_attr[] = {
         &format_attr_umask.attr,
         &format_attr_edge.attr,
         &format_attr_thresh8.attr,
+        &format_attr_match_rds.attr,
+        &format_attr_match_rnid30.attr,
+        &format_attr_match_rnid4.attr,
+        &format_attr_match_dnid.attr,
+        &format_attr_match_mc.attr,
+        &format_attr_match_opc.attr,
+        &format_attr_match_vnw.attr,
+        &format_attr_match0.attr,
+        &format_attr_match1.attr,
+        &format_attr_mask_rds.attr,
+        &format_attr_mask_rnid30.attr,
+        &format_attr_mask_rnid4.attr,
+        &format_attr_mask_dnid.attr,
+        &format_attr_mask_mc.attr,
+        &format_attr_mask_opc.attr,
+        &format_attr_mask_vnw.attr,
+        &format_attr_mask0.attr,
+        &format_attr_mask1.attr,
         NULL,
 };
 
@@ -1312,17 +1344,83 @@ static struct intel_uncore_type ivt_uncore_imc = {
         IVT_UNCORE_PCI_COMMON_INIT(),
 };
 
+/* registers in IRP boxes are not properly aligned */
+static unsigned ivt_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
+static unsigned ivt_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
+
+static void ivt_uncore_irp_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+
+        pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx],
+                               hwc->config | SNBEP_PMON_CTL_EN);
+}
+
+static void ivt_uncore_irp_disable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+
+        pci_write_config_dword(pdev, ivt_uncore_irp_ctls[hwc->idx], hwc->config);
+}
+
+static u64 ivt_uncore_irp_read_counter(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+        u64 count = 0;
+
+        pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx], (u32 *)&count);
+        pci_read_config_dword(pdev, ivt_uncore_irp_ctrs[hwc->idx] + 4, (u32 *)&count + 1);
+
+        return count;
+}
+
+static struct intel_uncore_ops ivt_uncore_irp_ops = {
+        .init_box       = ivt_uncore_pci_init_box,
+        .disable_box    = snbep_uncore_pci_disable_box,
+        .enable_box     = snbep_uncore_pci_enable_box,
+        .disable_event  = ivt_uncore_irp_disable_event,
+        .enable_event   = ivt_uncore_irp_enable_event,
+        .read_counter   = ivt_uncore_irp_read_counter,
+};
+
+static struct intel_uncore_type ivt_uncore_irp = {
+        .name                   = "irp",
+        .num_counters           = 4,
+        .num_boxes              = 1,
+        .perf_ctr_bits          = 48,
+        .event_mask             = IVT_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_PCI_PMON_BOX_CTL,
+        .ops                    = &ivt_uncore_irp_ops,
+        .format_group           = &ivt_uncore_format_group,
+};
+
+static struct intel_uncore_ops ivt_uncore_qpi_ops = {
+        .init_box       = ivt_uncore_pci_init_box,
+        .disable_box    = snbep_uncore_pci_disable_box,
+        .enable_box     = snbep_uncore_pci_enable_box,
+        .disable_event  = snbep_uncore_pci_disable_event,
+        .enable_event   = snbep_qpi_enable_event,
+        .read_counter   = snbep_uncore_pci_read_counter,
+        .hw_config      = snbep_qpi_hw_config,
+        .get_constraint = uncore_get_constraint,
+        .put_constraint = uncore_put_constraint,
+};
+
 static struct intel_uncore_type ivt_uncore_qpi = {
-        .name           = "qpi",
-        .num_counters   = 4,
-        .num_boxes      = 3,
-        .perf_ctr_bits  = 48,
-        .perf_ctr       = SNBEP_PCI_PMON_CTR0,
-        .event_ctl      = SNBEP_PCI_PMON_CTL0,
-        .event_mask     = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
-        .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,
-        .ops            = &ivt_uncore_pci_ops,
-        .format_group   = &ivt_uncore_qpi_format_group,
+        .name                   = "qpi",
+        .num_counters           = 4,
+        .num_boxes              = 3,
+        .perf_ctr_bits          = 48,
+        .perf_ctr               = SNBEP_PCI_PMON_CTR0,
+        .event_ctl              = SNBEP_PCI_PMON_CTL0,
+        .event_mask             = IVT_QPI_PCI_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_PCI_PMON_BOX_CTL,
+        .num_shared_regs        = 1,
+        .ops                    = &ivt_uncore_qpi_ops,
+        .format_group           = &ivt_uncore_qpi_format_group,
 };
 
 static struct intel_uncore_type ivt_uncore_r2pcie = {
@@ -1346,6 +1444,7 @@ static struct intel_uncore_type ivt_uncore_r3qpi = {
 enum {
         IVT_PCI_UNCORE_HA,
         IVT_PCI_UNCORE_IMC,
+        IVT_PCI_UNCORE_IRP,
         IVT_PCI_UNCORE_QPI,
         IVT_PCI_UNCORE_R2PCIE,
         IVT_PCI_UNCORE_R3QPI,
@@ -1354,6 +1453,7 @@ enum {
 static struct intel_uncore_type *ivt_pci_uncores[] = {
         [IVT_PCI_UNCORE_HA]     = &ivt_uncore_ha,
         [IVT_PCI_UNCORE_IMC]    = &ivt_uncore_imc,
+        [IVT_PCI_UNCORE_IRP]    = &ivt_uncore_irp,
         [IVT_PCI_UNCORE_QPI]    = &ivt_uncore_qpi,
         [IVT_PCI_UNCORE_R2PCIE] = &ivt_uncore_r2pcie,
         [IVT_PCI_UNCORE_R3QPI]  = &ivt_uncore_r3qpi,
@@ -1401,6 +1501,10 @@ static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids) = {
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
                 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IMC, 7),
         },
+        { /* IRP */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
+                .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_IRP, 0),
+        },
         { /* QPI0 Port 0 */
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
                 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_QPI, 0),
@@ -1429,6 +1533,16 @@ static DEFINE_PCI_DEVICE_TABLE(ivt_uncore_pci_ids) = {
                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
                 .driver_data = UNCORE_PCI_DEV_DATA(IVT_PCI_UNCORE_R3QPI, 2),
         },
+        { /* QPI Port 0 filter  */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
+                .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
+                                                   SNBEP_PCI_QPI_PORT0_FILTER),
+        },
+        { /* QPI Port 0 filter  */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
+                .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
+                                                   SNBEP_PCI_QPI_PORT1_FILTER),
+        },
         { /* end: all zeroes */ }
 };