1 files changed, 73 insertions, 5 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f31a1655d1ff..0fa4f242f050 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -190,9 +190,9 @@ static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
         EVENT_EXTRA_END
 };
 
-EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
-EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
+EVENT_ATTR_STR(mem-loads,       mem_ld_nhm,     "event=0x0b,umask=0x10,ldlat=3");
+EVENT_ATTR_STR(mem-loads,       mem_ld_snb,     "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores,      mem_st_snb,     "event=0xcd,umask=0x2");
 
 struct attribute *nhm_events_attrs[] = {
         EVENT_PTR(mem_ld_nhm),
@@ -1184,6 +1184,11 @@ static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
         wrmsrl(hwc->config_base, ctrl_val);
 }
 
+static inline bool event_is_checkpointed(struct perf_event *event)
+{
+        return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
+}
+
 static void intel_pmu_disable_event(struct perf_event *event)
 {
         struct hw_perf_event *hwc = &event->hw;
@@ -1197,6 +1202,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
 
         cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
         cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
+        cpuc->intel_cp_status &= ~(1ull << hwc->idx);
 
         /*
          * must disable before any actual event
@@ -1271,6 +1277,9 @@ static void intel_pmu_enable_event(struct perf_event *event)
         if (event->attr.exclude_guest)
                 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
 
+        if (unlikely(event_is_checkpointed(event)))
+                cpuc->intel_cp_status |= (1ull << hwc->idx);
+
         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                 intel_pmu_enable_fixed(hwc);
                 return;
@@ -1289,6 +1298,17 @@ static void intel_pmu_enable_event(struct perf_event *event)
 int intel_pmu_save_and_restart(struct perf_event *event)
 {
         x86_perf_event_update(event);
+        /*
+         * For a checkpointed counter always reset back to 0.  This
+         * avoids a situation where the counter overflows, aborts the
+         * transaction and is then set back to shortly before the
+         * overflow, and overflows and aborts again.
+         */
+        if (unlikely(event_is_checkpointed(event))) {
+                /* No race with NMIs because the counter should not be armed */
+                wrmsrl(event->hw.event_base, 0);
+                local64_set(&event->hw.prev_count, 0);
+        }
         return x86_perf_event_set_period(event);
 }
 
@@ -1372,6 +1392,13 @@ again:
                 x86_pmu.drain_pebs(regs);
         }
 
+        /*
+         * Checkpointed counters can lead to 'spurious' PMIs because the
+         * rollback caused by the PMI will have cleared the overflow status
+         * bit. Therefore always force probe these counters.
+         */
+        status |= cpuc->intel_cp_status;
+
         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
                 struct perf_event *event = cpuc->events[bit];
 
@@ -1837,6 +1864,20 @@ static int hsw_hw_config(struct perf_event *event)
               event->attr.precise_ip > 0))
                 return -EOPNOTSUPP;
 
+        if (event_is_checkpointed(event)) {
+                /*
+                 * Sampling of checkpointed events can cause situations where
+                 * the CPU constantly aborts because of a overflow, which is
+                 * then checkpointed back and ignored. Forbid checkpointing
+                 * for sampling.
+                 *
+                 * But still allow a long sampling period, so that perf stat
+                 * from KVM works.
+                 */
+                if (event->attr.sample_period > 0 &&
+                    event->attr.sample_period < 0x7fffffff)
+                        return -EOPNOTSUPP;
+        }
         return 0;
 }
 
@@ -2182,10 +2223,36 @@ static __init void intel_nehalem_quirk(void)
         }
 }
 
-EVENT_ATTR_STR(mem-loads,      mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
-EVENT_ATTR_STR(mem-stores,     mem_st_hsw,     "event=0xd0,umask=0x82")
+EVENT_ATTR_STR(mem-loads,       mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores,      mem_st_hsw,     "event=0xd0,umask=0x82")
+
+/* Haswell special events */
+EVENT_ATTR_STR(tx-start,        tx_start,       "event=0xc9,umask=0x1");
+EVENT_ATTR_STR(tx-commit,       tx_commit,      "event=0xc9,umask=0x2");
+EVENT_ATTR_STR(tx-abort,        tx_abort,       "event=0xc9,umask=0x4");
+EVENT_ATTR_STR(tx-capacity,     tx_capacity,    "event=0x54,umask=0x2");
+EVENT_ATTR_STR(tx-conflict,     tx_conflict,    "event=0x54,umask=0x1");
+EVENT_ATTR_STR(el-start,        el_start,       "event=0xc8,umask=0x1");
+EVENT_ATTR_STR(el-commit,       el_commit,      "event=0xc8,umask=0x2");
+EVENT_ATTR_STR(el-abort,        el_abort,       "event=0xc8,umask=0x4");
+EVENT_ATTR_STR(el-capacity,     el_capacity,    "event=0x54,umask=0x2");
+EVENT_ATTR_STR(el-conflict,     el_conflict,    "event=0x54,umask=0x1");
+EVENT_ATTR_STR(cycles-t,        cycles_t,       "event=0x3c,in_tx=1");
+EVENT_ATTR_STR(cycles-ct,       cycles_ct,      "event=0x3c,in_tx=1,in_tx_cp=1");
 
 static struct attribute *hsw_events_attrs[] = {
+        EVENT_PTR(tx_start),
+        EVENT_PTR(tx_commit),
+        EVENT_PTR(tx_abort),
+        EVENT_PTR(tx_capacity),
+        EVENT_PTR(tx_conflict),
+        EVENT_PTR(el_start),
+        EVENT_PTR(el_commit),
+        EVENT_PTR(el_abort),
+        EVENT_PTR(el_capacity),
+        EVENT_PTR(el_conflict),
+        EVENT_PTR(cycles_t),
+        EVENT_PTR(cycles_ct),
         EVENT_PTR(mem_ld_hsw),
         EVENT_PTR(mem_st_hsw),
         NULL
@@ -2452,6 +2519,7 @@ __init int intel_pmu_init(void)
                 x86_pmu.hw_config = hsw_hw_config;
                 x86_pmu.get_event_constraints = hsw_get_event_constraints;
                 x86_pmu.cpu_events = hsw_events_attrs;
+                x86_pmu.lbr_double_abort = true;
                 pr_cont("Haswell events, ");
                 break;