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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-15 23:01:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-15 23:01:36 -0400
commitd10902812c9cd5583130a4ebb9ad19c60b68149d (patch)
treeb1b28587970e8cebf74ba4d61edf49537f619ab7 /arch/x86/kernel/irqinit.c
parent181f977d134a9f8e3f8839f42af655b045fc059e (diff)
parent25874a299ef8037df03ce4ada570bc4e42f9748f (diff)
Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (27 commits) x86: Clean up apic.c and apic.h x86: Remove superflous goal definition of tsc_sync x86: dt: Correct local apic documentation in device tree bindings x86: dt: Cleanup local apic setup x86: dt: Fix OLPC=y/INTEL_CE=n build rtc: cmos: Add OF bindings x86: ce4100: Use OF to setup devices x86: ioapic: Add OF bindings for IO_APIC x86: dtb: Add generic bus probe x86: dtb: Add support for PCI devices backed by dtb nodes x86: dtb: Add device tree support for HPET x86: dtb: Add early parsing of IO_APIC x86: dtb: Add irq domain abstraction x86: dtb: Add a device tree for CE4100 x86: Add device tree support x86: e820: Remove conditional early mapping in parse_e820_ext x86: OLPC: Make OLPC=n build again x86: OLPC: Remove extra OLPC_OPENFIRMWARE_DT indirection x86: OLPC: Cleanup config maze completely x86: OLPC: Hide OLPC_OPENFIRMWARE config switch ... Fix up conflicts in arch/x86/platform/ce4100/ce4100.c
Diffstat (limited to 'arch/x86/kernel/irqinit.c')
-rw-r--r--arch/x86/kernel/irqinit.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index d30854b18d25..f470e4ef993e 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -25,6 +25,7 @@
25#include <asm/setup.h> 25#include <asm/setup.h>
26#include <asm/i8259.h> 26#include <asm/i8259.h>
27#include <asm/traps.h> 27#include <asm/traps.h>
28#include <asm/prom.h>
28 29
29/* 30/*
30 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 31 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
@@ -120,6 +121,12 @@ void __init init_IRQ(void)
120 int i; 121 int i;
121 122
122 /* 123 /*
124 * We probably need a better place for this, but it works for
125 * now ...
126 */
127 x86_add_irq_domains();
128
129 /*
123 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15. 130 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
124 * If these IRQ's are handled by legacy interrupt-controllers like PIC, 131 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
125 * then this configuration will likely be static after the boot. If 132 * then this configuration will likely be static after the boot. If
@@ -308,7 +315,7 @@ void __init native_init_IRQ(void)
308 set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]); 315 set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
309 } 316 }
310 317
311 if (!acpi_ioapic) 318 if (!acpi_ioapic && !of_ioapic)
312 setup_irq(2, &irq2); 319 setup_irq(2, &irq2);
313 320
314#ifdef CONFIG_X86_32 321#ifdef CONFIG_X86_32