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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-15 23:01:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-15 23:01:36 -0400
commitd10902812c9cd5583130a4ebb9ad19c60b68149d (patch)
treeb1b28587970e8cebf74ba4d61edf49537f619ab7 /arch/x86
parent181f977d134a9f8e3f8839f42af655b045fc059e (diff)
parent25874a299ef8037df03ce4ada570bc4e42f9748f (diff)
Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (27 commits) x86: Clean up apic.c and apic.h x86: Remove superflous goal definition of tsc_sync x86: dt: Correct local apic documentation in device tree bindings x86: dt: Cleanup local apic setup x86: dt: Fix OLPC=y/INTEL_CE=n build rtc: cmos: Add OF bindings x86: ce4100: Use OF to setup devices x86: ioapic: Add OF bindings for IO_APIC x86: dtb: Add generic bus probe x86: dtb: Add support for PCI devices backed by dtb nodes x86: dtb: Add device tree support for HPET x86: dtb: Add early parsing of IO_APIC x86: dtb: Add irq domain abstraction x86: dtb: Add a device tree for CE4100 x86: Add device tree support x86: e820: Remove conditional early mapping in parse_e820_ext x86: OLPC: Make OLPC=n build again x86: OLPC: Remove extra OLPC_OPENFIRMWARE_DT indirection x86: OLPC: Cleanup config maze completely x86: OLPC: Hide OLPC_OPENFIRMWARE config switch ... Fix up conflicts in arch/x86/platform/ce4100/ce4100.c
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/Kconfig22
-rw-r--r--arch/x86/include/asm/apic.h6
-rw-r--r--arch/x86/include/asm/bootparam.h1
-rw-r--r--arch/x86/include/asm/e820.h2
-rw-r--r--arch/x86/include/asm/irq.h3
-rw-r--r--arch/x86/include/asm/irq_controller.h12
-rw-r--r--arch/x86/include/asm/olpc_ofw.h14
-rw-r--r--arch/x86/include/asm/prom.h70
-rw-r--r--arch/x86/include/asm/x86_init.h2
-rw-r--r--arch/x86/kernel/Makefile5
-rw-r--r--arch/x86/kernel/apb_timer.c60
-rw-r--r--arch/x86/kernel/apic/apic.c69
-rw-r--r--arch/x86/kernel/devicetree.c441
-rw-r--r--arch/x86/kernel/e820.c8
-rw-r--r--arch/x86/kernel/head_32.S2
-rw-r--r--arch/x86/kernel/irq.c9
-rw-r--r--arch/x86/kernel/irqinit.c9
-rw-r--r--arch/x86/kernel/rtc.c3
-rw-r--r--arch/x86/kernel/setup.c25
-rw-r--r--arch/x86/kernel/x86_init.c1
-rw-r--r--arch/x86/pci/ce4100.c2
-rw-r--r--arch/x86/platform/ce4100/ce4100.c24
-rw-r--r--arch/x86/platform/ce4100/falconfalls.dts428
-rw-r--r--arch/x86/platform/mrst/mrst.c2
-rw-r--r--arch/x86/platform/mrst/vrtc.c16
-rw-r--r--arch/x86/platform/olpc/Makefile4
26 files changed, 1058 insertions, 182 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 159c2ff9c127..f8958b01b975 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -386,6 +386,8 @@ config X86_INTEL_CE
386 depends on X86_32 386 depends on X86_32
387 depends on X86_EXTENDED_PLATFORM 387 depends on X86_EXTENDED_PLATFORM
388 select X86_REBOOTFIXUPS 388 select X86_REBOOTFIXUPS
389 select OF
390 select OF_EARLY_FLATTREE
389 ---help--- 391 ---help---
390 Select for the Intel CE media processor (CE4100) SOC. 392 Select for the Intel CE media processor (CE4100) SOC.
391 This option compiles in support for the CE4100 SOC for settop 393 This option compiles in support for the CE4100 SOC for settop
@@ -2070,9 +2072,10 @@ config SCx200HR_TIMER
2070 2072
2071config OLPC 2073config OLPC
2072 bool "One Laptop Per Child support" 2074 bool "One Laptop Per Child support"
2075 depends on !X86_PAE
2073 select GPIOLIB 2076 select GPIOLIB
2074 select OLPC_OPENFIRMWARE 2077 select OF
2075 depends on !X86_64 && !X86_PAE 2078 select OF_PROMTREE if PROC_DEVICETREE
2076 ---help--- 2079 ---help---
2077 Add support for detecting the unique features of the OLPC 2080 Add support for detecting the unique features of the OLPC
2078 XO hardware. 2081 XO hardware.
@@ -2083,21 +2086,6 @@ config OLPC_XO1
2083 ---help--- 2086 ---help---
2084 Add support for non-essential features of the OLPC XO-1 laptop. 2087 Add support for non-essential features of the OLPC XO-1 laptop.
2085 2088
2086config OLPC_OPENFIRMWARE
2087 bool "Support for OLPC's Open Firmware"
2088 depends on !X86_64 && !X86_PAE
2089 default n
2090 select OF
2091 help
2092 This option adds support for the implementation of Open Firmware
2093 that is used on the OLPC XO-1 Children's Machine.
2094 If unsure, say N here.
2095
2096config OLPC_OPENFIRMWARE_DT
2097 bool
2098 default y if OLPC_OPENFIRMWARE && PROC_DEVICETREE
2099 select OF_PROMTREE
2100
2101endif # X86_32 2089endif # X86_32
2102 2090
2103config AMD_NB 2091config AMD_NB
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index b8a3484d69e9..a279d98ea95e 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -220,7 +220,6 @@ extern void enable_IR_x2apic(void);
220 220
221extern int get_physical_broadcast(void); 221extern int get_physical_broadcast(void);
222 222
223extern void apic_disable(void);
224extern int lapic_get_maxlvt(void); 223extern int lapic_get_maxlvt(void);
225extern void clear_local_APIC(void); 224extern void clear_local_APIC(void);
226extern void connect_bsp_APIC(void); 225extern void connect_bsp_APIC(void);
@@ -228,7 +227,6 @@ extern void disconnect_bsp_APIC(int virt_wire_setup);
228extern void disable_local_APIC(void); 227extern void disable_local_APIC(void);
229extern void lapic_shutdown(void); 228extern void lapic_shutdown(void);
230extern int verify_local_APIC(void); 229extern int verify_local_APIC(void);
231extern void cache_APIC_registers(void);
232extern void sync_Arb_IDs(void); 230extern void sync_Arb_IDs(void);
233extern void init_bsp_APIC(void); 231extern void init_bsp_APIC(void);
234extern void setup_local_APIC(void); 232extern void setup_local_APIC(void);
@@ -239,8 +237,7 @@ void register_lapic_address(unsigned long address);
239extern void setup_boot_APIC_clock(void); 237extern void setup_boot_APIC_clock(void);
240extern void setup_secondary_APIC_clock(void); 238extern void setup_secondary_APIC_clock(void);
241extern int APIC_init_uniprocessor(void); 239extern int APIC_init_uniprocessor(void);
242extern void enable_NMI_through_LVT0(void); 240extern int apic_force_enable(unsigned long addr);
243extern int apic_force_enable(void);
244 241
245/* 242/*
246 * On 32bit this is mach-xxx local 243 * On 32bit this is mach-xxx local
@@ -261,7 +258,6 @@ static inline void lapic_shutdown(void) { }
261#define local_apic_timer_c2_ok 1 258#define local_apic_timer_c2_ok 1
262static inline void init_apic_mappings(void) { } 259static inline void init_apic_mappings(void) { }
263static inline void disable_local_APIC(void) { } 260static inline void disable_local_APIC(void) { }
264static inline void apic_disable(void) { }
265# define setup_boot_APIC_clock x86_init_noop 261# define setup_boot_APIC_clock x86_init_noop
266# define setup_secondary_APIC_clock x86_init_noop 262# define setup_secondary_APIC_clock x86_init_noop
267#endif /* !CONFIG_X86_LOCAL_APIC */ 263#endif /* !CONFIG_X86_LOCAL_APIC */
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index c8bfe63a06de..e020d88ec02d 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -12,6 +12,7 @@
12/* setup data types */ 12/* setup data types */
13#define SETUP_NONE 0 13#define SETUP_NONE 0
14#define SETUP_E820_EXT 1 14#define SETUP_E820_EXT 1
15#define SETUP_DTB 2
15 16
16/* extensible setup data list node */ 17/* extensible setup data list node */
17struct setup_data { 18struct setup_data {
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index e99d55d74df5..908b96957d88 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -96,7 +96,7 @@ extern void e820_setup_gap(void);
96extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize, 96extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
97 unsigned long start_addr, unsigned long long end_addr); 97 unsigned long start_addr, unsigned long long end_addr);
98struct setup_data; 98struct setup_data;
99extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data); 99extern void parse_e820_ext(struct setup_data *data);
100 100
101#if defined(CONFIG_X86_64) || \ 101#if defined(CONFIG_X86_64) || \
102 (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION)) 102 (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index c704b38c57a2..ba870bb6dd8e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -10,9 +10,6 @@
10#include <asm/apicdef.h> 10#include <asm/apicdef.h>
11#include <asm/irq_vectors.h> 11#include <asm/irq_vectors.h>
12 12
13/* Even though we don't support this, supply it to appease OF */
14static inline void irq_dispose_mapping(unsigned int virq) { }
15
16static inline int irq_canonicalize(int irq) 13static inline int irq_canonicalize(int irq)
17{ 14{
18 return ((irq == 2) ? 9 : irq); 15 return ((irq == 2) ? 9 : irq);
diff --git a/arch/x86/include/asm/irq_controller.h b/arch/x86/include/asm/irq_controller.h
new file mode 100644
index 000000000000..423bbbddf36d
--- /dev/null
+++ b/arch/x86/include/asm/irq_controller.h
@@ -0,0 +1,12 @@
1#ifndef __IRQ_CONTROLLER__
2#define __IRQ_CONTROLLER__
3
4struct irq_domain {
5 int (*xlate)(struct irq_domain *h, const u32 *intspec, u32 intsize,
6 u32 *out_hwirq, u32 *out_type);
7 void *priv;
8 struct device_node *controller;
9 struct list_head l;
10};
11
12#endif
diff --git a/arch/x86/include/asm/olpc_ofw.h b/arch/x86/include/asm/olpc_ofw.h
index 641988efe063..c5d3a5abbb9f 100644
--- a/arch/x86/include/asm/olpc_ofw.h
+++ b/arch/x86/include/asm/olpc_ofw.h
@@ -6,7 +6,7 @@
6 6
7#define OLPC_OFW_SIG 0x2057464F /* aka "OFW " */ 7#define OLPC_OFW_SIG 0x2057464F /* aka "OFW " */
8 8
9#ifdef CONFIG_OLPC_OPENFIRMWARE 9#ifdef CONFIG_OLPC
10 10
11extern bool olpc_ofw_is_installed(void); 11extern bool olpc_ofw_is_installed(void);
12 12
@@ -26,19 +26,15 @@ extern void setup_olpc_ofw_pgd(void);
26/* check if OFW was detected during boot */ 26/* check if OFW was detected during boot */
27extern bool olpc_ofw_present(void); 27extern bool olpc_ofw_present(void);
28 28
29#else /* !CONFIG_OLPC_OPENFIRMWARE */ 29#else /* !CONFIG_OLPC */
30
31static inline bool olpc_ofw_is_installed(void) { return false; }
32static inline void olpc_ofw_detect(void) { } 30static inline void olpc_ofw_detect(void) { }
33static inline void setup_olpc_ofw_pgd(void) { } 31static inline void setup_olpc_ofw_pgd(void) { }
34static inline bool olpc_ofw_present(void) { return false; } 32#endif /* !CONFIG_OLPC */
35
36#endif /* !CONFIG_OLPC_OPENFIRMWARE */
37 33
38#ifdef CONFIG_OLPC_OPENFIRMWARE_DT 34#ifdef CONFIG_OF_PROMTREE
39extern void olpc_dt_build_devicetree(void); 35extern void olpc_dt_build_devicetree(void);
40#else 36#else
41static inline void olpc_dt_build_devicetree(void) { } 37static inline void olpc_dt_build_devicetree(void) { }
42#endif /* CONFIG_OLPC_OPENFIRMWARE_DT */ 38#endif
43 39
44#endif /* _ASM_X86_OLPC_OFW_H */ 40#endif /* _ASM_X86_OLPC_OFW_H */
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index b4ec95f07518..971e0b46446e 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -1 +1,69 @@
1/* dummy prom.h; here to make linux/of.h's #includes happy */ 1/*
2 * Definitions for Device tree / OpenFirmware handling on X86
3 *
4 * based on arch/powerpc/include/asm/prom.h which is
5 * Copyright (C) 1996-2005 Paul Mackerras.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _ASM_X86_PROM_H
14#define _ASM_X86_PROM_H
15#ifndef __ASSEMBLY__
16
17#include <linux/of.h>
18#include <linux/types.h>
19#include <linux/pci.h>
20
21#include <asm/irq.h>
22#include <asm/atomic.h>
23#include <asm/setup.h>
24#include <asm/irq_controller.h>
25
26#ifdef CONFIG_OF
27extern int of_ioapic;
28extern u64 initial_dtb;
29extern void add_dtb(u64 data);
30extern void x86_add_irq_domains(void);
31void __cpuinit x86_of_pci_init(void);
32void x86_dtb_init(void);
33
34static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
35{
36 return pdev ? pdev->dev.of_node : NULL;
37}
38
39static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
40{
41 return pci_device_to_OF_node(bus->self);
42}
43
44#else
45static inline void add_dtb(u64 data) { }
46static inline void x86_add_irq_domains(void) { }
47static inline void x86_of_pci_init(void) { }
48static inline void x86_dtb_init(void) { }
49#define of_ioapic 0
50#endif
51
52extern char cmd_line[COMMAND_LINE_SIZE];
53
54#define pci_address_to_pio pci_address_to_pio
55unsigned long pci_address_to_pio(phys_addr_t addr);
56
57/**
58 * irq_dispose_mapping - Unmap an interrupt
59 * @virq: linux virq number of the interrupt to unmap
60 *
61 * FIXME: We really should implement proper virq handling like power,
62 * but that's going to be major surgery.
63 */
64static inline void irq_dispose_mapping(unsigned int virq) { }
65
66#define HAVE_ARCH_DEVTREE_FIXUPS
67
68#endif /* __ASSEMBLY__ */
69#endif
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 64642ad019fb..643ebf2e2ad8 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -83,11 +83,13 @@ struct x86_init_paging {
83 * boot cpu 83 * boot cpu
84 * @tsc_pre_init: platform function called before TSC init 84 * @tsc_pre_init: platform function called before TSC init
85 * @timer_init: initialize the platform timer (default PIT/HPET) 85 * @timer_init: initialize the platform timer (default PIT/HPET)
86 * @wallclock_init: init the wallclock device
86 */ 87 */
87struct x86_init_timers { 88struct x86_init_timers {
88 void (*setup_percpu_clockev)(void); 89 void (*setup_percpu_clockev)(void);
89 void (*tsc_pre_init)(void); 90 void (*tsc_pre_init)(void);
90 void (*timer_init)(void); 91 void (*timer_init)(void);
92 void (*wallclock_init)(void);
91}; 93};
92 94
93/** 95/**
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 34244b2cd880..62445ba2f8a8 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -66,9 +66,9 @@ obj-$(CONFIG_PCI) += early-quirks.o
66apm-y := apm_32.o 66apm-y := apm_32.o
67obj-$(CONFIG_APM) += apm.o 67obj-$(CONFIG_APM) += apm.o
68obj-$(CONFIG_SMP) += smp.o 68obj-$(CONFIG_SMP) += smp.o
69obj-$(CONFIG_SMP) += smpboot.o tsc_sync.o 69obj-$(CONFIG_SMP) += smpboot.o
70obj-$(CONFIG_SMP) += tsc_sync.o
70obj-$(CONFIG_SMP) += setup_percpu.o 71obj-$(CONFIG_SMP) += setup_percpu.o
71obj-$(CONFIG_X86_64_SMP) += tsc_sync.o
72obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o 72obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
73obj-$(CONFIG_X86_MPPARSE) += mpparse.o 73obj-$(CONFIG_X86_MPPARSE) += mpparse.o
74obj-y += apic/ 74obj-y += apic/
@@ -109,6 +109,7 @@ obj-$(CONFIG_MICROCODE) += microcode.o
109obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o 109obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o
110 110
111obj-$(CONFIG_SWIOTLB) += pci-swiotlb.o 111obj-$(CONFIG_SWIOTLB) += pci-swiotlb.o
112obj-$(CONFIG_OF) += devicetree.o
112 113
113### 114###
114# 64 bit specific files 115# 64 bit specific files
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 51d4e1663066..1293c709ee85 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -508,64 +508,12 @@ static int apbt_next_event(unsigned long delta,
508 return 0; 508 return 0;
509} 509}
510 510
511/*
512 * APB timer clock is not in sync with pclk on Langwell, which translates to
513 * unreliable read value caused by sampling error. the error does not add up
514 * overtime and only happens when sampling a 0 as a 1 by mistake. so the time
515 * would go backwards. the following code is trying to prevent time traveling
516 * backwards. little bit paranoid.
517 */
518static cycle_t apbt_read_clocksource(struct clocksource *cs) 511static cycle_t apbt_read_clocksource(struct clocksource *cs)
519{ 512{
520 unsigned long t0, t1, t2; 513 unsigned long current_count;
521 static unsigned long last_read; 514
522 515 current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE);
523bad_count: 516 return (cycle_t)~current_count;
524 t1 = apbt_readl(phy_cs_timer_id,
525 APBTMR_N_CURRENT_VALUE);
526 t2 = apbt_readl(phy_cs_timer_id,
527 APBTMR_N_CURRENT_VALUE);
528 if (unlikely(t1 < t2)) {
529 pr_debug("APBT: read current count error %lx:%lx:%lx\n",
530 t1, t2, t2 - t1);
531 goto bad_count;
532 }
533 /*
534 * check against cached last read, makes sure time does not go back.
535 * it could be a normal rollover but we will do tripple check anyway
536 */
537 if (unlikely(t2 > last_read)) {
538 /* check if we have a normal rollover */
539 unsigned long raw_intr_status =
540 apbt_readl_reg(APBTMRS_RAW_INT_STATUS);
541 /*
542 * cs timer interrupt is masked but raw intr bit is set if
543 * rollover occurs. then we read EOI reg to clear it.
544 */
545 if (raw_intr_status & (1 << phy_cs_timer_id)) {
546 apbt_readl(phy_cs_timer_id, APBTMR_N_EOI);
547 goto out;
548 }
549 pr_debug("APB CS going back %lx:%lx:%lx ",
550 t2, last_read, t2 - last_read);
551bad_count_x3:
552 pr_debug("triple check enforced\n");
553 t0 = apbt_readl(phy_cs_timer_id,
554 APBTMR_N_CURRENT_VALUE);
555 udelay(1);
556 t1 = apbt_readl(phy_cs_timer_id,
557 APBTMR_N_CURRENT_VALUE);
558 udelay(1);
559 t2 = apbt_readl(phy_cs_timer_id,
560 APBTMR_N_CURRENT_VALUE);
561 if ((t2 > t1) || (t1 > t0)) {
562 printk(KERN_ERR "Error: APB CS tripple check failed\n");
563 goto bad_count_x3;
564 }
565 }
566out:
567 last_read = t2;
568 return (cycle_t)~t2;
569} 517}
570 518
571static int apbt_clocksource_register(void) 519static int apbt_clocksource_register(void)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 562a8325cc1c..966673f44141 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -93,7 +93,7 @@ DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
93 * 93 *
94 * +1=force-enable 94 * +1=force-enable
95 */ 95 */
96static int force_enable_local_apic; 96static int force_enable_local_apic __initdata;
97/* 97/*
98 * APIC command line parameters 98 * APIC command line parameters
99 */ 99 */
@@ -163,7 +163,7 @@ early_param("nox2apic", setup_nox2apic);
163unsigned long mp_lapic_addr; 163unsigned long mp_lapic_addr;
164int disable_apic; 164int disable_apic;
165/* Disable local APIC timer from the kernel commandline or via dmi quirk */ 165/* Disable local APIC timer from the kernel commandline or via dmi quirk */
166static int disable_apic_timer __cpuinitdata; 166static int disable_apic_timer __initdata;
167/* Local APIC timer works in C2 */ 167/* Local APIC timer works in C2 */
168int local_apic_timer_c2_ok; 168int local_apic_timer_c2_ok;
169EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 169EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
@@ -187,29 +187,8 @@ static struct resource lapic_resource = {
187 187
188static unsigned int calibration_result; 188static unsigned int calibration_result;
189 189
190static int lapic_next_event(unsigned long delta,
191 struct clock_event_device *evt);
192static void lapic_timer_setup(enum clock_event_mode mode,
193 struct clock_event_device *evt);
194static void lapic_timer_broadcast(const struct cpumask *mask);
195static void apic_pm_activate(void); 190static void apic_pm_activate(void);
196 191
197/*
198 * The local apic timer can be used for any function which is CPU local.
199 */
200static struct clock_event_device lapic_clockevent = {
201 .name = "lapic",
202 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
203 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
204 .shift = 32,
205 .set_mode = lapic_timer_setup,
206 .set_next_event = lapic_next_event,
207 .broadcast = lapic_timer_broadcast,
208 .rating = 100,
209 .irq = -1,
210};
211static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
212
213static unsigned long apic_phys; 192static unsigned long apic_phys;
214 193
215/* 194/*
@@ -248,7 +227,7 @@ static int modern_apic(void)
248 * right after this call apic become NOOP driven 227 * right after this call apic become NOOP driven
249 * so apic->write/read doesn't do anything 228 * so apic->write/read doesn't do anything
250 */ 229 */
251void apic_disable(void) 230static void __init apic_disable(void)
252{ 231{
253 pr_info("APIC: switched to apic NOOP\n"); 232 pr_info("APIC: switched to apic NOOP\n");
254 apic = &apic_noop; 233 apic = &apic_noop;
@@ -292,23 +271,6 @@ u64 native_apic_icr_read(void)
292 return icr1 | ((u64)icr2 << 32); 271 return icr1 | ((u64)icr2 << 32);
293} 272}
294 273
295/**
296 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
297 */
298void __cpuinit enable_NMI_through_LVT0(void)
299{
300 unsigned int v;
301
302 /* unmask and set to NMI */
303 v = APIC_DM_NMI;
304
305 /* Level triggered for 82489DX (32bit mode) */
306 if (!lapic_is_integrated())
307 v |= APIC_LVT_LEVEL_TRIGGER;
308
309 apic_write(APIC_LVT0, v);
310}
311
312#ifdef CONFIG_X86_32 274#ifdef CONFIG_X86_32
313/** 275/**
314 * get_physical_broadcast - Get number of physical broadcast IDs 276 * get_physical_broadcast - Get number of physical broadcast IDs
@@ -518,6 +480,23 @@ static void lapic_timer_broadcast(const struct cpumask *mask)
518#endif 480#endif
519} 481}
520 482
483
484/*
485 * The local apic timer can be used for any function which is CPU local.
486 */
487static struct clock_event_device lapic_clockevent = {
488 .name = "lapic",
489 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
490 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
491 .shift = 32,
492 .set_mode = lapic_timer_setup,
493 .set_next_event = lapic_next_event,
494 .broadcast = lapic_timer_broadcast,
495 .rating = 100,
496 .irq = -1,
497};
498static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
499
521/* 500/*
522 * Setup the local APIC timer for this CPU. Copy the initialized values 501 * Setup the local APIC timer for this CPU. Copy the initialized values
523 * of the boot CPU and register the clock event in the framework. 502 * of the boot CPU and register the clock event in the framework.
@@ -1560,7 +1539,7 @@ static int __init detect_init_APIC(void)
1560} 1539}
1561#else 1540#else
1562 1541
1563static int apic_verify(void) 1542static int __init apic_verify(void)
1564{ 1543{
1565 u32 features, h, l; 1544 u32 features, h, l;
1566 1545
@@ -1585,7 +1564,7 @@ static int apic_verify(void)
1585 return 0; 1564 return 0;
1586} 1565}
1587 1566
1588int apic_force_enable(void) 1567int __init apic_force_enable(unsigned long addr)
1589{ 1568{
1590 u32 h, l; 1569 u32 h, l;
1591 1570
@@ -1601,7 +1580,7 @@ int apic_force_enable(void)
1601 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1580 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1602 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1581 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1603 l &= ~MSR_IA32_APICBASE_BASE; 1582 l &= ~MSR_IA32_APICBASE_BASE;
1604 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1583 l |= MSR_IA32_APICBASE_ENABLE | addr;
1605 wrmsr(MSR_IA32_APICBASE, l, h); 1584 wrmsr(MSR_IA32_APICBASE, l, h);
1606 enabled_via_apicbase = 1; 1585 enabled_via_apicbase = 1;
1607 } 1586 }
@@ -1642,7 +1621,7 @@ static int __init detect_init_APIC(void)
1642 "you can enable it with \"lapic\"\n"); 1621 "you can enable it with \"lapic\"\n");
1643 return -1; 1622 return -1;
1644 } 1623 }
1645 if (apic_force_enable()) 1624 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1646 return -1; 1625 return -1;
1647 } else { 1626 } else {
1648 if (apic_verify()) 1627 if (apic_verify())
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
new file mode 100644
index 000000000000..7a8cebc9ff29
--- /dev/null
+++ b/arch/x86/kernel/devicetree.c
@@ -0,0 +1,441 @@
1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/io.h>
6#include <linux/interrupt.h>
7#include <linux/list.h>
8#include <linux/of.h>
9#include <linux/of_fdt.h>
10#include <linux/of_address.h>
11#include <linux/of_platform.h>
12#include <linux/of_irq.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/of_pci.h>
16
17#include <asm/hpet.h>
18#include <asm/irq_controller.h>
19#include <asm/apic.h>
20#include <asm/pci_x86.h>
21
22__initdata u64 initial_dtb;
23char __initdata cmd_line[COMMAND_LINE_SIZE];
24static LIST_HEAD(irq_domains);
25static DEFINE_RAW_SPINLOCK(big_irq_lock);
26
27int __initdata of_ioapic;
28
29#ifdef CONFIG_X86_IO_APIC
30static void add_interrupt_host(struct irq_domain *ih)
31{
32 unsigned long flags;
33
34 raw_spin_lock_irqsave(&big_irq_lock, flags);
35 list_add(&ih->l, &irq_domains);
36 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
37}
38#endif
39
40static struct irq_domain *get_ih_from_node(struct device_node *controller)
41{
42 struct irq_domain *ih, *found = NULL;
43 unsigned long flags;
44
45 raw_spin_lock_irqsave(&big_irq_lock, flags);
46 list_for_each_entry(ih, &irq_domains, l) {
47 if (ih->controller == controller) {
48 found = ih;
49 break;
50 }
51 }
52 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
53 return found;
54}
55
56unsigned int irq_create_of_mapping(struct device_node *controller,
57 const u32 *intspec, unsigned int intsize)
58{
59 struct irq_domain *ih;
60 u32 virq, type;
61 int ret;
62
63 ih = get_ih_from_node(controller);
64 if (!ih)
65 return 0;
66 ret = ih->xlate(ih, intspec, intsize, &virq, &type);
67 if (ret)
68 return ret;
69 if (type == IRQ_TYPE_NONE)
70 return virq;
71 /* set the mask if it is different from current */
72 if (type == (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK))
73 set_irq_type(virq, type);
74 return virq;
75}
76EXPORT_SYMBOL_GPL(irq_create_of_mapping);
77
78unsigned long pci_address_to_pio(phys_addr_t address)
79{
80 /*
81 * The ioport address can be directly used by inX / outX
82 */
83 BUG_ON(address >= (1 << 16));
84 return (unsigned long)address;
85}
86EXPORT_SYMBOL_GPL(pci_address_to_pio);
87
88void __init early_init_dt_scan_chosen_arch(unsigned long node)
89{
90 BUG();
91}
92
93void __init early_init_dt_add_memory_arch(u64 base, u64 size)
94{
95 BUG();
96}
97
98void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
99{
100 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
101}
102
103void __init add_dtb(u64 data)
104{
105 initial_dtb = data + offsetof(struct setup_data, data);
106}
107
108/*
109 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
110 */
111static struct of_device_id __initdata ce4100_ids[] = {
112 { .compatible = "intel,ce4100-cp", },
113 { .compatible = "isa", },
114 { .compatible = "pci", },
115 {},
116};
117
118static int __init add_bus_probe(void)
119{
120 if (!of_have_populated_dt())
121 return 0;
122
123 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
124}
125module_init(add_bus_probe);
126
127#ifdef CONFIG_PCI
128static int x86_of_pci_irq_enable(struct pci_dev *dev)
129{
130 struct of_irq oirq;
131 u32 virq;
132 int ret;
133 u8 pin;
134
135 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
136 if (ret)
137 return ret;
138 if (!pin)
139 return 0;
140
141 ret = of_irq_map_pci(dev, &oirq);
142 if (ret)
143 return ret;
144
145 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
146 oirq.size);
147 if (virq == 0)
148 return -EINVAL;
149 dev->irq = virq;
150 return 0;
151}
152
153static void x86_of_pci_irq_disable(struct pci_dev *dev)
154{
155}
156
157void __cpuinit x86_of_pci_init(void)
158{
159 struct device_node *np;
160
161 pcibios_enable_irq = x86_of_pci_irq_enable;
162 pcibios_disable_irq = x86_of_pci_irq_disable;
163
164 for_each_node_by_type(np, "pci") {
165 const void *prop;
166 struct pci_bus *bus;
167 unsigned int bus_min;
168 struct device_node *child;
169
170 prop = of_get_property(np, "bus-range", NULL);
171 if (!prop)
172 continue;
173 bus_min = be32_to_cpup(prop);
174
175 bus = pci_find_bus(0, bus_min);
176 if (!bus) {
177 printk(KERN_ERR "Can't find a node for bus %s.\n",
178 np->full_name);
179 continue;
180 }
181
182 if (bus->self)
183 bus->self->dev.of_node = np;
184 else
185 bus->dev.of_node = np;
186
187 for_each_child_of_node(np, child) {
188 struct pci_dev *dev;
189 u32 devfn;
190
191 prop = of_get_property(child, "reg", NULL);
192 if (!prop)
193 continue;
194
195 devfn = (be32_to_cpup(prop) >> 8) & 0xff;
196 dev = pci_get_slot(bus, devfn);
197 if (!dev)
198 continue;
199 dev->dev.of_node = child;
200 pci_dev_put(dev);
201 }
202 }
203}
204#endif
205
206static void __init dtb_setup_hpet(void)
207{
208#ifdef CONFIG_HPET_TIMER
209 struct device_node *dn;
210 struct resource r;
211 int ret;
212
213 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
214 if (!dn)
215 return;
216 ret = of_address_to_resource(dn, 0, &r);
217 if (ret) {
218 WARN_ON(1);
219 return;
220 }
221 hpet_address = r.start;
222#endif
223}
224
225static void __init dtb_lapic_setup(void)
226{
227#ifdef CONFIG_X86_LOCAL_APIC
228 struct device_node *dn;
229 struct resource r;
230 int ret;
231
232 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
233 if (!dn)
234 return;
235
236 ret = of_address_to_resource(dn, 0, &r);
237 if (WARN_ON(ret))
238 return;
239
240 /* Did the boot loader setup the local APIC ? */
241 if (!cpu_has_apic) {
242 if (apic_force_enable(r.start))
243 return;
244 }
245 smp_found_config = 1;
246 pic_mode = 1;
247 register_lapic_address(r.start);
248 generic_processor_info(boot_cpu_physical_apicid,
249 GET_APIC_VERSION(apic_read(APIC_LVR)));
250#endif
251}
252
253#ifdef CONFIG_X86_IO_APIC
254static unsigned int ioapic_id;
255
256static void __init dtb_add_ioapic(struct device_node *dn)
257{
258 struct resource r;
259 int ret;
260
261 ret = of_address_to_resource(dn, 0, &r);
262 if (ret) {
263 printk(KERN_ERR "Can't obtain address from node %s.\n",
264 dn->full_name);
265 return;
266 }
267 mp_register_ioapic(++ioapic_id, r.start, gsi_top);
268}
269
270static void __init dtb_ioapic_setup(void)
271{
272 struct device_node *dn;
273
274 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
275 dtb_add_ioapic(dn);
276
277 if (nr_ioapics) {
278 of_ioapic = 1;
279 return;
280 }
281 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
282}
283#else
284static void __init dtb_ioapic_setup(void) {}
285#endif
286
287static void __init dtb_apic_setup(void)
288{
289 dtb_lapic_setup();
290 dtb_ioapic_setup();
291}
292
293#ifdef CONFIG_OF_FLATTREE
294static void __init x86_flattree_get_config(void)
295{
296 u32 size, map_len;
297 void *new_dtb;
298
299 if (!initial_dtb)
300 return;
301
302 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
303 (u64)sizeof(struct boot_param_header));
304
305 initial_boot_params = early_memremap(initial_dtb, map_len);
306 size = be32_to_cpu(initial_boot_params->totalsize);
307 if (map_len < size) {
308 early_iounmap(initial_boot_params, map_len);
309 initial_boot_params = early_memremap(initial_dtb, size);
310 map_len = size;
311 }
312
313 new_dtb = alloc_bootmem(size);
314 memcpy(new_dtb, initial_boot_params, size);
315 early_iounmap(initial_boot_params, map_len);
316
317 initial_boot_params = new_dtb;
318
319 /* root level address cells */
320 of_scan_flat_dt(early_init_dt_scan_root, NULL);
321
322 unflatten_device_tree();
323}
324#else
325static inline void x86_flattree_get_config(void) { }
326#endif
327
328void __init x86_dtb_init(void)
329{
330 x86_flattree_get_config();
331
332 if (!of_have_populated_dt())
333 return;
334
335 dtb_setup_hpet();
336 dtb_apic_setup();
337}
338
339#ifdef CONFIG_X86_IO_APIC
340
341struct of_ioapic_type {
342 u32 out_type;
343 u32 trigger;
344 u32 polarity;
345};
346
347static struct of_ioapic_type of_ioapic_type[] =
348{
349 {
350 .out_type = IRQ_TYPE_EDGE_RISING,
351 .trigger = IOAPIC_EDGE,
352 .polarity = 1,
353 },
354 {
355 .out_type = IRQ_TYPE_LEVEL_LOW,
356 .trigger = IOAPIC_LEVEL,
357 .polarity = 0,
358 },
359 {
360 .out_type = IRQ_TYPE_LEVEL_HIGH,
361 .trigger = IOAPIC_LEVEL,
362 .polarity = 1,
363 },
364 {
365 .out_type = IRQ_TYPE_EDGE_FALLING,
366 .trigger = IOAPIC_EDGE,
367 .polarity = 0,
368 },
369};
370
371static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
372 u32 *out_hwirq, u32 *out_type)
373{
374 struct io_apic_irq_attr attr;
375 struct of_ioapic_type *it;
376 u32 line, idx, type;
377
378 if (intsize < 2)
379 return -EINVAL;
380
381 line = *intspec;
382 idx = (u32) id->priv;
383 *out_hwirq = line + mp_gsi_routing[idx].gsi_base;
384
385 intspec++;
386 type = *intspec;
387
388 if (type >= ARRAY_SIZE(of_ioapic_type))
389 return -EINVAL;
390
391 it = of_ioapic_type + type;
392 *out_type = it->out_type;
393
394 set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
395
396 return io_apic_setup_irq_pin(*out_hwirq, cpu_to_node(0), &attr);
397}
398
399static void __init ioapic_add_ofnode(struct device_node *np)
400{
401 struct resource r;
402 int i, ret;
403
404 ret = of_address_to_resource(np, 0, &r);
405 if (ret) {
406 printk(KERN_ERR "Failed to obtain address for %s\n",
407 np->full_name);
408 return;
409 }
410
411 for (i = 0; i < nr_ioapics; i++) {
412 if (r.start == mp_ioapics[i].apicaddr) {
413 struct irq_domain *id;
414
415 id = kzalloc(sizeof(*id), GFP_KERNEL);
416 BUG_ON(!id);
417 id->controller = np;
418 id->xlate = ioapic_xlate;
419 id->priv = (void *)i;
420 add_interrupt_host(id);
421 return;
422 }
423 }
424 printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
425}
426
427void __init x86_add_irq_domains(void)
428{
429 struct device_node *dp;
430
431 if (!of_have_populated_dt())
432 return;
433
434 for_each_node_with_property(dp, "interrupt-controller") {
435 if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
436 ioapic_add_ofnode(dp);
437 }
438}
439#else
440void __init x86_add_irq_domains(void) { }
441#endif
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 0b5e2b546566..cdf5bfd9d4d5 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -667,21 +667,15 @@ __init void e820_setup_gap(void)
667 * boot_params.e820_map, others are passed via SETUP_E820_EXT node of 667 * boot_params.e820_map, others are passed via SETUP_E820_EXT node of
668 * linked list of struct setup_data, which is parsed here. 668 * linked list of struct setup_data, which is parsed here.
669 */ 669 */
670void __init parse_e820_ext(struct setup_data *sdata, unsigned long pa_data) 670void __init parse_e820_ext(struct setup_data *sdata)
671{ 671{
672 u32 map_len;
673 int entries; 672 int entries;
674 struct e820entry *extmap; 673 struct e820entry *extmap;
675 674
676 entries = sdata->len / sizeof(struct e820entry); 675 entries = sdata->len / sizeof(struct e820entry);
677 map_len = sdata->len + sizeof(struct setup_data);
678 if (map_len > PAGE_SIZE)
679 sdata = early_ioremap(pa_data, map_len);
680 extmap = (struct e820entry *)(sdata->data); 676 extmap = (struct e820entry *)(sdata->data);
681 __append_e820_map(extmap, entries); 677 __append_e820_map(extmap, entries);
682 sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map); 678 sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
683 if (map_len > PAGE_SIZE)
684 early_iounmap(sdata, map_len);
685 printk(KERN_INFO "extended physical RAM map:\n"); 679 printk(KERN_INFO "extended physical RAM map:\n");
686 e820_print_map("extended"); 680 e820_print_map("extended");
687} 681}
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 187aa63b321f..ce0be7cd085e 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -137,7 +137,7 @@ ENTRY(startup_32)
137 movsl 137 movsl
1381: 1381:
139 139
140#ifdef CONFIG_OLPC_OPENFIRMWARE 140#ifdef CONFIG_OLPC
141 /* save OFW's pgdir table for later use when calling into OFW */ 141 /* save OFW's pgdir table for later use when calling into OFW */
142 movl %cr3, %eax 142 movl %cr3, %eax
143 movl %eax, pa(olpc_ofw_pgd) 143 movl %eax, pa(olpc_ofw_pgd)
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 5ee693faa111..948a31eae75f 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -223,15 +223,6 @@ void smp_x86_platform_ipi(struct pt_regs *regs)
223 223
224EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); 224EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
225 225
226#ifdef CONFIG_OF
227unsigned int irq_create_of_mapping(struct device_node *controller,
228 const u32 *intspec, unsigned int intsize)
229{
230 return intspec[0];
231}
232EXPORT_SYMBOL_GPL(irq_create_of_mapping);
233#endif
234
235#ifdef CONFIG_HOTPLUG_CPU 226#ifdef CONFIG_HOTPLUG_CPU
236/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ 227/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
237void fixup_irqs(void) 228void fixup_irqs(void)
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index d30854b18d25..f470e4ef993e 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -25,6 +25,7 @@
25#include <asm/setup.h> 25#include <asm/setup.h>
26#include <asm/i8259.h> 26#include <asm/i8259.h>
27#include <asm/traps.h> 27#include <asm/traps.h>
28#include <asm/prom.h>
28 29
29/* 30/*
30 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 31 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
@@ -120,6 +121,12 @@ void __init init_IRQ(void)
120 int i; 121 int i;
121 122
122 /* 123 /*
124 * We probably need a better place for this, but it works for
125 * now ...
126 */
127 x86_add_irq_domains();
128
129 /*
123 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15. 130 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
124 * If these IRQ's are handled by legacy interrupt-controllers like PIC, 131 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
125 * then this configuration will likely be static after the boot. If 132 * then this configuration will likely be static after the boot. If
@@ -308,7 +315,7 @@ void __init native_init_IRQ(void)
308 set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]); 315 set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
309 } 316 }
310 317
311 if (!acpi_ioapic) 318 if (!acpi_ioapic && !of_ioapic)
312 setup_irq(2, &irq2); 319 setup_irq(2, &irq2);
313 320
314#ifdef CONFIG_X86_32 321#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/rtc.c b/arch/x86/kernel/rtc.c
index 6f39cab052d5..3f2ad2640d85 100644
--- a/arch/x86/kernel/rtc.c
+++ b/arch/x86/kernel/rtc.c
@@ -6,6 +6,7 @@
6#include <linux/acpi.h> 6#include <linux/acpi.h>
7#include <linux/bcd.h> 7#include <linux/bcd.h>
8#include <linux/pnp.h> 8#include <linux/pnp.h>
9#include <linux/of.h>
9 10
10#include <asm/vsyscall.h> 11#include <asm/vsyscall.h>
11#include <asm/x86_init.h> 12#include <asm/x86_init.h>
@@ -236,6 +237,8 @@ static __init int add_rtc_cmos(void)
236 } 237 }
237 } 238 }
238#endif 239#endif
240 if (of_have_populated_dt())
241 return 0;
239 242
240 platform_device_register(&rtc_device); 243 platform_device_register(&rtc_device);
241 dev_info(&rtc_device.dev, 244 dev_info(&rtc_device.dev,
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index c3a606c41ce0..b176f2b1f45d 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -113,6 +113,7 @@
113#endif 113#endif
114#include <asm/mce.h> 114#include <asm/mce.h>
115#include <asm/alternative.h> 115#include <asm/alternative.h>
116#include <asm/prom.h>
116 117
117/* 118/*
118 * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries. 119 * end_pfn only includes RAM, while max_pfn_mapped includes all e820 entries.
@@ -453,16 +454,30 @@ static void __init parse_setup_data(void)
453 return; 454 return;
454 pa_data = boot_params.hdr.setup_data; 455 pa_data = boot_params.hdr.setup_data;
455 while (pa_data) { 456 while (pa_data) {
456 data = early_memremap(pa_data, PAGE_SIZE); 457 u32 data_len, map_len;
458
459 map_len = max(PAGE_SIZE - (pa_data & ~PAGE_MASK),
460 (u64)sizeof(struct setup_data));
461 data = early_memremap(pa_data, map_len);
462 data_len = data->len + sizeof(struct setup_data);
463 if (data_len > map_len) {
464 early_iounmap(data, map_len);
465 data = early_memremap(pa_data, data_len);
466 map_len = data_len;
467 }
468
457 switch (data->type) { 469 switch (data->type) {
458 case SETUP_E820_EXT: 470 case SETUP_E820_EXT:
459 parse_e820_ext(data, pa_data); 471 parse_e820_ext(data);
472 break;
473 case SETUP_DTB:
474 add_dtb(pa_data);
460 break; 475 break;
461 default: 476 default:
462 break; 477 break;
463 } 478 }
464 pa_data = data->next; 479 pa_data = data->next;
465 early_iounmap(data, PAGE_SIZE); 480 early_iounmap(data, map_len);
466 } 481 }
467} 482}
468 483
@@ -1030,8 +1045,8 @@ void __init setup_arch(char **cmdline_p)
1030 * Read APIC and some other early information from ACPI tables. 1045 * Read APIC and some other early information from ACPI tables.
1031 */ 1046 */
1032 acpi_boot_init(); 1047 acpi_boot_init();
1033
1034 sfi_init(); 1048 sfi_init();
1049 x86_dtb_init();
1035 1050
1036 /* 1051 /*
1037 * get boot-time SMP configuration: 1052 * get boot-time SMP configuration:
@@ -1065,6 +1080,8 @@ void __init setup_arch(char **cmdline_p)
1065#endif 1080#endif
1066 x86_init.oem.banner(); 1081 x86_init.oem.banner();
1067 1082
1083 x86_init.timers.wallclock_init();
1084
1068 mcheck_init(); 1085 mcheck_init();
1069 1086
1070 local_irq_save(flags); 1087 local_irq_save(flags);
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index ceb2911aa439..c11514e9128b 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -70,6 +70,7 @@ struct x86_init_ops x86_init __initdata = {
70 .setup_percpu_clockev = setup_boot_APIC_clock, 70 .setup_percpu_clockev = setup_boot_APIC_clock,
71 .tsc_pre_init = x86_init_noop, 71 .tsc_pre_init = x86_init_noop,
72 .timer_init = hpet_time_init, 72 .timer_init = hpet_time_init,
73 .wallclock_init = x86_init_noop,
73 }, 74 },
74 75
75 .iommu = { 76 .iommu = {
diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c
index 9260b3eb18d4..67858be4b52b 100644
--- a/arch/x86/pci/ce4100.c
+++ b/arch/x86/pci/ce4100.c
@@ -255,7 +255,7 @@ int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
255static int ce4100_conf_read(unsigned int seg, unsigned int bus, 255static int ce4100_conf_read(unsigned int seg, unsigned int bus,
256 unsigned int devfn, int reg, int len, u32 *value) 256 unsigned int devfn, int reg, int len, u32 *value)
257{ 257{
258 int i, retval = 1; 258 int i;
259 259
260 if (bus == 1) { 260 if (bus == 1) {
261 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { 261 for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index cd6f184c3b3f..28071bb31db7 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -16,21 +16,19 @@
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17 17
18#include <asm/ce4100.h> 18#include <asm/ce4100.h>
19#include <asm/prom.h>
19#include <asm/setup.h> 20#include <asm/setup.h>
21#include <asm/i8259.h>
20#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/io_apic.h>
21 24
22static int ce4100_i8042_detect(void) 25static int ce4100_i8042_detect(void)
23{ 26{
24 return 0; 27 return 0;
25} 28}
26 29
27static void __init sdv_find_smp_config(void)
28{
29}
30
31#ifdef CONFIG_SERIAL_8250 30#ifdef CONFIG_SERIAL_8250
32 31
33
34static unsigned int mem_serial_in(struct uart_port *p, int offset) 32static unsigned int mem_serial_in(struct uart_port *p, int offset)
35{ 33{
36 offset = offset << p->regshift; 34 offset = offset << p->regshift;
@@ -119,6 +117,15 @@ static void __init sdv_arch_setup(void)
119 sdv_serial_fixup(); 117 sdv_serial_fixup();
120} 118}
121 119
120#ifdef CONFIG_X86_IO_APIC
121static void __cpuinit sdv_pci_init(void)
122{
123 x86_of_pci_init();
124 /* We can't set this earlier, because we need to calibrate the timer */
125 legacy_pic = &null_legacy_pic;
126}
127#endif
128
122/* 129/*
123 * CE4100 specific x86_init function overrides and early setup 130 * CE4100 specific x86_init function overrides and early setup
124 * calls. 131 * calls.
@@ -129,6 +136,11 @@ void __init x86_ce4100_early_setup(void)
129 x86_platform.i8042_detect = ce4100_i8042_detect; 136 x86_platform.i8042_detect = ce4100_i8042_detect;
130 x86_init.resources.probe_roms = x86_init_noop; 137 x86_init.resources.probe_roms = x86_init_noop;
131 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 138 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
132 x86_init.mpparse.find_smp_config = sdv_find_smp_config; 139 x86_init.mpparse.find_smp_config = x86_init_noop;
133 x86_init.pci.init = ce4100_pci_init; 140 x86_init.pci.init = ce4100_pci_init;
141
142#ifdef CONFIG_X86_IO_APIC
143 x86_init.pci.init_irq = sdv_pci_init;
144 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
145#endif
134} 146}
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
new file mode 100644
index 000000000000..dc701ea58546
--- /dev/null
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -0,0 +1,428 @@
1/*
2 * CE4100 on Falcon Falls
3 *
4 * (c) Copyright 2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License.
9 */
10/dts-v1/;
11/ {
12 model = "intel,falconfalls";
13 compatible = "intel,falconfalls";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "intel,ce4100";
24 reg = <0>;
25 lapic = <&lapic0>;
26 };
27 };
28
29 soc@0 {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 compatible = "intel,ce4100-cp";
33 ranges;
34
35 ioapic1: interrupt-controller@fec00000 {
36 #interrupt-cells = <2>;
37 compatible = "intel,ce4100-ioapic";
38 interrupt-controller;
39 reg = <0xfec00000 0x1000>;
40 };
41
42 timer@fed00000 {
43 compatible = "intel,ce4100-hpet";
44 reg = <0xfed00000 0x200>;
45 };
46
47 lapic0: interrupt-controller@fee00000 {
48 compatible = "intel,ce4100-lapic";
49 reg = <0xfee00000 0x1000>;
50 };
51
52 pci@3fc {
53 #address-cells = <3>;
54 #size-cells = <2>;
55 compatible = "intel,ce4100-pci", "pci";
56 device_type = "pci";
57 bus-range = <0 0>;
58 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
59 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
60 0x0000000 0 0x0 0x0 0 0x100>;
61
62 /* Secondary IO-APIC */
63 ioapic2: interrupt-controller@0,1 {
64 #interrupt-cells = <2>;
65 compatible = "intel,ce4100-ioapic";
66 interrupt-controller;
67 reg = <0x100 0x0 0x0 0x0 0x0>;
68 assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
69 };
70
71 pci@1,0 {
72 #address-cells = <3>;
73 #size-cells = <2>;
74 compatible = "intel,ce4100-pci", "pci";
75 device_type = "pci";
76 bus-range = <1 1>;
77 ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
78
79 interrupt-parent = <&ioapic2>;
80
81 display@2,0 {
82 compatible = "pci8086,2e5b.2",
83 "pci8086,2e5b",
84 "pciclass038000",
85 "pciclass0380";
86
87 reg = <0x11000 0x0 0x0 0x0 0x0>;
88 interrupts = <0 1>;
89 };
90
91 multimedia@3,0 {
92 compatible = "pci8086,2e5c.2",
93 "pci8086,2e5c",
94 "pciclass048000",
95 "pciclass0480";
96
97 reg = <0x11800 0x0 0x0 0x0 0x0>;
98 interrupts = <2 1>;
99 };
100
101 multimedia@4,0 {
102 compatible = "pci8086,2e5d.2",
103 "pci8086,2e5d",
104 "pciclass048000",
105 "pciclass0480";
106
107 reg = <0x12000 0x0 0x0 0x0 0x0>;
108 interrupts = <4 1>;
109 };
110
111 multimedia@4,1 {
112 compatible = "pci8086,2e5e.2",
113 "pci8086,2e5e",
114 "pciclass048000",
115 "pciclass0480";
116
117 reg = <0x12100 0x0 0x0 0x0 0x0>;
118 interrupts = <5 1>;
119 };
120
121 sound@6,0 {
122 compatible = "pci8086,2e5f.2",
123 "pci8086,2e5f",
124 "pciclass040100",
125 "pciclass0401";
126
127 reg = <0x13000 0x0 0x0 0x0 0x0>;
128 interrupts = <6 1>;
129 };
130
131 sound@6,1 {
132 compatible = "pci8086,2e5f.2",
133 "pci8086,2e5f",
134 "pciclass040100",
135 "pciclass0401";
136
137 reg = <0x13100 0x0 0x0 0x0 0x0>;
138 interrupts = <7 1>;
139 };
140
141 sound@6,2 {
142 compatible = "pci8086,2e60.2",
143 "pci8086,2e60",
144 "pciclass040100",
145 "pciclass0401";
146
147 reg = <0x13200 0x0 0x0 0x0 0x0>;
148 interrupts = <8 1>;
149 };
150
151 display@8,0 {
152 compatible = "pci8086,2e61.2",
153 "pci8086,2e61",
154 "pciclass038000",
155 "pciclass0380";
156
157 reg = <0x14000 0x0 0x0 0x0 0x0>;
158 interrupts = <9 1>;
159 };
160
161 display@8,1 {
162 compatible = "pci8086,2e62.2",
163 "pci8086,2e62",
164 "pciclass038000",
165 "pciclass0380";
166
167 reg = <0x14100 0x0 0x0 0x0 0x0>;
168 interrupts = <10 1>;
169 };
170
171 multimedia@8,2 {
172 compatible = "pci8086,2e63.2",
173 "pci8086,2e63",
174 "pciclass048000",
175 "pciclass0480";
176
177 reg = <0x14200 0x0 0x0 0x0 0x0>;
178 interrupts = <11 1>;
179 };
180
181 entertainment-encryption@9,0 {
182 compatible = "pci8086,2e64.2",
183 "pci8086,2e64",
184 "pciclass101000",
185 "pciclass1010";
186
187 reg = <0x14800 0x0 0x0 0x0 0x0>;
188 interrupts = <12 1>;
189 };
190
191 localbus@a,0 {
192 compatible = "pci8086,2e65.2",
193 "pci8086,2e65",
194 "pciclassff0000",
195 "pciclassff00";
196
197 reg = <0x15000 0x0 0x0 0x0 0x0>;
198 };
199
200 serial@b,0 {
201 compatible = "pci8086,2e66.2",
202 "pci8086,2e66",
203 "pciclass070003",
204 "pciclass0700";
205
206 reg = <0x15800 0x0 0x0 0x0 0x0>;
207 interrupts = <14 1>;
208 };
209
210 gpio@b,1 {
211 compatible = "pci8086,2e67.2",
212 "pci8086,2e67",
213 "pciclassff0000",
214 "pciclassff00";
215
216 #gpio-cells = <2>;
217 reg = <0x15900 0x0 0x0 0x0 0x0>;
218 interrupts = <15 1>;
219 gpio-controller;
220 };
221
222 i2c-controller@b,2 {
223 #address-cells = <2>;
224 #size-cells = <1>;
225 compatible = "pci8086,2e68.2",
226 "pci8086,2e68",
227 "pciclass,ff0000",
228 "pciclass,ff00";
229
230 reg = <0x15a00 0x0 0x0 0x0 0x0>;
231 interrupts = <16 1>;
232 ranges = <0 0 0x02000000 0 0xdffe0500 0x100
233 1 0 0x02000000 0 0xdffe0600 0x100
234 2 0 0x02000000 0 0xdffe0700 0x100>;
235
236 i2c@0 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "intel,ce4100-i2c-controller";
240 reg = <0 0 0x100>;
241 };
242
243 i2c@1 {
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "intel,ce4100-i2c-controller";
247 reg = <1 0 0x100>;
248
249 gpio@26 {
250 #gpio-cells = <2>;
251 compatible = "ti,pcf8575";
252 reg = <0x26>;
253 gpio-controller;
254 };
255 };
256
257 i2c@2 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "intel,ce4100-i2c-controller";
261 reg = <2 0 0x100>;
262
263 gpio@26 {
264 #gpio-cells = <2>;
265 compatible = "ti,pcf8575";
266 reg = <0x26>;
267 gpio-controller;
268 };
269 };
270 };
271
272 smard-card@b,3 {
273 compatible = "pci8086,2e69.2",
274 "pci8086,2e69",
275 "pciclass070500",
276 "pciclass0705";
277
278 reg = <0x15b00 0x0 0x0 0x0 0x0>;
279 interrupts = <15 1>;
280 };
281
282 spi-controller@b,4 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible =
286 "pci8086,2e6a.2",
287 "pci8086,2e6a",
288 "pciclass,ff0000",
289 "pciclass,ff00";
290
291 reg = <0x15c00 0x0 0x0 0x0 0x0>;
292 interrupts = <15 1>;
293
294 dac@0 {
295 compatible = "ti,pcm1755";
296 reg = <0>;
297 spi-max-frequency = <115200>;
298 };
299
300 dac@1 {
301 compatible = "ti,pcm1609a";
302 reg = <1>;
303 spi-max-frequency = <115200>;
304 };
305
306 eeprom@2 {
307 compatible = "atmel,at93c46";
308 reg = <2>;
309 spi-max-frequency = <115200>;
310 };
311 };
312
313 multimedia@b,7 {
314 compatible = "pci8086,2e6d.2",
315 "pci8086,2e6d",
316 "pciclassff0000",
317 "pciclassff00";
318
319 reg = <0x15f00 0x0 0x0 0x0 0x0>;
320 };
321
322 ethernet@c,0 {
323 compatible = "pci8086,2e6e.2",
324 "pci8086,2e6e",
325 "pciclass020000",
326 "pciclass0200";
327
328 reg = <0x16000 0x0 0x0 0x0 0x0>;
329 interrupts = <21 1>;
330 };
331
332 clock@c,1 {
333 compatible = "pci8086,2e6f.2",
334 "pci8086,2e6f",
335 "pciclassff0000",
336 "pciclassff00";
337
338 reg = <0x16100 0x0 0x0 0x0 0x0>;
339 interrupts = <3 1>;
340 };
341
342 usb@d,0 {
343 compatible = "pci8086,2e70.2",
344 "pci8086,2e70",
345 "pciclass0c0320",
346 "pciclass0c03";
347
348 reg = <0x16800 0x0 0x0 0x0 0x0>;
349 interrupts = <22 3>;
350 };
351
352 usb@d,1 {
353 compatible = "pci8086,2e70.2",
354 "pci8086,2e70",
355 "pciclass0c0320",
356 "pciclass0c03";
357
358 reg = <0x16900 0x0 0x0 0x0 0x0>;
359 interrupts = <22 3>;
360 };
361
362 sata@e,0 {
363 compatible = "pci8086,2e71.0",
364 "pci8086,2e71",
365 "pciclass010601",
366 "pciclass0106";
367
368 reg = <0x17000 0x0 0x0 0x0 0x0>;
369 interrupts = <23 3>;
370 };
371
372 flash@f,0 {
373 compatible = "pci8086,701.1",
374 "pci8086,701",
375 "pciclass050100",
376 "pciclass0501";
377
378 reg = <0x17800 0x0 0x0 0x0 0x0>;
379 interrupts = <13 1>;
380 };
381
382 entertainment-encryption@10,0 {
383 compatible = "pci8086,702.1",
384 "pci8086,702",
385 "pciclass101000",
386 "pciclass1010";
387
388 reg = <0x18000 0x0 0x0 0x0 0x0>;
389 };
390
391 co-processor@11,0 {
392 compatible = "pci8086,703.1",
393 "pci8086,703",
394 "pciclass0b4000",
395 "pciclass0b40";
396
397 reg = <0x18800 0x0 0x0 0x0 0x0>;
398 interrupts = <1 1>;
399 };
400
401 multimedia@12,0 {
402 compatible = "pci8086,704.0",
403 "pci8086,704",
404 "pciclass048000",
405 "pciclass0480";
406
407 reg = <0x19000 0x0 0x0 0x0 0x0>;
408 };
409 };
410
411 isa@1f,0 {
412 #address-cells = <2>;
413 #size-cells = <1>;
414 compatible = "isa";
415 ranges = <1 0 0 0 0 0x100>;
416
417 rtc@70 {
418 compatible = "intel,ce4100-rtc", "motorola,mc146818";
419 interrupts = <8 3>;
420 interrupt-parent = <&ioapic1>;
421 ctrl-reg = <2>;
422 freq-reg = <0x26>;
423 reg = <1 0x70 2>;
424 };
425 };
426 };
427 };
428};
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index ea6529e93c6f..5c0207bf959b 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -31,6 +31,7 @@
31#include <asm/apic.h> 31#include <asm/apic.h>
32#include <asm/io_apic.h> 32#include <asm/io_apic.h>
33#include <asm/mrst.h> 33#include <asm/mrst.h>
34#include <asm/mrst-vrtc.h>
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/i8259.h> 36#include <asm/i8259.h>
36#include <asm/intel_scu_ipc.h> 37#include <asm/intel_scu_ipc.h>
@@ -268,6 +269,7 @@ void __init x86_mrst_early_setup(void)
268 269
269 x86_platform.calibrate_tsc = mrst_calibrate_tsc; 270 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
270 x86_platform.i8042_detect = mrst_i8042_detect; 271 x86_platform.i8042_detect = mrst_i8042_detect;
272 x86_init.timers.wallclock_init = mrst_rtc_init;
271 x86_init.pci.init = pci_mrst_init; 273 x86_init.pci.init = pci_mrst_init;
272 x86_init.pci.fixup_irqs = x86_init_noop; 274 x86_init.pci.fixup_irqs = x86_init_noop;
273 275
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
index 32cd7edd71a0..04cf645feb92 100644
--- a/arch/x86/platform/mrst/vrtc.c
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -100,22 +100,14 @@ int vrtc_set_mmss(unsigned long nowtime)
100 100
101void __init mrst_rtc_init(void) 101void __init mrst_rtc_init(void)
102{ 102{
103 unsigned long rtc_paddr; 103 unsigned long vrtc_paddr = sfi_mrtc_array[0].phys_addr;
104 void __iomem *virt_base;
105 104
106 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc); 105 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
107 if (!sfi_mrtc_num) 106 if (!sfi_mrtc_num || !vrtc_paddr)
108 return; 107 return;
109 108
110 rtc_paddr = sfi_mrtc_array[0].phys_addr; 109 vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC,
111 110 vrtc_paddr);
112 /* vRTC's register address may not be page aligned */
113 set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr);
114
115 virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC);
116 virt_base += rtc_paddr & ~PAGE_MASK;
117 vrtc_virt_base = virt_base;
118
119 x86_platform.get_wallclock = vrtc_get_time; 111 x86_platform.get_wallclock = vrtc_get_time;
120 x86_platform.set_wallclock = vrtc_set_mmss; 112 x86_platform.set_wallclock = vrtc_set_mmss;
121} 113}
diff --git a/arch/x86/platform/olpc/Makefile b/arch/x86/platform/olpc/Makefile
index e797428b163b..c2a8cab65e5d 100644
--- a/arch/x86/platform/olpc/Makefile
+++ b/arch/x86/platform/olpc/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_OLPC) += olpc.o 1obj-$(CONFIG_OLPC) += olpc.o
2obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o 2obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o
3obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o 3obj-$(CONFIG_OLPC) += olpc_ofw.o
4obj-$(CONFIG_OLPC_OPENFIRMWARE_DT) += olpc_dt.o 4obj-$(CONFIG_OF_PROMTREE) += olpc_dt.o
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 03:50:19 -0500