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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 12:00:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-23 12:00:40 -0400
commit1d767cae4dbd4116fc3b2cc3251a20760f98339f (patch)
tree79a1a48a67a9b4296ce062d61ee863fe7a46c77f /arch/sh/kernel
parent6101167727932a929e37fb8a6eeb68bdbf54d58e (diff)
parent5f19f14fed7786652b9617c633db101d26a42251 (diff)
Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
Pull SuperH updates from Paul Mundt: - New CPUs: SH7734 (SH-4A), SH7264 and SH7269 (SH-2A) - New boards: RSK2+SH7264, RSK2+SH7269 - Unbreaking kgdb for SMP - Consolidation of _32/_64 page fault handling. - watchdog and legacy DMA chainsawing, part 1 - Conversion to evt2irq() hwirq lookup, to support relocation of vectored IRQs for irqdomains. * tag 'sh-for-linus' of git://github.com/pmundt/linux-sh: (98 commits) sh: intc: Kill off special reservation interface. sh: Enable PIO API for hp6xx and se770x. sh: Kill off machvec IRQ hinting. sh: dma: More legacy cpu dma chainsawing. sh: Kill off MAX_DMA_ADDRESS leftovers. sh: Tidy up some of the cpu legacy dma header mess. sh: Move sh4a dma header from cpu-sh4 to cpu-sh4a. sh64: Fix up vmalloc fault range check. Revert "sh: Ensure fixmap and store queue space can co-exist." serial: sh-sci: Fix for port types without BRI interrupts. sh: legacy PCI evt2irq migration. sh: cpu dma evt2irq migration. sh: sh7763rdp evt2irq migration. sh: sdk7780 evt2irq migration. sh: migor evt2irq migration. sh: landisk evt2irq migration. sh: kfr2r09 evt2irq migration. sh: ecovec24 evt2irq migration. sh: ap325rxa evt2irq migration. sh: urquell evt2irq migration. ...
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/proc.c4
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/Makefile4
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7264.c153
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7269.c184
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c2136
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c2800
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c2
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c16
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7264.c606
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7269.c615
-rw-r--r--arch/sh/kernel/cpu/sh3/entry.S11
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c13
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c15
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c13
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c32
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c3
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c12
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c17
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c26
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7734.c266
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c2497
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c31
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c23
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c77
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c800
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c90
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c39
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c37
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c43
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c31
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S22
-rw-r--r--arch/sh/kernel/cpu/sh5/fpu.c3
-rw-r--r--arch/sh/kernel/irq.c6
-rw-r--r--arch/sh/kernel/kgdb.c105
-rw-r--r--arch/sh/kernel/machvec.c3
-rw-r--r--arch/sh/kernel/process.c7
-rw-r--r--arch/sh/kernel/process_32.c5
-rw-r--r--arch/sh/kernel/traps_64.c2
47 files changed, 10572 insertions, 379 deletions
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index f47be8727b3b..9e6624c9108b 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -7,6 +7,7 @@
7static const char *cpu_name[] = { 7static const char *cpu_name[] = {
8 [CPU_SH7201] = "SH7201", 8 [CPU_SH7201] = "SH7201",
9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", 9 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
10 [CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
10 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", 11 [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
11 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", 12 [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
12 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", 13 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
@@ -25,7 +26,8 @@ static const char *cpu_name[] = {
25 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 26 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
26 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 27 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
27 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724", 28 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
28 [CPU_SH7372] = "SH7372", [CPU_SH_NONE] = "Unknown" 29 [CPU_SH7372] = "SH7372", [CPU_SH7734] = "SH7734",
30 [CPU_SH_NONE] = "Unknown"
29}; 31};
30 32
31const char *get_cpu_subtype(struct sh_cpuinfo *c) 33const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 0f8befccf9fa..e0b740c831c7 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -65,7 +65,7 @@ static struct plat_sci_port scif0_platform_data = {
65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
66 .scbrr_algo_id = SCBRR_ALGO_2, 66 .scbrr_algo_id = SCBRR_ALGO_2,
67 .type = PORT_SCIF, 67 .type = PORT_SCIF,
68 .irqs = { 88, 88, 88, 88 }, 68 .irqs = SCIx_IRQ_MUXED(88),
69}; 69};
70 70
71static struct platform_device scif0_device = { 71static struct platform_device scif0_device = {
@@ -82,7 +82,7 @@ static struct plat_sci_port scif1_platform_data = {
82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
83 .scbrr_algo_id = SCBRR_ALGO_2, 83 .scbrr_algo_id = SCBRR_ALGO_2,
84 .type = PORT_SCIF, 84 .type = PORT_SCIF,
85 .irqs = { 92, 92, 92, 92 }, 85 .irqs = SCIx_IRQ_MUXED(92),
86}; 86};
87 87
88static struct platform_device scif1_device = { 88static struct platform_device scif1_device = {
@@ -99,7 +99,7 @@ static struct plat_sci_port scif2_platform_data = {
99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 99 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
100 .scbrr_algo_id = SCBRR_ALGO_2, 100 .scbrr_algo_id = SCBRR_ALGO_2,
101 .type = PORT_SCIF, 101 .type = PORT_SCIF,
102 .irqs = { 96, 96, 96, 96 }, 102 .irqs = SCIx_IRQ_MUXED(96),
103}; 103};
104 104
105static struct platform_device scif2_device = { 105static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 45f85c77ef75..7fdc102d0dd6 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -11,10 +11,14 @@ obj-$(CONFIG_SH_FPU) += fpu.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7201) += setup-sh7201.o clock-sh7201.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o
15obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o 17obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
16 18
17# Pinmux setup 19# Pinmux setup
18pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o 20pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
21pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
22pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
19 23
20obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) 24obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7264.c b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
new file mode 100644
index 000000000000..fdf585c95289
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
@@ -0,0 +1,153 @@
1/*
2 * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
3 *
4 * SH7264 clock framework support
5 *
6 * Copyright (C) 2012 Phil Edworthy
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16#include <asm/clock.h>
17
18/* SH7264 registers */
19#define FRQCR 0xfffe0010
20#define STBCR3 0xfffe0408
21#define STBCR4 0xfffe040c
22#define STBCR5 0xfffe0410
23#define STBCR6 0xfffe0414
24#define STBCR7 0xfffe0418
25#define STBCR8 0xfffe041c
26
27static const unsigned int pll1rate[] = {8, 12};
28
29static unsigned int pll1_div;
30
31/* Fixed 32 KHz root clock for RTC */
32static struct clk r_clk = {
33 .rate = 32768,
34};
35
36/*
37 * Default rate for the root input clock, reset this with clk_set_rate()
38 * from the platform code.
39 */
40static struct clk extal_clk = {
41 .rate = 18000000,
42};
43
44static unsigned long pll_recalc(struct clk *clk)
45{
46 unsigned long rate = clk->parent->rate / pll1_div;
47 return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
48}
49
50static struct sh_clk_ops pll_clk_ops = {
51 .recalc = pll_recalc,
52};
53
54static struct clk pll_clk = {
55 .ops = &pll_clk_ops,
56 .parent = &extal_clk,
57 .flags = CLK_ENABLE_ON_INIT,
58};
59
60struct clk *main_clks[] = {
61 &r_clk,
62 &extal_clk,
63 &pll_clk,
64};
65
66static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
67
68static struct clk_div_mult_table div4_div_mult_table = {
69 .divisors = div2,
70 .nr_divisors = ARRAY_SIZE(div2),
71};
72
73static struct clk_div4_table div4_table = {
74 .div_mult_table = &div4_div_mult_table,
75};
76
77enum { DIV4_I, DIV4_P,
78 DIV4_NR };
79
80#define DIV4(_reg, _bit, _mask, _flags) \
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
82
83/* The mask field specifies the div2 entries that are valid */
84struct clk div4_clks[DIV4_NR] = {
85 [DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
86 | CLK_ENABLE_ON_INIT),
87 [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
88};
89
90enum { MSTP77, MSTP74, MSTP72,
91 MSTP60,
92 MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
93 MSTP_NR };
94
95static struct clk mstp_clks[MSTP_NR] = {
96 [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
97 [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
98 [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
99 [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
100 [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
101 [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
102 [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
103 [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
104 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
105};
106
107static struct clk_lookup lookups[] = {
108 /* main clocks */
109 CLKDEV_CON_ID("rclk", &r_clk),
110 CLKDEV_CON_ID("extal", &extal_clk),
111 CLKDEV_CON_ID("pll_clk", &pll_clk),
112
113 /* DIV4 clocks */
114 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
115 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
116
117 /* MSTP clocks */
118 CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
119 CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
120 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
121 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
122 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
123 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
124 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
125 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
126 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
127};
128
129int __init arch_clk_init(void)
130{
131 int k, ret = 0;
132
133 if (test_mode_pin(MODE_PIN0)) {
134 if (test_mode_pin(MODE_PIN1))
135 pll1_div = 3;
136 else
137 pll1_div = 4;
138 } else
139 pll1_div = 1;
140
141 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
142 ret = clk_register(main_clks[k]);
143
144 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
145
146 if (!ret)
147 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
148
149 if (!ret)
150 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
151
152 return ret;
153}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7269.c b/arch/sh/kernel/cpu/sh2a/clock-sh7269.c
new file mode 100644
index 000000000000..6b787620de99
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7269.c
@@ -0,0 +1,184 @@
1/*
2 * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
3 *
4 * SH7269 clock framework support
5 *
6 * Copyright (C) 2012 Phil Edworthy
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16#include <asm/clock.h>
17
18/* SH7269 registers */
19#define FRQCR 0xfffe0010
20#define STBCR3 0xfffe0408
21#define STBCR4 0xfffe040c
22#define STBCR5 0xfffe0410
23#define STBCR6 0xfffe0414
24#define STBCR7 0xfffe0418
25
26#define PLL_RATE 20
27
28/* Fixed 32 KHz root clock for RTC */
29static struct clk r_clk = {
30 .rate = 32768,
31};
32
33/*
34 * Default rate for the root input clock, reset this with clk_set_rate()
35 * from the platform code.
36 */
37static struct clk extal_clk = {
38 .rate = 13340000,
39};
40
41static unsigned long pll_recalc(struct clk *clk)
42{
43 return clk->parent->rate * PLL_RATE;
44}
45
46static struct sh_clk_ops pll_clk_ops = {
47 .recalc = pll_recalc,
48};
49
50static struct clk pll_clk = {
51 .ops = &pll_clk_ops,
52 .parent = &extal_clk,
53 .flags = CLK_ENABLE_ON_INIT,
54};
55
56static unsigned long peripheral0_recalc(struct clk *clk)
57{
58 return clk->parent->rate / 8;
59}
60
61static struct sh_clk_ops peripheral0_clk_ops = {
62 .recalc = peripheral0_recalc,
63};
64
65static struct clk peripheral0_clk = {
66 .ops = &peripheral0_clk_ops,
67 .parent = &pll_clk,
68 .flags = CLK_ENABLE_ON_INIT,
69};
70
71static unsigned long peripheral1_recalc(struct clk *clk)
72{
73 return clk->parent->rate / 4;
74}
75
76static struct sh_clk_ops peripheral1_clk_ops = {
77 .recalc = peripheral1_recalc,
78};
79
80static struct clk peripheral1_clk = {
81 .ops = &peripheral1_clk_ops,
82 .parent = &pll_clk,
83 .flags = CLK_ENABLE_ON_INIT,
84};
85
86struct clk *main_clks[] = {
87 &r_clk,
88 &extal_clk,
89 &pll_clk,
90 &peripheral0_clk,
91 &peripheral1_clk,
92};
93
94static int div2[] = { 1, 2, 0, 4 };
95
96static struct clk_div_mult_table div4_div_mult_table = {
97 .divisors = div2,
98 .nr_divisors = ARRAY_SIZE(div2),
99};
100
101static struct clk_div4_table div4_table = {
102 .div_mult_table = &div4_div_mult_table,
103};
104
105enum { DIV4_I, DIV4_B,
106 DIV4_NR };
107
108#define DIV4(_reg, _bit, _mask, _flags) \
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
110
111/* The mask field specifies the div2 entries that are valid */
112struct clk div4_clks[DIV4_NR] = {
113 [DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
114 | CLK_ENABLE_ON_INIT),
115 [DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
116 | CLK_ENABLE_ON_INIT),
117};
118
119enum { MSTP72,
120 MSTP60,
121 MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
122 MSTP35, MSTP32, MSTP30,
123 MSTP_NR };
124
125static struct clk mstp_clks[MSTP_NR] = {
126 [MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
127 [MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
128 [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
129 [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
130 [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
131 [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
132 [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
133 [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
134 [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
135 [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
136 [MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
137 [MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
138 [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
139};
140
141static struct clk_lookup lookups[] = {
142 /* main clocks */
143 CLKDEV_CON_ID("rclk", &r_clk),
144 CLKDEV_CON_ID("extal", &extal_clk),
145 CLKDEV_CON_ID("pll_clk", &pll_clk),
146 CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
147
148 /* DIV4 clocks */
149 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
150 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
151
152 /* MSTP clocks */
153 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
154 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
155 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
156 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
157 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
158 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
159 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
160 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
161 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
162 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
163 CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
164 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
165 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
166};
167
168int __init arch_clk_init(void)
169{
170 int k, ret = 0;
171
172 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
173 ret = clk_register(main_clks[k]);
174
175 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
176
177 if (!ret)
178 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
179
180 if (!ret)
181 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
182
183 return ret;
184}
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
new file mode 100644
index 000000000000..b055b55d6f27
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -0,0 +1,2136 @@
1/*
2 * SH7264 Pinmux
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <cpu/sh7264.h>
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 /* Port A */
21 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
22 /* Port B */
23 PB22_DATA, PB21_DATA, PB20_DATA,
24 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
25 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
26 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
27 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
28 PB3_DATA, PB2_DATA, PB1_DATA,
29 /* Port C */
30 PC10_DATA, PC9_DATA, PC8_DATA,
31 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
32 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
33 /* Port D */
34 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
35 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
36 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
37 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
38 /* Port E */
39 PE5_DATA, PE4_DATA,
40 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
41 /* Port F */
42 PF12_DATA,
43 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
44 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
45 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
46 /* Port G */
47 PG24_DATA,
48 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
49 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
50 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
51 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
52 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
53 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
54 /* Port H */
55 /* NOTE - Port H does not have a Data Register, but PH Data is
56 connected to PH Port Register */
57 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
58 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
59 /* Port I - not on device */
60 /* Port J */
61 PJ12_DATA,
62 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
63 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
64 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
65 /* Port K */
66 PK12_DATA,
67 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
68 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
69 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
70 PINMUX_DATA_END,
71
72 PINMUX_INPUT_BEGIN,
73 FORCE_IN,
74 /* Port A */
75 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
76 /* Port B */
77 PB22_IN, PB21_IN, PB20_IN,
78 PB19_IN, PB18_IN, PB17_IN, PB16_IN,
79 PB15_IN, PB14_IN, PB13_IN, PB12_IN,
80 PB11_IN, PB10_IN, PB9_IN, PB8_IN,
81 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
82 PB3_IN, PB2_IN, PB1_IN,
83 /* Port C */
84 PC10_IN, PC9_IN, PC8_IN,
85 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
86 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
87 /* Port D */
88 PD15_IN, PD14_IN, PD13_IN, PD12_IN,
89 PD11_IN, PD10_IN, PD9_IN, PD8_IN,
90 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
91 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
92 /* Port E */
93 PE5_IN, PE4_IN,
94 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
95 /* Port F */
96 PF12_IN,
97 PF11_IN, PF10_IN, PF9_IN, PF8_IN,
98 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
99 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
100 /* Port G */
101 PG24_IN,
102 PG23_IN, PG22_IN, PG21_IN, PG20_IN,
103 PG19_IN, PG18_IN, PG17_IN, PG16_IN,
104 PG15_IN, PG14_IN, PG13_IN, PG12_IN,
105 PG11_IN, PG10_IN, PG9_IN, PG8_IN,
106 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
107 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
108 /* Port H - Port H does not have a Data Register */
109 /* Port I - not on device */
110 /* Port J */
111 PJ12_IN,
112 PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
113 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
114 PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
115 /* Port K */
116 PK12_IN,
117 PK11_IN, PK10_IN, PK9_IN, PK8_IN,
118 PK7_IN, PK6_IN, PK5_IN, PK4_IN,
119 PK3_IN, PK2_IN, PK1_IN, PK0_IN,
120 PINMUX_INPUT_END,
121
122 PINMUX_OUTPUT_BEGIN,
123 FORCE_OUT,
124 /* Port A */
125 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
126 /* Port B */
127 PB22_OUT, PB21_OUT, PB20_OUT,
128 PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
129 PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
130 PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
131 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
132 PB3_OUT, PB2_OUT, PB1_OUT,
133 /* Port C */
134 PC10_OUT, PC9_OUT, PC8_OUT,
135 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
136 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
137 /* Port D */
138 PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
139 PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
140 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
141 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
142 /* Port E */
143 PE5_OUT, PE4_OUT,
144 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
145 /* Port F */
146 PF12_OUT,
147 PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
148 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
149 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
150 /* Port G */
151 PG24_OUT,
152 PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
153 PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
154 PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
155 PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
156 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
157 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
158 /* Port H - Port H does not have a Data Register */
159 /* Port I - not on device */
160 /* Port J */
161 PJ12_OUT,
162 PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
163 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
164 PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
165 /* Port K */
166 PK12_OUT,
167 PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT,
168 PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
169 PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
170 PINMUX_OUTPUT_END,
171
172 PINMUX_FUNCTION_BEGIN,
173 /* Port A */
174 PA3_IOR_IN, PA3_IOR_OUT,
175 PA2_IOR_IN, PA2_IOR_OUT,
176 PA1_IOR_IN, PA1_IOR_OUT,
177 PA0_IOR_IN, PA0_IOR_OUT,
178
179 /* Port B */
180 PB11_IOR_IN, PB11_IOR_OUT,
181 PB10_IOR_IN, PB10_IOR_OUT,
182 PB9_IOR_IN, PB9_IOR_OUT,
183 PB8_IOR_IN, PB8_IOR_OUT,
184
185 PB22MD_00, PB22MD_01, PB22MD_10,
186 PB21MD_0, PB21MD_1,
187 PB20MD_0, PB20MD_1,
188 PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11,
189 PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11,
190 PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11,
191 PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11,
192 PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11,
193 PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11,
194 PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11,
195 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
196 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
197 PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
198 PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
199 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
200 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
201 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
202 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
203 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
204 PB3MD_0, PB3MD_1,
205 PB2MD_0, PB2MD_1,
206 PB1MD_0, PB1MD_1,
207
208 /* Port C */
209 PC14_IOR_IN, PC14_IOR_OUT,
210 PC13_IOR_IN, PC13_IOR_OUT,
211 PC12_IOR_IN, PC12_IOR_OUT,
212 PC11_IOR_IN, PC11_IOR_OUT,
213 PC10_IOR_IN, PC10_IOR_OUT,
214 PC9_IOR_IN, PC9_IOR_OUT,
215 PC8_IOR_IN, PC8_IOR_OUT,
216 PC7_IOR_IN, PC7_IOR_OUT,
217 PC6_IOR_IN, PC6_IOR_OUT,
218 PC5_IOR_IN, PC5_IOR_OUT,
219 PC4_IOR_IN, PC4_IOR_OUT,
220 PC3_IOR_IN, PC3_IOR_OUT,
221 PC2_IOR_IN, PC2_IOR_OUT,
222 PC1_IOR_IN, PC1_IOR_OUT,
223 PC0_IOR_IN, PC0_IOR_OUT,
224
225 PC10MD_0, PC10MD_1,
226 PC9MD_0, PC9MD_1,
227 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11,
228 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11,
229 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11,
230 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11,
231 PC4MD_0, PC4MD_1,
232 PC3MD_0, PC3MD_1,
233 PC2MD_0, PC2MD_1,
234 PC1MD_0, PC1MD_1,
235 PC0MD_0, PC0MD_1,
236
237 /* Port D */
238 PD15_IOR_IN, PD15_IOR_OUT,
239 PD14_IOR_IN, PD14_IOR_OUT,
240 PD13_IOR_IN, PD13_IOR_OUT,
241 PD12_IOR_IN, PD12_IOR_OUT,
242 PD11_IOR_IN, PD11_IOR_OUT,
243 PD10_IOR_IN, PD10_IOR_OUT,
244 PD9_IOR_IN, PD9_IOR_OUT,
245 PD8_IOR_IN, PD8_IOR_OUT,
246 PD7_IOR_IN, PD7_IOR_OUT,
247 PD6_IOR_IN, PD6_IOR_OUT,
248 PD5_IOR_IN, PD5_IOR_OUT,
249 PD4_IOR_IN, PD4_IOR_OUT,
250 PD3_IOR_IN, PD3_IOR_OUT,
251 PD2_IOR_IN, PD2_IOR_OUT,
252 PD1_IOR_IN, PD1_IOR_OUT,
253 PD0_IOR_IN, PD0_IOR_OUT,
254
255 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
256 PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
257 PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
258 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
259 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
260 PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
261 PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
262 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
263 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
264 PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
265 PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
266 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
267 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
268 PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
269 PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
270 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
271
272 /* Port E */
273 PE5_IOR_IN, PE5_IOR_OUT,
274 PE4_IOR_IN, PE4_IOR_OUT,
275 PE3_IOR_IN, PE3_IOR_OUT,
276 PE2_IOR_IN, PE2_IOR_OUT,
277 PE1_IOR_IN, PE1_IOR_OUT,
278 PE0_IOR_IN, PE0_IOR_OUT,
279
280 PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
281 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
282 PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11,
283 PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11,
284 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
285 PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
286 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
287
288 /* Port F */
289 PF12_IOR_IN, PF12_IOR_OUT,
290 PF11_IOR_IN, PF11_IOR_OUT,
291 PF10_IOR_IN, PF10_IOR_OUT,
292 PF9_IOR_IN, PF9_IOR_OUT,
293 PF8_IOR_IN, PF8_IOR_OUT,
294 PF7_IOR_IN, PF7_IOR_OUT,
295 PF6_IOR_IN, PF6_IOR_OUT,
296 PF5_IOR_IN, PF5_IOR_OUT,
297 PF4_IOR_IN, PF4_IOR_OUT,
298 PF3_IOR_IN, PF3_IOR_OUT,
299 PF2_IOR_IN, PF2_IOR_OUT,
300 PF1_IOR_IN, PF1_IOR_OUT,
301 PF0_IOR_IN, PF0_IOR_OUT,
302
303 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
304 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
305 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
306 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
307 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
308 PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
309 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
310 PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
311 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11,
312 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
313 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
314 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
315 PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
316 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
317 PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
318 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
319 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
320 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
321 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
322 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
323 PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
324 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
325 PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
326 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
327 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
328
329 /* Port G */
330 PG24_IOR_IN, PG24_IOR_OUT,
331 PG23_IOR_IN, PG23_IOR_OUT,
332 PG22_IOR_IN, PG22_IOR_OUT,
333 PG21_IOR_IN, PG21_IOR_OUT,
334 PG20_IOR_IN, PG20_IOR_OUT,
335 PG19_IOR_IN, PG19_IOR_OUT,
336 PG18_IOR_IN, PG18_IOR_OUT,
337 PG17_IOR_IN, PG17_IOR_OUT,
338 PG16_IOR_IN, PG16_IOR_OUT,
339 PG15_IOR_IN, PG15_IOR_OUT,
340 PG14_IOR_IN, PG14_IOR_OUT,
341 PG13_IOR_IN, PG13_IOR_OUT,
342 PG12_IOR_IN, PG12_IOR_OUT,
343 PG11_IOR_IN, PG11_IOR_OUT,
344 PG10_IOR_IN, PG10_IOR_OUT,
345 PG9_IOR_IN, PG9_IOR_OUT,
346 PG8_IOR_IN, PG8_IOR_OUT,
347 PG7_IOR_IN, PG7_IOR_OUT,
348 PG6_IOR_IN, PG6_IOR_OUT,
349 PG5_IOR_IN, PG5_IOR_OUT,
350 PG4_IOR_IN, PG4_IOR_OUT,
351 PG3_IOR_IN, PG3_IOR_OUT,
352 PG2_IOR_IN, PG2_IOR_OUT,
353 PG1_IOR_IN, PG1_IOR_OUT,
354 PG0_IOR_IN, PG0_IOR_OUT,
355
356 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
357 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11,
358 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11,
359 PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11,
360 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
361 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
362 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
363 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
364 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
365 PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
366 PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
367 PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111,
368 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
369 PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111,
370 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
371 PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111,
372 PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011,
373 PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111,
374 PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011,
375 PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111,
376 PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011,
377 PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111,
378 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
379 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
380 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
381 PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
382 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
383 PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
384 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
385 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
386 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11,
387 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11,
388 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11,
389 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11,
390 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11,
391 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11,
392 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11,
393 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
394 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
395
396 /* Port H */
397 PH7MD_0, PH7MD_1,
398 PH6MD_0, PH6MD_1,
399 PH5MD_0, PH5MD_1,
400 PH4MD_0, PH4MD_1,
401 PH3MD_0, PH3MD_1,
402 PH2MD_0, PH2MD_1,
403 PH1MD_0, PH1MD_1,
404 PH0MD_0, PH0MD_1,
405
406 /* Port I - not on device */
407
408 /* Port J */
409 PJ11_IOR_IN, PJ11_IOR_OUT,
410 PJ10_IOR_IN, PJ10_IOR_OUT,
411 PJ9_IOR_IN, PJ9_IOR_OUT,
412 PJ8_IOR_IN, PJ8_IOR_OUT,
413 PJ7_IOR_IN, PJ7_IOR_OUT,
414 PJ6_IOR_IN, PJ6_IOR_OUT,
415 PJ5_IOR_IN, PJ5_IOR_OUT,
416 PJ4_IOR_IN, PJ4_IOR_OUT,
417 PJ3_IOR_IN, PJ3_IOR_OUT,
418 PJ2_IOR_IN, PJ2_IOR_OUT,
419 PJ1_IOR_IN, PJ1_IOR_OUT,
420 PJ0_IOR_IN, PJ0_IOR_OUT,
421
422 PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11,
423 PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11,
424 PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11,
425 PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11,
426 PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11,
427 PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11,
428 PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11,
429 PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11,
430 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11,
431 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
432 PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
433 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
434 PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
435 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
436 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
437
438 /* Port K */
439 PK11_IOR_IN, PK11_IOR_OUT,
440 PK10_IOR_IN, PK10_IOR_OUT,
441 PK9_IOR_IN, PK9_IOR_OUT,
442 PK8_IOR_IN, PK8_IOR_OUT,
443 PK7_IOR_IN, PK7_IOR_OUT,
444 PK6_IOR_IN, PK6_IOR_OUT,
445 PK5_IOR_IN, PK5_IOR_OUT,
446 PK4_IOR_IN, PK4_IOR_OUT,
447 PK3_IOR_IN, PK3_IOR_OUT,
448 PK2_IOR_IN, PK2_IOR_OUT,
449 PK1_IOR_IN, PK1_IOR_OUT,
450 PK0_IOR_IN, PK0_IOR_OUT,
451
452 PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11,
453 PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11,
454 PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11,
455 PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11,
456 PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11,
457 PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11,
458 PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11,
459 PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11,
460 PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11,
461 PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11,
462 PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11,
463 PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11,
464 PINMUX_FUNCTION_END,
465
466 PINMUX_MARK_BEGIN,
467 /* Port A */
468
469 /* Port B */
470
471 /* Port C */
472
473 /* Port D */
474
475 /* Port E */
476
477 /* Port F */
478
479 /* Port G */
480
481 /* Port H */
482 PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
483 PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
484
485 /* Port I - not on device */
486
487 /* Port J */
488
489 /* Port K */
490
491 IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK,
492 IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
493 IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
494
495 PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
496 PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
497
498 SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
499 SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
500 CRX0_MARK, CRX1_MARK,
501 CTX0_MARK, CTX1_MARK,
502
503 PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
504 PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
505 PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
506 PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
507 IERXD_MARK, IETXD_MARK,
508 CRX0CRX1_MARK,
509 WDTOVF_MARK,
510
511 CRX0X1_MARK,
512
513 /* DMAC */
514 TEND0_MARK, DACK0_MARK, DREQ0_MARK,
515 TEND1_MARK, DACK1_MARK, DREQ1_MARK,
516
517 /* ADC */
518 ADTRG_MARK,
519
520 /* BSC */
521 A25_MARK, A24_MARK,
522 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
523 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
524 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
525 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
526 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
527 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
528 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
529 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
530 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
531 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
532 BS_MARK,
533 CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
534 CS6CE1B_MARK, CS5CE1A_MARK,
535 CE2A_MARK, CE2B_MARK,
536 RD_MARK, RDWR_MARK,
537 ICIOWRAH_MARK,
538 ICIORD_MARK,
539 WE1DQMUWE_MARK,
540 WE0DQML_MARK,
541 RAS_MARK, CAS_MARK, CKE_MARK,
542 WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
543
544 /* TMU */
545 TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
546 TIOC1A_MARK, TIOC1B_MARK,
547 TIOC2A_MARK, TIOC2B_MARK,
548 TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
549 TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
550 TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
551
552 /* SCIF */
553 SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK,
554 RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK,
555 TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK,
556 RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK,
557 TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK,
558 RTS1_MARK, RTS3_MARK,
559 CTS1_MARK, CTS3_MARK,
560
561 /* RSPI */
562 RSPCK0_MARK, RSPCK1_MARK,
563 MOSI0_MARK, MOSI1_MARK,
564 MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK,
565 SSL00_MARK, SSL10_MARK,
566
567 /* IIC3 */
568 SCL0_MARK, SCL1_MARK, SCL2_MARK,
569 SDA0_MARK, SDA1_MARK, SDA2_MARK,
570
571 /* SSI */
572 SSISCK0_MARK,
573 SSIWS0_MARK,
574 SSITXD0_MARK,
575 SSIRXD0_MARK,
576 SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK,
577 SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK,
578 SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK,
579 AUDIO_CLK_MARK,
580
581 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
582 SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
583
584 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
585 SPDIF_IN_MARK, SPDIF_OUT_MARK,
586
587 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
588 FCE_MARK,
589 FRB_MARK,
590
591 /* VDC3 */
592 DV_CLK_MARK,
593 DV_VSYNC_MARK, DV_HSYNC_MARK,
594 DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
595 DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
596 LCD_CLK_MARK, LCD_EXTCLK_MARK,
597 LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
598 LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
599 LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
600 LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
601 LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
602 LCD_M_DISP_MARK,
603 PINMUX_MARK_END,
604};
605
606static pinmux_enum_t pinmux_data[] = {
607
608 /* Port A */
609 PINMUX_DATA(PA3_DATA, PA3_IN),
610 PINMUX_DATA(PA2_DATA, PA2_IN),
611 PINMUX_DATA(PA1_DATA, PA1_IN),
612 PINMUX_DATA(PA0_DATA, PA0_IN),
613
614 /* Port B */
615 PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT),
616 PINMUX_DATA(A22_MARK, PB22MD_01),
617 PINMUX_DATA(CS4_MARK, PB22MD_10),
618
619 PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT),
620 PINMUX_DATA(A21_MARK, PB21MD_1),
621 PINMUX_DATA(A20_MARK, PB20MD_1),
622 PINMUX_DATA(A19_MARK, PB19MD_01),
623 PINMUX_DATA(A18_MARK, PB18MD_01),
624 PINMUX_DATA(A17_MARK, PB17MD_01),
625 PINMUX_DATA(A16_MARK, PB16MD_01),
626 PINMUX_DATA(A15_MARK, PB15MD_01),
627 PINMUX_DATA(A14_MARK, PB14MD_01),
628 PINMUX_DATA(A13_MARK, PB13MD_01),
629 PINMUX_DATA(A12_MARK, PB12MD_01),
630 PINMUX_DATA(A11_MARK, PB11MD_01),
631 PINMUX_DATA(A10_MARK, PB10MD_01),
632 PINMUX_DATA(A9_MARK, PB9MD_01),
633 PINMUX_DATA(A8_MARK, PB8MD_01),
634 PINMUX_DATA(A7_MARK, PB7MD_01),
635 PINMUX_DATA(A6_MARK, PB6MD_01),
636 PINMUX_DATA(A5_MARK, PB5MD_01),
637 PINMUX_DATA(A4_MARK, PB4MD_01),
638 PINMUX_DATA(A3_MARK, PB3MD_1),
639 PINMUX_DATA(A2_MARK, PB2MD_1),
640 PINMUX_DATA(A1_MARK, PB1MD_1),
641
642 /* Port C */
643 PINMUX_DATA(PC10_DATA, PC10MD_0),
644 PINMUX_DATA(TIOC2B_MARK, PC1MD_1),
645 PINMUX_DATA(PC9_DATA, PC9MD_0),
646 PINMUX_DATA(TIOC2A_MARK, PC9MD_1),
647 PINMUX_DATA(PC8_DATA, PC8MD_00),
648 PINMUX_DATA(CS3_MARK, PC8MD_01),
649 PINMUX_DATA(TIOC4D_MARK, PC8MD_10),
650 PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11),
651 PINMUX_DATA(PC7_DATA, PC7MD_00),
652 PINMUX_DATA(CKE_MARK, PC7MD_01),
653 PINMUX_DATA(TIOC4C_MARK, PC7MD_10),
654 PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11),
655 PINMUX_DATA(PC6_DATA, PC6MD_00),
656 PINMUX_DATA(CAS_MARK, PC6MD_01),
657 PINMUX_DATA(TIOC4B_MARK, PC6MD_10),
658 PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11),
659 PINMUX_DATA(PC5_DATA, PC5MD_00),
660 PINMUX_DATA(RAS_MARK, PC5MD_01),
661 PINMUX_DATA(TIOC4A_MARK, PC5MD_10),
662 PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11),
663 PINMUX_DATA(PC4_DATA, PC4MD_0),
664 PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1),
665 PINMUX_DATA(PC3_DATA, PC3MD_0),
666 PINMUX_DATA(WE0DQML_MARK, PC3MD_1),
667 PINMUX_DATA(PC2_DATA, PC2MD_0),
668 PINMUX_DATA(RDWR_MARK, PC2MD_1),
669 PINMUX_DATA(PC1_DATA, PC1MD_0),
670 PINMUX_DATA(RD_MARK, PC1MD_1),
671 PINMUX_DATA(PC0_DATA, PC0MD_0),
672 PINMUX_DATA(CS0_MARK, PC0MD_1),
673
674 /* Port D */
675 PINMUX_DATA(D15_MARK, PD15MD_01),
676 PINMUX_DATA(D14_MARK, PD14MD_01),
677 PINMUX_DATA(D13_MARK, PD13MD_01),
678 PINMUX_DATA(D12_MARK, PD12MD_01),
679 PINMUX_DATA(D11_MARK, PD11MD_01),
680 PINMUX_DATA(D10_MARK, PD10MD_01),
681 PINMUX_DATA(D9_MARK, PD9MD_01),
682 PINMUX_DATA(D8_MARK, PD8MD_01),
683 PINMUX_DATA(D7_MARK, PD7MD_01),
684 PINMUX_DATA(D6_MARK, PD6MD_01),
685 PINMUX_DATA(D5_MARK, PD5MD_01),
686 PINMUX_DATA(D4_MARK, PD4MD_01),
687 PINMUX_DATA(D3_MARK, PD3MD_01),
688 PINMUX_DATA(D2_MARK, PD2MD_01),
689 PINMUX_DATA(D1_MARK, PD1MD_01),
690 PINMUX_DATA(D0_MARK, PD0MD_01),
691
692 /* Port E */
693 PINMUX_DATA(PE5_DATA, PE5MD_00),
694 PINMUX_DATA(SDA2_MARK, PE5MD_01),
695 PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
696
697 PINMUX_DATA(PE4_DATA, PE4MD_00),
698 PINMUX_DATA(SCL2_MARK, PE4MD_01),
699 PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
700
701 PINMUX_DATA(PE3_DATA, PE3MD_00),
702 PINMUX_DATA(SDA1_MARK, PE3MD_01),
703 PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11),
704
705 PINMUX_DATA(PE2_DATA, PE2MD_00),
706 PINMUX_DATA(SCL1_MARK, PE2MD_01),
707 PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11),
708
709 PINMUX_DATA(PE1_DATA, PE1MD_000),
710 PINMUX_DATA(SDA0_MARK, PE1MD_001),
711 PINMUX_DATA(IOIS16_MARK, PE1MD_010),
712 PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011),
713 PINMUX_DATA(TCLKA_MARK, PE1MD_100),
714 PINMUX_DATA(ADTRG_MARK, PE1MD_101),
715
716 PINMUX_DATA(PE0_DATA, PE0MD_00),
717 PINMUX_DATA(SCL0_MARK, PE0MD_01),
718 PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10),
719 PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11),
720
721 /* Port F */
722 PINMUX_DATA(PF12_DATA, PF12MD_000),
723 PINMUX_DATA(BS_MARK, PF12MD_001),
724 PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011),
725 PINMUX_DATA(TIOC3D_MARK, PF12MD_100),
726 PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101),
727
728 PINMUX_DATA(PF11_DATA, PF11MD_000),
729 PINMUX_DATA(A25_MARK, PF11MD_001),
730 PINMUX_DATA(SSIDATA3_MARK, PF11MD_010),
731 PINMUX_DATA(MOSI0_MARK, PF11MD_011),
732 PINMUX_DATA(TIOC3C_MARK, PF11MD_100),
733 PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101),
734
735 PINMUX_DATA(PF10_DATA, PF10MD_000),
736 PINMUX_DATA(A24_MARK, PF10MD_001),
737 PINMUX_DATA(SSIWS3_MARK, PF10MD_010),
738 PINMUX_DATA(SSL00_MARK, PF10MD_011),
739 PINMUX_DATA(TIOC3B_MARK, PF10MD_100),
740 PINMUX_DATA(FCE_MARK, PF10MD_101),
741
742 PINMUX_DATA(PF9_DATA, PF9MD_000),
743 PINMUX_DATA(A23_MARK, PF9MD_001),
744 PINMUX_DATA(SSISCK3_MARK, PF9MD_010),
745 PINMUX_DATA(RSPCK0_MARK, PF9MD_011),
746 PINMUX_DATA(TIOC3A_MARK, PF9MD_100),
747 PINMUX_DATA(FRB_MARK, PF9MD_101),
748
749 PINMUX_DATA(PF8_DATA, PF8MD_00),
750 PINMUX_DATA(CE2B_MARK, PF8MD_01),
751 PINMUX_DATA(SSIDATA3_MARK, PF8MD_10),
752 PINMUX_DATA(DV_CLK_MARK, PF8MD_11),
753
754 PINMUX_DATA(PF7_DATA, PF7MD_000),
755 PINMUX_DATA(CE2A_MARK, PF7MD_001),
756 PINMUX_DATA(SSIWS3_MARK, PF7MD_010),
757 PINMUX_DATA(DV_DATA7_MARK, PF7MD_011),
758 PINMUX_DATA(TCLKD_MARK, PF7MD_100),
759
760 PINMUX_DATA(PF6_DATA, PF6MD_000),
761 PINMUX_DATA(CS6CE1B_MARK, PF6MD_001),
762 PINMUX_DATA(SSISCK3_MARK, PF6MD_010),
763 PINMUX_DATA(DV_DATA6_MARK, PF6MD_011),
764 PINMUX_DATA(TCLKB_MARK, PF6MD_100),
765
766 PINMUX_DATA(PF5_DATA, PF5MD_000),
767 PINMUX_DATA(CS5CE1A_MARK, PF5MD_001),
768 PINMUX_DATA(SSIDATA2_MARK, PF5MD_010),
769 PINMUX_DATA(DV_DATA5_MARK, PF5MD_011),
770 PINMUX_DATA(TCLKC_MARK, PF5MD_100),
771
772 PINMUX_DATA(PF4_DATA, PF4MD_000),
773 PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001),
774 PINMUX_DATA(SSIWS2_MARK, PF4MD_010),
775 PINMUX_DATA(DV_DATA4_MARK, PF4MD_011),
776 PINMUX_DATA(TXD3_MARK, PF4MD_100),
777
778 PINMUX_DATA(PF3_DATA, PF3MD_000),
779 PINMUX_DATA(ICIORD_MARK, PF3MD_001),
780 PINMUX_DATA(SSISCK2_MARK, PF3MD_010),
781 PINMUX_DATA(DV_DATA3_MARK, PF3MD_011),
782 PINMUX_DATA(RXD3_MARK, PF3MD_100),
783
784 PINMUX_DATA(PF2_DATA, PF2MD_000),
785 PINMUX_DATA(BACK_MARK, PF2MD_001),
786 PINMUX_DATA(SSIDATA1_MARK, PF2MD_010),
787 PINMUX_DATA(DV_DATA2_MARK, PF2MD_011),
788 PINMUX_DATA(TXD2_MARK, PF2MD_100),
789 PINMUX_DATA(DACK0_MARK, PF2MD_101),
790
791 PINMUX_DATA(PF1_DATA, PF1MD_000),
792 PINMUX_DATA(BREQ_MARK, PF1MD_001),
793 PINMUX_DATA(SSIWS1_MARK, PF1MD_010),
794 PINMUX_DATA(DV_DATA1_MARK, PF1MD_011),
795 PINMUX_DATA(RXD2_MARK, PF1MD_100),
796 PINMUX_DATA(DREQ0_MARK, PF1MD_101),
797
798 PINMUX_DATA(PF0_DATA, PF0MD_000),
799 PINMUX_DATA(WAIT_MARK, PF0MD_001),
800 PINMUX_DATA(SSISCK1_MARK, PF0MD_010),
801 PINMUX_DATA(DV_DATA0_MARK, PF0MD_011),
802 PINMUX_DATA(SCK2_MARK, PF0MD_100),
803 PINMUX_DATA(TEND0_MARK, PF0MD_101),
804
805 /* Port G */
806 PINMUX_DATA(PG24_DATA, PG24MD_00),
807 PINMUX_DATA(MOSI0_MARK, PG24MD_01),
808 PINMUX_DATA(TIOC0D_MARK, PG24MD_10),
809
810 PINMUX_DATA(PG23_DATA, PG23MD_00),
811 PINMUX_DATA(MOSI1_MARK, PG23MD_01),
812 PINMUX_DATA(TIOC0C_MARK, PG23MD_10),
813
814 PINMUX_DATA(PG22_DATA, PG22MD_00),
815 PINMUX_DATA(SSL10_MARK, PG22MD_01),
816 PINMUX_DATA(TIOC0B_MARK, PG22MD_10),
817
818 PINMUX_DATA(PG21_DATA, PG21MD_00),
819 PINMUX_DATA(RSPCK1_MARK, PG21MD_01),
820 PINMUX_DATA(TIOC0A_MARK, PG21MD_10),
821
822 PINMUX_DATA(PG20_DATA, PG20MD_000),
823 PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001),
824 PINMUX_DATA(MISO1_MARK, PG20MD_011),
825 PINMUX_DATA(TXD7_MARK, PG20MD_100),
826
827 PINMUX_DATA(PG19_DATA, PG19MD_000),
828 PINMUX_DATA(LCD_CLK_MARK, PG19MD_001),
829 PINMUX_DATA(TIOC2B_MARK, PG19MD_010),
830 PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011),
831 PINMUX_DATA(RXD7_MARK, PG19MD_100),
832
833 PINMUX_DATA(PG18_DATA, PG18MD_000),
834 PINMUX_DATA(LCD_DE_MARK, PG18MD_001),
835 PINMUX_DATA(TIOC2A_MARK, PG18MD_010),
836 PINMUX_DATA(SSL10_MARK, PG18MD_011),
837 PINMUX_DATA(TXD6_MARK, PG18MD_100),
838
839 PINMUX_DATA(PG17_DATA, PG17MD_000),
840 PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001),
841 PINMUX_DATA(TIOC1B_MARK, PG17MD_010),
842 PINMUX_DATA(RSPCK1_MARK, PG17MD_011),
843 PINMUX_DATA(RXD6_MARK, PG17MD_100),
844
845 PINMUX_DATA(PG16_DATA, PG16MD_000),
846 PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001),
847 PINMUX_DATA(TIOC1A_MARK, PG16MD_010),
848 PINMUX_DATA(TXD3_MARK, PG16MD_011),
849 PINMUX_DATA(CTS1_MARK, PG16MD_100),
850
851 PINMUX_DATA(PG15_DATA, PG15MD_000),
852 PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001),
853 PINMUX_DATA(TIOC0D_MARK, PG15MD_010),
854 PINMUX_DATA(RXD3_MARK, PG15MD_011),
855 PINMUX_DATA(RTS1_MARK, PG15MD_100),
856
857 PINMUX_DATA(PG14_DATA, PG14MD_000),
858 PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001),
859 PINMUX_DATA(TIOC0C_MARK, PG14MD_010),
860 PINMUX_DATA(SCK1_MARK, PG14MD_100),
861
862 PINMUX_DATA(PG13_DATA, PG13MD_000),
863 PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001),
864 PINMUX_DATA(TIOC0B_MARK, PG13MD_010),
865 PINMUX_DATA(TXD1_MARK, PG13MD_100),
866
867 PINMUX_DATA(PG12_DATA, PG12MD_000),
868 PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001),
869 PINMUX_DATA(TIOC0A_MARK, PG12MD_010),
870 PINMUX_DATA(RXD1_MARK, PG12MD_100),
871
872 PINMUX_DATA(PG11_DATA, PG11MD_000),
873 PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001),
874 PINMUX_DATA(SSITXD0_MARK, PG11MD_010),
875 PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011),
876 PINMUX_DATA(TXD5_MARK, PG11MD_100),
877 PINMUX_DATA(SIOFTXD_MARK, PG11MD_101),
878
879 PINMUX_DATA(PG10_DATA, PG10MD_000),
880 PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001),
881 PINMUX_DATA(SSIRXD0_MARK, PG10MD_010),
882 PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011),
883 PINMUX_DATA(RXD5_MARK, PG10MD_100),
884 PINMUX_DATA(SIOFRXD_MARK, PG10MD_101),
885
886 PINMUX_DATA(PG9_DATA, PG9MD_000),
887 PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001),
888 PINMUX_DATA(SSIWS0_MARK, PG9MD_010),
889 PINMUX_DATA(TXD4_MARK, PG9MD_100),
890 PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101),
891
892 PINMUX_DATA(PG8_DATA, PG8MD_000),
893 PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001),
894 PINMUX_DATA(SSISCK0_MARK, PG8MD_010),
895 PINMUX_DATA(RXD4_MARK, PG8MD_100),
896 PINMUX_DATA(SIOFSCK_MARK, PG8MD_101),
897
898 PINMUX_DATA(PG7_DATA, PG7MD_00),
899 PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01),
900 PINMUX_DATA(SD_CD_MARK, PG7MD_10),
901 PINMUX_DATA(PINT7_PG_MARK, PG7MD_11),
902
903 PINMUX_DATA(PG6_DATA, PG7MD_00),
904 PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01),
905 PINMUX_DATA(SD_WP_MARK, PG7MD_10),
906 PINMUX_DATA(PINT6_PG_MARK, PG7MD_11),
907
908 PINMUX_DATA(PG5_DATA, PG5MD_00),
909 PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01),
910 PINMUX_DATA(SD_D1_MARK, PG5MD_10),
911 PINMUX_DATA(PINT5_PG_MARK, PG5MD_11),
912
913 PINMUX_DATA(PG4_DATA, PG4MD_00),
914 PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01),
915 PINMUX_DATA(SD_D0_MARK, PG4MD_10),
916 PINMUX_DATA(PINT4_PG_MARK, PG4MD_11),
917
918 PINMUX_DATA(PG3_DATA, PG3MD_00),
919 PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01),
920 PINMUX_DATA(SD_CLK_MARK, PG3MD_10),
921 PINMUX_DATA(PINT3_PG_MARK, PG3MD_11),
922
923 PINMUX_DATA(PG2_DATA, PG2MD_00),
924 PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01),
925 PINMUX_DATA(SD_CMD_MARK, PG2MD_10),
926 PINMUX_DATA(PINT2_PG_MARK, PG2MD_11),
927
928 PINMUX_DATA(PG1_DATA, PG1MD_00),
929 PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01),
930 PINMUX_DATA(SD_D3_MARK, PG1MD_10),
931 PINMUX_DATA(PINT1_PG_MARK, PG1MD_11),
932
933 PINMUX_DATA(PG0_DATA, PG0MD_000),
934 PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001),
935 PINMUX_DATA(SD_D2_MARK, PG0MD_010),
936 PINMUX_DATA(PINT0_PG_MARK, PG0MD_011),
937 PINMUX_DATA(WDTOVF_MARK, PG0MD_100),
938
939 /* Port H */
940 PINMUX_DATA(PH7_DATA, PH7MD_0),
941 PINMUX_DATA(PHAN7_MARK, PH7MD_1),
942
943 PINMUX_DATA(PH6_DATA, PH6MD_0),
944 PINMUX_DATA(PHAN6_MARK, PH6MD_1),
945
946 PINMUX_DATA(PH5_DATA, PH5MD_0),
947 PINMUX_DATA(PHAN5_MARK, PH5MD_1),
948
949 PINMUX_DATA(PH4_DATA, PH4MD_0),
950 PINMUX_DATA(PHAN4_MARK, PH4MD_1),
951
952 PINMUX_DATA(PH3_DATA, PH3MD_0),
953 PINMUX_DATA(PHAN3_MARK, PH3MD_1),
954
955 PINMUX_DATA(PH2_DATA, PH2MD_0),
956 PINMUX_DATA(PHAN2_MARK, PH2MD_1),
957
958 PINMUX_DATA(PH1_DATA, PH1MD_0),
959 PINMUX_DATA(PHAN1_MARK, PH1MD_1),
960
961 PINMUX_DATA(PH0_DATA, PH0MD_0),
962 PINMUX_DATA(PHAN0_MARK, PH0MD_1),
963
964 /* Port I - not on device */
965
966 /* Port J */
967 PINMUX_DATA(PJ11_DATA, PJ11MD_00),
968 PINMUX_DATA(PWM2H_MARK, PJ11MD_01),
969 PINMUX_DATA(DACK1_MARK, PJ11MD_10),
970
971 PINMUX_DATA(PJ10_DATA, PJ10MD_00),
972 PINMUX_DATA(PWM2G_MARK, PJ10MD_01),
973 PINMUX_DATA(DREQ1_MARK, PJ10MD_10),
974
975 PINMUX_DATA(PJ9_DATA, PJ9MD_00),
976 PINMUX_DATA(PWM2F_MARK, PJ9MD_01),
977 PINMUX_DATA(TEND1_MARK, PJ9MD_10),
978
979 PINMUX_DATA(PJ8_DATA, PJ8MD_00),
980 PINMUX_DATA(PWM2E_MARK, PJ8MD_01),
981 PINMUX_DATA(RTS3_MARK, PJ8MD_10),
982
983 PINMUX_DATA(PJ7_DATA, PJ7MD_00),
984 PINMUX_DATA(TIOC1B_MARK, PJ7MD_01),
985 PINMUX_DATA(CTS3_MARK, PJ7MD_10),
986
987 PINMUX_DATA(PJ6_DATA, PJ6MD_00),
988 PINMUX_DATA(TIOC1A_MARK, PJ6MD_01),
989 PINMUX_DATA(SCK3_MARK, PJ6MD_10),
990
991 PINMUX_DATA(PJ5_DATA, PJ5MD_00),
992 PINMUX_DATA(IERXD_MARK, PJ5MD_01),
993 PINMUX_DATA(TXD3_MARK, PJ5MD_10),
994
995 PINMUX_DATA(PJ4_DATA, PJ4MD_00),
996 PINMUX_DATA(IETXD_MARK, PJ4MD_01),
997 PINMUX_DATA(RXD3_MARK, PJ4MD_10),
998
999 PINMUX_DATA(PJ3_DATA, PJ3MD_00),
1000 PINMUX_DATA(CRX1_MARK, PJ3MD_01),
1001 PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
1002 PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
1003
1004 PINMUX_DATA(PJ2_DATA, PJ2MD_000),
1005 PINMUX_DATA(CTX1_MARK, PJ2MD_001),
1006 PINMUX_DATA(CRX0CRX1_MARK, PJ2MD_010),
1007 PINMUX_DATA(CS2_MARK, PJ2MD_011),
1008 PINMUX_DATA(SCK0_MARK, PJ2MD_100),
1009 PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
1010
1011 PINMUX_DATA(PJ1_DATA, PJ1MD_000),
1012 PINMUX_DATA(CRX0_MARK, PJ1MD_001),
1013 PINMUX_DATA(IERXD_MARK, PJ1MD_010),
1014 PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011),
1015 PINMUX_DATA(RXD0_MARK, PJ1MD_100),
1016
1017 PINMUX_DATA(PJ0_DATA, PJ0MD_000),
1018 PINMUX_DATA(CTX0_MARK, PJ0MD_001),
1019 PINMUX_DATA(IERXD_MARK, PJ0MD_010),
1020 PINMUX_DATA(CS1_MARK, PJ0MD_011),
1021 PINMUX_DATA(TXD0_MARK, PJ0MD_100),
1022 PINMUX_DATA(A0_MARK, PJ0MD_101),
1023
1024 /* Port K */
1025 PINMUX_DATA(PK11_DATA, PK11MD_00),
1026 PINMUX_DATA(PWM2D_MARK, PK11MD_01),
1027 PINMUX_DATA(SSITXD0_MARK, PK11MD_10),
1028
1029 PINMUX_DATA(PK10_DATA, PK10MD_00),
1030 PINMUX_DATA(PWM2C_MARK, PK10MD_01),
1031 PINMUX_DATA(SSIRXD0_MARK, PK10MD_10),
1032
1033 PINMUX_DATA(PK9_DATA, PK9MD_00),
1034 PINMUX_DATA(PWM2B_MARK, PK9MD_01),
1035 PINMUX_DATA(SSIWS0_MARK, PK9MD_10),
1036
1037 PINMUX_DATA(PK8_DATA, PK8MD_00),
1038 PINMUX_DATA(PWM2A_MARK, PK8MD_01),
1039 PINMUX_DATA(SSISCK0_MARK, PK8MD_10),
1040
1041 PINMUX_DATA(PK7_DATA, PK7MD_00),
1042 PINMUX_DATA(PWM1H_MARK, PK7MD_01),
1043 PINMUX_DATA(SD_CD_MARK, PK7MD_10),
1044
1045 PINMUX_DATA(PK6_DATA, PK6MD_00),
1046 PINMUX_DATA(PWM1G_MARK, PK6MD_01),
1047 PINMUX_DATA(SD_WP_MARK, PK6MD_10),
1048
1049 PINMUX_DATA(PK5_DATA, PK5MD_00),
1050 PINMUX_DATA(PWM1F_MARK, PK5MD_01),
1051 PINMUX_DATA(SD_D1_MARK, PK5MD_10),
1052
1053 PINMUX_DATA(PK4_DATA, PK4MD_00),
1054 PINMUX_DATA(PWM1E_MARK, PK4MD_01),
1055 PINMUX_DATA(SD_D0_MARK, PK4MD_10),
1056
1057 PINMUX_DATA(PK3_DATA, PK3MD_00),
1058 PINMUX_DATA(PWM1D_MARK, PK3MD_01),
1059 PINMUX_DATA(SD_CLK_MARK, PK3MD_10),
1060
1061 PINMUX_DATA(PK2_DATA, PK2MD_00),
1062 PINMUX_DATA(PWM1C_MARK, PK2MD_01),
1063 PINMUX_DATA(SD_CMD_MARK, PK2MD_10),
1064
1065 PINMUX_DATA(PK1_DATA, PK1MD_00),
1066 PINMUX_DATA(PWM1B_MARK, PK1MD_01),
1067 PINMUX_DATA(SD_D3_MARK, PK1MD_10),
1068
1069 PINMUX_DATA(PK0_DATA, PK0MD_00),
1070 PINMUX_DATA(PWM1A_MARK, PK0MD_01),
1071 PINMUX_DATA(SD_D2_MARK, PK0MD_10),
1072};
1073
1074static struct pinmux_gpio pinmux_gpios[] = {
1075
1076 /* Port A */
1077 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
1078 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
1079 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
1080 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
1081
1082 /* Port B */
1083 PINMUX_GPIO(GPIO_PB22, PB22_DATA),
1084 PINMUX_GPIO(GPIO_PB21, PB21_DATA),
1085 PINMUX_GPIO(GPIO_PB20, PB20_DATA),
1086 PINMUX_GPIO(GPIO_PB19, PB19_DATA),
1087 PINMUX_GPIO(GPIO_PB18, PB18_DATA),
1088 PINMUX_GPIO(GPIO_PB17, PB17_DATA),
1089 PINMUX_GPIO(GPIO_PB16, PB16_DATA),
1090 PINMUX_GPIO(GPIO_PB15, PB15_DATA),
1091 PINMUX_GPIO(GPIO_PB14, PB14_DATA),
1092 PINMUX_GPIO(GPIO_PB13, PB13_DATA),
1093 PINMUX_GPIO(GPIO_PB12, PB12_DATA),
1094 PINMUX_GPIO(GPIO_PB11, PB11_DATA),
1095 PINMUX_GPIO(GPIO_PB10, PB10_DATA),
1096 PINMUX_GPIO(GPIO_PB9, PB9_DATA),
1097 PINMUX_GPIO(GPIO_PB8, PB8_DATA),
1098 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
1099 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
1100 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
1101 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
1102 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
1103 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
1104 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
1105
1106 /* Port C */
1107 PINMUX_GPIO(GPIO_PC10, PC10_DATA),
1108 PINMUX_GPIO(GPIO_PC9, PC9_DATA),
1109 PINMUX_GPIO(GPIO_PC8, PC8_DATA),
1110 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
1111 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
1112 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
1113 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
1114 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
1115 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
1116 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
1117 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
1118
1119 /* Port D */
1120 PINMUX_GPIO(GPIO_PD15, PD15_DATA),
1121 PINMUX_GPIO(GPIO_PD14, PD14_DATA),
1122 PINMUX_GPIO(GPIO_PD13, PD13_DATA),
1123 PINMUX_GPIO(GPIO_PD12, PD12_DATA),
1124 PINMUX_GPIO(GPIO_PD11, PD11_DATA),
1125 PINMUX_GPIO(GPIO_PD10, PD10_DATA),
1126 PINMUX_GPIO(GPIO_PD9, PD9_DATA),
1127 PINMUX_GPIO(GPIO_PD8, PD8_DATA),
1128 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
1129 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
1130 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
1131 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
1132 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
1133 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
1134 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
1135 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
1136
1137 /* Port E */
1138 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
1139 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
1140 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
1141 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
1142 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
1143 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
1144
1145 /* Port F */
1146 PINMUX_GPIO(GPIO_PF12, PF12_DATA),
1147 PINMUX_GPIO(GPIO_PF11, PF11_DATA),
1148 PINMUX_GPIO(GPIO_PF10, PF10_DATA),
1149 PINMUX_GPIO(GPIO_PF9, PF9_DATA),
1150 PINMUX_GPIO(GPIO_PF8, PF8_DATA),
1151 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
1152 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
1153 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
1154 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
1155 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
1156 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
1157 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
1158 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
1159
1160 /* Port G */
1161 PINMUX_GPIO(GPIO_PG24, PG24_DATA),
1162 PINMUX_GPIO(GPIO_PG23, PG23_DATA),
1163 PINMUX_GPIO(GPIO_PG22, PG22_DATA),
1164 PINMUX_GPIO(GPIO_PG21, PG21_DATA),
1165 PINMUX_GPIO(GPIO_PG20, PG20_DATA),
1166 PINMUX_GPIO(GPIO_PG19, PG19_DATA),
1167 PINMUX_GPIO(GPIO_PG18, PG18_DATA),
1168 PINMUX_GPIO(GPIO_PG17, PG17_DATA),
1169 PINMUX_GPIO(GPIO_PG16, PG16_DATA),
1170 PINMUX_GPIO(GPIO_PG15, PG15_DATA),
1171 PINMUX_GPIO(GPIO_PG14, PG14_DATA),
1172 PINMUX_GPIO(GPIO_PG13, PG13_DATA),
1173 PINMUX_GPIO(GPIO_PG12, PG12_DATA),
1174 PINMUX_GPIO(GPIO_PG11, PG11_DATA),
1175 PINMUX_GPIO(GPIO_PG10, PG10_DATA),
1176 PINMUX_GPIO(GPIO_PG9, PG9_DATA),
1177 PINMUX_GPIO(GPIO_PG8, PG8_DATA),
1178 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
1179 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
1180 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
1181 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
1182 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
1183 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
1184 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
1185 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
1186
1187 /* Port H - Port H does not have a Data Register */
1188
1189 /* Port I - not on device */
1190
1191 /* Port J */
1192 PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
1193 PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
1194 PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
1195 PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
1196 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
1197 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
1198 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
1199 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
1200 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
1201 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
1202 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
1203 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
1204
1205 /* Port K */
1206 PINMUX_GPIO(GPIO_PK11, PK11_DATA),
1207 PINMUX_GPIO(GPIO_PK10, PK10_DATA),
1208 PINMUX_GPIO(GPIO_PK9, PK9_DATA),
1209 PINMUX_GPIO(GPIO_PK8, PK8_DATA),
1210 PINMUX_GPIO(GPIO_PK7, PK7_DATA),
1211 PINMUX_GPIO(GPIO_PK6, PK6_DATA),
1212 PINMUX_GPIO(GPIO_PK5, PK5_DATA),
1213 PINMUX_GPIO(GPIO_PK4, PK4_DATA),
1214 PINMUX_GPIO(GPIO_PK3, PK3_DATA),
1215 PINMUX_GPIO(GPIO_PK2, PK2_DATA),
1216 PINMUX_GPIO(GPIO_PK1, PK1_DATA),
1217 PINMUX_GPIO(GPIO_PK0, PK0_DATA),
1218
1219 /* INTC */
1220 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
1221 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
1222 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
1223 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
1224 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
1225 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
1226 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
1227
1228 PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
1229 PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
1230 PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
1231 PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
1232 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
1233 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
1234 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
1235 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
1236 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
1237 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
1238 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
1239 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
1240
1241 /* WDT */
1242 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1243
1244 /* CAN */
1245 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
1246 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
1247 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
1248 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
1249 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK),
1250
1251 /* DMAC */
1252 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1253 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1254 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1255 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1256 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1257 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1258
1259 /* ADC */
1260 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
1261
1262 /* BSCh */
1263 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1264 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1265 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1266 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1267 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1268 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1269 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1270 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1271 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1272 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1273 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1274 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1275 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1276 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1277 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1278 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1279 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1280 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1281 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1282 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1283 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1284 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1285 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1286 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1287 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1288 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1289
1290 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1291 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1292 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1293 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1294 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1295 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1296 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1297 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1298 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1299 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1300 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1301 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1302 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1303 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1304 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1305 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1306
1307 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1308 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1309 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
1310 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
1311 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
1312 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1313 PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
1314 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
1315 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
1316 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
1317 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1318 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1319 PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
1320 PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
1321 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
1322 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
1323 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
1324 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
1325 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
1326 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1327 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
1328 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
1329 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1330
1331 /* TMU */
1332 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
1333 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
1334 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
1335 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
1336 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
1337 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
1338 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
1339 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
1340 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
1341 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
1342 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
1343 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
1344 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
1345 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
1346 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
1347 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
1348 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
1349 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
1350 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
1351 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
1352
1353 /* SCIF */
1354 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
1355 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
1356 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
1357 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
1358 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
1359 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
1360 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1361 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1362 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1363 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1364 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1365 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1366 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1367 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1368 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1369 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1370 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
1371 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
1372 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
1373 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
1374 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
1375 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
1377 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
1378
1379 /* RSPI */
1380 PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
1381 PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
1382 PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
1383 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
1384 PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
1385 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
1386 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
1387 PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
1388 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
1389
1390 /* IIC3 */
1391 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1392 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1393 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1394 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1395 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1396 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1397
1398 /* SSI */
1399 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
1400 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
1401 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
1402 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
1403 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
1404 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
1405 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
1406 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
1407 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
1408 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
1409 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
1410 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
1411 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
1412 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
1413
1414 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1415 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
1416 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
1417 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
1418 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
1419
1420 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1421 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
1422 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
1423
1424 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1425 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1426 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1427
1428 /* VDC3 */
1429 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1430 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1431 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1432
1433 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
1434 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
1435 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
1436 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
1437 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
1438 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
1439 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
1440 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
1441
1442 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
1443 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
1444 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
1445 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
1446 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
1447
1448 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
1449 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
1450 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
1451 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
1452 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
1453 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
1454 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
1455 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
1456 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
1457 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
1458 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
1459 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
1460 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
1461 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
1462 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
1463 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
1464
1465 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
1466};
1467
1468static struct pinmux_cfg_reg pinmux_config_regs[] = {
1469 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1470 0, 0, 0, 0, 0, 0, 0, 0,
1471 0, 0, 0, 0, 0, 0, 0, 0,
1472 0, 0, 0, 0, 0, 0, 0, 0,
1473 PA3_IN, PA3_OUT,
1474 PA2_IN, PA2_OUT,
1475 PA1_IN, PA1_OUT,
1476 PA0_IN, PA0_OUT }
1477 },
1478
1479 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
1480 0, 0, 0, 0, 0, 0, 0, 0,
1481 0, 0, 0, 0, 0, 0, 0, 0,
1482 PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
1483 0, 0, 0, 0, 0, 0, 0, 0,
1484 PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
1485 0, 0, 0, 0, 0, 0, 0, 0,
1486 0, PB20MD_1, 0, 0, 0, 0, 0, 0,
1487 0, 0, 0, 0, 0, 0, 0, 0 }
1488
1489 },
1490 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
1491 0, PB19MD_01, 0, 0, 0, 0, 0, 0,
1492 0, 0, 0, 0, 0, 0, 0, 0,
1493 0, PB18MD_01, 0, 0, 0, 0, 0, 0,
1494 0, 0, 0, 0, 0, 0, 0, 0,
1495 0, PB17MD_01, 0, 0, 0, 0, 0, 0,
1496 0, 0, 0, 0, 0, 0, 0, 0,
1497 0, PB16MD_01, 0, 0, 0, 0, 0, 0,
1498 0, 0, 0, 0, 0, 0, 0, 0 }
1499 },
1500 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
1501 0, PB15MD_01, 0, 0, 0, 0, 0, 0,
1502 0, 0, 0, 0, 0, 0, 0, 0,
1503 0, PB14MD_01, 0, 0, 0, 0, 0, 0,
1504 0, 0, 0, 0, 0, 0, 0, 0,
1505 0, PB13MD_01, 0, 0, 0, 0, 0, 0,
1506 0, 0, 0, 0, 0, 0, 0, 0,
1507 0, PB12MD_01, 0, 0, 0, 0, 0, 0,
1508 0, 0, 0, 0, 0, 0, 0, 0 }
1509 },
1510 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
1511 0, PB11MD_01, 0, 0, 0, 0, 0, 0,
1512 0, 0, 0, 0, 0, 0, 0, 0,
1513 0, PB10MD_01, 0, 0, 0, 0, 0, 0,
1514 0, 0, 0, 0, 0, 0, 0, 0,
1515 0, PB9MD_01, 0, 0, 0, 0, 0, 0,
1516 0, 0, 0, 0, 0, 0, 0, 0,
1517 0, PB8MD_01, 0, 0, 0, 0, 0, 0,
1518 0, 0, 0, 0, 0, 0, 0, 0 }
1519 },
1520 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
1521 0, PB7MD_01, 0, 0, 0, 0, 0, 0,
1522 0, 0, 0, 0, 0, 0, 0, 0,
1523 0, PB6MD_01, 0, 0, 0, 0, 0, 0,
1524 0, 0, 0, 0, 0, 0, 0, 0,
1525 0, PB5MD_01, 0, 0, 0, 0, 0, 0,
1526 0, 0, 0, 0, 0, 0, 0, 0,
1527 0, PB4MD_01, 0, 0, 0, 0, 0, 0,
1528 0, 0, 0, 0, 0, 0, 0, 0 }
1529 },
1530 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
1531 0, PB3MD_1, 0, 0, 0, 0, 0, 0,
1532 0, 0, 0, 0, 0, 0, 0, 0,
1533 0, PB2MD_1, 0, 0, 0, 0, 0, 0,
1534 0, 0, 0, 0, 0, 0, 0, 0,
1535 0, PB1MD_1, 0, 0, 0, 0, 0, 0,
1536 0, 0, 0, 0, 0, 0, 0, 0,
1537 0, 0, 0, 0, 0, 0, 0, 0,
1538 0, 0, 0, 0, 0, 0, 0, 0 }
1539 },
1540
1541 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
1542 0, 0, 0, 0, 0, 0, 0, 0,
1543 0, 0, 0, 0, 0, 0, 0, 0,
1544 0, 0,
1545 PB22_IN, PB22_OUT,
1546 PB21_IN, PB21_OUT,
1547 PB20_IN, PB20_OUT,
1548 PB19_IN, PB19_OUT,
1549 PB18_IN, PB18_OUT,
1550 PB17_IN, PB17_OUT,
1551 PB16_IN, PB16_OUT }
1552 },
1553
1554 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
1555 PB15_IN, PB15_OUT,
1556 PB14_IN, PB14_OUT,
1557 PB13_IN, PB13_OUT,
1558 PB12_IN, PB12_OUT,
1559 PB11_IN, PB11_OUT,
1560 PB10_IN, PB10_OUT,
1561 PB9_IN, PB9_OUT,
1562 PB8_IN, PB8_OUT,
1563 PB7_IN, PB7_OUT,
1564 PB6_IN, PB6_OUT,
1565 PB5_IN, PB5_OUT,
1566 PB4_IN, PB4_OUT,
1567 PB3_IN, PB3_OUT,
1568 PB2_IN, PB2_OUT,
1569 PB1_IN, PB1_OUT,
1570 0, 0 }
1571 },
1572
1573 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
1574 0, 0, 0, 0, 0, 0, 0, 0,
1575 0, 0, 0, 0, 0, 0, 0, 0,
1576 PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
1577 0, 0, 0, 0, 0, 0, 0, 0,
1578 PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
1579 0, 0, 0, 0, 0, 0, 0, 0,
1580 PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
1581 0, 0, 0, 0, 0, 0, 0, 0 }
1582 },
1583 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
1584 PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
1585 0, 0, 0, 0, 0, 0, 0, 0,
1586 PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
1587 0, 0, 0, 0, 0, 0, 0, 0,
1588 PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
1589 0, 0, 0, 0, 0, 0, 0, 0,
1590 PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
1591 0, 0, 0, 0, 0, 0, 0, 0 }
1592 },
1593 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
1594 PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0,
1596 PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
1597 0, 0, 0, 0, 0, 0, 0, 0,
1598 PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
1599 0, 0, 0, 0, 0, 0, 0, 0,
1600 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
1601 0, 0, 0, 0, 0, 0, 0, 0 }
1602 },
1603
1604 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
1605 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1606 PC10_IN, PC10_OUT,
1607 PC9_IN, PC9_OUT,
1608 PC8_IN, PC8_OUT,
1609 PC7_IN, PC7_OUT,
1610 PC6_IN, PC6_OUT,
1611 PC5_IN, PC5_OUT,
1612 PC4_IN, PC4_OUT,
1613 PC3_IN, PC3_OUT,
1614 PC2_IN, PC2_OUT,
1615 PC1_IN, PC1_OUT,
1616 PC0_IN, PC0_OUT
1617 }
1618 },
1619
1620 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
1621 0, PD15MD_01, 0, 0, 0, 0, 0, 0,
1622 0, 0, 0, 0, 0, 0, 0, 0,
1623 0, PD14MD_01, 0, 0, 0, 0, 0, 0,
1624 0, 0, 0, 0, 0, 0, 0, 0,
1625 0, PD13MD_01, 0, 0, 0, 0, 0, 0,
1626 0, 0, 0, 0, 0, 0, 0, 0,
1627 0, PD12MD_01, 0, 0, 0, 0, 0, 0,
1628 0, 0, 0, 0, 0, 0, 0, 0 }
1629 },
1630 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
1631 0, PD11MD_01, 0, 0, 0, 0, 0, 0,
1632 0, 0, 0, 0, 0, 0, 0, 0,
1633 0, PD10MD_01, 0, 0, 0, 0, 0, 0,
1634 0, 0, 0, 0, 0, 0, 0, 0,
1635 0, PD9MD_01, 0, 0, 0, 0, 0, 0,
1636 0, 0, 0, 0, 0, 0, 0, 0,
1637 0, PD8MD_01, 0, 0, 0, 0, 0, 0,
1638 0, 0, 0, 0, 0, 0, 0, 0 }
1639 },
1640 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
1641 0, PD7MD_01, 0, 0, 0, 0, 0, 0,
1642 0, 0, 0, 0, 0, 0, 0, 0,
1643 0, PD6MD_01, 0, 0, 0, 0, 0, 0,
1644 0, 0, 0, 0, 0, 0, 0, 0,
1645 0, PD5MD_01, 0, 0, 0, 0, 0, 0,
1646 0, 0, 0, 0, 0, 0, 0, 0,
1647 0, PD4MD_01, 0, 0, 0, 0, 0, 0,
1648 0, 0, 0, 0, 0, 0, 0, 0 }
1649 },
1650 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
1651 0, PD3MD_01, 0, 0, 0, 0, 0, 0,
1652 0, 0, 0, 0, 0, 0, 0, 0,
1653 0, PD2MD_01, 0, 0, 0, 0, 0, 0,
1654 0, 0, 0, 0, 0, 0, 0, 0,
1655 0, PD1MD_01, 0, 0, 0, 0, 0, 0,
1656 0, 0, 0, 0, 0, 0, 0, 0,
1657 0, PD0MD_01, 0, 0, 0, 0, 0, 0,
1658 0, 0, 0, 0, 0, 0, 0, 0 }
1659 },
1660
1661 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
1662 PD15_IN, PD15_OUT,
1663 PD14_IN, PD14_OUT,
1664 PD13_IN, PD13_OUT,
1665 PD12_IN, PD12_OUT,
1666 PD11_IN, PD11_OUT,
1667 PD10_IN, PD10_OUT,
1668 PD9_IN, PD9_OUT,
1669 PD8_IN, PD8_OUT,
1670 PD7_IN, PD7_OUT,
1671 PD6_IN, PD6_OUT,
1672 PD5_IN, PD5_OUT,
1673 PD4_IN, PD4_OUT,
1674 PD3_IN, PD3_OUT,
1675 PD2_IN, PD2_OUT,
1676 PD1_IN, PD1_OUT,
1677 PD0_IN, PD0_OUT }
1678 },
1679
1680 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
1681 0, 0, 0, 0, 0, 0, 0, 0,
1682 0, 0, 0, 0, 0, 0, 0, 0,
1683 0, 0, 0, 0, 0, 0, 0, 0,
1684 0, 0, 0, 0, 0, 0, 0, 0,
1685 PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
1686 0, 0, 0, 0, 0, 0, 0, 0,
1687 PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
1688 0, 0, 0, 0, 0, 0, 0, 0 }
1689 },
1690
1691 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
1692 PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
1693 0, 0, 0, 0, 0, 0, 0, 0,
1694 PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
1695 0, 0, 0, 0, 0, 0, 0, 0,
1696 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
1697 PE1MD_100, PE1MD_101, 0, 0,
1698 0, 0, 0, 0, 0, 0, 0, 0,
1699 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
1700 0, 0, 0, 0, 0, 0, 0, 0 }
1701 },
1702
1703 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
1704 0, 0, 0, 0, 0, 0, 0, 0,
1705 0, 0, 0, 0, 0, 0, 0, 0,
1706 0, 0, 0, 0,
1707 PE5_IN, PE5_OUT,
1708 PE4_IN, PE4_OUT,
1709 PE3_IN, PE3_OUT,
1710 PE2_IN, PE2_OUT,
1711 PE1_IN, PE1_OUT,
1712 PE0_IN, PE0_OUT }
1713 },
1714
1715 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
1716 PF12MD_000, PF12MD_001, 0, PF12MD_011,
1717 PF12MD_100, PF12MD_101, 0, 0,
1718 0, 0, 0, 0, 0, 0, 0, 0 }
1719 },
1720
1721 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
1722 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
1723 PF11MD_100, PF11MD_101, 0, 0,
1724 0, 0, 0, 0, 0, 0, 0, 0,
1725 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
1726 PF10MD_100, PF10MD_101, 0, 0,
1727 0, 0, 0, 0, 0, 0, 0, 0,
1728 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
1729 PF9MD_100, PF9MD_101, 0, 0,
1730 0, 0, 0, 0, 0, 0, 0, 0,
1731 PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
1732 0, 0, 0, 0, 0, 0, 0, 0 }
1733 },
1734
1735 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
1736 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
1737 PF7MD_100, 0, 0, 0,
1738 0, 0, 0, 0, 0, 0, 0, 0,
1739 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
1740 PF6MD_100, 0, 0, 0,
1741 0, 0, 0, 0, 0, 0, 0, 0,
1742 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
1743 PF5MD_100, 0, 0, 0,
1744 0, 0, 0, 0, 0, 0, 0, 0,
1745 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
1746 PF4MD_100, 0, 0, 0,
1747 0, 0, 0, 0, 0, 0, 0, 0 }
1748 },
1749
1750 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
1751 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
1752 PF3MD_100, 0, 0, 0,
1753 0, 0, 0, 0, 0, 0, 0, 0,
1754 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
1755 PF2MD_100, PF2MD_101, 0, 0,
1756 0, 0, 0, 0, 0, 0, 0, 0,
1757 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
1758 PF1MD_100, PF1MD_101, 0, 0,
1759 0, 0, 0, 0, 0, 0, 0, 0
1760 }
1761 },
1762
1763 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
1764 0, 0, 0, 0, 0, 0,
1765 PF12_IN, PF12_OUT,
1766 PF11_IN, PF11_OUT,
1767 PF10_IN, PF10_OUT,
1768 PF9_IN, PF9_OUT,
1769 PF8_IN, PF8_OUT,
1770 PF7_IN, PF7_OUT,
1771 PF6_IN, PF6_OUT,
1772 PF5_IN, PF5_OUT,
1773 PF4_IN, PF4_OUT,
1774 PF3_IN, PF3_OUT,
1775 PF2_IN, PF2_OUT,
1776 PF1_IN, PF1_OUT,
1777 PF0_IN, PF0_OUT }
1778 },
1779
1780 { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) {
1781 0, 0, 0, 0, 0, 0, 0, 0,
1782 0, 0, 0, 0, 0, 0, 0, 0,
1783 0, 0, 0, 0, 0, 0, 0, 0,
1784 0, 0, 0, 0, 0, 0, 0, 0,
1785 0, 0, 0, 0, 0, 0, 0, 0,
1786 0, 0, 0, 0, 0, 0, 0, 0,
1787 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
1788 PG0MD_100, 0, 0, 0,
1789 0, 0, 0, 0, 0, 0, 0, 0 }
1790 },
1791
1792 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
1793 0, 0, 0, 0, 0, 0, 0, 0,
1794 0, 0, 0, 0, 0, 0, 0, 0,
1795 0, 0, 0, 0, 0, 0, 0, 0,
1796 0, 0, 0, 0, 0, 0, 0, 0,
1797 0, 0, 0, 0, 0, 0, 0, 0,
1798 0, 0, 0, 0, 0, 0, 0, 0,
1799 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
1800 0, 0, 0, 0, 0, 0, 0, 0 }
1801 },
1802
1803 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
1804 PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
1805 0, 0, 0, 0, 0, 0, 0, 0,
1806 PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
1807 0, 0, 0, 0, 0, 0, 0, 0,
1808 PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0,
1809 0, 0, 0, 0, 0, 0, 0, 0,
1810 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
1811 PG20MD_100, 0, 0, 0,
1812 0, 0, 0, 0, 0, 0, 0, 0 }
1813 },
1814
1815 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
1816 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
1817 PG19MD_100, 0, 0, 0,
1818 0, 0, 0, 0, 0, 0, 0, 0,
1819 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
1820 PG18MD_100, 0, 0, 0,
1821 0, 0, 0, 0, 0, 0, 0, 0,
1822 PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
1823 PG17MD_100, 0, 0, 0,
1824 0, 0, 0, 0, 0, 0, 0, 0,
1825 PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
1826 PG16MD_100, 0, 0, 0,
1827 0, 0, 0, 0, 0, 0, 0, 0 }
1828 },
1829
1830 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
1831 PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
1832 PG15MD_100, 0, 0, 0,
1833 0, 0, 0, 0, 0, 0, 0, 0,
1834 PG14MD_000, PG14MD_001, PG14MD_010, 0,
1835 PG14MD_100, 0, 0, 0,
1836 0, 0, 0, 0, 0, 0, 0, 0,
1837 PG13MD_000, PG13MD_001, PG13MD_010, 0,
1838 PG13MD_100, 0, 0, 0,
1839 0, 0, 0, 0, 0, 0, 0, 0,
1840 PG12MD_000, PG12MD_001, PG12MD_010, 0,
1841 PG12MD_100, 0, 0, 0,
1842 0, 0, 0, 0, 0, 0, 0, 0 }
1843 },
1844 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
1845 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
1846 PG11MD_100, PG11MD_101, 0, 0,
1847 0, 0, 0, 0, 0, 0, 0, 0,
1848 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
1849 PG10MD_100, PG10MD_101, 0, 0,
1850 0, 0, 0, 0, 0, 0, 0, 0,
1851 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
1852 PG9MD_100, PG9MD_101, 0, 0,
1853 0, 0, 0, 0, 0, 0, 0, 0,
1854 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
1855 PG8MD_100, PG8MD_101, 0, 0,
1856 0, 0, 0, 0, 0, 0, 0, 0 }
1857 },
1858
1859 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
1860 PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
1861 0, 0, 0, 0, 0, 0, 0, 0,
1862 PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
1863 0, 0, 0, 0, 0, 0, 0, 0,
1864 PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
1865 0, 0, 0, 0, 0, 0, 0, 0,
1866 PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
1867 0, 0, 0, 0, 0, 0, 0, 0 }
1868 },
1869 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
1870 PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
1871 0, 0, 0, 0, 0, 0, 0, 0,
1872 PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
1873 0, 0, 0, 0, 0, 0, 0, 0,
1874 PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
1875 0, 0, 0, 0, 0, 0, 0, 0,
1876 0, 0, 0, 0, 0, 0, 0, 0,
1877 0, 0, 0, 0, 0, 0, 0, 0 }
1878 },
1879 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
1880 0, 0, 0, 0, 0, 0, 0, 0,
1881 0, 0, 0, 0, 0, 0,
1882 PG24_IN, PG24_OUT,
1883 PG23_IN, PG23_OUT,
1884 PG22_IN, PG22_OUT,
1885 PG21_IN, PG21_OUT,
1886 PG20_IN, PG20_OUT,
1887 PG19_IN, PG19_OUT,
1888 PG18_IN, PG18_OUT,
1889 PG17_IN, PG17_OUT,
1890 PG16_IN, PG16_OUT }
1891 },
1892
1893 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
1894 PG15_IN, PG15_OUT,
1895 PG14_IN, PG14_OUT,
1896 PG13_IN, PG13_OUT,
1897 PG12_IN, PG12_OUT,
1898 PG11_IN, PG11_OUT,
1899 PG10_IN, PG10_OUT,
1900 PG9_IN, PG9_OUT,
1901 PG8_IN, PG8_OUT,
1902 PG7_IN, PG7_OUT,
1903 PG6_IN, PG6_OUT,
1904 PG5_IN, PG5_OUT,
1905 PG4_IN, PG4_OUT,
1906 PG3_IN, PG3_OUT,
1907 PG2_IN, PG2_OUT,
1908 PG1_IN, PG1_OUT,
1909 PG0_IN, PG0_OUT
1910 }
1911 },
1912
1913 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
1914 PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
1915 0, 0, 0, 0, 0, 0, 0, 0,
1916 PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
1917 0, 0, 0, 0, 0, 0, 0, 0,
1918 PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
1919 0, 0, 0, 0, 0, 0, 0, 0,
1920 PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
1921 0, 0, 0, 0, 0, 0, 0, 0 }
1922 },
1923
1924 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
1925 PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
1926 0, 0, 0, 0, 0, 0, 0, 0,
1927 PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
1928 0, 0, 0, 0, 0, 0, 0, 0,
1929 PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
1930 0, 0, 0, 0, 0, 0, 0, 0,
1931 PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
1932 0, 0, 0, 0, 0, 0, 0, 0 }
1933 },
1934
1935 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
1936 PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
1937 0, 0, 0, 0, 0, 0, 0, 0,
1938 PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
1939 0, 0, 0, 0, 0, 0, 0, 0,
1940 PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
1941 0, 0, 0, 0, 0, 0, 0, 0,
1942 PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
1943 0, 0, 0, 0, 0, 0, 0, 0 }
1944 },
1945 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
1946 PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
1947 0, 0, 0, 0, 0, 0, 0, 0,
1948 PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
1949 0, 0, 0, 0, 0, 0, 0, 0,
1950 PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
1951 0, 0, 0, 0, 0, 0, 0, 0,
1952 PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
1953 0, 0, 0, 0, 0, 0, 0, 0 }
1954 },
1955 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
1956 PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
1957 0, 0, 0, 0, 0, 0, 0, 0,
1958 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
1959 PJ2MD_100, PJ2MD_101, 0, 0,
1960 0, 0, 0, 0, 0, 0, 0, 0,
1961 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
1962 PJ1MD_100, 0, 0, 0,
1963 0, 0, 0, 0, 0, 0, 0, 0,
1964 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
1965 PJ0MD_100, PJ0MD_101, 0, 0,
1966 0, 0, 0, 0, 0, 0, 0, 0, }
1967 },
1968 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
1969 0, 0, 0, 0, 0, 0, 0, 0,
1970 PJ11_IN, PJ11_OUT,
1971 PJ10_IN, PJ10_OUT,
1972 PJ9_IN, PJ9_OUT,
1973 PJ8_IN, PJ8_OUT,
1974 PJ7_IN, PJ7_OUT,
1975 PJ6_IN, PJ6_OUT,
1976 PJ5_IN, PJ5_OUT,
1977 PJ4_IN, PJ4_OUT,
1978 PJ3_IN, PJ3_OUT,
1979 PJ2_IN, PJ2_OUT,
1980 PJ1_IN, PJ1_OUT,
1981 PJ0_IN, PJ0_OUT }
1982 },
1983
1984 { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) {
1985 PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
1986 0, 0, 0, 0, 0, 0, 0, 0,
1987 PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
1988 0, 0, 0, 0, 0, 0, 0, 0,
1989 PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
1990 0, 0, 0, 0, 0, 0, 0, 0,
1991 PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
1992 0, 0, 0, 0, 0, 0, 0, 0 }
1993 },
1994
1995 { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) {
1996 PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
1997 0, 0, 0, 0, 0, 0, 0, 0,
1998 PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0,
1999 0, 0, 0, 0, 0, 0, 0, 0,
2000 PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
2001 0, 0, 0, 0, 0, 0, 0, 0,
2002 PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
2003 0, 0, 0, 0, 0, 0, 0, 0 }
2004 },
2005 { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) {
2006 PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
2007 0, 0, 0, 0, 0, 0, 0, 0,
2008 PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
2009 0, 0, 0, 0, 0, 0, 0, 0,
2010 PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
2011 0, 0, 0, 0, 0, 0, 0, 0,
2012 PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
2013 0, 0, 0, 0, 0, 0, 0, 0 }
2014 },
2015
2016 { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) {
2017 0, 0, 0, 0, 0, 0, 0, 0,
2018 PJ11_IN, PJ11_OUT,
2019 PJ10_IN, PJ10_OUT,
2020 PJ9_IN, PJ9_OUT,
2021 PJ8_IN, PJ8_OUT,
2022 PJ7_IN, PJ7_OUT,
2023 PJ6_IN, PJ6_OUT,
2024 PJ5_IN, PJ5_OUT,
2025 PJ4_IN, PJ4_OUT,
2026 PJ3_IN, PJ3_OUT,
2027 PJ2_IN, PJ2_OUT,
2028 PJ1_IN, PJ1_OUT,
2029 PJ0_IN, PJ0_OUT }
2030 },
2031 {}
2032};
2033
2034static struct pinmux_data_reg pinmux_data_regs[] = {
2035 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
2036 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
2037 0, 0, 0, 0, 0, 0, 0, PA2_DATA }
2038 },
2039
2040 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
2041 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2042 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
2043 },
2044
2045 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
2046 0, 0, 0, 0, 0, 0, 0, 0,
2047 0, PB22_DATA, PB21_DATA, PB20_DATA,
2048 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
2049 },
2050
2051 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
2052 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
2053 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
2054 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
2055 PB3_DATA, PB2_DATA, PB1_DATA, 0 }
2056 },
2057
2058 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
2059 0, 0, 0, 0,
2060 0, PC10_DATA, PC9_DATA, PC8_DATA,
2061 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
2062 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
2063 },
2064
2065 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
2066 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
2067 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
2068 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
2069 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
2070 },
2071
2072 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
2073 0, 0, 0, 0, 0, 0, 0, 0,
2074 0, 0, PE5_DATA, PE4_DATA,
2075 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
2076 },
2077
2078 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
2079 0, 0, 0, PF12_DATA,
2080 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
2081 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
2082 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
2083 },
2084
2085 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
2086 0, 0, 0, 0, 0, 0, 0, PG24_DATA,
2087 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
2088 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
2089 },
2090
2091 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
2092 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
2093 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
2094 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
2095 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
2096 },
2097 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
2098 0, 0, 0, PJ12_DATA,
2099 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
2100 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
2101 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
2102 },
2103 { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
2104 0, 0, 0, PK12_DATA,
2105 PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
2106 PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
2107 PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
2108 },
2109 { }
2110};
2111
2112static struct pinmux_info sh7264_pinmux_info = {
2113 .name = "sh7264_pfc",
2114 .reserved_id = PINMUX_RESERVED,
2115 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2116 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2117 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2118 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2119 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2120
2121 .first_gpio = GPIO_PA3,
2122 .last_gpio = GPIO_FN_LCD_M_DISP,
2123
2124 .gpios = pinmux_gpios,
2125 .cfg_regs = pinmux_config_regs,
2126 .data_regs = pinmux_data_regs,
2127
2128 .gpio_data = pinmux_data,
2129 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2130};
2131
2132static int __init plat_pinmux_setup(void)
2133{
2134 return register_pinmux(&sh7264_pinmux_info);
2135}
2136arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
new file mode 100644
index 000000000000..f25127c46eca
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -0,0 +1,2800 @@
1/*
2 * SH7269 Pinmux
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 * Copyright (C) 2012 Phil Edworthy
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15#include <cpu/sh7269.h>
16
17enum {
18 PINMUX_RESERVED = 0,
19
20 PINMUX_DATA_BEGIN,
21 /* Port A */
22 PA1_DATA, PA0_DATA,
23 /* Port B */
24 PB22_DATA, PB21_DATA, PB20_DATA,
25 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
26 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
27 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
28 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
29 PB3_DATA, PB2_DATA, PB1_DATA,
30 /* Port C */
31 PC8_DATA,
32 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
33 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
34 /* Port D */
35 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
36 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
37 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
38 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
39 /* Port E */
40 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
41 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
42 /* Port F */
43 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
44 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA,
45 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
46 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
47 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
48 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
49 /* Port G */
50 PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
51 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
52 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
53 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
54 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
55 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
56 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
57 /* Port H */
58 /* NOTE - Port H does not have a Data Register, but PH Data is
59 connected to PH Port Register */
60 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
61 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
62 /* Port I - not on device */
63 /* Port J */
64 PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
65 PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
66 PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
67 PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA,
68 PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
69 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
70 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
71 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
72 PINMUX_DATA_END,
73
74 PINMUX_INPUT_BEGIN,
75 FORCE_IN,
76 /* Port A */
77 PA1_IN, PA0_IN,
78 /* Port B */
79 PB22_IN, PB21_IN, PB20_IN,
80 PB19_IN, PB18_IN, PB17_IN, PB16_IN,
81 PB15_IN, PB14_IN, PB13_IN, PB12_IN,
82 PB11_IN, PB10_IN, PB9_IN, PB8_IN,
83 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
84 PB3_IN, PB2_IN, PB1_IN,
85 /* Port C */
86 PC8_IN,
87 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
88 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
89 /* Port D */
90 PD15_IN, PD14_IN, PD13_IN, PD12_IN,
91 PD11_IN, PD10_IN, PD9_IN, PD8_IN,
92 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
93 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
94 /* Port E */
95 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
96 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
97 /* Port F */
98 PF23_IN, PF22_IN, PF21_IN, PF20_IN,
99 PF19_IN, PF18_IN, PF17_IN, PF16_IN,
100 PF15_IN, PF14_IN, PF13_IN, PF12_IN,
101 PF11_IN, PF10_IN, PF9_IN, PF8_IN,
102 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
103 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
104 /* Port G */
105 PG27_IN, PG26_IN, PG25_IN, PG24_IN,
106 PG23_IN, PG22_IN, PG21_IN, PG20_IN,
107 PG19_IN, PG18_IN, PG17_IN, PG16_IN,
108 PG15_IN, PG14_IN, PG13_IN, PG12_IN,
109 PG11_IN, PG10_IN, PG9_IN, PG8_IN,
110 PG7_IN, PG6_IN, PG5_IN, PG4_IN,
111 PG3_IN, PG2_IN, PG1_IN, PG0_IN,
112 /* Port H - Port H does not have a Data Register */
113 /* Port I - not on device */
114 /* Port J */
115 PJ31_IN, PJ30_IN, PJ29_IN, PJ28_IN,
116 PJ27_IN, PJ26_IN, PJ25_IN, PJ24_IN,
117 PJ23_IN, PJ22_IN, PJ21_IN, PJ20_IN,
118 PJ19_IN, PJ18_IN, PJ17_IN, PJ16_IN,
119 PJ15_IN, PJ14_IN, PJ13_IN, PJ12_IN,
120 PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
121 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
122 PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
123 PINMUX_INPUT_END,
124
125 PINMUX_OUTPUT_BEGIN,
126 FORCE_OUT,
127 /* Port A */
128 PA1_OUT, PA0_OUT,
129 /* Port B */
130 PB22_OUT, PB21_OUT, PB20_OUT,
131 PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
132 PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
133 PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
134 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
135 PB3_OUT, PB2_OUT, PB1_OUT,
136 /* Port C */
137 PC8_OUT,
138 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
139 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
140 /* Port D */
141 PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
142 PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
143 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
144 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
145 /* Port E */
146 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
147 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
148 /* Port F */
149 PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT,
150 PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT,
151 PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT,
152 PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
153 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
154 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
155 /* Port G */
156 PG27_OUT, PG26_OUT, PG25_OUT, PG24_OUT,
157 PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
158 PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
159 PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
160 PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
161 PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
162 PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
163 /* Port H - Port H does not have a Data Register */
164 /* Port I - not on device */
165 /* Port J */
166 PJ31_OUT, PJ30_OUT, PJ29_OUT, PJ28_OUT,
167 PJ27_OUT, PJ26_OUT, PJ25_OUT, PJ24_OUT,
168 PJ23_OUT, PJ22_OUT, PJ21_OUT, PJ20_OUT,
169 PJ19_OUT, PJ18_OUT, PJ17_OUT, PJ16_OUT,
170 PJ15_OUT, PJ14_OUT, PJ13_OUT, PJ12_OUT,
171 PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
172 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
173 PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
174 PINMUX_OUTPUT_END,
175
176 PINMUX_FUNCTION_BEGIN,
177 /* Port A */
178 PA1_IOR_IN, PA1_IOR_OUT,
179 PA0_IOR_IN, PA0_IOR_OUT,
180
181 /* Port B */
182 PB22_IOR_IN, PB22_IOR_OUT,
183 PB21_IOR_IN, PB21_IOR_OUT,
184 PB20_IOR_IN, PB20_IOR_OUT,
185 PB19_IOR_IN, PB19_IOR_OUT,
186 PB18_IOR_IN, PB18_IOR_OUT,
187 PB17_IOR_IN, PB17_IOR_OUT,
188 PB16_IOR_IN, PB16_IOR_OUT,
189
190 PB15_IOR_IN, PB15_IOR_OUT,
191 PB14_IOR_IN, PB14_IOR_OUT,
192 PB13_IOR_IN, PB13_IOR_OUT,
193 PB12_IOR_IN, PB12_IOR_OUT,
194 PB11_IOR_IN, PB11_IOR_OUT,
195 PB10_IOR_IN, PB10_IOR_OUT,
196 PB9_IOR_IN, PB9_IOR_OUT,
197 PB8_IOR_IN, PB8_IOR_OUT,
198
199 PB7_IOR_IN, PB7_IOR_OUT,
200 PB6_IOR_IN, PB6_IOR_OUT,
201 PB5_IOR_IN, PB5_IOR_OUT,
202 PB4_IOR_IN, PB4_IOR_OUT,
203 PB3_IOR_IN, PB3_IOR_OUT,
204 PB2_IOR_IN, PB2_IOR_OUT,
205 PB1_IOR_IN, PB1_IOR_OUT,
206 PB0_IOR_IN, PB0_IOR_OUT,
207
208 PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
209 PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111,
210 PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11,
211 PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
212 PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
213 PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
214 PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
215 PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011,
216 PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111,
217 PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011,
218 PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111,
219 PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
220 PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
221 PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
222 PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
223 PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011,
224 PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111,
225 PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011,
226 PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111,
227 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
228
229 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
230 PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
231 PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
232 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
233
234 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
235 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
236 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
237 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
238
239 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
240 PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
241 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
242
243 /* Port C */
244 PC8_IOR_IN, PC8_IOR_OUT,
245 PC7_IOR_IN, PC7_IOR_OUT,
246 PC6_IOR_IN, PC6_IOR_OUT,
247 PC5_IOR_IN, PC5_IOR_OUT,
248 PC4_IOR_IN, PC4_IOR_OUT,
249 PC3_IOR_IN, PC3_IOR_OUT,
250 PC2_IOR_IN, PC2_IOR_OUT,
251 PC1_IOR_IN, PC1_IOR_OUT,
252 PC0_IOR_IN, PC0_IOR_OUT,
253
254 PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
255 PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
256 PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
257 PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
258 PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011,
259 PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111,
260 PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011,
261 PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111,
262 PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11,
263
264 PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11,
265 PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11,
266 PC1MD_0, PC1MD_1,
267 PC0MD_0, PC0MD_1,
268
269 /* Port D */
270 PD15_IOR_IN, PD15_IOR_OUT,
271 PD14_IOR_IN, PD14_IOR_OUT,
272 PD13_IOR_IN, PD13_IOR_OUT,
273 PD12_IOR_IN, PD12_IOR_OUT,
274 PD11_IOR_IN, PD11_IOR_OUT,
275 PD10_IOR_IN, PD10_IOR_OUT,
276 PD9_IOR_IN, PD9_IOR_OUT,
277 PD8_IOR_IN, PD8_IOR_OUT,
278 PD7_IOR_IN, PD7_IOR_OUT,
279 PD6_IOR_IN, PD6_IOR_OUT,
280 PD5_IOR_IN, PD5_IOR_OUT,
281 PD4_IOR_IN, PD4_IOR_OUT,
282 PD3_IOR_IN, PD3_IOR_OUT,
283 PD2_IOR_IN, PD2_IOR_OUT,
284 PD1_IOR_IN, PD1_IOR_OUT,
285 PD0_IOR_IN, PD0_IOR_OUT,
286
287 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
288 PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
289 PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
290 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
291
292 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
293 PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
294 PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
295 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
296
297 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
298 PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
299 PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
300 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
301
302 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
303 PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
304 PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
305 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
306
307 /* Port E */
308 PE7_IOR_IN, PE7_IOR_OUT,
309 PE6_IOR_IN, PE6_IOR_OUT,
310 PE5_IOR_IN, PE5_IOR_OUT,
311 PE4_IOR_IN, PE4_IOR_OUT,
312 PE3_IOR_IN, PE3_IOR_OUT,
313 PE2_IOR_IN, PE2_IOR_OUT,
314 PE1_IOR_IN, PE1_IOR_OUT,
315 PE0_IOR_IN, PE0_IOR_OUT,
316
317 PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11,
318 PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11,
319 PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
320 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
321
322 PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
323 PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
324 PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011,
325 PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111,
326 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
327 PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
328 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
329
330 /* Port F */
331 PF23_IOR_IN, PF23_IOR_OUT,
332 PF22_IOR_IN, PF22_IOR_OUT,
333 PF21_IOR_IN, PF21_IOR_OUT,
334 PF20_IOR_IN, PF20_IOR_OUT,
335 PF19_IOR_IN, PF19_IOR_OUT,
336 PF18_IOR_IN, PF18_IOR_OUT,
337 PF17_IOR_IN, PF17_IOR_OUT,
338 PF16_IOR_IN, PF16_IOR_OUT,
339 PF15_IOR_IN, PF15_IOR_OUT,
340 PF14_IOR_IN, PF14_IOR_OUT,
341 PF13_IOR_IN, PF13_IOR_OUT,
342 PF12_IOR_IN, PF12_IOR_OUT,
343 PF11_IOR_IN, PF11_IOR_OUT,
344 PF10_IOR_IN, PF10_IOR_OUT,
345 PF9_IOR_IN, PF9_IOR_OUT,
346 PF8_IOR_IN, PF8_IOR_OUT,
347 PF7_IOR_IN, PF7_IOR_OUT,
348 PF6_IOR_IN, PF6_IOR_OUT,
349 PF5_IOR_IN, PF5_IOR_OUT,
350 PF4_IOR_IN, PF4_IOR_OUT,
351 PF3_IOR_IN, PF3_IOR_OUT,
352 PF2_IOR_IN, PF2_IOR_OUT,
353 PF1_IOR_IN, PF1_IOR_OUT,
354 PF0_IOR_IN, PF0_IOR_OUT,
355
356 PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
357 PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
358 PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011,
359 PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111,
360 PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011,
361 PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111,
362 PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
363 PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
364
365 PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
366 PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
367 PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011,
368 PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111,
369 PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011,
370 PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111,
371 PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
372 PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
373
374 PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
375 PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
376 PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
377 PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111,
378 PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011,
379 PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111,
380 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
381 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
382
383 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
384 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
385 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
386 PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
387 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
388 PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
389 PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
390 PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
391
392 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
393 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
394 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
395 PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
396 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
397 PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
398 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
399 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
400
401 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
402 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
403 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
404 PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
405 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
406 PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
407 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
408 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
409
410 /* Port G */
411 PG27_IOR_IN, PG27_IOR_OUT,
412 PG26_IOR_IN, PG26_IOR_OUT,
413 PG25_IOR_IN, PG25_IOR_OUT,
414 PG24_IOR_IN, PG24_IOR_OUT,
415 PG23_IOR_IN, PG23_IOR_OUT,
416 PG22_IOR_IN, PG22_IOR_OUT,
417 PG21_IOR_IN, PG21_IOR_OUT,
418 PG20_IOR_IN, PG20_IOR_OUT,
419 PG19_IOR_IN, PG19_IOR_OUT,
420 PG18_IOR_IN, PG18_IOR_OUT,
421 PG17_IOR_IN, PG17_IOR_OUT,
422 PG16_IOR_IN, PG16_IOR_OUT,
423 PG15_IOR_IN, PG15_IOR_OUT,
424 PG14_IOR_IN, PG14_IOR_OUT,
425 PG13_IOR_IN, PG13_IOR_OUT,
426 PG12_IOR_IN, PG12_IOR_OUT,
427 PG11_IOR_IN, PG11_IOR_OUT,
428 PG10_IOR_IN, PG10_IOR_OUT,
429 PG9_IOR_IN, PG9_IOR_OUT,
430 PG8_IOR_IN, PG8_IOR_OUT,
431 PG7_IOR_IN, PG7_IOR_OUT,
432 PG6_IOR_IN, PG6_IOR_OUT,
433 PG5_IOR_IN, PG5_IOR_OUT,
434 PG4_IOR_IN, PG4_IOR_OUT,
435 PG3_IOR_IN, PG3_IOR_OUT,
436 PG2_IOR_IN, PG2_IOR_OUT,
437 PG1_IOR_IN, PG1_IOR_OUT,
438 PG0_IOR_IN, PG0_IOR_OUT,
439
440 PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11,
441 PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11,
442 PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11,
443 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
444
445 PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
446 PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
447 PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011,
448 PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111,
449 PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011,
450 PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111,
451 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
452 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
453
454 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
455 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
456 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
457 PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
458 PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11,
459 PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11,
460
461 PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11,
462 PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11,
463 PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11,
464 PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11,
465
466 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
467 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
468 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
469 PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
470 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
471 PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
472 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
473 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
474
475 PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
476 PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
477 PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011,
478 PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111,
479 PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011,
480 PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111,
481 PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
482 PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
483
484 PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
485 PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
486 PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011,
487 PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111,
488 PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011,
489 PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111,
490 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
491 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
492
493 /* Port H */
494 PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11,
495 PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11,
496 PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11,
497 PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11,
498
499 PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11,
500 PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11,
501 PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11,
502 PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11,
503
504 /* Port I - not on device */
505
506 /* Port J */
507 PJ31_IOR_IN, PJ31_IOR_OUT,
508 PJ30_IOR_IN, PJ30_IOR_OUT,
509 PJ29_IOR_IN, PJ29_IOR_OUT,
510 PJ28_IOR_IN, PJ28_IOR_OUT,
511 PJ27_IOR_IN, PJ27_IOR_OUT,
512 PJ26_IOR_IN, PJ26_IOR_OUT,
513 PJ25_IOR_IN, PJ25_IOR_OUT,
514 PJ24_IOR_IN, PJ24_IOR_OUT,
515 PJ23_IOR_IN, PJ23_IOR_OUT,
516 PJ22_IOR_IN, PJ22_IOR_OUT,
517 PJ21_IOR_IN, PJ21_IOR_OUT,
518 PJ20_IOR_IN, PJ20_IOR_OUT,
519 PJ19_IOR_IN, PJ19_IOR_OUT,
520 PJ18_IOR_IN, PJ18_IOR_OUT,
521 PJ17_IOR_IN, PJ17_IOR_OUT,
522 PJ16_IOR_IN, PJ16_IOR_OUT,
523 PJ15_IOR_IN, PJ15_IOR_OUT,
524 PJ14_IOR_IN, PJ14_IOR_OUT,
525 PJ13_IOR_IN, PJ13_IOR_OUT,
526 PJ12_IOR_IN, PJ12_IOR_OUT,
527 PJ11_IOR_IN, PJ11_IOR_OUT,
528 PJ10_IOR_IN, PJ10_IOR_OUT,
529 PJ9_IOR_IN, PJ9_IOR_OUT,
530 PJ8_IOR_IN, PJ8_IOR_OUT,
531 PJ7_IOR_IN, PJ7_IOR_OUT,
532 PJ6_IOR_IN, PJ6_IOR_OUT,
533 PJ5_IOR_IN, PJ5_IOR_OUT,
534 PJ4_IOR_IN, PJ4_IOR_OUT,
535 PJ3_IOR_IN, PJ3_IOR_OUT,
536 PJ2_IOR_IN, PJ2_IOR_OUT,
537 PJ1_IOR_IN, PJ1_IOR_OUT,
538 PJ0_IOR_IN, PJ0_IOR_OUT,
539
540 PJ31MD_0, PJ31MD_1,
541 PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011,
542 PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111,
543 PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011,
544 PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111,
545 PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
546 PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
547
548 PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
549 PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
550 PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011,
551 PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111,
552 PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011,
553 PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111,
554 PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
555 PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
556
557 PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
558 PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
559 PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011,
560 PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111,
561 PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011,
562 PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111,
563 PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
564 PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
565
566 PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
567 PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
568 PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011,
569 PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111,
570 PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011,
571 PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111,
572 PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
573 PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
574
575 PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
576 PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
577 PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011,
578 PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111,
579 PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011,
580 PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111,
581 PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
582 PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
583
584 PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
585 PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
586 PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011,
587 PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111,
588 PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011,
589 PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111,
590 PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
591 PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
592
593 PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
594 PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
595 PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011,
596 PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111,
597 PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011,
598 PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111,
599 PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
600 PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
601
602 PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
603 PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
604 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
605 PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
606 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
607 PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
608 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
609 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
610
611 PINMUX_FUNCTION_END,
612
613 PINMUX_MARK_BEGIN,
614 /* Port H */
615 PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
616 PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
617
618 /* IRQs */
619 IRQ7_PG_MARK, IRQ6_PG_MARK, IRQ5_PG_MARK, IRQ4_PG_MARK,
620 IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PG_MARK, IRQ0_PG_MARK,
621 IRQ7_PF_MARK, IRQ6_PF_MARK, IRQ5_PF_MARK, IRQ4_PF_MARK,
622 IRQ3_PJ_MARK, IRQ2_PJ_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
623 IRQ1_PC_MARK, IRQ0_PC_MARK,
624
625 PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
626 PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
627 PINT7_PH_MARK, PINT6_PH_MARK, PINT5_PH_MARK, PINT4_PH_MARK,
628 PINT3_PH_MARK, PINT2_PH_MARK, PINT1_PH_MARK, PINT0_PH_MARK,
629 PINT7_PJ_MARK, PINT6_PJ_MARK, PINT5_PJ_MARK, PINT4_PJ_MARK,
630 PINT3_PJ_MARK, PINT2_PJ_MARK, PINT1_PJ_MARK, PINT0_PJ_MARK,
631
632 /* SD */
633 SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
634 SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK, SD_CD_MARK,
635
636 /* MMC */
637 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
638 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
639 MMC_CLK_MARK, MMC_CMD_MARK, MMC_CD_MARK,
640
641 /* PWM */
642 PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
643 PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
644 PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
645 PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
646
647 /* IEBus */
648 IERXD_MARK, IETXD_MARK,
649
650 /* WDT */
651 WDTOVF_MARK,
652
653 /* DMAC */
654 TEND0_MARK, DACK0_MARK, DREQ0_MARK,
655 TEND1_MARK, DACK1_MARK, DREQ1_MARK,
656
657 /* ADC */
658 ADTRG_MARK,
659
660 /* BSC */
661 A25_MARK, A24_MARK,
662 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
663 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
664 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
665 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
666 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
667 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
668 D31_MARK, D30_MARK, D29_MARK, D28_MARK,
669 D27_MARK, D26_MARK, D25_MARK, D24_MARK,
670 D23_MARK, D22_MARK, D21_MARK, D20_MARK,
671 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
672 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
673 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
674 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
675 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
676 BS_MARK,
677 CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
678 CS5CE1A_MARK,
679 CE2A_MARK, CE2B_MARK,
680 RD_MARK, RDWR_MARK,
681 WE3ICIOWRAHDQMUU_MARK,
682 WE2ICIORDDQMUL_MARK,
683 WE1DQMUWE_MARK,
684 WE0DQML_MARK,
685 RAS_MARK, CAS_MARK, CKE_MARK,
686 WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
687
688 /* TMU */
689 TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
690 TIOC1A_MARK, TIOC1B_MARK,
691 TIOC2A_MARK, TIOC2B_MARK,
692 TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
693 TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
694 TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
695
696 /* SCIF */
697 SCK0_MARK, RXD0_MARK, TXD0_MARK,
698 SCK1_MARK, RXD1_MARK, TXD1_MARK, RTS1_MARK, CTS1_MARK,
699 SCK2_MARK, RXD2_MARK, TXD2_MARK,
700 SCK3_MARK, RXD3_MARK, TXD3_MARK,
701 SCK4_MARK, RXD4_MARK, TXD4_MARK,
702 SCK5_MARK, RXD5_MARK, TXD5_MARK, RTS5_MARK, CTS5_MARK,
703 SCK6_MARK, RXD6_MARK, TXD6_MARK,
704 SCK7_MARK, RXD7_MARK, TXD7_MARK, RTS7_MARK, CTS7_MARK,
705
706 /* RSPI */
707 MISO0_PB20_MARK, MOSI0_PB19_MARK, SSL00_PB18_MARK, RSPCK0_PB17_MARK,
708 MISO0_PJ19_MARK, MOSI0_PJ18_MARK, SSL00_PJ17_MARK, RSPCK0_PJ16_MARK,
709 MISO1_MARK, MOSI1_MARK, SSL10_MARK, RSPCK1_MARK,
710
711 /* IIC3 */
712 SCL0_MARK, SDA0_MARK,
713 SCL1_MARK, SDA1_MARK,
714 SCL2_MARK, SDA2_MARK,
715 SCL3_MARK, SDA3_MARK,
716
717 /* SSI */
718 SSISCK0_MARK, SSIWS0_MARK, SSITXD0_MARK, SSIRXD0_MARK,
719 SSISCK1_MARK, SSIWS1_MARK, SSIDATA1_MARK,
720 SSISCK2_MARK, SSIWS2_MARK, SSIDATA2_MARK,
721 SSISCK3_MARK, SSIWS3_MARK, SSIDATA3_MARK,
722 SSISCK4_MARK, SSIWS4_MARK, SSIDATA4_MARK,
723 SSISCK5_MARK, SSIWS5_MARK, SSIDATA5_MARK,
724 AUDIO_CLK_MARK,
725 AUDIO_XOUT_MARK,
726
727 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
728 SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
729
730 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
731 SPDIF_IN_MARK, SPDIF_OUT_MARK,
732 SPDIF_IN_PJ24_MARK, SPDIF_OUT_PJ25_MARK,
733
734 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
735 FCE_MARK,
736 FRB_MARK,
737
738 /* CAN */
739 CRX0_MARK, CTX0_MARK,
740 CRX1_MARK, CTX1_MARK,
741 CRX2_MARK, CTX2_MARK,
742 CRX0CRX1_MARK,
743 CRX0CRX1CRX2_MARK,
744 CTX0CTX1CTX2_MARK,
745 CRX1_PJ22_MARK, CTX1_PJ23_MARK,
746 CRX2_PJ20_MARK, CTX2_PJ21_MARK,
747 CRX0CRX1_PJ22_MARK,
748 CRX0CRX1CRX2_PJ20_MARK,
749
750 /* VDC */
751 DV_CLK_MARK,
752 DV_VSYNC_MARK, DV_HSYNC_MARK,
753 DV_DATA23_MARK, DV_DATA22_MARK, DV_DATA21_MARK, DV_DATA20_MARK,
754 DV_DATA19_MARK, DV_DATA18_MARK, DV_DATA17_MARK, DV_DATA16_MARK,
755 DV_DATA15_MARK, DV_DATA14_MARK, DV_DATA13_MARK, DV_DATA12_MARK,
756 DV_DATA11_MARK, DV_DATA10_MARK, DV_DATA9_MARK, DV_DATA8_MARK,
757 DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
758 DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
759 LCD_CLK_MARK, LCD_EXTCLK_MARK,
760 LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
761 LCD_DATA23_MARK, LCD_DATA22_MARK, LCD_DATA21_MARK, LCD_DATA20_MARK,
762 LCD_DATA19_MARK, LCD_DATA18_MARK, LCD_DATA17_MARK, LCD_DATA16_MARK,
763 LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
764 LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
765 LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
766 LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
767 LCD_TCON6_MARK, LCD_TCON5_MARK, LCD_TCON4_MARK,
768 LCD_TCON3_MARK, LCD_TCON2_MARK, LCD_TCON1_MARK, LCD_TCON0_MARK,
769 LCD_M_DISP_MARK,
770 PINMUX_MARK_END,
771};
772
773static pinmux_enum_t pinmux_data[] = {
774
775 /* Port A */
776 PINMUX_DATA(PA1_DATA, PA1_IN),
777 PINMUX_DATA(PA0_DATA, PA0_IN),
778
779 /* Port B */
780 PINMUX_DATA(PB22_DATA, PB22MD_000, PB22_IN, PB22_OUT),
781 PINMUX_DATA(A22_MARK, PB22MD_001),
782 PINMUX_DATA(CTX2_MARK, PB22MD_010),
783 PINMUX_DATA(IETXD_MARK, PB22MD_011),
784 PINMUX_DATA(CS4_MARK, PB22MD_100),
785
786 PINMUX_DATA(PB21_DATA, PB21MD_00, PB21_IN, PB21_OUT),
787 PINMUX_DATA(A21_MARK, PB21MD_01),
788 PINMUX_DATA(CRX2_MARK, PB21MD_10),
789 PINMUX_DATA(IERXD_MARK, PB21MD_11),
790
791 PINMUX_DATA(A20_MARK, PB20MD_001),
792 PINMUX_DATA(A19_MARK, PB19MD_001),
793 PINMUX_DATA(A18_MARK, PB18MD_001),
794 PINMUX_DATA(A17_MARK, PB17MD_001),
795 PINMUX_DATA(A16_MARK, PB16MD_001),
796 PINMUX_DATA(A15_MARK, PB15MD_001),
797 PINMUX_DATA(A14_MARK, PB14MD_001),
798 PINMUX_DATA(A13_MARK, PB13MD_001),
799 PINMUX_DATA(A12_MARK, PB12MD_01),
800 PINMUX_DATA(A11_MARK, PB11MD_01),
801 PINMUX_DATA(A10_MARK, PB10MD_01),
802 PINMUX_DATA(A9_MARK, PB9MD_01),
803 PINMUX_DATA(A8_MARK, PB8MD_01),
804 PINMUX_DATA(A7_MARK, PB7MD_01),
805 PINMUX_DATA(A6_MARK, PB6MD_01),
806 PINMUX_DATA(A5_MARK, PB5MD_01),
807 PINMUX_DATA(A4_MARK, PB4MD_01),
808 PINMUX_DATA(A3_MARK, PB3MD_01),
809 PINMUX_DATA(A2_MARK, PB2MD_01),
810 PINMUX_DATA(A1_MARK, PB1MD_01),
811
812 /* Port C */
813 PINMUX_DATA(PC8_DATA, PC8MD_000),
814 PINMUX_DATA(CS3_MARK, PC8MD_001),
815 PINMUX_DATA(TXD7_MARK, PC8MD_010),
816 PINMUX_DATA(CTX1_MARK, PC8MD_011),
817
818 PINMUX_DATA(PC7_DATA, PC7MD_000),
819 PINMUX_DATA(CKE_MARK, PC7MD_001),
820 PINMUX_DATA(RXD7_MARK, PC7MD_010),
821 PINMUX_DATA(CRX1_MARK, PC7MD_011),
822 PINMUX_DATA(CRX0CRX1_MARK, PC7MD_100),
823 PINMUX_DATA(IRQ1_PC_MARK, PC7MD_101),
824
825 PINMUX_DATA(PC6_DATA, PC6MD_000),
826 PINMUX_DATA(CAS_MARK, PC6MD_001),
827 PINMUX_DATA(SCK7_MARK, PC6MD_010),
828 PINMUX_DATA(CTX0_MARK, PC6MD_011),
829
830 PINMUX_DATA(PC5_DATA, PC5MD_000),
831 PINMUX_DATA(RAS_MARK, PC5MD_001),
832 PINMUX_DATA(CRX0_MARK, PC5MD_011),
833 PINMUX_DATA(CTX0CTX1CTX2_MARK, PC5MD_100),
834 PINMUX_DATA(IRQ0_PC_MARK, PC5MD_101),
835
836 PINMUX_DATA(PC4_DATA, PC4MD_00),
837 PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_01),
838 PINMUX_DATA(TXD6_MARK, PC4MD_10),
839
840 PINMUX_DATA(PC3_DATA, PC3MD_00),
841 PINMUX_DATA(WE0DQML_MARK, PC3MD_01),
842 PINMUX_DATA(RXD6_MARK, PC3MD_10),
843
844 PINMUX_DATA(PC2_DATA, PC2MD_00),
845 PINMUX_DATA(RDWR_MARK, PC2MD_01),
846 PINMUX_DATA(SCK5_MARK, PC2MD_10),
847
848 PINMUX_DATA(PC1_DATA, PC1MD_0),
849 PINMUX_DATA(RD_MARK, PC1MD_1),
850
851 PINMUX_DATA(PC0_DATA, PC0MD_0),
852 PINMUX_DATA(CS0_MARK, PC0MD_1),
853
854 /* Port D */
855 PINMUX_DATA(D15_MARK, PD15MD_01),
856 PINMUX_DATA(D14_MARK, PD14MD_01),
857
858 PINMUX_DATA(PD13_DATA, PD13MD_00),
859 PINMUX_DATA(D13_MARK, PD13MD_01),
860 PINMUX_DATA(PWM2F_MARK, PD13MD_10),
861
862 PINMUX_DATA(PD12_DATA, PD12MD_00),
863 PINMUX_DATA(D12_MARK, PD12MD_01),
864 PINMUX_DATA(PWM2E_MARK, PD12MD_10),
865
866 PINMUX_DATA(D11_MARK, PD11MD_01),
867 PINMUX_DATA(D10_MARK, PD10MD_01),
868 PINMUX_DATA(D9_MARK, PD9MD_01),
869 PINMUX_DATA(D8_MARK, PD8MD_01),
870 PINMUX_DATA(D7_MARK, PD7MD_01),
871 PINMUX_DATA(D6_MARK, PD6MD_01),
872 PINMUX_DATA(D5_MARK, PD5MD_01),
873 PINMUX_DATA(D4_MARK, PD4MD_01),
874 PINMUX_DATA(D3_MARK, PD3MD_01),
875 PINMUX_DATA(D2_MARK, PD2MD_01),
876 PINMUX_DATA(D1_MARK, PD1MD_01),
877 PINMUX_DATA(D0_MARK, PD0MD_01),
878
879 /* Port E */
880 PINMUX_DATA(PE7_DATA, PE7MD_00),
881 PINMUX_DATA(SDA3_MARK, PE7MD_01),
882 PINMUX_DATA(RXD7_MARK, PE7MD_10),
883
884 PINMUX_DATA(PE6_DATA, PE6MD_00),
885 PINMUX_DATA(SCL3_MARK, PE6MD_01),
886 PINMUX_DATA(RXD6_MARK, PE6MD_10),
887
888 PINMUX_DATA(PE5_DATA, PE5MD_00),
889 PINMUX_DATA(SDA2_MARK, PE5MD_01),
890 PINMUX_DATA(RXD5_MARK, PE5MD_10),
891 PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
892
893 PINMUX_DATA(PE4_DATA, PE4MD_00),
894 PINMUX_DATA(SCL2_MARK, PE4MD_01),
895 PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
896
897 PINMUX_DATA(PE3_DATA, PE3MD_000),
898 PINMUX_DATA(SDA1_MARK, PE3MD_001),
899 PINMUX_DATA(TCLKD_MARK, PE3MD_010),
900 PINMUX_DATA(ADTRG_MARK, PE3MD_011),
901 PINMUX_DATA(DV_HSYNC_MARK, PE3MD_100),
902
903 PINMUX_DATA(PE2_DATA, PE2MD_000),
904 PINMUX_DATA(SCL1_MARK, PE2MD_001),
905 PINMUX_DATA(TCLKD_MARK, PE2MD_010),
906 PINMUX_DATA(IOIS16_MARK, PE2MD_011),
907 PINMUX_DATA(DV_VSYNC_MARK, PE2MD_100),
908
909 PINMUX_DATA(PE1_DATA, PE1MD_000),
910 PINMUX_DATA(SDA0_MARK, PE1MD_001),
911 PINMUX_DATA(TCLKB_MARK, PE1MD_010),
912 PINMUX_DATA(AUDIO_CLK_MARK, PE1MD_010),
913 PINMUX_DATA(DV_CLK_MARK, PE1MD_100),
914
915 PINMUX_DATA(PE0_DATA, PE0MD_00),
916 PINMUX_DATA(SCL0_MARK, PE0MD_01),
917 PINMUX_DATA(TCLKA_MARK, PE0MD_10),
918 PINMUX_DATA(LCD_EXTCLK_MARK, PE0MD_11),
919
920 /* Port F */
921 PINMUX_DATA(PF23_DATA, PF23MD_000),
922 PINMUX_DATA(SD_D2_MARK, PF23MD_001),
923 PINMUX_DATA(TXD3_MARK, PF23MD_100),
924 PINMUX_DATA(MMC_D2_MARK, PF23MD_101),
925
926 PINMUX_DATA(PF22_DATA, PF22MD_000),
927 PINMUX_DATA(SD_D3_MARK, PF22MD_001),
928 PINMUX_DATA(RXD3_MARK, PF22MD_100),
929 PINMUX_DATA(MMC_D3_MARK, PF22MD_101),
930
931 PINMUX_DATA(PF21_DATA, PF21MD_000),
932 PINMUX_DATA(SD_CMD_MARK, PF21MD_001),
933 PINMUX_DATA(SCK3_MARK, PF21MD_100),
934 PINMUX_DATA(MMC_CMD_MARK, PF21MD_101),
935
936 PINMUX_DATA(PF20_DATA, PF20MD_000),
937 PINMUX_DATA(SD_CLK_MARK, PF20MD_001),
938 PINMUX_DATA(SSIDATA3_MARK, PF20MD_010),
939 PINMUX_DATA(MMC_CLK_MARK, PF20MD_101),
940
941 PINMUX_DATA(PF19_DATA, PF19MD_000),
942 PINMUX_DATA(SD_D0_MARK, PF19MD_001),
943 PINMUX_DATA(SSIWS3_MARK, PF19MD_010),
944 PINMUX_DATA(IRQ7_PF_MARK, PF19MD_100),
945 PINMUX_DATA(MMC_D0_MARK, PF19MD_101),
946
947 PINMUX_DATA(PF18_DATA, PF18MD_000),
948 PINMUX_DATA(SD_D1_MARK, PF18MD_001),
949 PINMUX_DATA(SSISCK3_MARK, PF18MD_010),
950 PINMUX_DATA(IRQ6_PF_MARK, PF18MD_100),
951 PINMUX_DATA(MMC_D1_MARK, PF18MD_101),
952
953 PINMUX_DATA(PF17_DATA, PF17MD_000),
954 PINMUX_DATA(SD_WP_MARK, PF17MD_001),
955 PINMUX_DATA(FRB_MARK, PF17MD_011),
956 PINMUX_DATA(IRQ5_PF_MARK, PF17MD_100),
957
958 PINMUX_DATA(PF16_DATA, PF16MD_000),
959 PINMUX_DATA(SD_CD_MARK, PF16MD_001),
960 PINMUX_DATA(FCE_MARK, PF16MD_011),
961 PINMUX_DATA(IRQ4_PF_MARK, PF16MD_100),
962 PINMUX_DATA(MMC_CD_MARK, PF16MD_101),
963
964 PINMUX_DATA(PF15_DATA, PF15MD_000),
965 PINMUX_DATA(A0_MARK, PF15MD_001),
966 PINMUX_DATA(SSIDATA2_MARK, PF15MD_010),
967 PINMUX_DATA(WDTOVF_MARK, PF15MD_011),
968 PINMUX_DATA(TXD2_MARK, PF15MD_100),
969
970 PINMUX_DATA(PF14_DATA, PF14MD_000),
971 PINMUX_DATA(A25_MARK, PF14MD_001),
972 PINMUX_DATA(SSIWS2_MARK, PF14MD_010),
973 PINMUX_DATA(RXD2_MARK, PF14MD_100),
974
975 PINMUX_DATA(PF13_DATA, PF13MD_000),
976 PINMUX_DATA(A24_MARK, PF13MD_001),
977 PINMUX_DATA(SSISCK2_MARK, PF13MD_010),
978 PINMUX_DATA(SCK2_MARK, PF13MD_100),
979
980 PINMUX_DATA(PF12_DATA, PF12MD_000),
981 PINMUX_DATA(SSIDATA1_MARK, PF12MD_010),
982 PINMUX_DATA(DV_DATA12_MARK, PF12MD_011),
983 PINMUX_DATA(TXD1_MARK, PF12MD_100),
984 PINMUX_DATA(MMC_D7_MARK, PF12MD_101),
985
986 PINMUX_DATA(PF11_DATA, PF11MD_000),
987 PINMUX_DATA(SSIWS1_MARK, PF11MD_010),
988 PINMUX_DATA(DV_DATA2_MARK, PF11MD_011),
989 PINMUX_DATA(RXD1_MARK, PF11MD_100),
990 PINMUX_DATA(MMC_D6_MARK, PF11MD_101),
991
992 PINMUX_DATA(PF10_DATA, PF10MD_000),
993 PINMUX_DATA(CS1_MARK, PF10MD_001),
994 PINMUX_DATA(SSISCK1_MARK, PF10MD_010),
995 PINMUX_DATA(DV_DATA1_MARK, PF10MD_011),
996 PINMUX_DATA(SCK1_MARK, PF10MD_100),
997 PINMUX_DATA(MMC_D5_MARK, PF10MD_101),
998
999 PINMUX_DATA(PF9_DATA, PF9MD_000),
1000 PINMUX_DATA(BS_MARK, PF9MD_001),
1001 PINMUX_DATA(DV_DATA0_MARK, PF9MD_011),
1002 PINMUX_DATA(SCK0_MARK, PF9MD_100),
1003 PINMUX_DATA(MMC_D4_MARK, PF9MD_101),
1004 PINMUX_DATA(RTS1_MARK, PF9MD_110),
1005
1006 PINMUX_DATA(PF8_DATA, PF8MD_000),
1007 PINMUX_DATA(A23_MARK, PF8MD_001),
1008 PINMUX_DATA(TXD0_MARK, PF8MD_100),
1009
1010 PINMUX_DATA(PF7_DATA, PF7MD_000),
1011 PINMUX_DATA(SSIRXD0_MARK, PF7MD_010),
1012 PINMUX_DATA(RXD0_MARK, PF7MD_100),
1013 PINMUX_DATA(CTS1_MARK, PF7MD_110),
1014
1015 PINMUX_DATA(PF6_DATA, PF6MD_000),
1016 PINMUX_DATA(CE2A_MARK, PF6MD_001),
1017 PINMUX_DATA(SSITXD0_MARK, PF6MD_010),
1018
1019 PINMUX_DATA(PF5_DATA, PF5MD_000),
1020 PINMUX_DATA(SSIWS0_MARK, PF5MD_010),
1021
1022 PINMUX_DATA(PF4_DATA, PF4MD_000),
1023 PINMUX_DATA(CS5CE1A_MARK, PF4MD_001),
1024 PINMUX_DATA(SSISCK0_MARK, PF4MD_010),
1025
1026 PINMUX_DATA(PF3_DATA, PF3MD_000),
1027 PINMUX_DATA(CS2_MARK, PF3MD_001),
1028 PINMUX_DATA(MISO1_MARK, PF3MD_011),
1029 PINMUX_DATA(TIOC4D_MARK, PF3MD_100),
1030
1031 PINMUX_DATA(PF2_DATA, PF2MD_000),
1032 PINMUX_DATA(WAIT_MARK, PF2MD_001),
1033 PINMUX_DATA(MOSI1_MARK, PF2MD_011),
1034 PINMUX_DATA(TIOC4C_MARK, PF2MD_100),
1035 PINMUX_DATA(TEND0_MARK, PF2MD_101),
1036
1037 PINMUX_DATA(PF1_DATA, PF1MD_000),
1038 PINMUX_DATA(BACK_MARK, PF1MD_001),
1039 PINMUX_DATA(TIOC4B_MARK, PF1MD_100),
1040 PINMUX_DATA(DACK0_MARK, PF1MD_101),
1041
1042 PINMUX_DATA(PF0_DATA, PF0MD_000),
1043 PINMUX_DATA(BREQ_MARK, PF0MD_001),
1044 PINMUX_DATA(RSPCK1_MARK, PF0MD_011),
1045 PINMUX_DATA(TIOC4A_MARK, PF0MD_100),
1046 PINMUX_DATA(DREQ0_MARK, PF0MD_101),
1047
1048 /* Port G */
1049 PINMUX_DATA(PG27_DATA, PG27MD_00),
1050 PINMUX_DATA(LCD_TCON2_MARK, PG27MD_10),
1051 PINMUX_DATA(LCD_EXTCLK_MARK, PG27MD_11),
1052
1053 PINMUX_DATA(PG26_DATA, PG26MD_00),
1054 PINMUX_DATA(LCD_TCON1_MARK, PG26MD_10),
1055
1056 PINMUX_DATA(PG25_DATA, PG25MD_00),
1057 PINMUX_DATA(LCD_TCON0_MARK, PG25MD_10),
1058
1059 PINMUX_DATA(PG24_DATA, PG24MD_00),
1060 PINMUX_DATA(LCD_CLK_MARK, PG24MD_10),
1061
1062 PINMUX_DATA(PG23_DATA, PG23MD_000),
1063 PINMUX_DATA(LCD_DATA23_MARK, PG23MD_010),
1064 PINMUX_DATA(LCD_TCON6_MARK, PG23MD_011),
1065 PINMUX_DATA(TXD5_MARK, PG23MD_100),
1066
1067 PINMUX_DATA(PG22_DATA, PG22MD_000),
1068 PINMUX_DATA(LCD_DATA22_MARK, PG22MD_010),
1069 PINMUX_DATA(LCD_TCON5_MARK, PG22MD_011),
1070 PINMUX_DATA(RXD5_MARK, PG22MD_100),
1071
1072 PINMUX_DATA(PG21_DATA, PG21MD_000),
1073 PINMUX_DATA(DV_DATA7_MARK, PG21MD_001),
1074 PINMUX_DATA(LCD_DATA21_MARK, PG21MD_010),
1075 PINMUX_DATA(LCD_TCON4_MARK, PG21MD_011),
1076 PINMUX_DATA(TXD4_MARK, PG21MD_100),
1077
1078 PINMUX_DATA(PG20_DATA, PG20MD_000),
1079 PINMUX_DATA(DV_DATA6_MARK, PG20MD_001),
1080 PINMUX_DATA(LCD_DATA20_MARK, PG21MD_010),
1081 PINMUX_DATA(LCD_TCON3_MARK, PG20MD_011),
1082 PINMUX_DATA(RXD4_MARK, PG20MD_100),
1083
1084 PINMUX_DATA(PG19_DATA, PG19MD_000),
1085 PINMUX_DATA(DV_DATA5_MARK, PG19MD_001),
1086 PINMUX_DATA(LCD_DATA19_MARK, PG19MD_010),
1087 PINMUX_DATA(SPDIF_OUT_MARK, PG19MD_011),
1088 PINMUX_DATA(SCK5_MARK, PG19MD_100),
1089
1090 PINMUX_DATA(PG18_DATA, PG18MD_000),
1091 PINMUX_DATA(DV_DATA4_MARK, PG18MD_001),
1092 PINMUX_DATA(LCD_DATA18_MARK, PG18MD_010),
1093 PINMUX_DATA(SPDIF_IN_MARK, PG18MD_011),
1094 PINMUX_DATA(SCK4_MARK, PG18MD_100),
1095
1096// TODO hardware manual has PG17 3 bits wide in reg picture and 2 bits in description
1097// we're going with 2 bits
1098 PINMUX_DATA(PG17_DATA, PG17MD_00),
1099 PINMUX_DATA(WE3ICIOWRAHDQMUU_MARK, PG17MD_01),
1100 PINMUX_DATA(LCD_DATA17_MARK, PG17MD_10),
1101
1102// TODO hardware manual has PG16 3 bits wide in reg picture and 2 bits in description
1103// we're going with 2 bits
1104 PINMUX_DATA(PG16_DATA, PG16MD_00),
1105 PINMUX_DATA(WE2ICIORDDQMUL_MARK, PG16MD_01),
1106 PINMUX_DATA(LCD_DATA16_MARK, PG16MD_10),
1107
1108 PINMUX_DATA(PG15_DATA, PG15MD_00),
1109 PINMUX_DATA(D31_MARK, PG15MD_01),
1110 PINMUX_DATA(LCD_DATA15_MARK, PG15MD_10),
1111 PINMUX_DATA(PINT7_PG_MARK, PG15MD_11),
1112
1113 PINMUX_DATA(PG14_DATA, PG14MD_00),
1114 PINMUX_DATA(D30_MARK, PG14MD_01),
1115 PINMUX_DATA(LCD_DATA14_MARK, PG14MD_10),
1116 PINMUX_DATA(PINT6_PG_MARK, PG14MD_11),
1117
1118 PINMUX_DATA(PG13_DATA, PG13MD_00),
1119 PINMUX_DATA(D29_MARK, PG13MD_01),
1120 PINMUX_DATA(LCD_DATA13_MARK, PG13MD_10),
1121 PINMUX_DATA(PINT5_PG_MARK, PG13MD_11),
1122
1123 PINMUX_DATA(PG12_DATA, PG12MD_00),
1124 PINMUX_DATA(D28_MARK, PG12MD_01),
1125 PINMUX_DATA(LCD_DATA12_MARK, PG12MD_10),
1126 PINMUX_DATA(PINT4_PG_MARK, PG12MD_11),
1127
1128 PINMUX_DATA(PG11_DATA, PG11MD_000),
1129 PINMUX_DATA(D27_MARK, PG11MD_001),
1130 PINMUX_DATA(LCD_DATA11_MARK, PG11MD_010),
1131 PINMUX_DATA(PINT3_PG_MARK, PG11MD_011),
1132 PINMUX_DATA(TIOC3D_MARK, PG11MD_100),
1133
1134 PINMUX_DATA(PG10_DATA, PG10MD_000),
1135 PINMUX_DATA(D26_MARK, PG10MD_001),
1136 PINMUX_DATA(LCD_DATA10_MARK, PG10MD_010),
1137 PINMUX_DATA(PINT2_PG_MARK, PG10MD_011),
1138 PINMUX_DATA(TIOC3C_MARK, PG10MD_100),
1139
1140 PINMUX_DATA(PG9_DATA, PG9MD_000),
1141 PINMUX_DATA(D25_MARK, PG9MD_001),
1142 PINMUX_DATA(LCD_DATA9_MARK, PG9MD_010),
1143 PINMUX_DATA(PINT1_PG_MARK, PG9MD_011),
1144 PINMUX_DATA(TIOC3B_MARK, PG9MD_100),
1145
1146 PINMUX_DATA(PG8_DATA, PG8MD_000),
1147 PINMUX_DATA(D24_MARK, PG8MD_001),
1148 PINMUX_DATA(LCD_DATA8_MARK, PG8MD_010),
1149 PINMUX_DATA(PINT0_PG_MARK, PG8MD_011),
1150 PINMUX_DATA(TIOC3A_MARK, PG8MD_100),
1151
1152 PINMUX_DATA(PG7_DATA, PG7MD_000),
1153 PINMUX_DATA(D23_MARK, PG7MD_001),
1154 PINMUX_DATA(LCD_DATA7_MARK, PG7MD_010),
1155 PINMUX_DATA(IRQ7_PG_MARK, PG7MD_011),
1156 PINMUX_DATA(TIOC2B_MARK, PG7MD_100),
1157
1158 PINMUX_DATA(PG6_DATA, PG6MD_000),
1159 PINMUX_DATA(D22_MARK, PG6MD_001),
1160 PINMUX_DATA(LCD_DATA6_MARK, PG6MD_010),
1161 PINMUX_DATA(IRQ6_PG_MARK, PG6MD_011),
1162 PINMUX_DATA(TIOC2A_MARK, PG6MD_100),
1163
1164 PINMUX_DATA(PG5_DATA, PG5MD_000),
1165 PINMUX_DATA(D21_MARK, PG5MD_001),
1166 PINMUX_DATA(LCD_DATA5_MARK, PG5MD_010),
1167 PINMUX_DATA(IRQ5_PG_MARK, PG5MD_011),
1168 PINMUX_DATA(TIOC1B_MARK, PG5MD_100),
1169
1170 PINMUX_DATA(PG4_DATA, PG4MD_000),
1171 PINMUX_DATA(D20_MARK, PG4MD_001),
1172 PINMUX_DATA(LCD_DATA4_MARK, PG4MD_010),
1173 PINMUX_DATA(IRQ4_PG_MARK, PG4MD_011),
1174 PINMUX_DATA(TIOC1A_MARK, PG4MD_100),
1175
1176 PINMUX_DATA(PG3_DATA, PG3MD_000),
1177 PINMUX_DATA(D19_MARK, PG3MD_001),
1178 PINMUX_DATA(LCD_DATA3_MARK, PG3MD_010),
1179 PINMUX_DATA(IRQ3_PG_MARK, PG3MD_011),
1180 PINMUX_DATA(TIOC0D_MARK, PG3MD_100),
1181
1182 PINMUX_DATA(PG2_DATA, PG2MD_000),
1183 PINMUX_DATA(D18_MARK, PG2MD_001),
1184 PINMUX_DATA(LCD_DATA2_MARK, PG2MD_010),
1185 PINMUX_DATA(IRQ2_PG_MARK, PG2MD_011),
1186 PINMUX_DATA(TIOC0C_MARK, PG2MD_100),
1187
1188 PINMUX_DATA(PG1_DATA, PG1MD_000),
1189 PINMUX_DATA(D17_MARK, PG1MD_001),
1190 PINMUX_DATA(LCD_DATA1_MARK, PG1MD_010),
1191 PINMUX_DATA(IRQ1_PG_MARK, PG1MD_011),
1192 PINMUX_DATA(TIOC0B_MARK, PG1MD_100),
1193
1194 PINMUX_DATA(PG0_DATA, PG0MD_000),
1195 PINMUX_DATA(D16_MARK, PG0MD_001),
1196 PINMUX_DATA(LCD_DATA0_MARK, PG0MD_010),
1197 PINMUX_DATA(IRQ0_PG_MARK, PG0MD_011),
1198 PINMUX_DATA(TIOC0A_MARK, PG0MD_100),
1199
1200 /* Port H */
1201 PINMUX_DATA(PH7_DATA, PH7MD_00),
1202 PINMUX_DATA(PHAN7_MARK, PH7MD_01),
1203 PINMUX_DATA(PINT7_PH_MARK, PH7MD_10),
1204
1205 PINMUX_DATA(PH6_DATA, PH6MD_00),
1206 PINMUX_DATA(PHAN6_MARK, PH6MD_01),
1207 PINMUX_DATA(PINT6_PH_MARK, PH6MD_10),
1208
1209 PINMUX_DATA(PH5_DATA, PH5MD_00),
1210 PINMUX_DATA(PHAN5_MARK, PH5MD_01),
1211 PINMUX_DATA(PINT5_PH_MARK, PH5MD_10),
1212 PINMUX_DATA(LCD_EXTCLK_MARK, PH5MD_11),
1213
1214 PINMUX_DATA(PH4_DATA, PH4MD_00),
1215 PINMUX_DATA(PHAN4_MARK, PH4MD_01),
1216 PINMUX_DATA(PINT4_PH_MARK, PH4MD_10),
1217
1218 PINMUX_DATA(PH3_DATA, PH3MD_00),
1219 PINMUX_DATA(PHAN3_MARK, PH3MD_01),
1220 PINMUX_DATA(PINT3_PH_MARK, PH3MD_10),
1221
1222 PINMUX_DATA(PH2_DATA, PH2MD_00),
1223 PINMUX_DATA(PHAN2_MARK, PH2MD_01),
1224 PINMUX_DATA(PINT2_PH_MARK, PH2MD_10),
1225
1226 PINMUX_DATA(PH1_DATA, PH1MD_00),
1227 PINMUX_DATA(PHAN1_MARK, PH1MD_01),
1228 PINMUX_DATA(PINT1_PH_MARK, PH1MD_10),
1229
1230 PINMUX_DATA(PH0_DATA, PH0MD_00),
1231 PINMUX_DATA(PHAN0_MARK, PH0MD_01),
1232 PINMUX_DATA(PINT0_PH_MARK, PH0MD_10),
1233
1234 /* Port I - not on device */
1235
1236 /* Port J */
1237 PINMUX_DATA(PJ31_DATA, PJ31MD_0),
1238 PINMUX_DATA(DV_CLK_MARK, PJ31MD_1),
1239
1240 PINMUX_DATA(PJ30_DATA, PJ30MD_000),
1241 PINMUX_DATA(SSIDATA5_MARK, PJ30MD_010),
1242 PINMUX_DATA(TIOC2B_MARK, PJ30MD_100),
1243 PINMUX_DATA(IETXD_MARK, PJ30MD_101),
1244
1245 PINMUX_DATA(PJ29_DATA, PJ29MD_000),
1246 PINMUX_DATA(SSIWS5_MARK, PJ29MD_010),
1247 PINMUX_DATA(TIOC2A_MARK, PJ29MD_100),
1248 PINMUX_DATA(IERXD_MARK, PJ29MD_101),
1249
1250 PINMUX_DATA(PJ28_DATA, PJ28MD_000),
1251 PINMUX_DATA(SSISCK5_MARK, PJ28MD_010),
1252 PINMUX_DATA(TIOC1B_MARK, PJ28MD_100),
1253 PINMUX_DATA(RTS7_MARK, PJ28MD_101),
1254
1255 PINMUX_DATA(PJ27_DATA, PJ27MD_000),
1256 PINMUX_DATA(TIOC1A_MARK, PJ27MD_100),
1257 PINMUX_DATA(CTS7_MARK, PJ27MD_101),
1258
1259 PINMUX_DATA(PJ26_DATA, PJ26MD_000),
1260 PINMUX_DATA(SSIDATA4_MARK, PJ26MD_010),
1261 PINMUX_DATA(LCD_TCON5_MARK, PJ26MD_011),
1262 PINMUX_DATA(TXD7_MARK, PJ26MD_101),
1263
1264 PINMUX_DATA(PJ25_DATA, PJ25MD_000),
1265 PINMUX_DATA(SSIWS4_MARK, PJ25MD_010),
1266 PINMUX_DATA(LCD_TCON4_MARK, PJ25MD_011),
1267 PINMUX_DATA(SPDIF_OUT_MARK, PJ25MD_100),
1268 PINMUX_DATA(RXD7_MARK, PJ25MD_101),
1269
1270 PINMUX_DATA(PJ24_DATA, PJ24MD_000),
1271 PINMUX_DATA(SSISCK4_MARK, PJ24MD_010),
1272 PINMUX_DATA(LCD_TCON3_MARK, PJ24MD_011),
1273 PINMUX_DATA(SPDIF_IN_MARK, PJ24MD_100),
1274 PINMUX_DATA(SCK7_MARK, PJ24MD_101),
1275
1276 PINMUX_DATA(PJ23_DATA, PJ23MD_000),
1277 PINMUX_DATA(DV_DATA23_MARK, PJ23MD_001),
1278 PINMUX_DATA(LCD_DATA23_MARK, PJ23MD_010),
1279 PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
1280 PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
1281 PINMUX_DATA(CTX1_MARK, PJ23MD_101),
1282
1283 PINMUX_DATA(PJ22_DATA, PJ22MD_000),
1284 PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
1285 PINMUX_DATA(LCD_DATA22_MARK, PJ22MD_010),
1286 PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
1287 PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
1288 PINMUX_DATA(CRX1_MARK, PJ22MD_101),
1289 PINMUX_DATA(CRX0CRX1_MARK, PJ22MD_110),
1290
1291 PINMUX_DATA(PJ21_DATA, PJ21MD_000),
1292 PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
1293 PINMUX_DATA(LCD_DATA21_MARK, PJ21MD_010),
1294 PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
1295 PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
1296 PINMUX_DATA(CTX2_MARK, PJ21MD_101),
1297
1298 PINMUX_DATA(PJ20_DATA, PJ20MD_000),
1299 PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
1300 PINMUX_DATA(LCD_DATA20_MARK, PJ20MD_010),
1301 PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
1302 PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
1303 PINMUX_DATA(CRX2_MARK, PJ20MD_101),
1304 PINMUX_DATA(CRX0CRX1CRX2_PJ20_MARK, PJ20MD_110),
1305
1306 PINMUX_DATA(PJ19_DATA, PJ19MD_000),
1307 PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
1308 PINMUX_DATA(LCD_DATA19_MARK, PJ19MD_010),
1309 PINMUX_DATA(MISO0_PJ19_MARK, PJ19MD_011),
1310 PINMUX_DATA(TIOC0D_MARK, PJ19MD_100),
1311 PINMUX_DATA(SIOFRXD_MARK, PJ19MD_101),
1312 PINMUX_DATA(AUDIO_XOUT_MARK, PJ19MD_110),
1313
1314 PINMUX_DATA(PJ18_DATA, PJ18MD_000),
1315 PINMUX_DATA(DV_DATA18_MARK, PJ18MD_001),
1316 PINMUX_DATA(LCD_DATA18_MARK, PJ18MD_010),
1317 PINMUX_DATA(MOSI0_PJ18_MARK, PJ18MD_011),
1318 PINMUX_DATA(TIOC0C_MARK, PJ18MD_100),
1319 PINMUX_DATA(SIOFTXD_MARK, PJ18MD_101),
1320
1321 PINMUX_DATA(PJ17_DATA, PJ17MD_000),
1322 PINMUX_DATA(DV_DATA17_MARK, PJ17MD_001),
1323 PINMUX_DATA(LCD_DATA17_MARK, PJ17MD_010),
1324 PINMUX_DATA(SSL00_PJ17_MARK, PJ17MD_011),
1325 PINMUX_DATA(TIOC0B_MARK, PJ17MD_100),
1326 PINMUX_DATA(SIOFSYNC_MARK, PJ17MD_101),
1327
1328 PINMUX_DATA(PJ16_DATA, PJ16MD_000),
1329 PINMUX_DATA(DV_DATA16_MARK, PJ16MD_001),
1330 PINMUX_DATA(LCD_DATA16_MARK, PJ16MD_010),
1331 PINMUX_DATA(RSPCK0_PJ16_MARK, PJ16MD_011),
1332 PINMUX_DATA(TIOC0A_MARK, PJ16MD_100),
1333 PINMUX_DATA(SIOFSCK_MARK, PJ16MD_101),
1334
1335 PINMUX_DATA(PJ15_DATA, PJ15MD_000),
1336 PINMUX_DATA(DV_DATA15_MARK, PJ15MD_001),
1337 PINMUX_DATA(LCD_DATA15_MARK, PJ15MD_010),
1338 PINMUX_DATA(PINT7_PJ_MARK, PJ15MD_011),
1339 PINMUX_DATA(PWM2H_MARK, PJ15MD_100),
1340 PINMUX_DATA(TXD7_MARK, PJ15MD_101),
1341
1342 PINMUX_DATA(PJ14_DATA, PJ14MD_000),
1343 PINMUX_DATA(DV_DATA14_MARK, PJ14MD_001),
1344 PINMUX_DATA(LCD_DATA14_MARK, PJ14MD_010),
1345 PINMUX_DATA(PINT6_PJ_MARK, PJ14MD_011),
1346 PINMUX_DATA(PWM2G_MARK, PJ14MD_100),
1347 PINMUX_DATA(TXD6_MARK, PJ14MD_101),
1348
1349 PINMUX_DATA(PJ13_DATA, PJ13MD_000),
1350 PINMUX_DATA(DV_DATA13_MARK, PJ13MD_001),
1351 PINMUX_DATA(LCD_DATA13_MARK, PJ13MD_010),
1352 PINMUX_DATA(PINT5_PJ_MARK, PJ13MD_011),
1353 PINMUX_DATA(PWM2F_MARK, PJ13MD_100),
1354 PINMUX_DATA(TXD5_MARK, PJ13MD_101),
1355
1356 PINMUX_DATA(PJ12_DATA, PJ12MD_000),
1357 PINMUX_DATA(DV_DATA12_MARK, PJ12MD_001),
1358 PINMUX_DATA(LCD_DATA12_MARK, PJ12MD_010),
1359 PINMUX_DATA(PINT4_PJ_MARK, PJ12MD_011),
1360 PINMUX_DATA(PWM2E_MARK, PJ12MD_100),
1361 PINMUX_DATA(SCK7_MARK, PJ12MD_101),
1362
1363 PINMUX_DATA(PJ11_DATA, PJ11MD_000),
1364 PINMUX_DATA(DV_DATA11_MARK, PJ11MD_001),
1365 PINMUX_DATA(LCD_DATA11_MARK, PJ11MD_010),
1366 PINMUX_DATA(PINT3_PJ_MARK, PJ11MD_011),
1367 PINMUX_DATA(PWM2D_MARK, PJ11MD_100),
1368 PINMUX_DATA(SCK6_MARK, PJ11MD_101),
1369
1370 PINMUX_DATA(PJ10_DATA, PJ10MD_000),
1371 PINMUX_DATA(DV_DATA10_MARK, PJ10MD_001),
1372 PINMUX_DATA(LCD_DATA10_MARK, PJ10MD_010),
1373 PINMUX_DATA(PINT2_PJ_MARK, PJ10MD_011),
1374 PINMUX_DATA(PWM2C_MARK, PJ10MD_100),
1375 PINMUX_DATA(SCK5_MARK, PJ10MD_101),
1376
1377 PINMUX_DATA(PJ9_DATA, PJ9MD_000),
1378 PINMUX_DATA(DV_DATA9_MARK, PJ9MD_001),
1379 PINMUX_DATA(LCD_DATA9_MARK, PJ9MD_010),
1380 PINMUX_DATA(PINT1_PJ_MARK, PJ9MD_011),
1381 PINMUX_DATA(PWM2B_MARK, PJ9MD_100),
1382 PINMUX_DATA(RTS5_MARK, PJ9MD_101),
1383
1384 PINMUX_DATA(PJ8_DATA, PJ8MD_000),
1385 PINMUX_DATA(DV_DATA8_MARK, PJ8MD_001),
1386 PINMUX_DATA(LCD_DATA8_MARK, PJ8MD_010),
1387 PINMUX_DATA(PINT0_PJ_MARK, PJ8MD_011),
1388 PINMUX_DATA(PWM2A_MARK, PJ8MD_100),
1389 PINMUX_DATA(CTS5_MARK, PJ8MD_101),
1390
1391 PINMUX_DATA(PJ7_DATA, PJ7MD_000),
1392 PINMUX_DATA(DV_DATA7_MARK, PJ7MD_001),
1393 PINMUX_DATA(LCD_DATA7_MARK, PJ7MD_010),
1394 PINMUX_DATA(SD_D2_MARK, PJ7MD_011),
1395 PINMUX_DATA(PWM1H_MARK, PJ7MD_100),
1396
1397 PINMUX_DATA(PJ6_DATA, PJ6MD_000),
1398 PINMUX_DATA(DV_DATA6_MARK, PJ6MD_001),
1399 PINMUX_DATA(LCD_DATA6_MARK, PJ6MD_010),
1400 PINMUX_DATA(SD_D3_MARK, PJ6MD_011),
1401 PINMUX_DATA(PWM1G_MARK, PJ6MD_100),
1402
1403 PINMUX_DATA(PJ5_DATA, PJ5MD_000),
1404 PINMUX_DATA(DV_DATA5_MARK, PJ5MD_001),
1405 PINMUX_DATA(LCD_DATA5_MARK, PJ5MD_010),
1406 PINMUX_DATA(SD_CMD_MARK, PJ5MD_011),
1407 PINMUX_DATA(PWM1F_MARK, PJ5MD_100),
1408
1409 PINMUX_DATA(PJ4_DATA, PJ4MD_000),
1410 PINMUX_DATA(DV_DATA4_MARK, PJ4MD_001),
1411 PINMUX_DATA(LCD_DATA4_MARK, PJ4MD_010),
1412 PINMUX_DATA(SD_CLK_MARK, PJ4MD_011),
1413 PINMUX_DATA(PWM1E_MARK, PJ4MD_100),
1414
1415 PINMUX_DATA(PJ3_DATA, PJ3MD_000),
1416 PINMUX_DATA(DV_DATA3_MARK, PJ3MD_001),
1417 PINMUX_DATA(LCD_DATA3_MARK, PJ3MD_010),
1418 PINMUX_DATA(SD_D0_MARK, PJ3MD_011),
1419 PINMUX_DATA(PWM1D_MARK, PJ3MD_100),
1420
1421 PINMUX_DATA(PJ2_DATA, PJ2MD_000),
1422 PINMUX_DATA(DV_DATA2_MARK, PJ2MD_001),
1423 PINMUX_DATA(LCD_DATA2_MARK, PJ2MD_010),
1424 PINMUX_DATA(SD_D1_MARK, PJ2MD_011),
1425 PINMUX_DATA(PWM1C_MARK, PJ2MD_100),
1426
1427 PINMUX_DATA(PJ1_DATA, PJ1MD_000),
1428 PINMUX_DATA(DV_DATA1_MARK, PJ1MD_001),
1429 PINMUX_DATA(LCD_DATA1_MARK, PJ1MD_010),
1430 PINMUX_DATA(SD_WP_MARK, PJ1MD_011),
1431 PINMUX_DATA(PWM1B_MARK, PJ1MD_100),
1432
1433 PINMUX_DATA(PJ0_DATA, PJ0MD_000),
1434 PINMUX_DATA(DV_DATA0_MARK, PJ0MD_001),
1435 PINMUX_DATA(LCD_DATA0_MARK, PJ0MD_010),
1436 PINMUX_DATA(SD_CD_MARK, PJ0MD_011),
1437 PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
1438};
1439
1440static struct pinmux_gpio pinmux_gpios[] = {
1441 /* Port A */
1442 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
1443 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
1444
1445 /* Port B */
1446 PINMUX_GPIO(GPIO_PB22, PB22_DATA),
1447 PINMUX_GPIO(GPIO_PB21, PB21_DATA),
1448 PINMUX_GPIO(GPIO_PB20, PB20_DATA),
1449 PINMUX_GPIO(GPIO_PB19, PB19_DATA),
1450 PINMUX_GPIO(GPIO_PB18, PB18_DATA),
1451 PINMUX_GPIO(GPIO_PB17, PB17_DATA),
1452 PINMUX_GPIO(GPIO_PB16, PB16_DATA),
1453 PINMUX_GPIO(GPIO_PB15, PB15_DATA),
1454 PINMUX_GPIO(GPIO_PB14, PB14_DATA),
1455 PINMUX_GPIO(GPIO_PB13, PB13_DATA),
1456 PINMUX_GPIO(GPIO_PB12, PB12_DATA),
1457 PINMUX_GPIO(GPIO_PB11, PB11_DATA),
1458 PINMUX_GPIO(GPIO_PB10, PB10_DATA),
1459 PINMUX_GPIO(GPIO_PB9, PB9_DATA),
1460 PINMUX_GPIO(GPIO_PB8, PB8_DATA),
1461 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
1462 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
1463 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
1464 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
1465 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
1466 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
1467 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
1468
1469 /* Port C */
1470 PINMUX_GPIO(GPIO_PC8, PC8_DATA),
1471 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
1472 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
1473 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
1474 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
1475 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
1476 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
1477 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
1478 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
1479
1480 /* Port D */
1481 PINMUX_GPIO(GPIO_PD15, PD15_DATA),
1482 PINMUX_GPIO(GPIO_PD14, PD14_DATA),
1483 PINMUX_GPIO(GPIO_PD13, PD13_DATA),
1484 PINMUX_GPIO(GPIO_PD12, PD12_DATA),
1485 PINMUX_GPIO(GPIO_PD11, PD11_DATA),
1486 PINMUX_GPIO(GPIO_PD10, PD10_DATA),
1487 PINMUX_GPIO(GPIO_PD9, PD9_DATA),
1488 PINMUX_GPIO(GPIO_PD8, PD8_DATA),
1489 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
1490 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
1491 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
1492 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
1493 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
1494 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
1495 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
1496 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
1497
1498 /* Port E */
1499 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
1500 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
1501 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
1502 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
1503 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
1504 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
1505 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
1506 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
1507
1508 /* Port F */
1509 PINMUX_GPIO(GPIO_PF23, PF23_DATA),
1510 PINMUX_GPIO(GPIO_PF22, PF22_DATA),
1511 PINMUX_GPIO(GPIO_PF21, PF21_DATA),
1512 PINMUX_GPIO(GPIO_PF20, PF20_DATA),
1513 PINMUX_GPIO(GPIO_PF19, PF19_DATA),
1514 PINMUX_GPIO(GPIO_PF18, PF18_DATA),
1515 PINMUX_GPIO(GPIO_PF17, PF17_DATA),
1516 PINMUX_GPIO(GPIO_PF16, PF16_DATA),
1517 PINMUX_GPIO(GPIO_PF15, PF15_DATA),
1518 PINMUX_GPIO(GPIO_PF14, PF14_DATA),
1519 PINMUX_GPIO(GPIO_PF13, PF13_DATA),
1520 PINMUX_GPIO(GPIO_PF12, PF12_DATA),
1521 PINMUX_GPIO(GPIO_PF11, PF11_DATA),
1522 PINMUX_GPIO(GPIO_PF10, PF10_DATA),
1523 PINMUX_GPIO(GPIO_PF9, PF9_DATA),
1524 PINMUX_GPIO(GPIO_PF8, PF8_DATA),
1525 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
1526 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
1527 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
1528 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
1529 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
1530 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
1531 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
1532 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
1533
1534 /* Port G */
1535 PINMUX_GPIO(GPIO_PG27, PG27_DATA),
1536 PINMUX_GPIO(GPIO_PG26, PG26_DATA),
1537 PINMUX_GPIO(GPIO_PG25, PG25_DATA),
1538 PINMUX_GPIO(GPIO_PG24, PG24_DATA),
1539 PINMUX_GPIO(GPIO_PG23, PG23_DATA),
1540 PINMUX_GPIO(GPIO_PG22, PG22_DATA),
1541 PINMUX_GPIO(GPIO_PG21, PG21_DATA),
1542 PINMUX_GPIO(GPIO_PG20, PG20_DATA),
1543 PINMUX_GPIO(GPIO_PG19, PG19_DATA),
1544 PINMUX_GPIO(GPIO_PG18, PG18_DATA),
1545 PINMUX_GPIO(GPIO_PG17, PG17_DATA),
1546 PINMUX_GPIO(GPIO_PG16, PG16_DATA),
1547 PINMUX_GPIO(GPIO_PG15, PG15_DATA),
1548 PINMUX_GPIO(GPIO_PG14, PG14_DATA),
1549 PINMUX_GPIO(GPIO_PG13, PG13_DATA),
1550 PINMUX_GPIO(GPIO_PG12, PG12_DATA),
1551 PINMUX_GPIO(GPIO_PG11, PG11_DATA),
1552 PINMUX_GPIO(GPIO_PG10, PG10_DATA),
1553 PINMUX_GPIO(GPIO_PG9, PG9_DATA),
1554 PINMUX_GPIO(GPIO_PG8, PG8_DATA),
1555 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
1556 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
1557 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
1558 PINMUX_GPIO(GPIO_PG4, PG4_DATA),
1559 PINMUX_GPIO(GPIO_PG3, PG3_DATA),
1560 PINMUX_GPIO(GPIO_PG2, PG2_DATA),
1561 PINMUX_GPIO(GPIO_PG1, PG1_DATA),
1562 PINMUX_GPIO(GPIO_PG0, PG0_DATA),
1563
1564 /* Port H - Port H does not have a Data Register */
1565
1566 /* Port I - not on device */
1567
1568 /* Port J */
1569 PINMUX_GPIO(GPIO_PJ31, PJ31_DATA),
1570 PINMUX_GPIO(GPIO_PJ30, PJ30_DATA),
1571 PINMUX_GPIO(GPIO_PJ29, PJ29_DATA),
1572 PINMUX_GPIO(GPIO_PJ28, PJ28_DATA),
1573 PINMUX_GPIO(GPIO_PJ27, PJ27_DATA),
1574 PINMUX_GPIO(GPIO_PJ26, PJ26_DATA),
1575 PINMUX_GPIO(GPIO_PJ25, PJ25_DATA),
1576 PINMUX_GPIO(GPIO_PJ24, PJ24_DATA),
1577 PINMUX_GPIO(GPIO_PJ23, PJ23_DATA),
1578 PINMUX_GPIO(GPIO_PJ22, PJ22_DATA),
1579 PINMUX_GPIO(GPIO_PJ21, PJ21_DATA),
1580 PINMUX_GPIO(GPIO_PJ20, PJ20_DATA),
1581 PINMUX_GPIO(GPIO_PJ19, PJ19_DATA),
1582 PINMUX_GPIO(GPIO_PJ18, PJ18_DATA),
1583 PINMUX_GPIO(GPIO_PJ17, PJ17_DATA),
1584 PINMUX_GPIO(GPIO_PJ16, PJ16_DATA),
1585 PINMUX_GPIO(GPIO_PJ15, PJ15_DATA),
1586 PINMUX_GPIO(GPIO_PJ14, PJ14_DATA),
1587 PINMUX_GPIO(GPIO_PJ13, PJ13_DATA),
1588 PINMUX_GPIO(GPIO_PJ12, PJ12_DATA),
1589 PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
1590 PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
1591 PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
1592 PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
1593 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
1594 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
1595 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
1596 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
1597 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
1598 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
1599 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
1600 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
1601
1602 /* INTC */
1603 PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK),
1604 PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK),
1605 PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK),
1606 PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK),
1607 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
1608 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
1609 PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK),
1610 PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK),
1611 PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK),
1612 PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK),
1613 PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK),
1614 PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK),
1615 PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK),
1616 PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK),
1617 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
1618 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
1619 PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK),
1620 PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK),
1621
1622 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
1623 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
1624 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
1625 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
1626 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
1627 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
1628 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
1629 PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK),
1630 PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK),
1631 PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK),
1632 PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK),
1633 PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK),
1634 PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK),
1635 PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK),
1636 PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK),
1637 PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK),
1638 PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK),
1639 PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK),
1640 PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK),
1641 PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK),
1642 PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK),
1643 PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK),
1644 PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK),
1645 PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK),
1646
1647 /* WDT */
1648 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
1649
1650 /* CAN */
1651 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
1652 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
1653 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
1654 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
1655 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK),
1656 PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0CRX1CRX2_MARK),
1657
1658 /* DMAC */
1659 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1660 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1661 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1662 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1663 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1664 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1665
1666 /* ADC */
1667 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
1668
1669 /* BSCh */
1670 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1671 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1672 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1673 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1674 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1675 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1676 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1677 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1678 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1679 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1680 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1681 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1682 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1683 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1684 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1685 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1686 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1687 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1688 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1689 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1690 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1691 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1692 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1693 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1694 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1695 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1696
1697 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1698 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1699 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1700 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1701 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1702 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1703 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1704 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1705 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1706 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1707 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1708 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1709 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1710 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1711 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1712 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1713
1714 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1715 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1716 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
1717 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
1718 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
1719 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1720 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
1721 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
1722 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
1723 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1724 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1725 PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK),
1726 PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK),
1727 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
1728 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
1729 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
1730 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
1731 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
1732 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1733 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
1734 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
1735 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1736
1737 /* TMU */
1738 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
1739 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
1740 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
1741 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
1742 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
1743 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
1744 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
1745 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
1746 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
1747 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
1748 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
1749 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
1750 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
1751 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
1752 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
1753 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
1754 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
1755 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
1756 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
1757 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
1758
1759 /* SCIF */
1760 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
1761 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
1762 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
1763 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
1764 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
1765 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
1766 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
1767 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
1768 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1769 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1770 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1771 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1772 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1773 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1774 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1775 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1776 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1777 PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK),
1778 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
1779 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
1780 PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK),
1781 PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK),
1782 PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK),
1783 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
1784 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
1785 PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK),
1786 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
1787 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
1788 PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK),
1789 PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK),
1790
1791 /* RSPI */
1792 PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK),
1793 PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK),
1794 PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK),
1795 PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK),
1796 PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK),
1797 PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK),
1798 PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK),
1799 PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK),
1800 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
1801 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
1802 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
1803 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
1804
1805 /* IIC3 */
1806 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1807 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1808 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1809 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1810 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1811 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1812
1813 /* SSI */
1814 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
1815 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
1816 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
1817 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
1818 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
1819 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
1820 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
1821 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
1822 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
1823 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
1824 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
1825 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
1826 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
1827 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
1828 PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK),
1829
1830 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1831 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
1832 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
1833 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
1834 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
1835
1836 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1837 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
1838 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
1839
1840 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1841 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1842 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1843
1844 /* VDC3 */
1845 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1846 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1847 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1848
1849 PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK),
1850 PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK),
1851 PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK),
1852 PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK),
1853 PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK),
1854 PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK),
1855 PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK),
1856 PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK),
1857 PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK),
1858 PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK),
1859 PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK),
1860 PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK),
1861 PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK),
1862 PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK),
1863 PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK),
1864 PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK),
1865 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
1866 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
1867 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
1868 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
1869 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
1870 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
1871 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
1872 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
1873
1874 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
1875 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
1876 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
1877 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
1878 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
1879
1880 PINMUX_GPIO(GPIO_FN_LCD_DATA23, LCD_DATA23_MARK),
1881 PINMUX_GPIO(GPIO_FN_LCD_DATA22, LCD_DATA22_MARK),
1882 PINMUX_GPIO(GPIO_FN_LCD_DATA21, LCD_DATA21_MARK),
1883 PINMUX_GPIO(GPIO_FN_LCD_DATA20, LCD_DATA20_MARK),
1884 PINMUX_GPIO(GPIO_FN_LCD_DATA19, LCD_DATA19_MARK),
1885 PINMUX_GPIO(GPIO_FN_LCD_DATA18, LCD_DATA18_MARK),
1886 PINMUX_GPIO(GPIO_FN_LCD_DATA17, LCD_DATA17_MARK),
1887 PINMUX_GPIO(GPIO_FN_LCD_DATA16, LCD_DATA16_MARK),
1888 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
1889 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
1890 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
1891 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
1892 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
1893 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
1894 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
1895 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
1896 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
1897 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
1898 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
1899 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
1900 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
1901 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
1902 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
1903 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
1904
1905 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
1906};
1907
1908static struct pinmux_cfg_reg pinmux_config_regs[] = {
1909 /* "name" addr register_size Field_Width */
1910
1911 /* where Field_Width is 1 for single mode registers or 4 for upto 16
1912 mode registers and modes are described in assending order [0..16] */
1913
1914 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1915 0, 0, 0, 0, 0, 0, 0, 0,
1916 0, 0, 0, 0, 0, 0, PA1_IN, PA1_OUT,
1917 0, 0, 0, 0, 0, 0, 0, 0,
1918 0, 0, 0, 0, 0, 0, PA0_IN, PA0_OUT }
1919 },
1920 { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
1921 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1922
1923 PB22MD_000, PB22MD_001, PB22MD_010, PB22MD_011,
1924 PB22MD_100, PB22MD_101, PB22MD_110, PB22MD_111,
1925 0, 0, 0, 0, 0, 0, 0, 0,
1926
1927 PB21MD_00, PB21MD_01, PB21MD_10, PB21MD_11, 0, 0, 0, 0,
1928 0, 0, 0, 0, 0, 0, 0, 0,
1929
1930 PB20MD_000, PB20MD_001, PB20MD_010, PB20MD_011,
1931 PB20MD_100, PB20MD_101, PB20MD_110, PB20MD_111,
1932 0, 0, 0, 0, 0, 0, 0, 0 }
1933 },
1934 { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
1935 PB19MD_000, PB19MD_001, PB19MD_010, PB19MD_011,
1936 PB19MD_100, PB19MD_101, PB19MD_110, PB19MD_111,
1937 0, 0, 0, 0, 0, 0, 0, 0,
1938
1939 PB18MD_000, PB18MD_001, PB18MD_010, PB18MD_011,
1940 PB18MD_100, PB18MD_101, PB18MD_110, PB18MD_111,
1941 0, 0, 0, 0, 0, 0, 0, 0,
1942
1943 PB17MD_000, PB17MD_001, PB17MD_010, PB17MD_011,
1944 PB17MD_100, PB17MD_101, PB17MD_110, PB17MD_111,
1945 0, 0, 0, 0, 0, 0, 0, 0,
1946
1947 PB16MD_000, PB16MD_001, PB16MD_010, PB16MD_011,
1948 PB16MD_100, PB16MD_101, PB16MD_110, PB16MD_111,
1949 0, 0, 0, 0, 0, 0, 0, 0 }
1950 },
1951 { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
1952 PB15MD_000, PB15MD_001, PB15MD_010, PB15MD_011,
1953 PB15MD_100, PB15MD_101, PB15MD_110, PB15MD_111,
1954 0, 0, 0, 0, 0, 0, 0, 0,
1955
1956 PB14MD_000, PB14MD_001, PB14MD_010, PB14MD_011,
1957 PB14MD_100, PB14MD_101, PB14MD_110, PB14MD_111,
1958 0, 0, 0, 0, 0, 0, 0, 0,
1959
1960 PB13MD_000, PB13MD_001, PB13MD_010, PB13MD_011,
1961 PB13MD_100, PB13MD_101, PB13MD_110, PB13MD_111,
1962 0, 0, 0, 0, 0, 0, 0, 0,
1963
1964 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11, 0, 0, 0, 0,
1965 0, 0, 0, 0, 0, 0, 0, 0 }
1966 },
1967 { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
1968 PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11, 0, 0, 0, 0,
1969 0, 0, 0, 0, 0, 0, 0, 0,
1970
1971 PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11, 0, 0, 0, 0,
1972 0, 0, 0, 0, 0, 0, 0, 0,
1973
1974 PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11, 0, 0, 0, 0,
1975 0, 0, 0, 0, 0, 0, 0, 0,
1976
1977 PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11, 0, 0, 0, 0,
1978 0, 0, 0, 0, 0, 0, 0, 0 }
1979 },
1980 { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
1981 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11, 0, 0, 0, 0,
1982 0, 0, 0, 0, 0, 0, 0, 0,
1983
1984 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11, 0, 0, 0, 0,
1985 0, 0, 0, 0, 0, 0, 0, 0,
1986
1987 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11, 0, 0, 0, 0,
1988 0, 0, 0, 0, 0, 0, 0, 0,
1989
1990 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11, 0, 0, 0, 0,
1991 0, 0, 0, 0, 0, 0, 0, 0 }
1992 },
1993 { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
1994 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11, 0, 0, 0, 0,
1995 0, 0, 0, 0, 0, 0, 0, 0,
1996
1997 PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11, 0, 0, 0, 0,
1998 0, 0, 0, 0, 0, 0, 0, 0,
1999
2000 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11, 0, 0, 0, 0,
2001 0, 0, 0, 0, 0, 0, 0, 0,
2002
2003 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
2004 },
2005
2006 { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
2007 0, 0, 0, 0, 0, 0, 0, 0,
2008 0, 0, 0, 0, 0, 0, 0, 0,
2009 0, 0,
2010 PB22_IN, PB22_OUT,
2011 PB21_IN, PB21_OUT,
2012 PB20_IN, PB20_OUT,
2013 PB19_IN, PB19_OUT,
2014 PB18_IN, PB18_OUT,
2015 PB17_IN, PB17_OUT,
2016 PB16_IN, PB16_OUT }
2017 },
2018 { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
2019 PB15_IN, PB15_OUT,
2020 PB14_IN, PB14_OUT,
2021 PB13_IN, PB13_OUT,
2022 PB12_IN, PB12_OUT,
2023 PB11_IN, PB11_OUT,
2024 PB10_IN, PB10_OUT,
2025 PB9_IN, PB9_OUT,
2026 PB8_IN, PB8_OUT,
2027 PB7_IN, PB7_OUT,
2028 PB6_IN, PB6_OUT,
2029 PB5_IN, PB5_OUT,
2030 PB4_IN, PB4_OUT,
2031 PB3_IN, PB3_OUT,
2032 PB2_IN, PB2_OUT,
2033 PB1_IN, PB1_OUT,
2034 0, 0 }
2035 },
2036
2037 { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
2038 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2039
2040 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2041
2042 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2043
2044 PC8MD_000, PC8MD_001, PC8MD_010, PC8MD_011,
2045 PC8MD_100, PC8MD_101, PC8MD_110, PC8MD_111,
2046 0, 0, 0, 0, 0, 0, 0, 0 }
2047 },
2048 { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
2049 PC7MD_000, PC7MD_001, PC7MD_010, PC7MD_011,
2050 PC7MD_100, PC7MD_101, PC7MD_110, PC7MD_111,
2051 0, 0, 0, 0, 0, 0, 0, 0,
2052
2053 PC6MD_000, PC6MD_001, PC6MD_010, PC6MD_011,
2054 PC6MD_100, PC6MD_101, PC6MD_110, PC6MD_111,
2055 0, 0, 0, 0, 0, 0, 0, 0,
2056
2057 PC5MD_000, PC5MD_001, PC5MD_010, PC5MD_011,
2058 PC5MD_100, PC5MD_101, PC5MD_110, PC5MD_111,
2059 0, 0, 0, 0, 0, 0, 0, 0,
2060
2061 PC4MD_00, PC4MD_01, PC4MD_10, PC4MD_11, 0, 0, 0, 0,
2062 0, 0, 0, 0, 0, 0, 0, 0 }
2063 },
2064 { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
2065 PC3MD_00, PC3MD_01, PC3MD_10, PC3MD_11, 0, 0, 0, 0,
2066 0, 0, 0, 0, 0, 0, 0, 0,
2067
2068 PC2MD_00, PC2MD_01, PC2MD_10, PC2MD_11, 0, 0, 0, 0,
2069 0, 0, 0, 0, 0, 0, 0, 0,
2070
2071 PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
2072 0, 0, 0, 0, 0, 0, 0, 0,
2073
2074 PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
2075 0, 0, 0, 0, 0, 0, 0, 0 }
2076 },
2077
2078 { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
2079 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2080 PC8_IN, PC8_OUT,
2081 PC7_IN, PC7_OUT,
2082 PC6_IN, PC6_OUT,
2083 PC5_IN, PC5_OUT,
2084 PC4_IN, PC4_OUT,
2085 PC3_IN, PC3_OUT,
2086 PC2_IN, PC2_OUT,
2087 PC1_IN, PC1_OUT,
2088 PC0_IN, PC0_OUT }
2089 },
2090
2091 { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
2092 PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11, 0, 0, 0, 0,
2093 0, 0, 0, 0, 0, 0, 0, 0,
2094
2095 PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11, 0, 0, 0, 0,
2096 0, 0, 0, 0, 0, 0, 0, 0,
2097
2098 PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11, 0, 0, 0, 0,
2099 0, 0, 0, 0, 0, 0, 0, 0,
2100
2101 PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11, 0, 0, 0, 0,
2102 0, 0, 0, 0, 0, 0, 0, 0 }
2103 },
2104 { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
2105 PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11, 0, 0, 0, 0,
2106 0, 0, 0, 0, 0, 0, 0, 0,
2107
2108 PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11, 0, 0, 0, 0,
2109 0, 0, 0, 0, 0, 0, 0, 0,
2110
2111 PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11, 0, 0, 0, 0,
2112 0, 0, 0, 0, 0, 0, 0, 0,
2113
2114 PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11, 0, 0, 0, 0,
2115 0, 0, 0, 0, 0, 0, 0, 0 }
2116 },
2117 { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
2118 PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11, 0, 0, 0, 0,
2119 0, 0, 0, 0, 0, 0, 0, 0,
2120
2121 PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11, 0, 0, 0, 0,
2122 0, 0, 0, 0, 0, 0, 0, 0,
2123
2124 PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11, 0, 0, 0, 0,
2125 0, 0, 0, 0, 0, 0, 0, 0,
2126
2127 PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11, 0, 0, 0, 0,
2128 0, 0, 0, 0, 0, 0, 0, 0 }
2129 },
2130 { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
2131 PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11, 0, 0, 0, 0,
2132 0, 0, 0, 0, 0, 0, 0, 0,
2133
2134 PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11, 0, 0, 0, 0,
2135 0, 0, 0, 0, 0, 0, 0, 0,
2136
2137 PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11, 0, 0, 0, 0,
2138 0, 0, 0, 0, 0, 0, 0, 0,
2139
2140 PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11, 0, 0, 0, 0,
2141 0, 0, 0, 0, 0, 0, 0, 0 }
2142 },
2143
2144 { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
2145 PD15_IN, PD15_OUT,
2146 PD14_IN, PD14_OUT,
2147 PD13_IN, PD13_OUT,
2148 PD12_IN, PD12_OUT,
2149 PD11_IN, PD11_OUT,
2150 PD10_IN, PD10_OUT,
2151 PD9_IN, PD9_OUT,
2152 PD8_IN, PD8_OUT,
2153 PD7_IN, PD7_OUT,
2154 PD6_IN, PD6_OUT,
2155 PD5_IN, PD5_OUT,
2156 PD4_IN, PD4_OUT,
2157 PD3_IN, PD3_OUT,
2158 PD2_IN, PD2_OUT,
2159 PD1_IN, PD1_OUT,
2160 PD0_IN, PD0_OUT }
2161 },
2162
2163 { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
2164 PE7MD_00, PE7MD_01, PE7MD_10, PE7MD_11, 0, 0, 0, 0,
2165 0, 0, 0, 0, 0, 0, 0, 0,
2166
2167 PE6MD_00, PE6MD_01, PE6MD_10, PE6MD_11, 0, 0, 0, 0,
2168 0, 0, 0, 0, 0, 0, 0, 0,
2169
2170 PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11, 0, 0, 0, 0,
2171 0, 0, 0, 0, 0, 0, 0, 0,
2172
2173 PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11, 0, 0, 0, 0,
2174 0, 0, 0, 0, 0, 0, 0, 0 }
2175 },
2176 { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
2177 PE3MD_000, PE3MD_001, PE3MD_010, PE3MD_011,
2178 PE3MD_100, PE3MD_101, PE3MD_110, PE3MD_111,
2179 0, 0, 0, 0, 0, 0, 0, 0,
2180
2181 PE2MD_000, PE2MD_001, PE2MD_010, PE2MD_011,
2182 PE2MD_100, PE2MD_101, PE2MD_110, PE2MD_111,
2183 0, 0, 0, 0, 0, 0, 0, 0,
2184
2185 PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
2186 PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
2187 0, 0, 0, 0, 0, 0, 0, 0,
2188
2189 PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
2190 0, 0, 0, 0, 0, 0, 0, 0 }
2191 },
2192 { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
2193 0, 0, 0, 0, 0, 0, 0, 0,
2194 0, 0, 0, 0, 0, 0, 0, 0,
2195 PE7_IN, PE7_OUT,
2196 PE6_IN, PE6_OUT,
2197 PE5_IN, PE5_OUT,
2198 PE4_IN, PE4_OUT,
2199 PE3_IN, PE3_OUT,
2200 PE2_IN, PE2_OUT,
2201 PE1_IN, PE1_OUT,
2202 PE0_IN, PE0_OUT }
2203 },
2204
2205 { PINMUX_CFG_REG("PFCR6", 0xfffe38a2, 16, 4) {
2206 PF23MD_000, PF23MD_001, PF23MD_010, PF23MD_011,
2207 PF23MD_100, PF23MD_101, PF23MD_110, PF23MD_111,
2208 0, 0, 0, 0, 0, 0, 0, 0,
2209
2210 PF22MD_000, PF22MD_001, PF22MD_010, PF22MD_011,
2211 PF22MD_100, PF22MD_101, PF22MD_110, PF22MD_111,
2212 0, 0, 0, 0, 0, 0, 0, 0,
2213
2214 PF21MD_000, PF21MD_001, PF21MD_010, PF21MD_011,
2215 PF21MD_100, PF21MD_101, PF21MD_110, PF21MD_111,
2216 0, 0, 0, 0, 0, 0, 0, 0,
2217
2218 PF20MD_000, PF20MD_001, PF20MD_010, PF20MD_011,
2219 PF20MD_100, PF20MD_101, PF20MD_110, PF20MD_111,
2220 0, 0, 0, 0, 0, 0, 0, 0 }
2221 },
2222 { PINMUX_CFG_REG("PFCR5", 0xfffe38a4, 16, 4) {
2223 PF19MD_000, PF19MD_001, PF19MD_010, PF19MD_011,
2224 PF19MD_100, PF19MD_101, PF19MD_110, PF19MD_111,
2225 0, 0, 0, 0, 0, 0, 0, 0,
2226
2227 PF18MD_000, PF18MD_001, PF18MD_010, PF18MD_011,
2228 PF18MD_100, PF18MD_101, PF18MD_110, PF18MD_111,
2229 0, 0, 0, 0, 0, 0, 0, 0,
2230
2231 PF17MD_000, PF17MD_001, PF17MD_010, PF17MD_011,
2232 PF17MD_100, PF17MD_101, PF17MD_110, PF17MD_111,
2233 0, 0, 0, 0, 0, 0, 0, 0,
2234
2235 PF16MD_000, PF16MD_001, PF16MD_010, PF16MD_011,
2236 PF16MD_100, PF16MD_101, PF16MD_110, PF16MD_111,
2237 0, 0, 0, 0, 0, 0, 0, 0 }
2238 },
2239 { PINMUX_CFG_REG("PFCR4", 0xfffe38a6, 16, 4) {
2240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2241
2242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2243
2244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2245
2246 PF15MD_000, PF15MD_001, PF15MD_010, PF15MD_011,
2247 PF15MD_100, PF15MD_101, PF15MD_110, PF15MD_111,
2248 0, 0, 0, 0, 0, 0, 0, 0 }
2249 },
2250 { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
2251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2252
2253 PF14MD_000, PF14MD_001, PF14MD_010, PF14MD_011,
2254 PF14MD_100, PF14MD_101, PF14MD_110, PF14MD_111,
2255 0, 0, 0, 0, 0, 0, 0, 0,
2256
2257 PF13MD_000, PF13MD_001, PF13MD_010, PF13MD_011,
2258 PF13MD_100, PF13MD_101, PF13MD_110, PF13MD_111,
2259 0, 0, 0, 0, 0, 0, 0, 0,
2260
2261 PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
2262 PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
2263 0, 0, 0, 0, 0, 0, 0, 0 }
2264 },
2265 { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
2266 PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
2267 PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
2268 0, 0, 0, 0, 0, 0, 0, 0,
2269
2270 PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
2271 PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
2272 0, 0, 0, 0, 0, 0, 0, 0,
2273
2274 PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
2275 PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
2276 0, 0, 0, 0, 0, 0, 0, 0,
2277
2278 PF8MD_000, PF8MD_001, PF8MD_010, PF8MD_011,
2279 PF8MD_100, PF8MD_101, PF8MD_110, PF8MD_111,
2280 0, 0, 0, 0, 0, 0, 0, 0 }
2281 },
2282 { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
2283 PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
2284 PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
2285 0, 0, 0, 0, 0, 0, 0, 0,
2286
2287 PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
2288 PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
2289 0, 0, 0, 0, 0, 0, 0, 0,
2290
2291 PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
2292 PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
2293 0, 0, 0, 0, 0, 0, 0, 0,
2294
2295 PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
2296 PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
2297 0, 0, 0, 0, 0, 0, 0, 0 }
2298 },
2299 { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
2300 PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
2301 PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
2302 0, 0, 0, 0, 0, 0, 0, 0,
2303
2304 PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
2305 PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
2306 0, 0, 0, 0, 0, 0, 0, 0,
2307
2308 PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
2309 PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
2310 0, 0, 0, 0, 0, 0, 0, 0,
2311
2312 PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
2313 PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
2314 0, 0, 0, 0, 0, 0, 0, 0 }
2315 },
2316
2317 { PINMUX_CFG_REG("PFIOR1", 0xfffe38b0, 16, 1) {
2318 0, 0, 0, 0, 0, 0, 0, 0,
2319 0, 0, 0, 0, 0, 0, 0, 0,
2320 PF23_IN, PF23_OUT,
2321 PF22_IN, PF22_OUT,
2322 PF21_IN, PF21_OUT,
2323 PF20_IN, PF20_OUT,
2324 PF19_IN, PF19_OUT,
2325 PF18_IN, PF18_OUT,
2326 PF17_IN, PF17_OUT,
2327 PF16_IN, PF16_OUT }
2328 },
2329 { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
2330 PF15_IN, PF15_OUT,
2331 PF14_IN, PF14_OUT,
2332 PF13_IN, PF13_OUT,
2333 PF12_IN, PF12_OUT,
2334 PF11_IN, PF11_OUT,
2335 PF10_IN, PF10_OUT,
2336 PF9_IN, PF9_OUT,
2337 PF8_IN, PF8_OUT,
2338 PF7_IN, PF7_OUT,
2339 PF6_IN, PF6_OUT,
2340 PF5_IN, PF5_OUT,
2341 PF4_IN, PF4_OUT,
2342 PF3_IN, PF3_OUT,
2343 PF2_IN, PF2_OUT,
2344 PF1_IN, PF1_OUT,
2345 PF0_IN, PF0_OUT }
2346 },
2347
2348 { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
2349 PG27MD_00, PG27MD_01, PG27MD_10, PG27MD_11, 0, 0, 0, 0,
2350 0, 0, 0, 0, 0, 0, 0, 0,
2351
2352 PG26MD_00, PG26MD_01, PG26MD_10, PG26MD_11, 0, 0, 0, 0,
2353 0, 0, 0, 0, 0, 0, 0, 0,
2354
2355 PG25MD_00, PG25MD_01, PG25MD_10, PG25MD_11, 0, 0, 0, 0,
2356 0, 0, 0, 0, 0, 0, 0, 0,
2357
2358 PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
2359 0, 0, 0, 0, 0, 0, 0, 0 }
2360 },
2361 { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
2362 PG23MD_000, PG23MD_001, PG23MD_010, PG23MD_011,
2363 PG23MD_100, PG23MD_101, PG23MD_110, PG23MD_111,
2364 0, 0, 0, 0, 0, 0, 0, 0,
2365
2366 PG22MD_000, PG22MD_001, PG22MD_010, PG22MD_011,
2367 PG22MD_100, PG22MD_101, PG22MD_110, PG22MD_111,
2368 0, 0, 0, 0, 0, 0, 0, 0,
2369
2370 PG21MD_000, PG21MD_001, PG21MD_010, PG21MD_011,
2371 PG21MD_100, PG21MD_101, PG21MD_110, PG21MD_111,
2372 0, 0, 0, 0, 0, 0, 0, 0,
2373
2374 PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
2375 PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
2376 0, 0, 0, 0, 0, 0, 0, 0 }
2377 },
2378 { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
2379 PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
2380 PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
2381 0, 0, 0, 0, 0, 0, 0, 0,
2382
2383 PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
2384 PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
2385 0, 0, 0, 0, 0, 0, 0, 0,
2386
2387 PG17MD_00, PG17MD_01, PG17MD_10, PG17MD_11, 0, 0, 0, 0,
2388 0, 0, 0, 0, 0, 0, 0, 0,
2389
2390 PG16MD_00, PG16MD_01, PG16MD_10, PG16MD_11, 0, 0, 0, 0,
2391 0, 0, 0, 0, 0, 0, 0, 0 }
2392 },
2393 { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
2394 PG15MD_00, PG15MD_01, PG15MD_10, PG15MD_11, 0, 0, 0, 0,
2395 0, 0, 0, 0, 0, 0, 0, 0,
2396
2397 PG14MD_00, PG14MD_01, PG14MD_10, PG14MD_11, 0, 0, 0, 0,
2398 0, 0, 0, 0, 0, 0, 0, 0,
2399
2400 PG13MD_00, PG13MD_01, PG13MD_10, PG13MD_11, 0, 0, 0, 0,
2401 0, 0, 0, 0, 0, 0, 0, 0,
2402
2403 PG12MD_00, PG12MD_01, PG12MD_10, PG12MD_11, 0, 0, 0, 0,
2404 0, 0, 0, 0, 0, 0, 0, 0 }
2405 },
2406 { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
2407 PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
2408 PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
2409 0, 0, 0, 0, 0, 0, 0, 0,
2410
2411 PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
2412 PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
2413 0, 0, 0, 0, 0, 0, 0, 0,
2414
2415 PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
2416 PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
2417 0, 0, 0, 0, 0, 0, 0, 0,
2418
2419 PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
2420 PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
2421 0, 0, 0, 0, 0, 0, 0, 0 }
2422 },
2423
2424 { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
2425 PG7MD_000, PG7MD_001, PG7MD_010, PG7MD_011,
2426 PG7MD_100, PG7MD_101, PG7MD_110, PG7MD_111,
2427 0, 0, 0, 0, 0, 0, 0, 0,
2428
2429 PG6MD_000, PG6MD_001, PG6MD_010, PG6MD_011,
2430 PG6MD_100, PG6MD_101, PG6MD_110, PG6MD_111,
2431 0, 0, 0, 0, 0, 0, 0, 0,
2432
2433 PG5MD_000, PG5MD_001, PG5MD_010, PG5MD_011,
2434 PG5MD_100, PG5MD_101, PG5MD_110, PG5MD_111,
2435 0, 0, 0, 0, 0, 0, 0, 0,
2436
2437 PG4MD_000, PG4MD_001, PG4MD_010, PG4MD_011,
2438 PG4MD_100, PG4MD_101, PG4MD_110, PG4MD_111,
2439 0, 0, 0, 0, 0, 0, 0, 0 }
2440 },
2441 { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
2442 PG3MD_000, PG3MD_001, PG3MD_010, PG3MD_011,
2443 PG3MD_100, PG3MD_101, PG3MD_110, PG3MD_111,
2444 0, 0, 0, 0, 0, 0, 0, 0,
2445
2446 PG2MD_000, PG2MD_001, PG2MD_010, PG2MD_011,
2447 PG2MD_100, PG2MD_101, PG2MD_110, PG2MD_111,
2448 0, 0, 0, 0, 0, 0, 0, 0,
2449
2450 PG1MD_000, PG1MD_001, PG1MD_010, PG1MD_011,
2451 PG1MD_100, PG1MD_101, PG1MD_110, PG1MD_111,
2452 0, 0, 0, 0, 0, 0, 0, 0,
2453
2454 PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
2455 PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
2456 0, 0, 0, 0, 0, 0, 0, 0 }
2457 },
2458
2459 { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
2460 0, 0, 0, 0, 0, 0, 0, 0,
2461 PG27_IN, PG27_OUT,
2462 PG26_IN, PG26_OUT,
2463 PG25_IN, PG25_OUT,
2464 PG24_IN, PG24_OUT,
2465 PG23_IN, PG23_OUT,
2466 PG22_IN, PG22_OUT,
2467 PG21_IN, PG21_OUT,
2468 PG20_IN, PG20_OUT,
2469 PG19_IN, PG19_OUT,
2470 PG18_IN, PG18_OUT,
2471 PG17_IN, PG17_OUT,
2472 PG16_IN, PG16_OUT }
2473 },
2474 { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
2475 PG15_IN, PG15_OUT,
2476 PG14_IN, PG14_OUT,
2477 PG13_IN, PG13_OUT,
2478 PG12_IN, PG12_OUT,
2479 PG11_IN, PG11_OUT,
2480 PG10_IN, PG10_OUT,
2481 PG9_IN, PG9_OUT,
2482 PG8_IN, PG8_OUT,
2483 PG7_IN, PG7_OUT,
2484 PG6_IN, PG6_OUT,
2485 PG5_IN, PG5_OUT,
2486 PG4_IN, PG4_OUT,
2487 PG3_IN, PG3_OUT,
2488 PG2_IN, PG2_OUT,
2489 PG1_IN, PG1_OUT,
2490 PG0_IN, PG0_OUT }
2491 },
2492
2493 { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
2494 PH7MD_00, PH7MD_01, PH7MD_10, PH7MD_11, 0, 0, 0, 0,
2495 0, 0, 0, 0, 0, 0, 0, 0,
2496
2497 PH6MD_00, PH6MD_01, PH6MD_10, PH6MD_11, 0, 0, 0, 0,
2498 0, 0, 0, 0, 0, 0, 0, 0,
2499
2500 PH5MD_00, PH5MD_01, PH5MD_10, PH5MD_11, 0, 0, 0, 0,
2501 0, 0, 0, 0, 0, 0, 0, 0,
2502
2503 PH4MD_00, PH4MD_01, PH4MD_10, PH4MD_11, 0, 0, 0, 0,
2504 0, 0, 0, 0, 0, 0, 0, 0 }
2505 },
2506
2507 { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
2508 PH3MD_00, PH3MD_01, PH3MD_10, PH3MD_11, 0, 0, 0, 0,
2509 0, 0, 0, 0, 0, 0, 0, 0,
2510
2511 PH2MD_00, PH2MD_01, PH2MD_10, PH2MD_11, 0, 0, 0, 0,
2512 0, 0, 0, 0, 0, 0, 0, 0,
2513
2514 PH1MD_00, PH1MD_01, PH1MD_10, PH1MD_11, 0, 0, 0, 0,
2515 0, 0, 0, 0, 0, 0, 0, 0,
2516
2517 PH0MD_00, PH0MD_01, PH0MD_10, PH0MD_11, 0, 0, 0, 0,
2518 0, 0, 0, 0, 0, 0, 0, 0 }
2519 },
2520
2521 { PINMUX_CFG_REG("PJCR7", 0xfffe3900, 16, 4) {
2522 PJ31MD_0, PJ31MD_1, 0, 0, 0, 0, 0, 0,
2523 0, 0, 0, 0, 0, 0, 0, 0,
2524
2525 PJ30MD_000, PJ30MD_001, PJ30MD_010, PJ30MD_011,
2526 PJ30MD_100, PJ30MD_101, PJ30MD_110, PJ30MD_111,
2527 0, 0, 0, 0, 0, 0, 0, 0,
2528
2529 PJ29MD_000, PJ29MD_001, PJ29MD_010, PJ29MD_011,
2530 PJ29MD_100, PJ29MD_101, PJ29MD_110, PJ29MD_111,
2531 0, 0, 0, 0, 0, 0, 0, 0,
2532
2533 PJ28MD_000, PJ28MD_001, PJ28MD_010, PJ28MD_011,
2534 PJ28MD_100, PJ28MD_101, PJ28MD_110, PJ28MD_111,
2535 0, 0, 0, 0, 0, 0, 0, 0 }
2536 },
2537 { PINMUX_CFG_REG("PJCR6", 0xfffe3902, 16, 4) {
2538 PJ27MD_000, PJ27MD_001, PJ27MD_010, PJ27MD_011,
2539 PJ27MD_100, PJ27MD_101, PJ27MD_110, PJ27MD_111,
2540 0, 0, 0, 0, 0, 0, 0, 0,
2541
2542 PJ26MD_000, PJ26MD_001, PJ26MD_010, PJ26MD_011,
2543 PJ26MD_100, PJ26MD_101, PJ26MD_110, PJ26MD_111,
2544 0, 0, 0, 0, 0, 0, 0, 0,
2545
2546 PJ25MD_000, PJ25MD_001, PJ25MD_010, PJ25MD_011,
2547 PJ25MD_100, PJ25MD_101, PJ25MD_110, PJ25MD_111,
2548 0, 0, 0, 0, 0, 0, 0, 0,
2549
2550 PJ24MD_000, PJ24MD_001, PJ24MD_010, PJ24MD_011,
2551 PJ24MD_100, PJ24MD_101, PJ24MD_110, PJ24MD_111,
2552 0, 0, 0, 0, 0, 0, 0, 0 }
2553 },
2554 { PINMUX_CFG_REG("PJCR5", 0xfffe3904, 16, 4) {
2555 PJ23MD_000, PJ23MD_001, PJ23MD_010, PJ23MD_011,
2556 PJ23MD_100, PJ23MD_101, PJ23MD_110, PJ23MD_111,
2557 0, 0, 0, 0, 0, 0, 0, 0,
2558
2559 PJ22MD_000, PJ22MD_001, PJ22MD_010, PJ22MD_011,
2560 PJ22MD_100, PJ22MD_101, PJ22MD_110, PJ22MD_111,
2561 0, 0, 0, 0, 0, 0, 0, 0,
2562
2563 PJ21MD_000, PJ21MD_001, PJ21MD_010, PJ21MD_011,
2564 PJ21MD_100, PJ21MD_101, PJ21MD_110, PJ21MD_111,
2565 0, 0, 0, 0, 0, 0, 0, 0,
2566
2567 PJ20MD_000, PJ20MD_001, PJ20MD_010, PJ20MD_011,
2568 PJ20MD_100, PJ20MD_101, PJ20MD_110, PJ20MD_111,
2569 0, 0, 0, 0, 0, 0, 0, 0 }
2570 },
2571 { PINMUX_CFG_REG("PJCR4", 0xfffe3906, 16, 4) {
2572 PJ19MD_000, PJ19MD_001, PJ19MD_010, PJ19MD_011,
2573 PJ19MD_100, PJ19MD_101, PJ19MD_110, PJ19MD_111,
2574 0, 0, 0, 0, 0, 0, 0, 0,
2575
2576 PJ18MD_000, PJ18MD_001, PJ18MD_010, PJ18MD_011,
2577 PJ18MD_100, PJ18MD_101, PJ18MD_110, PJ18MD_111,
2578 0, 0, 0, 0, 0, 0, 0, 0,
2579
2580 PJ17MD_000, PJ17MD_001, PJ17MD_010, PJ17MD_011,
2581 PJ17MD_100, PJ17MD_101, PJ17MD_110, PJ17MD_111,
2582 0, 0, 0, 0, 0, 0, 0, 0,
2583
2584 PJ16MD_000, PJ16MD_001, PJ16MD_010, PJ16MD_011,
2585 PJ16MD_100, PJ16MD_101, PJ16MD_110, PJ16MD_111,
2586 0, 0, 0, 0, 0, 0, 0, 0 }
2587 },
2588 { PINMUX_CFG_REG("PJCR3", 0xfffe3908, 16, 4) {
2589 PJ15MD_000, PJ15MD_001, PJ15MD_010, PJ15MD_011,
2590 PJ15MD_100, PJ15MD_101, PJ15MD_110, PJ15MD_111,
2591 0, 0, 0, 0, 0, 0, 0, 0,
2592
2593 PJ14MD_000, PJ14MD_001, PJ14MD_010, PJ14MD_011,
2594 PJ14MD_100, PJ14MD_101, PJ14MD_110, PJ14MD_111,
2595 0, 0, 0, 0, 0, 0, 0, 0,
2596
2597 PJ13MD_000, PJ13MD_001, PJ13MD_010, PJ13MD_011,
2598 PJ13MD_100, PJ13MD_101, PJ13MD_110, PJ13MD_111,
2599 0, 0, 0, 0, 0, 0, 0, 0,
2600
2601 PJ12MD_000, PJ12MD_001, PJ12MD_010, PJ12MD_011,
2602 PJ12MD_100, PJ12MD_101, PJ12MD_110, PJ12MD_111,
2603 0, 0, 0, 0, 0, 0, 0, 0 }
2604 },
2605 { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
2606 PJ11MD_000, PJ11MD_001, PJ11MD_010, PJ11MD_011,
2607 PJ11MD_100, PJ11MD_101, PJ11MD_110, PJ11MD_111,
2608 0, 0, 0, 0, 0, 0, 0, 0,
2609
2610 PJ10MD_000, PJ10MD_001, PJ10MD_010, PJ10MD_011,
2611 PJ10MD_100, PJ10MD_101, PJ10MD_110, PJ10MD_111,
2612 0, 0, 0, 0, 0, 0, 0, 0,
2613
2614 PJ9MD_000, PJ9MD_001, PJ9MD_010, PJ9MD_011,
2615 PJ9MD_100, PJ9MD_101, PJ9MD_110, PJ9MD_111,
2616 0, 0, 0, 0, 0, 0, 0, 0,
2617
2618 PJ8MD_000, PJ8MD_001, PJ8MD_010, PJ8MD_011,
2619 PJ8MD_100, PJ8MD_101, PJ8MD_110, PJ8MD_111,
2620 0, 0, 0, 0, 0, 0, 0, 0 }
2621 },
2622 { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
2623 PJ7MD_000, PJ7MD_001, PJ7MD_010, PJ7MD_011,
2624 PJ7MD_100, PJ7MD_101, PJ7MD_110, PJ7MD_111,
2625 0, 0, 0, 0, 0, 0, 0, 0,
2626
2627 PJ6MD_000, PJ6MD_001, PJ6MD_010, PJ6MD_011,
2628 PJ6MD_100, PJ6MD_101, PJ6MD_110, PJ6MD_111,
2629 0, 0, 0, 0, 0, 0, 0, 0,
2630
2631 PJ5MD_000, PJ5MD_001, PJ5MD_010, PJ5MD_011,
2632 PJ5MD_100, PJ5MD_101, PJ5MD_110, PJ5MD_111,
2633 0, 0, 0, 0, 0, 0, 0, 0,
2634
2635 PJ4MD_000, PJ4MD_001, PJ4MD_010, PJ4MD_011,
2636 PJ4MD_100, PJ4MD_101, PJ4MD_110, PJ4MD_111,
2637 0, 0, 0, 0, 0, 0, 0, 0 }
2638 },
2639 { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
2640 PJ3MD_000, PJ3MD_001, PJ3MD_010, PJ3MD_011,
2641 PJ3MD_100, PJ3MD_101, PJ3MD_110, PJ3MD_111,
2642 0, 0, 0, 0, 0, 0, 0, 0,
2643
2644 PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
2645 PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
2646 0, 0, 0, 0, 0, 0, 0, 0,
2647
2648 PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
2649 PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
2650 0, 0, 0, 0, 0, 0, 0, 0,
2651
2652 PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
2653 PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
2654 0, 0, 0, 0, 0, 0, 0, 0 }
2655 },
2656
2657 { PINMUX_CFG_REG("PJIOR1", 0xfffe3910, 16, 1) {
2658 PJ31_IN, PJ31_OUT,
2659 PJ30_IN, PJ30_OUT,
2660 PJ29_IN, PJ29_OUT,
2661 PJ28_IN, PJ28_OUT,
2662 PJ27_IN, PJ27_OUT,
2663 PJ26_IN, PJ26_OUT,
2664 PJ25_IN, PJ25_OUT,
2665 PJ24_IN, PJ24_OUT,
2666 PJ23_IN, PJ23_OUT,
2667 PJ22_IN, PJ22_OUT,
2668 PJ21_IN, PJ21_OUT,
2669 PJ20_IN, PJ20_OUT,
2670 PJ19_IN, PJ19_OUT,
2671 PJ18_IN, PJ18_OUT,
2672 PJ17_IN, PJ17_OUT,
2673 PJ16_IN, PJ16_OUT }
2674 },
2675 { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
2676 PJ15_IN, PJ15_OUT,
2677 PJ14_IN, PJ14_OUT,
2678 PJ13_IN, PJ13_OUT,
2679 PJ12_IN, PJ12_OUT,
2680 PJ11_IN, PJ11_OUT,
2681 PJ10_IN, PJ10_OUT,
2682 PJ9_IN, PJ9_OUT,
2683 PJ8_IN, PJ8_OUT,
2684 PJ7_IN, PJ7_OUT,
2685 PJ6_IN, PJ6_OUT,
2686 PJ5_IN, PJ5_OUT,
2687 PJ4_IN, PJ4_OUT,
2688 PJ3_IN, PJ3_OUT,
2689 PJ2_IN, PJ2_OUT,
2690 PJ1_IN, PJ1_OUT,
2691 PJ0_IN, PJ0_OUT }
2692 },
2693
2694 {}
2695};
2696
2697static struct pinmux_data_reg pinmux_data_regs[] = {
2698 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
2699 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2700 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
2701 },
2702
2703 { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
2704 0, 0, 0, 0, 0, 0, 0, 0,
2705 0, PB22_DATA, PB21_DATA, PB20_DATA,
2706 PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
2707 },
2708 { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
2709 PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
2710 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
2711 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
2712 PB3_DATA, PB2_DATA, PB1_DATA, 0 }
2713 },
2714
2715 { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
2716 0, 0, 0, 0,
2717 0, 0, 0, PC8_DATA,
2718 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
2719 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
2720 },
2721
2722 { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
2723 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
2724 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
2725 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
2726 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
2727 },
2728
2729 { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
2730 0, 0, 0, 0, 0, 0, 0, 0,
2731 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
2732 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
2733 },
2734
2735 { PINMUX_DATA_REG("PFDR1", 0xfffe38b4, 16) {
2736 0, 0, 0, 0, 0, 0, 0, 0,
2737 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
2738 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
2739 },
2740 { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
2741 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
2742 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
2743 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
2744 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
2745 },
2746
2747 { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
2748 0, 0, 0, 0,
2749 PG27_DATA, PG26_DATA, PG25_DATA, PG24_DATA,
2750 PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
2751 PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
2752 },
2753 { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
2754 PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
2755 PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
2756 PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
2757 PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
2758 },
2759
2760 { PINMUX_DATA_REG("PJDR1", 0xfffe3914, 16) {
2761 PJ31_DATA, PJ30_DATA, PJ29_DATA, PJ28_DATA,
2762 PJ27_DATA, PJ26_DATA, PJ25_DATA, PJ24_DATA,
2763 PJ23_DATA, PJ22_DATA, PJ21_DATA, PJ20_DATA,
2764 PJ19_DATA, PJ18_DATA, PJ17_DATA, PJ16_DATA }
2765 },
2766 { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
2767 PJ15_DATA, PJ14_DATA, PJ13_DATA, PJ12_DATA,
2768 PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
2769 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
2770 PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
2771 },
2772
2773 { }
2774};
2775
2776static struct pinmux_info sh7269_pinmux_info = {
2777 .name = "sh7269_pfc",
2778 .reserved_id = PINMUX_RESERVED,
2779 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2780 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2781 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2782 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2783 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2784
2785 .first_gpio = GPIO_PA1,
2786 .last_gpio = GPIO_FN_LCD_M_DISP,
2787
2788 .gpios = pinmux_gpios,
2789 .cfg_regs = pinmux_config_regs,
2790 .data_regs = pinmux_data_regs,
2791
2792 .gpio_data = pinmux_data,
2793 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2794};
2795
2796static int __init plat_pinmux_setup(void)
2797{
2798 return register_pinmux(&sh7269_pinmux_info);
2799}
2800arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 48e97a2a0c8d..5170b6aa4129 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -29,6 +29,12 @@ void __cpuinit cpu_probe(void)
29#elif defined(CONFIG_CPU_SUBTYPE_SH7263) 29#elif defined(CONFIG_CPU_SUBTYPE_SH7263)
30 boot_cpu_data.type = CPU_SH7263; 30 boot_cpu_data.type = CPU_SH7263;
31 boot_cpu_data.flags |= CPU_HAS_FPU; 31 boot_cpu_data.flags |= CPU_HAS_FPU;
32#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
33 boot_cpu_data.type = CPU_SH7264;
34 boot_cpu_data.flags |= CPU_HAS_FPU;
35#elif defined(CONFIG_CPU_SUBTYPE_SH7269)
36 boot_cpu_data.type = CPU_SH7269;
37 boot_cpu_data.flags |= CPU_HAS_FPU;
32#elif defined(CONFIG_CPU_SUBTYPE_SH7206) 38#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
33 boot_cpu_data.type = CPU_SH7206; 39 boot_cpu_data.type = CPU_SH7206;
34 boot_cpu_data.flags |= CPU_HAS_DSP; 40 boot_cpu_data.flags |= CPU_HAS_DSP;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 949bf2bac28c..f7f1cf2af302 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -204,7 +204,7 @@ static struct plat_sci_port scif0_platform_data = {
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2, 205 .scbrr_algo_id = SCBRR_ALGO_2,
206 .type = PORT_SCIF, 206 .type = PORT_SCIF,
207 .irqs = { 220, 220, 220, 220 }, 207 .irqs = SCIx_IRQ_MUXED(220),
208}; 208};
209 209
210static struct platform_device scif0_device = { 210static struct platform_device scif0_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 9df558dcdb86..7b84785b8962 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -183,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = {
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2, 184 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 185 .type = PORT_SCIF,
186 .irqs = { 180, 180, 180, 180 } 186 .irqs = SCIx_IRQ_MUXED(180),
187}; 187};
188 188
189static struct platform_device scif0_device = { 189static struct platform_device scif0_device = {
@@ -200,7 +200,7 @@ static struct plat_sci_port scif1_platform_data = {
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2, 201 .scbrr_algo_id = SCBRR_ALGO_2,
202 .type = PORT_SCIF, 202 .type = PORT_SCIF,
203 .irqs = { 184, 184, 184, 184 } 203 .irqs = SCIx_IRQ_MUXED(184),
204}; 204};
205 205
206static struct platform_device scif1_device = { 206static struct platform_device scif1_device = {
@@ -217,7 +217,7 @@ static struct plat_sci_port scif2_platform_data = {
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2, 218 .scbrr_algo_id = SCBRR_ALGO_2,
219 .type = PORT_SCIF, 219 .type = PORT_SCIF,
220 .irqs = { 188, 188, 188, 188 } 220 .irqs = SCIx_IRQ_MUXED(188),
221}; 221};
222 222
223static struct platform_device scif2_device = { 223static struct platform_device scif2_device = {
@@ -234,7 +234,7 @@ static struct plat_sci_port scif3_platform_data = {
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2, 235 .scbrr_algo_id = SCBRR_ALGO_2,
236 .type = PORT_SCIF, 236 .type = PORT_SCIF,
237 .irqs = { 192, 192, 192, 192 } 237 .irqs = SCIx_IRQ_MUXED(192),
238}; 238};
239 239
240static struct platform_device scif3_device = { 240static struct platform_device scif3_device = {
@@ -251,7 +251,7 @@ static struct plat_sci_port scif4_platform_data = {
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2, 252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 253 .type = PORT_SCIF,
254 .irqs = { 196, 196, 196, 196 } 254 .irqs = SCIx_IRQ_MUXED(196),
255}; 255};
256 256
257static struct platform_device scif4_device = { 257static struct platform_device scif4_device = {
@@ -268,7 +268,7 @@ static struct plat_sci_port scif5_platform_data = {
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2, 269 .scbrr_algo_id = SCBRR_ALGO_2,
270 .type = PORT_SCIF, 270 .type = PORT_SCIF,
271 .irqs = { 200, 200, 200, 200 } 271 .irqs = SCIx_IRQ_MUXED(200),
272}; 272};
273 273
274static struct platform_device scif5_device = { 274static struct platform_device scif5_device = {
@@ -285,7 +285,7 @@ static struct plat_sci_port scif6_platform_data = {
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2, 286 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 287 .type = PORT_SCIF,
288 .irqs = { 204, 204, 204, 204 } 288 .irqs = SCIx_IRQ_MUXED(204),
289}; 289};
290 290
291static struct platform_device scif6_device = { 291static struct platform_device scif6_device = {
@@ -302,7 +302,7 @@ static struct plat_sci_port scif7_platform_data = {
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2, 303 .scbrr_algo_id = SCBRR_ALGO_2,
304 .type = PORT_SCIF, 304 .type = PORT_SCIF,
305 .irqs = { 208, 208, 208, 208 } 305 .irqs = SCIx_IRQ_MUXED(208),
306}; 306};
307 307
308static struct platform_device scif7_device = { 308static struct platform_device scif7_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 0bd744f9a3b7..bfc33f6a28c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -180,7 +180,7 @@ static struct plat_sci_port scif0_platform_data = {
180 SCSCR_REIE, 180 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2, 181 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF, 182 .type = PORT_SCIF,
183 .irqs = { 192, 192, 192, 192 }, 183 .irqs = SCIx_IRQ_MUXED(192),
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185}; 185};
186 186
@@ -199,7 +199,7 @@ static struct plat_sci_port scif1_platform_data = {
199 SCSCR_REIE, 199 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2, 200 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF, 201 .type = PORT_SCIF,
202 .irqs = { 196, 196, 196, 196 }, 202 .irqs = SCIx_IRQ_MUXED(196),
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204}; 204};
205 205
@@ -218,7 +218,7 @@ static struct plat_sci_port scif2_platform_data = {
218 SCSCR_REIE, 218 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2, 219 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 220 .type = PORT_SCIF,
221 .irqs = { 200, 200, 200, 200 }, 221 .irqs = SCIx_IRQ_MUXED(200),
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223}; 223};
224 224
@@ -237,7 +237,7 @@ static struct plat_sci_port scif3_platform_data = {
237 SCSCR_REIE, 237 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2, 238 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF, 239 .type = PORT_SCIF,
240 .irqs = { 204, 204, 204, 204 }, 240 .irqs = SCIx_IRQ_MUXED(204),
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242}; 242};
243 243
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 5d14f849aea3..a5010741de85 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -139,7 +139,7 @@ static struct plat_sci_port scif0_platform_data = {
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2, 140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 141 .type = PORT_SCIF,
142 .irqs = { 240, 240, 240, 240 }, 142 .irqs = SCIx_IRQ_MUXED(240),
143}; 143};
144 144
145static struct platform_device scif0_device = { 145static struct platform_device scif0_device = {
@@ -156,7 +156,7 @@ static struct plat_sci_port scif1_platform_data = {
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2, 157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 158 .type = PORT_SCIF,
159 .irqs = { 244, 244, 244, 244 }, 159 .irqs = SCIx_IRQ_MUXED(244),
160}; 160};
161 161
162static struct platform_device scif1_device = { 162static struct platform_device scif1_device = {
@@ -173,7 +173,7 @@ static struct plat_sci_port scif2_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2, 174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 248, 248, 248, 248 }, 176 .irqs = SCIx_IRQ_MUXED(248),
177}; 177};
178 178
179static struct platform_device scif2_device = { 179static struct platform_device scif2_device = {
@@ -190,7 +190,7 @@ static struct plat_sci_port scif3_platform_data = {
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2, 191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF, 192 .type = PORT_SCIF,
193 .irqs = { 252, 252, 252, 252 }, 193 .irqs = SCIx_IRQ_MUXED(252),
194}; 194};
195 195
196static struct platform_device scif3_device = { 196static struct platform_device scif3_device = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
new file mode 100644
index 000000000000..ce5c1b5aebfa
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -0,0 +1,606 @@
1/*
2 * SH7264 Setup
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/usb/r8a66597.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
17
18enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24
25 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
26 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
27 USB, VDC3, CMT0, CMT1, BSC, WDT,
28 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
30 PWMT1, PWMT2, ADC_ADI,
31 SSIF0, SSII1, SSII2, SSII3,
32 RSPDIF,
33 IIC30, IIC31, IIC32, IIC33,
34 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
35 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
36 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
37 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
38 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
39 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
40 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
41 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
42 SIO_FIFO, RSPIC0, RSPIC1,
43 RCAN0, RCAN1, IEBC, CD_ROMD,
44 NFMC, SDHI, RTC,
45 SRCC0, SRCC1, DCOMU, OFFI, IFEI,
46
47 /* interrupt groups */
48 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
49};
50
51static struct intc_vect vectors[] __initdata = {
52 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
53 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
54 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
55 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
56
57 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
58 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
59 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
60 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
61
62 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
63 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
64 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
65 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
66 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
67 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
68 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
69 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
70 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
71 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
72 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
73 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
74 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
75 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
76 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
77 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
78
79 INTC_IRQ(USB, 170),
80 INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
81 INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
82 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
83 INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
84
85 INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
86 INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
87 INTC_IRQ(MTU0_VEF, 183),
88 INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
89 INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
90 INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
91 INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
92 INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
93 INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
94 INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
95 INTC_IRQ(MTU3_TCI3V, 198),
96 INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
97 INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
98 INTC_IRQ(MTU4_TCI4V, 203),
99
100 INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
101
102 INTC_IRQ(ADC_ADI, 206),
103
104 INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
105 INTC_IRQ(SSIF0, 209),
106 INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
107 INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
108 INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
109
110 INTC_IRQ(RSPDIF, 216),
111
112 INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
113 INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
114 INTC_IRQ(IIC30, 221),
115 INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
116 INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
117 INTC_IRQ(IIC31, 226),
118 INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
119 INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
120 INTC_IRQ(IIC32, 231),
121
122 INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
123 INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
124 INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
125 INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
126 INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
127 INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
128 INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
129 INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
130 INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
131 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
132 INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
133 INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
134 INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
135 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
136 INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
137 INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
138
139 INTC_IRQ(SIO_FIFO, 264),
140
141 INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
142 INTC_IRQ(RSPIC0, 267),
143 INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
144 INTC_IRQ(RSPIC1, 270),
145
146 INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
147 INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
148 INTC_IRQ(RCAN0, 275),
149 INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
150 INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
151 INTC_IRQ(RCAN1, 280),
152
153 INTC_IRQ(IEBC, 281),
154
155 INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
156 INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
157 INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
158
159 INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
160 INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
161
162 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
163 INTC_IRQ(SDHI, 294),
164
165 INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
166 INTC_IRQ(RTC, 298),
167
168 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
169 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
170 INTC_IRQ(SRCC0, 303),
171 INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
172 INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
173 INTC_IRQ(SRCC1, 308),
174
175 INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
176 INTC_IRQ(DCOMU, 312),
177};
178
179static struct intc_group groups[] __initdata = {
180 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
181 PINT4, PINT5, PINT6, PINT7),
182 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
183 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
184 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
185 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
186 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
187 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
188 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
189 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
190};
191
192static struct intc_prio_reg prio_registers[] __initdata = {
193 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
194 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
195 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
196 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
197 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
198 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
199 DMAC10, DMAC11 } },
200 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
201 DMAC14, DMAC15 } },
202 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
203 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
204 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
205 MTU2_AB, MTU2_VU } },
206 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
207 MTU4_ABCD, MTU4_TCI4V } },
208 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
209 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
210 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
211 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
212 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
213 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
214 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
215 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
216 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
217};
218
219static struct intc_mask_reg mask_registers[] __initdata = {
220 { 0xfffe0808, 0, 16, /* PINTER */
221 { 0, 0, 0, 0, 0, 0, 0, 0,
222 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
223};
224
225static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 mask_registers, prio_registers, NULL);
227
228static struct plat_sci_port scif0_platform_data = {
229 .mapbase = 0xfffe8000,
230 .flags = UPF_BOOT_AUTOCONF,
231 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 SCSCR_REIE | SCSCR_TOIE,
233 .scbrr_algo_id = SCBRR_ALGO_2,
234 .type = PORT_SCIF,
235 .irqs = { 233, 234, 235, 232 },
236 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237};
238
239static struct platform_device scif0_device = {
240 .name = "sh-sci",
241 .id = 0,
242 .dev = {
243 .platform_data = &scif0_platform_data,
244 },
245};
246
247static struct plat_sci_port scif1_platform_data = {
248 .mapbase = 0xfffe8800,
249 .flags = UPF_BOOT_AUTOCONF,
250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 SCSCR_REIE | SCSCR_TOIE,
252 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF,
254 .irqs = { 237, 238, 239, 236 },
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256};
257
258static struct platform_device scif1_device = {
259 .name = "sh-sci",
260 .id = 1,
261 .dev = {
262 .platform_data = &scif1_platform_data,
263 },
264};
265
266static struct plat_sci_port scif2_platform_data = {
267 .mapbase = 0xfffe9000,
268 .flags = UPF_BOOT_AUTOCONF,
269 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 SCSCR_REIE | SCSCR_TOIE,
271 .scbrr_algo_id = SCBRR_ALGO_2,
272 .type = PORT_SCIF,
273 .irqs = { 241, 242, 243, 240 },
274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275};
276
277static struct platform_device scif2_device = {
278 .name = "sh-sci",
279 .id = 2,
280 .dev = {
281 .platform_data = &scif2_platform_data,
282 },
283};
284
285static struct plat_sci_port scif3_platform_data = {
286 .mapbase = 0xfffe9800,
287 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 SCSCR_REIE | SCSCR_TOIE,
290 .scbrr_algo_id = SCBRR_ALGO_2,
291 .type = PORT_SCIF,
292 .irqs = { 245, 246, 247, 244 },
293 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294};
295
296static struct platform_device scif3_device = {
297 .name = "sh-sci",
298 .id = 3,
299 .dev = {
300 .platform_data = &scif3_platform_data,
301 },
302};
303
304static struct plat_sci_port scif4_platform_data = {
305 .mapbase = 0xfffea000,
306 .flags = UPF_BOOT_AUTOCONF,
307 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 SCSCR_REIE | SCSCR_TOIE,
309 .scbrr_algo_id = SCBRR_ALGO_2,
310 .type = PORT_SCIF,
311 .irqs = { 249, 250, 251, 248 },
312 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313};
314
315static struct platform_device scif4_device = {
316 .name = "sh-sci",
317 .id = 4,
318 .dev = {
319 .platform_data = &scif4_platform_data,
320 },
321};
322
323static struct plat_sci_port scif5_platform_data = {
324 .mapbase = 0xfffea800,
325 .flags = UPF_BOOT_AUTOCONF,
326 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 SCSCR_REIE | SCSCR_TOIE,
328 .scbrr_algo_id = SCBRR_ALGO_2,
329 .type = PORT_SCIF,
330 .irqs = { 253, 254, 255, 252 },
331 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332};
333
334static struct platform_device scif5_device = {
335 .name = "sh-sci",
336 .id = 5,
337 .dev = {
338 .platform_data = &scif5_platform_data,
339 },
340};
341
342static struct plat_sci_port scif6_platform_data = {
343 .mapbase = 0xfffeb000,
344 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 SCSCR_REIE | SCSCR_TOIE,
347 .scbrr_algo_id = SCBRR_ALGO_2,
348 .type = PORT_SCIF,
349 .irqs = { 257, 258, 259, 256 },
350 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351};
352
353static struct platform_device scif6_device = {
354 .name = "sh-sci",
355 .id = 6,
356 .dev = {
357 .platform_data = &scif6_platform_data,
358 },
359};
360
361static struct plat_sci_port scif7_platform_data = {
362 .mapbase = 0xfffeb800,
363 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 SCSCR_REIE | SCSCR_TOIE,
366 .scbrr_algo_id = SCBRR_ALGO_2,
367 .type = PORT_SCIF,
368 .irqs = { 261, 262, 263, 260 },
369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370};
371
372static struct platform_device scif7_device = {
373 .name = "sh-sci",
374 .id = 7,
375 .dev = {
376 .platform_data = &scif7_platform_data,
377 },
378};
379
380static struct sh_timer_config cmt0_platform_data = {
381 .channel_offset = 0x02,
382 .timer_bit = 0,
383 .clockevent_rating = 125,
384 .clocksource_rating = 0, /* disabled due to code generation issues */
385};
386
387static struct resource cmt0_resources[] = {
388 [0] = {
389 .name = "CMT0",
390 .start = 0xfffec002,
391 .end = 0xfffec007,
392 .flags = IORESOURCE_MEM,
393 },
394 [1] = {
395 .start = 175,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
400static struct platform_device cmt0_device = {
401 .name = "sh_cmt",
402 .id = 0,
403 .dev = {
404 .platform_data = &cmt0_platform_data,
405 },
406 .resource = cmt0_resources,
407 .num_resources = ARRAY_SIZE(cmt0_resources),
408};
409
410static struct sh_timer_config cmt1_platform_data = {
411 .name = "CMT1",
412 .channel_offset = 0x08,
413 .timer_bit = 1,
414 .clockevent_rating = 125,
415 .clocksource_rating = 0, /* disabled due to code generation issues */
416};
417
418static struct resource cmt1_resources[] = {
419 [0] = {
420 .name = "CMT1",
421 .start = 0xfffec008,
422 .end = 0xfffec00d,
423 .flags = IORESOURCE_MEM,
424 },
425 [1] = {
426 .start = 176,
427 .flags = IORESOURCE_IRQ,
428 },
429};
430
431static struct platform_device cmt1_device = {
432 .name = "sh_cmt",
433 .id = 1,
434 .dev = {
435 .platform_data = &cmt1_platform_data,
436 },
437 .resource = cmt1_resources,
438 .num_resources = ARRAY_SIZE(cmt1_resources),
439};
440
441static struct sh_timer_config mtu2_0_platform_data = {
442 .name = "MTU2_0",
443 .channel_offset = -0x80,
444 .timer_bit = 0,
445 .clockevent_rating = 200,
446};
447
448static struct resource mtu2_0_resources[] = {
449 [0] = {
450 .name = "MTU2_0",
451 .start = 0xfffe4300,
452 .end = 0xfffe4326,
453 .flags = IORESOURCE_MEM,
454 },
455 [1] = {
456 .start = 179,
457 .flags = IORESOURCE_IRQ,
458 },
459};
460
461static struct platform_device mtu2_0_device = {
462 .name = "sh_mtu2",
463 .id = 0,
464 .dev = {
465 .platform_data = &mtu2_0_platform_data,
466 },
467 .resource = mtu2_0_resources,
468 .num_resources = ARRAY_SIZE(mtu2_0_resources),
469};
470
471static struct sh_timer_config mtu2_1_platform_data = {
472 .name = "MTU2_1",
473 .channel_offset = -0x100,
474 .timer_bit = 1,
475 .clockevent_rating = 200,
476};
477
478static struct resource mtu2_1_resources[] = {
479 [0] = {
480 .name = "MTU2_1",
481 .start = 0xfffe4380,
482 .end = 0xfffe4390,
483 .flags = IORESOURCE_MEM,
484 },
485 [1] = {
486 .start = 186,
487 .flags = IORESOURCE_IRQ,
488 },
489};
490
491static struct platform_device mtu2_1_device = {
492 .name = "sh_mtu2",
493 .id = 1,
494 .dev = {
495 .platform_data = &mtu2_1_platform_data,
496 },
497 .resource = mtu2_1_resources,
498 .num_resources = ARRAY_SIZE(mtu2_1_resources),
499};
500
501static struct resource rtc_resources[] = {
502 [0] = {
503 .start = 0xfffe6000,
504 .end = 0xfffe6000 + 0x30 - 1,
505 .flags = IORESOURCE_IO,
506 },
507 [1] = {
508 /* Shared Period/Carry/Alarm IRQ */
509 .start = 296,
510 .flags = IORESOURCE_IRQ,
511 },
512};
513
514static struct platform_device rtc_device = {
515 .name = "sh-rtc",
516 .id = -1,
517 .num_resources = ARRAY_SIZE(rtc_resources),
518 .resource = rtc_resources,
519};
520
521/* USB Host */
522static void usb_port_power(int port, int power)
523{
524 __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
525}
526
527static struct r8a66597_platdata r8a66597_data = {
528 .on_chip = 1,
529 .endian = 1,
530 .port_power = usb_port_power,
531};
532
533static struct resource r8a66597_usb_host_resources[] = {
534 [0] = {
535 .start = 0xffffc000,
536 .end = 0xffffc0e4,
537 .flags = IORESOURCE_MEM,
538 },
539 [1] = {
540 .start = 170,
541 .end = 170,
542 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
543 },
544};
545
546static struct platform_device r8a66597_usb_host_device = {
547 .name = "r8a66597_hcd",
548 .id = 0,
549 .dev = {
550 .dma_mask = NULL, /* not use dma */
551 .coherent_dma_mask = 0xffffffff,
552 .platform_data = &r8a66597_data,
553 },
554 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
555 .resource = r8a66597_usb_host_resources,
556};
557
558static struct platform_device *sh7264_devices[] __initdata = {
559 &scif0_device,
560 &scif1_device,
561 &scif2_device,
562 &scif3_device,
563 &scif4_device,
564 &scif5_device,
565 &scif6_device,
566 &scif7_device,
567 &cmt0_device,
568 &cmt1_device,
569 &mtu2_0_device,
570 &mtu2_1_device,
571 &rtc_device,
572 &r8a66597_usb_host_device,
573};
574
575static int __init sh7264_devices_setup(void)
576{
577 return platform_add_devices(sh7264_devices,
578 ARRAY_SIZE(sh7264_devices));
579}
580arch_initcall(sh7264_devices_setup);
581
582void __init plat_irq_setup(void)
583{
584 register_intc_controller(&intc_desc);
585}
586
587static struct platform_device *sh7264_early_devices[] __initdata = {
588 &scif0_device,
589 &scif1_device,
590 &scif2_device,
591 &scif3_device,
592 &scif4_device,
593 &scif5_device,
594 &scif6_device,
595 &scif7_device,
596 &cmt0_device,
597 &cmt1_device,
598 &mtu2_0_device,
599 &mtu2_1_device,
600};
601
602void __init plat_early_device_setup(void)
603{
604 early_platform_add_devices(sh7264_early_devices,
605 ARRAY_SIZE(sh7264_early_devices));
606}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
new file mode 100644
index 000000000000..e82ae9d8d3bc
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
@@ -0,0 +1,615 @@
1/*
2 * SH7269 Setup
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 * Copyright (C) 2012 Phil Edworthy
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/usb/r8a66597.h>
16#include <linux/sh_timer.h>
17#include <linux/io.h>
18
19enum {
20 UNUSED = 0,
21
22 /* interrupt sources */
23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
24 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
25
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
28 USB, VDC4, CMT0, CMT1, BSC, WDT,
29 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
30 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
31 PWMT1, PWMT2, ADC_ADI,
32 SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
33 RSPDIF,
34 IIC30, IIC31, IIC32, IIC33,
35 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
36 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
37 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
38 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
39 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
40 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
41 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
42 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
43 RCAN0, RCAN1, RCAN2,
44 RSPIC0, RSPIC1,
45 IEBC, CD_ROMD,
46 NFMC,
47 SDHI0, SDHI1,
48 RTC,
49 SRCC0, SRCC1, SRCC2,
50
51 /* interrupt groups */
52 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
53};
54
55static struct intc_vect vectors[] __initdata = {
56 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
57 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
58 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
59 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
60
61 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
62 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
63 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
64 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
65
66 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
67 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
68 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
69 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
70 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
71 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
72 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
73 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
74 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
75 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
76 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
77 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
78 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
79 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
80 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
81 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
82
83 INTC_IRQ(USB, 170),
84
85 INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
86 INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
87 INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
88 INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
89
90 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
91
92 INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
93
94 INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
95 INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
96 INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
97 INTC_IRQ(MTU0_VEF, 198),
98 INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
99 INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
100 INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
101 INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
102 INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
103 INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
104 INTC_IRQ(MTU3_TCI3V, 211),
105 INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
106 INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
107 INTC_IRQ(MTU4_TCI4V, 216),
108
109 INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
110
111 INTC_IRQ(ADC_ADI, 223),
112
113 INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
114 INTC_IRQ(SSIF0, 226),
115 INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
116 INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
117 INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
118 INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
119 INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
120
121 INTC_IRQ(RSPDIF, 237),
122
123 INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
124 INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
125 INTC_IRQ(IIC30, 242),
126 INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
127 INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
128 INTC_IRQ(IIC31, 247),
129 INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
130 INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
131 INTC_IRQ(IIC32, 252),
132 INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
133 INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
134 INTC_IRQ(IIC33, 257),
135
136 INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
137 INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
138 INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
139 INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
140 INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
141 INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
142 INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
143 INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
144 INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
145 INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
146 INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
147 INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
148 INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
149 INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
150 INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
151 INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
152
153 INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
154 INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
155 INTC_IRQ(RCAN0, 295),
156 INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
157 INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
158 INTC_IRQ(RCAN1, 300),
159 INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
160 INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
161 INTC_IRQ(RCAN2, 305),
162
163 INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
164 INTC_IRQ(RSPIC0, 308),
165 INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
166 INTC_IRQ(RSPIC1, 311),
167
168 INTC_IRQ(IEBC, 318),
169
170 INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
171 INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
172 INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
173
174 INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
175 INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
176
177 INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
178 INTC_IRQ(SDHI0, 334),
179 INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
180 INTC_IRQ(SDHI1, 337),
181
182 INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
183 INTC_IRQ(RTC, 340),
184
185 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
186 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
187 INTC_IRQ(SRCC0, 345),
188 INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
189 INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
190 INTC_IRQ(SRCC1, 350),
191 INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
192 INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
193 INTC_IRQ(SRCC2, 355),
194};
195
196static struct intc_group groups[] __initdata = {
197 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
198 PINT4, PINT5, PINT6, PINT7),
199 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
200 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
201 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
202 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
203 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
204 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
205 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
206 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
207};
208
209static struct intc_prio_reg prio_registers[] __initdata = {
210 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
211 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
212 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
213 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
214 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
215 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
216 DMAC10, DMAC11 } },
217 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
218 DMAC14, DMAC15 } },
219 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
220 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
221 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
222 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
223 MTU1_AB, MTU1_VU } },
224 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
225 MTU3_ABCD, MTU3_TCI3V } },
226 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
227 PWMT1, PWMT2 } },
228 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
229 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
230 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
231 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
232 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
233 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
234 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
235 { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
236 { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
237 { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
238 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
239};
240
241static struct intc_mask_reg mask_registers[] __initdata = {
242 { 0xfffe0808, 0, 16, /* PINTER */
243 { 0, 0, 0, 0, 0, 0, 0, 0,
244 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
245};
246
247static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL);
249
250static struct plat_sci_port scif0_platform_data = {
251 .mapbase = 0xe8007000,
252 .flags = UPF_BOOT_AUTOCONF,
253 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
254 SCSCR_REIE | SCSCR_TOIE,
255 .scbrr_algo_id = SCBRR_ALGO_2,
256 .type = PORT_SCIF,
257 .irqs = { 259, 260, 261, 258 },
258 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
259};
260
261static struct platform_device scif0_device = {
262 .name = "sh-sci",
263 .id = 0,
264 .dev = {
265 .platform_data = &scif0_platform_data,
266 },
267};
268
269static struct plat_sci_port scif1_platform_data = {
270 .mapbase = 0xe8007800,
271 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
273 SCSCR_REIE | SCSCR_TOIE,
274 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF,
276 .irqs = { 263, 264, 265, 262 },
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278};
279
280static struct platform_device scif1_device = {
281 .name = "sh-sci",
282 .id = 1,
283 .dev = {
284 .platform_data = &scif1_platform_data,
285 },
286};
287
288static struct plat_sci_port scif2_platform_data = {
289 .mapbase = 0xe8008000,
290 .flags = UPF_BOOT_AUTOCONF,
291 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
292 SCSCR_REIE | SCSCR_TOIE,
293 .scbrr_algo_id = SCBRR_ALGO_2,
294 .type = PORT_SCIF,
295 .irqs = { 267, 268, 269, 266 },
296 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
297};
298
299static struct platform_device scif2_device = {
300 .name = "sh-sci",
301 .id = 2,
302 .dev = {
303 .platform_data = &scif2_platform_data,
304 },
305};
306
307static struct plat_sci_port scif3_platform_data = {
308 .mapbase = 0xe8008800,
309 .flags = UPF_BOOT_AUTOCONF,
310 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
311 SCSCR_REIE | SCSCR_TOIE,
312 .scbrr_algo_id = SCBRR_ALGO_2,
313 .type = PORT_SCIF,
314 .irqs = { 271, 272, 273, 270 },
315 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
316};
317
318static struct platform_device scif3_device = {
319 .name = "sh-sci",
320 .id = 3,
321 .dev = {
322 .platform_data = &scif3_platform_data,
323 },
324};
325
326static struct plat_sci_port scif4_platform_data = {
327 .mapbase = 0xe8009000,
328 .flags = UPF_BOOT_AUTOCONF,
329 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
330 SCSCR_REIE | SCSCR_TOIE,
331 .scbrr_algo_id = SCBRR_ALGO_2,
332 .type = PORT_SCIF,
333 .irqs = { 275, 276, 277, 274 },
334 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
335};
336
337static struct platform_device scif4_device = {
338 .name = "sh-sci",
339 .id = 4,
340 .dev = {
341 .platform_data = &scif4_platform_data,
342 },
343};
344
345static struct plat_sci_port scif5_platform_data = {
346 .mapbase = 0xe8009800,
347 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
349 SCSCR_REIE | SCSCR_TOIE,
350 .scbrr_algo_id = SCBRR_ALGO_2,
351 .type = PORT_SCIF,
352 .irqs = { 279, 280, 281, 278 },
353 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
354};
355
356static struct platform_device scif5_device = {
357 .name = "sh-sci",
358 .id = 5,
359 .dev = {
360 .platform_data = &scif5_platform_data,
361 },
362};
363
364static struct plat_sci_port scif6_platform_data = {
365 .mapbase = 0xe800a000,
366 .flags = UPF_BOOT_AUTOCONF,
367 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
368 SCSCR_REIE | SCSCR_TOIE,
369 .scbrr_algo_id = SCBRR_ALGO_2,
370 .type = PORT_SCIF,
371 .irqs = { 283, 284, 285, 282 },
372 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
373};
374
375static struct platform_device scif6_device = {
376 .name = "sh-sci",
377 .id = 6,
378 .dev = {
379 .platform_data = &scif6_platform_data,
380 },
381};
382
383static struct plat_sci_port scif7_platform_data = {
384 .mapbase = 0xe800a800,
385 .flags = UPF_BOOT_AUTOCONF,
386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387 SCSCR_REIE | SCSCR_TOIE,
388 .scbrr_algo_id = SCBRR_ALGO_2,
389 .type = PORT_SCIF,
390 .irqs = { 287, 288, 289, 286 },
391 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
392};
393
394static struct platform_device scif7_device = {
395 .name = "sh-sci",
396 .id = 7,
397 .dev = {
398 .platform_data = &scif7_platform_data,
399 },
400};
401
402static struct sh_timer_config cmt0_platform_data = {
403 .channel_offset = 0x02,
404 .timer_bit = 0,
405 .clockevent_rating = 125,
406 .clocksource_rating = 0, /* disabled due to code generation issues */
407};
408
409static struct resource cmt0_resources[] = {
410 [0] = {
411 .start = 0xfffec002,
412 .end = 0xfffec007,
413 .flags = IORESOURCE_MEM,
414 },
415 [1] = {
416 .start = 188,
417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421static struct platform_device cmt0_device = {
422 .name = "sh_cmt",
423 .id = 0,
424 .dev = {
425 .platform_data = &cmt0_platform_data,
426 },
427 .resource = cmt0_resources,
428 .num_resources = ARRAY_SIZE(cmt0_resources),
429};
430
431static struct sh_timer_config cmt1_platform_data = {
432 .channel_offset = 0x08,
433 .timer_bit = 1,
434 .clockevent_rating = 125,
435 .clocksource_rating = 0, /* disabled due to code generation issues */
436};
437
438static struct resource cmt1_resources[] = {
439 [0] = {
440 .start = 0xfffec008,
441 .end = 0xfffec00d,
442 .flags = IORESOURCE_MEM,
443 },
444 [1] = {
445 .start = 189,
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450static struct platform_device cmt1_device = {
451 .name = "sh_cmt",
452 .id = 1,
453 .dev = {
454 .platform_data = &cmt1_platform_data,
455 },
456 .resource = cmt1_resources,
457 .num_resources = ARRAY_SIZE(cmt1_resources),
458};
459
460static struct sh_timer_config mtu2_0_platform_data = {
461 .channel_offset = -0x80,
462 .timer_bit = 0,
463 .clockevent_rating = 200,
464};
465
466static struct resource mtu2_0_resources[] = {
467 [0] = {
468 .start = 0xfffe4300,
469 .end = 0xfffe4326,
470 .flags = IORESOURCE_MEM,
471 },
472 [1] = {
473 .start = 192,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct platform_device mtu2_0_device = {
479 .name = "sh_mtu2",
480 .id = 0,
481 .dev = {
482 .platform_data = &mtu2_0_platform_data,
483 },
484 .resource = mtu2_0_resources,
485 .num_resources = ARRAY_SIZE(mtu2_0_resources),
486};
487
488static struct sh_timer_config mtu2_1_platform_data = {
489 .channel_offset = -0x100,
490 .timer_bit = 1,
491 .clockevent_rating = 200,
492};
493
494static struct resource mtu2_1_resources[] = {
495 [0] = {
496 .start = 0xfffe4380,
497 .end = 0xfffe4390,
498 .flags = IORESOURCE_MEM,
499 },
500 [1] = {
501 .start = 203,
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device mtu2_1_device = {
507 .name = "sh_mtu2",
508 .id = 1,
509 .dev = {
510 .platform_data = &mtu2_1_platform_data,
511 },
512 .resource = mtu2_1_resources,
513 .num_resources = ARRAY_SIZE(mtu2_1_resources),
514};
515
516static struct resource rtc_resources[] = {
517 [0] = {
518 .start = 0xfffe6000,
519 .end = 0xfffe6000 + 0x30 - 1,
520 .flags = IORESOURCE_IO,
521 },
522 [1] = {
523 /* Shared Period/Carry/Alarm IRQ */
524 .start = 338,
525 .flags = IORESOURCE_IRQ,
526 },
527};
528
529static struct platform_device rtc_device = {
530 .name = "sh-rtc",
531 .id = -1,
532 .num_resources = ARRAY_SIZE(rtc_resources),
533 .resource = rtc_resources,
534};
535
536/* USB Host */
537static struct r8a66597_platdata r8a66597_data = {
538 .on_chip = 1,
539 .endian = 1,
540};
541
542static struct resource r8a66597_usb_host_resources[] = {
543 [0] = {
544 .start = 0xe8010000,
545 .end = 0xe80100e4,
546 .flags = IORESOURCE_MEM,
547 },
548 [1] = {
549 .start = 170,
550 .end = 170,
551 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
552 },
553};
554
555static struct platform_device r8a66597_usb_host_device = {
556 .name = "r8a66597_hcd",
557 .id = 0,
558 .dev = {
559 .dma_mask = NULL, /* not use dma */
560 .coherent_dma_mask = 0xffffffff,
561 .platform_data = &r8a66597_data,
562 },
563 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
564 .resource = r8a66597_usb_host_resources,
565};
566
567static struct platform_device *sh7269_devices[] __initdata = {
568 &scif0_device,
569 &scif1_device,
570 &scif2_device,
571 &scif3_device,
572 &scif4_device,
573 &scif5_device,
574 &scif6_device,
575 &scif7_device,
576 &cmt0_device,
577 &cmt1_device,
578 &mtu2_0_device,
579 &mtu2_1_device,
580 &rtc_device,
581 &r8a66597_usb_host_device,
582};
583
584static int __init sh7269_devices_setup(void)
585{
586 return platform_add_devices(sh7269_devices,
587 ARRAY_SIZE(sh7269_devices));
588}
589arch_initcall(sh7269_devices_setup);
590
591void __init plat_irq_setup(void)
592{
593 register_intc_controller(&intc_desc);
594}
595
596static struct platform_device *sh7269_early_devices[] __initdata = {
597 &scif0_device,
598 &scif1_device,
599 &scif2_device,
600 &scif3_device,
601 &scif4_device,
602 &scif5_device,
603 &scif6_device,
604 &scif7_device,
605 &cmt0_device,
606 &cmt1_device,
607 &mtu2_0_device,
608 &mtu2_1_device,
609};
610
611void __init plat_early_device_setup(void)
612{
613 early_platform_add_devices(sh7269_early_devices,
614 ARRAY_SIZE(sh7269_early_devices));
615}
diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S
index f6a389c996cb..262db6ec067b 100644
--- a/arch/sh/kernel/cpu/sh3/entry.S
+++ b/arch/sh/kernel/cpu/sh3/entry.S
@@ -2,7 +2,7 @@
2 * arch/sh/kernel/cpu/sh3/entry.S 2 * arch/sh/kernel/cpu/sh3/entry.S
3 * 3 *
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
5 * Copyright (C) 2003 - 2006 Paul Mundt 5 * Copyright (C) 2003 - 2012 Paul Mundt
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -17,6 +17,7 @@
17#include <cpu/mmu_context.h> 17#include <cpu/mmu_context.h>
18#include <asm/page.h> 18#include <asm/page.h>
19#include <asm/cache.h> 19#include <asm/cache.h>
20#include <asm/thread_info.h>
20 21
21! NOTE: 22! NOTE:
22! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address 23! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
@@ -114,22 +115,22 @@ ENTRY(tlb_miss_load)
114 .align 2 115 .align 2
115ENTRY(tlb_miss_store) 116ENTRY(tlb_miss_store)
116 bra call_handle_tlbmiss 117 bra call_handle_tlbmiss
117 mov #1, r5 118 mov #FAULT_CODE_WRITE, r5
118 119
119 .align 2 120 .align 2
120ENTRY(initial_page_write) 121ENTRY(initial_page_write)
121 bra call_handle_tlbmiss 122 bra call_handle_tlbmiss
122 mov #2, r5 123 mov #FAULT_CODE_INITIAL, r5
123 124
124 .align 2 125 .align 2
125ENTRY(tlb_protection_violation_load) 126ENTRY(tlb_protection_violation_load)
126 bra call_do_page_fault 127 bra call_do_page_fault
127 mov #0, r5 128 mov #FAULT_CODE_PROT, r5
128 129
129 .align 2 130 .align 2
130ENTRY(tlb_protection_violation_store) 131ENTRY(tlb_protection_violation_store)
131 bra call_do_page_fault 132 bra call_do_page_fault
132 mov #1, r5 133 mov #(FAULT_CODE_PROT | FAULT_CODE_WRITE), r5
133 134
134call_handle_tlbmiss: 135call_handle_tlbmiss:
135 mov.l 1f, r0 136 mov.l 1f, r0
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 2309618c015d..03e4c96f2b11 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -14,6 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
17#include <asm/rtc.h> 18#include <asm/rtc.h>
18#include <cpu/serial.h> 19#include <cpu/serial.h>
19 20
@@ -75,7 +76,7 @@ static struct plat_sci_port scif0_platform_data = {
75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 76 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
76 .scbrr_algo_id = SCBRR_ALGO_4, 77 .scbrr_algo_id = SCBRR_ALGO_4,
77 .type = PORT_SCIF, 78 .type = PORT_SCIF,
78 .irqs = { 56, 56, 56 }, 79 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
79 .ops = &sh770x_sci_port_ops, 80 .ops = &sh770x_sci_port_ops,
80 .regtype = SCIx_SH7705_SCIF_REGTYPE, 81 .regtype = SCIx_SH7705_SCIF_REGTYPE,
81}; 82};
@@ -94,7 +95,7 @@ static struct plat_sci_port scif1_platform_data = {
94 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 95 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
95 .scbrr_algo_id = SCBRR_ALGO_4, 96 .scbrr_algo_id = SCBRR_ALGO_4,
96 .type = PORT_SCIF, 97 .type = PORT_SCIF,
97 .irqs = { 52, 52, 52 }, 98 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
98 .ops = &sh770x_sci_port_ops, 99 .ops = &sh770x_sci_port_ops,
99 .regtype = SCIx_SH7705_SCIF_REGTYPE, 100 .regtype = SCIx_SH7705_SCIF_REGTYPE,
100}; 101};
@@ -114,7 +115,7 @@ static struct resource rtc_resources[] = {
114 .flags = IORESOURCE_IO, 115 .flags = IORESOURCE_IO,
115 }, 116 },
116 [1] = { 117 [1] = {
117 .start = 20, 118 .start = evt2irq(0x480),
118 .flags = IORESOURCE_IRQ, 119 .flags = IORESOURCE_IRQ,
119 }, 120 },
120}; 121};
@@ -146,7 +147,7 @@ static struct resource tmu0_resources[] = {
146 .flags = IORESOURCE_MEM, 147 .flags = IORESOURCE_MEM,
147 }, 148 },
148 [1] = { 149 [1] = {
149 .start = 16, 150 .start = evt2irq(0x400),
150 .flags = IORESOURCE_IRQ, 151 .flags = IORESOURCE_IRQ,
151 }, 152 },
152}; 153};
@@ -174,7 +175,7 @@ static struct resource tmu1_resources[] = {
174 .flags = IORESOURCE_MEM, 175 .flags = IORESOURCE_MEM,
175 }, 176 },
176 [1] = { 177 [1] = {
177 .start = 17, 178 .start = evt2irq(0x420),
178 .flags = IORESOURCE_IRQ, 179 .flags = IORESOURCE_IRQ,
179 }, 180 },
180}; 181};
@@ -201,7 +202,7 @@ static struct resource tmu2_resources[] = {
201 .flags = IORESOURCE_MEM, 202 .flags = IORESOURCE_MEM,
202 }, 203 },
203 [1] = { 204 [1] = {
204 .start = 18, 205 .start = evt2irq(0x440),
205 .flags = IORESOURCE_IRQ, 206 .flags = IORESOURCE_IRQ,
206 }, 207 },
207}; 208};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 3f3d5fe5892d..ba26cd9ce69b 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -19,6 +19,7 @@
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <linux/sh_intc.h>
22#include <cpu/serial.h> 23#include <cpu/serial.h>
23 24
24enum { 25enum {
@@ -95,7 +96,7 @@ static struct resource rtc_resources[] = {
95 .flags = IORESOURCE_IO, 96 .flags = IORESOURCE_IO,
96 }, 97 },
97 [1] = { 98 [1] = {
98 .start = 20, 99 .start = evt2irq(0x480),
99 .flags = IORESOURCE_IRQ, 100 .flags = IORESOURCE_IRQ,
100 }, 101 },
101}; 102};
@@ -114,7 +115,7 @@ static struct plat_sci_port scif0_platform_data = {
114 .scscr = SCSCR_TE | SCSCR_RE, 115 .scscr = SCSCR_TE | SCSCR_RE,
115 .scbrr_algo_id = SCBRR_ALGO_2, 116 .scbrr_algo_id = SCBRR_ALGO_2,
116 .type = PORT_SCI, 117 .type = PORT_SCI,
117 .irqs = { 23, 23, 23, 0 }, 118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
118 .ops = &sh770x_sci_port_ops, 119 .ops = &sh770x_sci_port_ops,
119 .regshift = 1, 120 .regshift = 1,
120}; 121};
@@ -135,7 +136,7 @@ static struct plat_sci_port scif1_platform_data = {
135 .scscr = SCSCR_TE | SCSCR_RE, 136 .scscr = SCSCR_TE | SCSCR_RE,
136 .scbrr_algo_id = SCBRR_ALGO_2, 137 .scbrr_algo_id = SCBRR_ALGO_2,
137 .type = PORT_SCIF, 138 .type = PORT_SCIF,
138 .irqs = { 56, 56, 56, 56 }, 139 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
139 .ops = &sh770x_sci_port_ops, 140 .ops = &sh770x_sci_port_ops,
140 .regtype = SCIx_SH3_SCIF_REGTYPE, 141 .regtype = SCIx_SH3_SCIF_REGTYPE,
141}; 142};
@@ -157,7 +158,7 @@ static struct plat_sci_port scif2_platform_data = {
157 .scscr = SCSCR_TE | SCSCR_RE, 158 .scscr = SCSCR_TE | SCSCR_RE,
158 .scbrr_algo_id = SCBRR_ALGO_2, 159 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_IRDA, 160 .type = PORT_IRDA,
160 .irqs = { 52, 52, 52, 52 }, 161 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
161 .ops = &sh770x_sci_port_ops, 162 .ops = &sh770x_sci_port_ops,
162 .regshift = 1, 163 .regshift = 1,
163}; 164};
@@ -184,7 +185,7 @@ static struct resource tmu0_resources[] = {
184 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
185 }, 186 },
186 [1] = { 187 [1] = {
187 .start = 16, 188 .start = evt2irq(0x400),
188 .flags = IORESOURCE_IRQ, 189 .flags = IORESOURCE_IRQ,
189 }, 190 },
190}; 191};
@@ -212,7 +213,7 @@ static struct resource tmu1_resources[] = {
212 .flags = IORESOURCE_MEM, 213 .flags = IORESOURCE_MEM,
213 }, 214 },
214 [1] = { 215 [1] = {
215 .start = 17, 216 .start = evt2irq(0x420),
216 .flags = IORESOURCE_IRQ, 217 .flags = IORESOURCE_IRQ,
217 }, 218 },
218}; 219};
@@ -239,7 +240,7 @@ static struct resource tmu2_resources[] = {
239 .flags = IORESOURCE_MEM, 240 .flags = IORESOURCE_MEM,
240 }, 241 },
241 [1] = { 242 [1] = {
242 .start = 18, 243 .start = evt2irq(0x440),
243 .flags = IORESOURCE_IRQ, 244 .flags = IORESOURCE_IRQ,
244 }, 245 },
245}; 246};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 78f6b01d42c3..93c9c5e24a7a 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -14,6 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
17#include <asm/rtc.h> 18#include <asm/rtc.h>
18 19
19enum { 20enum {
@@ -77,7 +78,7 @@ static struct resource rtc_resources[] = {
77 .flags = IORESOURCE_IO, 78 .flags = IORESOURCE_IO,
78 }, 79 },
79 [1] = { 80 [1] = {
80 .start = 20, 81 .start = evt2irq(0x480),
81 .flags = IORESOURCE_IRQ, 82 .flags = IORESOURCE_IRQ,
82 }, 83 },
83}; 84};
@@ -103,7 +104,7 @@ static struct plat_sci_port scif0_platform_data = {
103 SCSCR_CKE1 | SCSCR_CKE0, 104 SCSCR_CKE1 | SCSCR_CKE0,
104 .scbrr_algo_id = SCBRR_ALGO_2, 105 .scbrr_algo_id = SCBRR_ALGO_2,
105 .type = PORT_SCIF, 106 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 }, 107 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
107}; 108};
108 109
109static struct platform_device scif0_device = { 110static struct platform_device scif0_device = {
@@ -121,7 +122,7 @@ static struct plat_sci_port scif1_platform_data = {
121 SCSCR_CKE1 | SCSCR_CKE0, 122 SCSCR_CKE1 | SCSCR_CKE0,
122 .scbrr_algo_id = SCBRR_ALGO_2, 123 .scbrr_algo_id = SCBRR_ALGO_2,
123 .type = PORT_SCIF, 124 .type = PORT_SCIF,
124 .irqs = { 56, 56, 56, 56 }, 125 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
125}; 126};
126 127
127static struct platform_device scif1_device = { 128static struct platform_device scif1_device = {
@@ -145,7 +146,7 @@ static struct resource tmu0_resources[] = {
145 .flags = IORESOURCE_MEM, 146 .flags = IORESOURCE_MEM,
146 }, 147 },
147 [1] = { 148 [1] = {
148 .start = 16, 149 .start = evt2irq(0x400),
149 .flags = IORESOURCE_IRQ, 150 .flags = IORESOURCE_IRQ,
150 }, 151 },
151}; 152};
@@ -173,7 +174,7 @@ static struct resource tmu1_resources[] = {
173 .flags = IORESOURCE_MEM, 174 .flags = IORESOURCE_MEM,
174 }, 175 },
175 [1] = { 176 [1] = {
176 .start = 17, 177 .start = evt2irq(0x420),
177 .flags = IORESOURCE_IRQ, 178 .flags = IORESOURCE_IRQ,
178 }, 179 },
179}; 180};
@@ -200,7 +201,7 @@ static struct resource tmu2_resources[] = {
200 .flags = IORESOURCE_MEM, 201 .flags = IORESOURCE_MEM,
201 }, 202 },
202 [1] = { 203 [1] = {
203 .start = 18, 204 .start = evt2irq(0x440),
204 .flags = IORESOURCE_IRQ, 205 .flags = IORESOURCE_IRQ,
205 }, 206 },
206}; 207};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 94920345c14d..0c2f1b2c2e19 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <linux/sh_intc.h>
22#include <asm/rtc.h> 23#include <asm/rtc.h>
23#include <cpu/serial.h> 24#include <cpu/serial.h>
24 25
@@ -30,7 +31,7 @@ static struct resource rtc_resources[] = {
30 }, 31 },
31 [1] = { 32 [1] = {
32 /* Shared Period/Carry/Alarm IRQ */ 33 /* Shared Period/Carry/Alarm IRQ */
33 .start = 20, 34 .start = evt2irq(0x480),
34 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
35 }, 36 },
36}; 37};
@@ -55,7 +56,7 @@ static struct plat_sci_port scif0_platform_data = {
55 .scscr = SCSCR_RE | SCSCR_TE, 56 .scscr = SCSCR_RE | SCSCR_TE,
56 .scbrr_algo_id = SCBRR_ALGO_4, 57 .scbrr_algo_id = SCBRR_ALGO_4,
57 .type = PORT_SCIF, 58 .type = PORT_SCIF,
58 .irqs = { 80, 80, 80, 80 }, 59 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
59 .ops = &sh7720_sci_port_ops, 60 .ops = &sh7720_sci_port_ops,
60 .regtype = SCIx_SH7705_SCIF_REGTYPE, 61 .regtype = SCIx_SH7705_SCIF_REGTYPE,
61}; 62};
@@ -74,7 +75,7 @@ static struct plat_sci_port scif1_platform_data = {
74 .scscr = SCSCR_RE | SCSCR_TE, 75 .scscr = SCSCR_RE | SCSCR_TE,
75 .scbrr_algo_id = SCBRR_ALGO_4, 76 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF, 77 .type = PORT_SCIF,
77 .irqs = { 81, 81, 81, 81 }, 78 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
78 .ops = &sh7720_sci_port_ops, 79 .ops = &sh7720_sci_port_ops,
79 .regtype = SCIx_SH7705_SCIF_REGTYPE, 80 .regtype = SCIx_SH7705_SCIF_REGTYPE,
80}; 81};
@@ -94,13 +95,14 @@ static struct resource usb_ohci_resources[] = {
94 .flags = IORESOURCE_MEM, 95 .flags = IORESOURCE_MEM,
95 }, 96 },
96 [1] = { 97 [1] = {
97 .start = 67, 98 .start = evt2irq(0xa60),
98 .end = 67, 99 .end = evt2irq(0xa60),
99 .flags = IORESOURCE_IRQ, 100 .flags = IORESOURCE_IRQ,
100 }, 101 },
101}; 102};
102 103
103static u64 usb_ohci_dma_mask = 0xffffffffUL; 104static u64 usb_ohci_dma_mask = 0xffffffffUL;
105
104static struct platform_device usb_ohci_device = { 106static struct platform_device usb_ohci_device = {
105 .name = "sh_ohci", 107 .name = "sh_ohci",
106 .id = -1, 108 .id = -1,
@@ -121,8 +123,8 @@ static struct resource usbf_resources[] = {
121 }, 123 },
122 [1] = { 124 [1] = {
123 .name = "sh_udc", 125 .name = "sh_udc",
124 .start = 65, 126 .start = evt2irq(0xa20),
125 .end = 65, 127 .end = evt2irq(0xa20),
126 .flags = IORESOURCE_IRQ, 128 .flags = IORESOURCE_IRQ,
127 }, 129 },
128}; 130};
@@ -152,7 +154,7 @@ static struct resource cmt0_resources[] = {
152 .flags = IORESOURCE_MEM, 154 .flags = IORESOURCE_MEM,
153 }, 155 },
154 [1] = { 156 [1] = {
155 .start = 104, 157 .start = evt2irq(0xf00),
156 .flags = IORESOURCE_IRQ, 158 .flags = IORESOURCE_IRQ,
157 }, 159 },
158}; 160};
@@ -179,7 +181,7 @@ static struct resource cmt1_resources[] = {
179 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
180 }, 182 },
181 [1] = { 183 [1] = {
182 .start = 104, 184 .start = evt2irq(0xf00),
183 .flags = IORESOURCE_IRQ, 185 .flags = IORESOURCE_IRQ,
184 }, 186 },
185}; 187};
@@ -206,7 +208,7 @@ static struct resource cmt2_resources[] = {
206 .flags = IORESOURCE_MEM, 208 .flags = IORESOURCE_MEM,
207 }, 209 },
208 [1] = { 210 [1] = {
209 .start = 104, 211 .start = evt2irq(0xf00),
210 .flags = IORESOURCE_IRQ, 212 .flags = IORESOURCE_IRQ,
211 }, 213 },
212}; 214};
@@ -233,7 +235,7 @@ static struct resource cmt3_resources[] = {
233 .flags = IORESOURCE_MEM, 235 .flags = IORESOURCE_MEM,
234 }, 236 },
235 [1] = { 237 [1] = {
236 .start = 104, 238 .start = evt2irq(0xf00),
237 .flags = IORESOURCE_IRQ, 239 .flags = IORESOURCE_IRQ,
238 }, 240 },
239}; 241};
@@ -260,7 +262,7 @@ static struct resource cmt4_resources[] = {
260 .flags = IORESOURCE_MEM, 262 .flags = IORESOURCE_MEM,
261 }, 263 },
262 [1] = { 264 [1] = {
263 .start = 104, 265 .start = evt2irq(0xf00),
264 .flags = IORESOURCE_IRQ, 266 .flags = IORESOURCE_IRQ,
265 }, 267 },
266}; 268};
@@ -288,7 +290,7 @@ static struct resource tmu0_resources[] = {
288 .flags = IORESOURCE_MEM, 290 .flags = IORESOURCE_MEM,
289 }, 291 },
290 [1] = { 292 [1] = {
291 .start = 16, 293 .start = evt2irq(0x400),
292 .flags = IORESOURCE_IRQ, 294 .flags = IORESOURCE_IRQ,
293 }, 295 },
294}; 296};
@@ -316,7 +318,7 @@ static struct resource tmu1_resources[] = {
316 .flags = IORESOURCE_MEM, 318 .flags = IORESOURCE_MEM,
317 }, 319 },
318 [1] = { 320 [1] = {
319 .start = 17, 321 .start = evt2irq(0x420),
320 .flags = IORESOURCE_IRQ, 322 .flags = IORESOURCE_IRQ,
321 }, 323 },
322}; 324};
@@ -343,7 +345,7 @@ static struct resource tmu2_resources[] = {
343 .flags = IORESOURCE_MEM, 345 .flags = IORESOURCE_MEM,
344 }, 346 },
345 [1] = { 347 [1] = {
346 .start = 18, 348 .start = evt2irq(0x440),
347 .flags = IORESOURCE_IRQ, 349 .flags = IORESOURCE_IRQ,
348 }, 350 },
349}; 351};
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 971cf0fce4f5..0fbbd50bc8ad 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -158,6 +158,9 @@ void __cpuinit cpu_probe(void)
158 case 0x40: /* yon-ten-go */ 158 case 0x40: /* yon-ten-go */
159 boot_cpu_data.type = CPU_SH7372; 159 boot_cpu_data.type = CPU_SH7372;
160 break; 160 break;
161 case 0xE0: /* 0x4E0 */
162 boot_cpu_data.type = CPU_SH7734; /* SH7733/SH7734 */
163 break;
161 164
162 } 165 }
163 break; 166 break;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 5b2833159b7d..2a5320aa73bb 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -13,6 +13,7 @@
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
16#include <linux/io.h> 17#include <linux/io.h>
17 18
18static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
@@ -21,7 +22,10 @@ static struct plat_sci_port scif0_platform_data = {
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
22 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 24 .type = PORT_SCIF,
24 .irqs = { 40, 41, 43, 42 }, 25 .irqs = { evt2irq(0x700),
26 evt2irq(0x720),
27 evt2irq(0x760),
28 evt2irq(0x740) },
25}; 29};
26 30
27static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -45,7 +49,7 @@ static struct resource tmu0_resources[] = {
45 .flags = IORESOURCE_MEM, 49 .flags = IORESOURCE_MEM,
46 }, 50 },
47 [1] = { 51 [1] = {
48 .start = 16, 52 .start = evt2irq(0x400),
49 .flags = IORESOURCE_IRQ, 53 .flags = IORESOURCE_IRQ,
50 }, 54 },
51}; 55};
@@ -73,7 +77,7 @@ static struct resource tmu1_resources[] = {
73 .flags = IORESOURCE_MEM, 77 .flags = IORESOURCE_MEM,
74 }, 78 },
75 [1] = { 79 [1] = {
76 .start = 17, 80 .start = evt2irq(0x420),
77 .flags = IORESOURCE_IRQ, 81 .flags = IORESOURCE_IRQ,
78 }, 82 },
79}; 83};
@@ -100,7 +104,7 @@ static struct resource tmu2_resources[] = {
100 .flags = IORESOURCE_MEM, 104 .flags = IORESOURCE_MEM,
101 }, 105 },
102 [1] = { 106 [1] = {
103 .start = 18, 107 .start = evt2irq(0x440),
104 .flags = IORESOURCE_IRQ, 108 .flags = IORESOURCE_IRQ,
105 }, 109 },
106}; 110};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 98cc0c794c76..04a45512596f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -13,6 +13,7 @@
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
16#include <linux/serial_sci.h> 17#include <linux/serial_sci.h>
17#include <generated/machtypes.h> 18#include <generated/machtypes.h>
18 19
@@ -24,7 +25,7 @@ static struct resource rtc_resources[] = {
24 }, 25 },
25 [1] = { 26 [1] = {
26 /* Shared Period/Carry/Alarm IRQ */ 27 /* Shared Period/Carry/Alarm IRQ */
27 .start = 20, 28 .start = evt2irq(0x480),
28 .flags = IORESOURCE_IRQ, 29 .flags = IORESOURCE_IRQ,
29 }, 30 },
30}; 31};
@@ -43,7 +44,7 @@ static struct plat_sci_port sci_platform_data = {
43 .scscr = SCSCR_TE | SCSCR_RE, 44 .scscr = SCSCR_TE | SCSCR_RE,
44 .scbrr_algo_id = SCBRR_ALGO_2, 45 .scbrr_algo_id = SCBRR_ALGO_2,
45 .type = PORT_SCI, 46 .type = PORT_SCI,
46 .irqs = { 23, 23, 23, 0 }, 47 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
47 .regshift = 2, 48 .regshift = 2,
48}; 49};
49 50
@@ -61,7 +62,7 @@ static struct plat_sci_port scif_platform_data = {
61 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 62 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2, 63 .scbrr_algo_id = SCBRR_ALGO_2,
63 .type = PORT_SCIF, 64 .type = PORT_SCIF,
64 .irqs = { 40, 40, 40, 40 }, 65 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
65}; 66};
66 67
67static struct platform_device scif_device = { 68static struct platform_device scif_device = {
@@ -85,7 +86,7 @@ static struct resource tmu0_resources[] = {
85 .flags = IORESOURCE_MEM, 86 .flags = IORESOURCE_MEM,
86 }, 87 },
87 [1] = { 88 [1] = {
88 .start = 16, 89 .start = evt2irq(0x400),
89 .flags = IORESOURCE_IRQ, 90 .flags = IORESOURCE_IRQ,
90 }, 91 },
91}; 92};
@@ -113,7 +114,7 @@ static struct resource tmu1_resources[] = {
113 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
114 }, 115 },
115 [1] = { 116 [1] = {
116 .start = 17, 117 .start = evt2irq(0x420),
117 .flags = IORESOURCE_IRQ, 118 .flags = IORESOURCE_IRQ,
118 }, 119 },
119}; 120};
@@ -140,7 +141,7 @@ static struct resource tmu2_resources[] = {
140 .flags = IORESOURCE_MEM, 141 .flags = IORESOURCE_MEM,
141 }, 142 },
142 [1] = { 143 [1] = {
143 .start = 18, 144 .start = evt2irq(0x440),
144 .flags = IORESOURCE_IRQ, 145 .flags = IORESOURCE_IRQ,
145 }, 146 },
146}; 147};
@@ -172,7 +173,7 @@ static struct resource tmu3_resources[] = {
172 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
173 }, 174 },
174 [1] = { 175 [1] = {
175 .start = 72, 176 .start = evt2irq(0xb00),
176 .flags = IORESOURCE_IRQ, 177 .flags = IORESOURCE_IRQ,
177 }, 178 },
178}; 179};
@@ -199,7 +200,7 @@ static struct resource tmu4_resources[] = {
199 .flags = IORESOURCE_MEM, 200 .flags = IORESOURCE_MEM,
200 }, 201 },
201 [1] = { 202 [1] = {
202 .start = 76, 203 .start = evt2irq(0xb80),
203 .flags = IORESOURCE_IRQ, 204 .flags = IORESOURCE_IRQ,
204 }, 205 },
205}; 206};
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index c0b4c774700e..98e075ada44e 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/sh_timer.h> 13#include <linux/sh_timer.h>
14#include <linux/sh_intc.h>
14#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
15#include <linux/io.h> 16#include <linux/io.h>
16 17
@@ -132,7 +133,10 @@ static struct plat_sci_port scif0_platform_data = {
132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
133 .scbrr_algo_id = SCBRR_ALGO_2, 134 .scbrr_algo_id = SCBRR_ALGO_2,
134 .type = PORT_SCIF, 135 .type = PORT_SCIF,
135 .irqs = { 52, 53, 55, 54 }, 136 .irqs = { evt2irq(0x880),
137 evt2irq(0x8a0),
138 evt2irq(0x8e0),
139 evt2irq(0x8c0) },
136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 140 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
137}; 141};
138 142
@@ -150,7 +154,10 @@ static struct plat_sci_port scif1_platform_data = {
150 .type = PORT_SCIF, 154 .type = PORT_SCIF,
151 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 155 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
152 .scbrr_algo_id = SCBRR_ALGO_2, 156 .scbrr_algo_id = SCBRR_ALGO_2,
153 .irqs = { 72, 73, 75, 74 }, 157 .irqs = { evt2irq(0xb00),
158 evt2irq(0xb20),
159 evt2irq(0xb60),
160 evt2irq(0xb40) },
154 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 161 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
155}; 162};
156 163
@@ -168,7 +175,10 @@ static struct plat_sci_port scif2_platform_data = {
168 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 175 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
169 .scbrr_algo_id = SCBRR_ALGO_2, 176 .scbrr_algo_id = SCBRR_ALGO_2,
170 .type = PORT_SCIF, 177 .type = PORT_SCIF,
171 .irqs = { 76, 77, 79, 78 }, 178 .irqs = { evt2irq(0xb80),
179 evt2irq(0xba0),
180 evt2irq(0xbe0),
181 evt2irq(0xbc0) },
172 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 182 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
173}; 183};
174 184
@@ -186,7 +196,9 @@ static struct plat_sci_port scif3_platform_data = {
186 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
187 .scbrr_algo_id = SCBRR_ALGO_2, 197 .scbrr_algo_id = SCBRR_ALGO_2,
188 .type = PORT_SCI, 198 .type = PORT_SCI,
189 .irqs = { 80, 81, 82, 0 }, 199 .irqs = { evt2irq(0xc00),
200 evt2irq(0xc20),
201 evt2irq(0xc40), },
190 .regshift = 2, 202 .regshift = 2,
191}; 203};
192 204
@@ -211,7 +223,7 @@ static struct resource tmu0_resources[] = {
211 .flags = IORESOURCE_MEM, 223 .flags = IORESOURCE_MEM,
212 }, 224 },
213 [1] = { 225 [1] = {
214 .start = 16, 226 .start = evt2irq(0x400),
215 .flags = IORESOURCE_IRQ, 227 .flags = IORESOURCE_IRQ,
216 }, 228 },
217}; 229};
@@ -239,7 +251,7 @@ static struct resource tmu1_resources[] = {
239 .flags = IORESOURCE_MEM, 251 .flags = IORESOURCE_MEM,
240 }, 252 },
241 [1] = { 253 [1] = {
242 .start = 17, 254 .start = evt2irq(0x420),
243 .flags = IORESOURCE_IRQ, 255 .flags = IORESOURCE_IRQ,
244 }, 256 },
245}; 257};
@@ -266,7 +278,7 @@ static struct resource tmu2_resources[] = {
266 .flags = IORESOURCE_MEM, 278 .flags = IORESOURCE_MEM,
267 }, 279 },
268 [1] = { 280 [1] = {
269 .start = 18, 281 .start = evt2irq(0x440),
270 .flags = IORESOURCE_IRQ, 282 .flags = IORESOURCE_IRQ,
271 }, 283 },
272}; 284};
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 0b22d108f4c5..8fc6ec2be2fa 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7734) += setup-sh7734.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 17obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
17obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o 18obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o intc-shx3.o
18 19
@@ -30,6 +31,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
30clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 31clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o 32clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
32clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o 33clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
34clock-$(CONFIG_CPU_SUBTYPE_SH7734) := clock-sh7734.o
33clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o 35clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
34clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 36clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35 37
@@ -37,6 +39,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
38pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 40pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
39pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7734) := pinmux-sh7734.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o 43pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 44pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 45pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7734.c b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
new file mode 100644
index 000000000000..1697642c1f73
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7734.c
@@ -0,0 +1,266 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7734.c
3 *
4 * Clock framework for SH7734
5 *
6 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011, 2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/clkdev.h>
18#include <linux/delay.h>
19#include <asm/clock.h>
20#include <asm/freq.h>
21
22static struct clk extal_clk = {
23 .rate = 33333333,
24};
25
26#define MODEMR (0xFFCC0020)
27#define MODEMR_MASK (0x6)
28#define MODEMR_533MHZ (0x2)
29
30static unsigned long pll_recalc(struct clk *clk)
31{
32 int mode = 12;
33 u32 r = __raw_readl(MODEMR);
34
35 if ((r & MODEMR_MASK) & MODEMR_533MHZ)
36 mode = 16;
37
38 return clk->parent->rate * mode;
39}
40
41static struct sh_clk_ops pll_clk_ops = {
42 .recalc = pll_recalc,
43};
44
45static struct clk pll_clk = {
46 .ops = &pll_clk_ops,
47 .parent = &extal_clk,
48 .flags = CLK_ENABLE_ON_INIT,
49};
50
51static struct clk *main_clks[] = {
52 &extal_clk,
53 &pll_clk,
54};
55
56static int multipliers[] = { 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
57static int divisors[] = { 1, 3, 2, 3, 4, 6, 8, 9, 12, 16, 18, 24 };
58
59static struct clk_div_mult_table div4_div_mult_table = {
60 .divisors = divisors,
61 .nr_divisors = ARRAY_SIZE(divisors),
62 .multipliers = multipliers,
63 .nr_multipliers = ARRAY_SIZE(multipliers),
64};
65
66static struct clk_div4_table div4_table = {
67 .div_mult_table = &div4_div_mult_table,
68};
69
70enum { DIV4_I, DIV4_S, DIV4_B, DIV4_M, DIV4_S1, DIV4_P, DIV4_NR };
71
72#define DIV4(_reg, _bit, _mask, _flags) \
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
74
75struct clk div4_clks[DIV4_NR] = {
76 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
77 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
79 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
80 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
81 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
82};
83
84#define MSTPCR0 0xFFC80030
85#define MSTPCR1 0xFFC80034
86#define MSTPCR3 0xFFC8003C
87
88enum {
89 MSTP030, MSTP029, /* IIC */
90 MSTP026, MSTP025, MSTP024, /* SCIF */
91 MSTP023,
92 MSTP022, MSTP021,
93 MSTP019, /* HSCIF */
94 MSTP016, MSTP015, MSTP014, /* TMU / TIMER */
95 MSTP012, MSTP011, MSTP010, MSTP009, MSTP008, /* SSI */
96 MSTP007, /* HSPI */
97 MSTP115, /* ADMAC */
98 MSTP114, /* GETHER */
99 MSTP111, /* DMAC */
100 MSTP109, /* VIDEOIN1 */
101 MSTP108, /* VIDEOIN0 */
102 MSTP107, /* RGPVBG */
103 MSTP106, /* 2DG */
104 MSTP103, /* VIEW */
105 MSTP100, /* USB */
106 MSTP331, /* MMC */
107 MSTP330, /* MIMLB */
108 MSTP323, /* SDHI0 */
109 MSTP322, /* SDHI1 */
110 MSTP321, /* SDHI2 */
111 MSTP320, /* RQSPI */
112 MSTP319, /* SRC0 */
113 MSTP318, /* SRC1 */
114 MSTP317, /* RSPI */
115 MSTP316, /* RCAN0 */
116 MSTP315, /* RCAN1 */
117 MSTP314, /* FLTCL */
118 MSTP313, /* ADC */
119 MSTP312, /* MTU */
120 MSTP304, /* IE-BUS */
121 MSTP303, /* RTC */
122 MSTP302, /* HIF */
123 MSTP301, /* STIF0 */
124 MSTP300, /* STIF1 */
125 MSTP_NR };
126
127static struct clk mstp_clks[MSTP_NR] = {
128 /* MSTPCR0 */
129 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0),
130 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
131 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
132 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
133 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
134 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
135 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
136 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
137 [MSTP019] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
138 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
139 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
140 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
141 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
142 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
143 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
144 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
145 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
146 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
147
148 /* MSTPCR1 */
149 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0),
150 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
151 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
152 [MSTP109] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
153 [MSTP108] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
154 [MSTP107] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 7, 0),
155 [MSTP106] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 6, 0),
156 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
157 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0),
158
159 /* MSTPCR3 */
160 [MSTP331] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 31, 0),
161 [MSTP330] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 30, 0),
162 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0),
163 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0),
164 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0),
165 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0),
166 [MSTP319] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 19, 0),
167 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 18, 0),
168 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 17, 0),
169 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 16, 0),
170 [MSTP315] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 15, 0),
171 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 14, 0),
172 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 13, 0),
173 [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 12, 0),
174 [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 4, 0),
175 [MSTP303] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 3, 0),
176 [MSTP302] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 2, 0),
177 [MSTP301] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 1, 0),
178 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 0, 0),
179};
180
181static struct clk_lookup lookups[] = {
182 /* main clocks */
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("pll_clk", &pll_clk),
185
186 /* clocks */
187 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
188 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
189 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_M]),
190 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
191 CLKDEV_CON_ID("shyway_clk1", &div4_clks[DIV4_S1]),
192 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
193
194 /* MSTP32 clocks */
195 CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
196 CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
197 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]),
198 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
199 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]),
200 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]),
201 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]),
202 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]),
203 CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
204 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[MSTP016]),
205 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[MSTP016]),
206 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[MSTP016]),
207 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[MSTP015]),
208 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[MSTP015]),
209 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[MSTP015]),
210 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.6", &mstp_clks[MSTP014]),
211 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.7", &mstp_clks[MSTP014]),
212 CLKDEV_ICK_ID("tmu_fck", "sh_tmu.8", &mstp_clks[MSTP014]),
213 CLKDEV_CON_ID("ssi0", &mstp_clks[MSTP012]),
214 CLKDEV_CON_ID("ssi1", &mstp_clks[MSTP011]),
215 CLKDEV_CON_ID("ssi2", &mstp_clks[MSTP010]),
216 CLKDEV_CON_ID("ssi3", &mstp_clks[MSTP009]),
217 CLKDEV_CON_ID("sss", &mstp_clks[MSTP008]),
218 CLKDEV_CON_ID("hspi", &mstp_clks[MSTP007]),
219 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP100]),
220 CLKDEV_CON_ID("videoin0", &mstp_clks[MSTP109]),
221 CLKDEV_CON_ID("videoin1", &mstp_clks[MSTP108]),
222 CLKDEV_CON_ID("rgpvg", &mstp_clks[MSTP107]),
223 CLKDEV_CON_ID("2dg", &mstp_clks[MSTP106]),
224 CLKDEV_CON_ID("view", &mstp_clks[MSTP103]),
225
226 CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP331]),
227 CLKDEV_CON_ID("mimlb0", &mstp_clks[MSTP330]),
228 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP323]),
229 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP322]),
230 CLKDEV_CON_ID("sdhi2", &mstp_clks[MSTP321]),
231 CLKDEV_CON_ID("rqspi0", &mstp_clks[MSTP320]),
232 CLKDEV_CON_ID("src0", &mstp_clks[MSTP319]),
233 CLKDEV_CON_ID("src1", &mstp_clks[MSTP318]),
234 CLKDEV_CON_ID("rsp0", &mstp_clks[MSTP317]),
235 CLKDEV_CON_ID("rcan0", &mstp_clks[MSTP316]),
236 CLKDEV_CON_ID("rcan1", &mstp_clks[MSTP315]),
237 CLKDEV_CON_ID("fltcl0", &mstp_clks[MSTP314]),
238 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP313]),
239 CLKDEV_CON_ID("mtu0", &mstp_clks[MSTP312]),
240 CLKDEV_CON_ID("iebus0", &mstp_clks[MSTP304]),
241 CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[MSTP114]),
242 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP303]),
243 CLKDEV_CON_ID("hif0", &mstp_clks[MSTP302]),
244 CLKDEV_CON_ID("stif0", &mstp_clks[MSTP301]),
245 CLKDEV_CON_ID("stif1", &mstp_clks[MSTP300]),
246};
247
248int __init arch_clk_init(void)
249{
250 int i, ret = 0;
251
252 for (i = 0; i < ARRAY_SIZE(main_clks); i++)
253 ret |= clk_register(main_clks[i]);
254
255 for (i = 0; i < ARRAY_SIZE(lookups); i++)
256 clkdev_add(&lookups[i]);
257
258 if (!ret)
259 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
260 &div4_table);
261
262 if (!ret)
263 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
264
265 return ret;
266}
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c
new file mode 100644
index 000000000000..eed3b9d19d38
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7734.c
@@ -0,0 +1,2497 @@
1/*
2 * SH7734 processor support - PFC hardware block
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <linux/ioport.h>
15#include <cpu/sh7734.h>
16
17#define CPU_32_PORT(fn, pfx, sfx) \
18 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
19 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
20 PORT_1(fn, pfx##31, sfx)
21
22#define CPU_32_PORT5(fn, pfx, sfx) \
23 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
24 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
25 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
26 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
27 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \
28 PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx)
29
30/* GPSR0 - GPSR5 */
31#define CPU_ALL_PORT(fn, pfx, sfx) \
32 CPU_32_PORT(fn, pfx##_0_, sfx), \
33 CPU_32_PORT(fn, pfx##_1_, sfx), \
34 CPU_32_PORT(fn, pfx##_2_, sfx), \
35 CPU_32_PORT(fn, pfx##_3_, sfx), \
36 CPU_32_PORT(fn, pfx##_4_, sfx), \
37 CPU_32_PORT5(fn, pfx##_5_, sfx)
38
39#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
40#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
41 GP##pfx##_IN, GP##pfx##_OUT)
42
43#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
44#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
45
46#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
47#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
48#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
49
50#define PORT_10_REV(fn, pfx, sfx) \
51 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
52 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
53 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
54 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
55 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
56
57#define CPU_32_PORT_REV(fn, pfx, sfx) \
58 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
59 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
60 PORT_10_REV(fn, pfx, sfx)
61
62#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
63#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
64
65#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
66#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
67 FN_##ipsr, FN_##fn)
68
69enum {
70 PINMUX_RESERVED = 0,
71
72 PINMUX_DATA_BEGIN,
73 GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
74 PINMUX_DATA_END,
75
76 PINMUX_INPUT_BEGIN,
77 GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
78 PINMUX_INPUT_END,
79
80 PINMUX_OUTPUT_BEGIN,
81 GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
82 PINMUX_OUTPUT_END,
83
84 PINMUX_FUNCTION_BEGIN,
85 GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
86
87 /* GPSR0 */
88 FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
89 FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
90 FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
91 FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
92 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
93 FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
94 FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
95 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
96
97 /* GPSR1 */
98 FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
99 FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
100 FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
101 FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
102 FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
103 FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
104 FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
105 FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
106
107 /* GPSR2 */
108 FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
109 FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
110 FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
111 FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
112 FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
113 FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
114 FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
115 FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
116
117 /* GPSR3 */
118 FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
119 FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
120 FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
121 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
122 FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
123 FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
124 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
125 FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
126
127 /* GPSR4 */
128 FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
129 FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
130 FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
131 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
132 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
133 FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
134 FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
135 FN_USB_OVC0, FN_IP11_18_16,
136 FN_IP10_22, FN_IP10_24_23,
137
138 /* GPSR5 */
139 FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
140 FN_IP10_27_26, /* 10 */
141 FN_IP10_29_28, /* 11 */
142
143 /* IPSR0 */
144 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
145 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
146 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
147 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
148 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
149 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
150 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
151 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
152 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
153 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
154 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
155 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
156 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
157 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
158 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
159 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
160
161 /* IPSR1 */
162 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
163 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
164 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
165 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
166 FN_A25, FN_TX2_D, FN_ST1_D2,
167 FN_A24, FN_RX2_D, FN_ST1_D1,
168 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
169 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
170 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
171 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
172 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
173 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
174 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
175 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
176
177 /* IPSR2 */
178 FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
179 FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B,
180 FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
181 FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
182 FN_ET0_ETXD3_B,
183 FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
184 FN_ET0_ETXD2_B,
185 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
186 FN_ET0_ETXD1_B,
187 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
188 FN_ET0_GTX_CLK_B,
189 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
190 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
191 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
192 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
193
194 /* IPSR3 */
195 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
196 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
197 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
198 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
199 FN_ET0_LINK_C, FN_ET0_ETXD5_A,
200 FN_EX_WAIT0, FN_TCLK1_B,
201 FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
202 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
203 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
204 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
205 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
206 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
207 FN_CS1_A26, FN_QIO3_B,
208 FN_D15, FN_SCK2_B,
209
210 /* IPSR4 */
211 FN_SCK2_A, FN_VI0_G3,
212 FN_RTS1_B, FN_VI0_G2,
213 FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
214 FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
215 FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
216 FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
217 FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
218 FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
219 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
220 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
221 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
222 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
223 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
224
225 /* IPSR5 */
226 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
227 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
228 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
229 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
230 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
231 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
232 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
233 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
234 FN_REF125CK, FN_ADTRG, FN_RX5_C,
235 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
236
237 /* IPSR6 */
238 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
239 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
240 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
241 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
242 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
243 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
244 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
245 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
246 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
247 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
248
249 /* IPSR7 */
250 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
251 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
252 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
253 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
254 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
255 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
256 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
257 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
258 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
259 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
260 FN_DU0_DB4, FN_HIFINT,
261
262 /* IPSR8 */
263 FN_DU0_DB5, FN_HIFDREQ,
264 FN_DU0_DB6, FN_HIFRDY,
265 FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
266 FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
267 FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
268 FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
269 FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
270 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
271 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
272 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
273 FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
274 FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
275 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
276 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
277
278 /* IPSR9 */
279 FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
280 FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
281 FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
282 FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
283 FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
284 FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
285 FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
286 FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
287 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
288 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
289 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
290 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
291 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
292 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
293 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
294
295 /* IPSR10 */
296 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
297 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
298 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
299 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
300 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
301 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
302 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
303 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
304 FN_CAN_CLK_A, FN_RX4_D,
305 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
306 FN_CAN1_RX_A, FN_IRQ1_B,
307 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
308 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
309
310 /* IPSR11 */
311 FN_SCL1, FN_SCIF_CLK_C,
312 FN_SDA1, FN_RX1_E,
313 FN_SDA0, FN_HIFEBL_A,
314 FN_SDSELF, FN_RTS1_E,
315 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
316 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
317 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
318 FN_TX0_A, FN_HSPI_TX_A,
319 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
320 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
321 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
322 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
323 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
324 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
325 FN_PRESETOUT, FN_ST_CLKOUT,
326
327 /* MOD_SEL1 */
328 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
329 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
330 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
331 FN_SEL_HIF_0, FN_SEL_HIF_1,
332 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
333 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
334 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
335 FN_SEL_ET0_0, FN_SEL_ET0_1,
336 FN_SEL_RMII_0, FN_SEL_RMII_1,
337 FN_SEL_TMU_0, FN_SEL_TMU_1,
338 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
339 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
340 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
341 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
342 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
343 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
344 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
345 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
346 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
347 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
348 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
349 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
350 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
351 FN_SEL_MMC_0, FN_SEL_MMC_1,
352 FN_SEL_INTC_0, FN_SEL_INTC_1,
353
354 /* MOD_SEL2 */
355 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
356 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
357 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
358 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
359 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
360 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
361 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
362 FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
363 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
364 FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
365 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
366 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
367 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
368 FN_SEL_SCIF2_3,
369 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
370 FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
371 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
372 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
373
374 PINMUX_FUNCTION_END,
375
376 PINMUX_MARK_BEGIN,
377
378 CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
379 WE0_MARK, WE1_MARK,
380
381 SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
382
383 IRQ2_B_MARK, IRQ3_B_MARK,
384
385 /* IPSR0 */
386 A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
387 A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
388 A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
389 A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
390 A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
391 A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
392 A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
393 A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
394 A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
395 A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
396 A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
397 A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
398 A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
399 A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
400 A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
401 A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
402
403 /* IPSR1 */
404 D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
405 D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
406 D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
407 D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
408 A25_MARK, TX2_D_MARK, ST1_D2_MARK,
409 A24_MARK, RX2_D_MARK, ST1_D1_MARK,
410 A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
411 A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
412 A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
413 A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
414 A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK,
415 A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
416 A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
417 A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
418
419 /* IPSR2 */
420 D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
421 D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
422 D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
423 D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
424 ET0_ETXD3_B_MARK,
425 D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
426 ET0_ETXD2_B_MARK,
427 D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
428 FCLE_A_MARK, ET0_ETXD1_B_MARK,
429 D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
430 FCE_A_MARK, ET0_GTX_CLK_B_MARK,
431 D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
432 FD7_A_MARK,
433 D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
434 FD6_A_MARK,
435 D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
436 D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
437 FD4_A_MARK,
438
439 /* IPSR3 */
440 DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
441 EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
442 ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
443 EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
444 ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
445 EX_WAIT0_MARK, TCLK1_B_MARK,
446 RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
447 EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
448 ET0_ETXD3_A_MARK,
449 EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
450 ET0_ETXD2_A_MARK,
451 EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
452 ET0_ETXD1_A_MARK,
453 EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
454 ET0_GTX_CLK_A_MARK,
455 EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
456 ET0_ETXD0_MARK,
457 CS1_A26_MARK, QIO3_B_MARK,
458 D15_MARK, SCK2_B_MARK,
459
460 /* IPSR4 */
461 SCK2_A_MARK, VI0_G3_MARK,
462 RTS1_B_MARK, VI0_G2_MARK,
463 CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
464 TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
465 RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
466 SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
467 RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
468 CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
469 ET0_MDC_MARK,
470 HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
471 RMII0_MDC_A_MARK, ET0_COL_MARK,
472 HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
473 RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
474 HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
475 RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
476 HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
477 RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
478 HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
479 RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
480
481 /* IPSR5 */
482 SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
483 SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
484 SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
485 SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
486 SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
487 SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
488 SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
489 SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
490 REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
491 REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
492
493 /* IPSR6 */
494 DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
495 TCLKA_A_MARK, HIFD00_MARK,
496 DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
497 TCLKB_A_MARK, HIFD01_MARK,
498 DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
499 DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
500 DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
501 DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
502 DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
503 DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
504 DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
505 TIOC1A_A_MARK, HIFD08_MARK,
506 DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
507 HIFD09_MARK,
508
509 /* IPSR7 */
510 DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
511 HIFD10_MARK,
512 DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
513 HIFD11_MARK,
514 DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
515 HIFD12_MARK,
516 DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
517 HIFD13_MARK,
518 DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
519 HIFD14_MARK,
520 DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
521 HIFD15_MARK,
522 DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
523 HIFCS_MARK,
524 DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
525 HIFRS_MARK,
526 DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
527 HIFWR_MARK,
528 DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
529 DU0_DB4_MARK, HIFINT_MARK,
530
531 /* IPSR8 */
532 DU0_DB5_MARK, HIFDREQ_MARK,
533 DU0_DB6_MARK, HIFRDY_MARK,
534 DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
535 DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
536 DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
537 DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
538 DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
539 DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
540 SSI_SDATA1_B_MARK,
541 DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
542 DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
543 IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
544 IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
545 IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
546 IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
547
548 /* IPSR9 */
549 VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
550 VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
551 VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
552 VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
553 VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
554 VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
555 VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
556 VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
557 VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
558 SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
559 SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
560 SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
561 SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
562 SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
563 SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
564
565 /* IPSR10 */
566 SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
567 LCD_DATA15_B_MARK,
568 SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
569 FALE_B_MARK, LCD_DON_B_MARK,
570 SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
571 LCD_CL1_B_MARK,
572 SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
573 LCD_CL2_B_MARK,
574 AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
575 LCD_FLM_B_MARK,
576 AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
577 AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
578 LCD_VEPWC_B_MARK,
579 AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
580 LCD_M_DISP_B_MARK,
581 CAN_CLK_A_MARK, RX4_D_MARK,
582 CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
583 CAN1_RX_A_MARK, IRQ1_B_MARK,
584 CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
585 CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
586
587 /* IPSR11 */
588 SCL1_MARK, SCIF_CLK_C_MARK,
589 SDA1_MARK, RX1_E_MARK,
590 SDA0_MARK, HIFEBL_A_MARK,
591 SDSELF_MARK, RTS1_E_MARK,
592 SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
593 ET0_ERXD4_MARK,
594 SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
595 ET0_ERXD5_MARK,
596 RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
597 TX0_A_MARK, HSPI_TX_A_MARK,
598 PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
599 IETX_B_MARK,
600 USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
601 IERX_B_MARK,
602 DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
603 DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
604 DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
605 ET0_TX_CLK_A_MARK,
606 DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
607 PRESETOUT_MARK, ST_CLKOUT_MARK,
608
609 PINMUX_MARK_END,
610};
611
612static pinmux_enum_t pinmux_data[] = {
613 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
614
615 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
616 PINMUX_DATA(BS_MARK, FN_BS), PINMUX_DATA(CS0_MARK, FN_CS0),
617 PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
618 PINMUX_DATA(RD_MARK, FN_RD), PINMUX_DATA(WE0_MARK, FN_WE0),
619 PINMUX_DATA(WE1_MARK, FN_WE1),
620 PINMUX_DATA(SCL0_MARK, FN_SCL0), PINMUX_DATA(PENC0_MARK, FN_PENC0),
621 PINMUX_DATA(USB_OVC0_MARK, FN_USB_OVC0),
622 PINMUX_DATA(IRQ2_B_MARK, FN_IRQ2_B),
623 PINMUX_DATA(IRQ3_B_MARK, FN_IRQ3_B),
624
625 /* IPSR0 */
626 PINMUX_IPSR_DATA(IP0_1_0, A0),
627 PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
628 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
629 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
630
631 PINMUX_IPSR_DATA(IP0_3_2, A1),
632 PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
633 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
634 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
635
636 PINMUX_IPSR_DATA(IP0_5_4, A2),
637 PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
638 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
639 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
640
641 PINMUX_IPSR_DATA(IP0_7_6, A3),
642 PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
643 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
644 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
645
646 PINMUX_IPSR_DATA(IP0_9_8, A4),
647 PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
648 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
649 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
650
651 PINMUX_IPSR_DATA(IP0_11_10, A5),
652 PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
653 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
654 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
655
656 PINMUX_IPSR_DATA(IP0_13_12, A6),
657 PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
658 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
659 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
660
661 PINMUX_IPSR_DATA(IP0_15_14, A7),
662 PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
663 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
664 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
665
666 PINMUX_IPSR_DATA(IP0_17_16, A8),
667 PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
668 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
669 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
670
671 PINMUX_IPSR_DATA(IP0_19_18, A9),
672 PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
673 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
674 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
675
676 PINMUX_IPSR_DATA(IP0_21_20, A10),
677 PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
678 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
679 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
680
681 PINMUX_IPSR_DATA(IP0_23_22, A11),
682 PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
683 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
684 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
685
686 PINMUX_IPSR_DATA(IP0_25_24, A12),
687 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
688 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
689
690 PINMUX_IPSR_DATA(IP0_27_26, A13),
691 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
692 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
693
694 PINMUX_IPSR_DATA(IP0_29_28, A14),
695 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
696 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
697
698 PINMUX_IPSR_DATA(IP0_31_30, A15),
699 PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
700 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
701 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
702
703
704 /* IPSR1 */
705 PINMUX_IPSR_DATA(IP1_1_0, A16),
706 PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
707 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
708 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
709
710 PINMUX_IPSR_DATA(IP1_3_2, A17),
711 PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
712 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
713 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
714
715 PINMUX_IPSR_DATA(IP1_5_4, A18),
716 PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
717 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
718 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
719
720 PINMUX_IPSR_DATA(IP1_7_6, A19),
721 PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
722 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
723 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
724
725 PINMUX_IPSR_DATA(IP1_9_8, A20),
726 PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
727 PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
728
729 PINMUX_IPSR_DATA(IP1_11_10, A21),
730 PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
731 PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
732
733 PINMUX_IPSR_DATA(IP1_13_12, A22),
734 PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
735 PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
736
737 PINMUX_IPSR_DATA(IP1_15_14, A23),
738 PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
739 PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
740
741 PINMUX_IPSR_DATA(IP1_17_16, A24),
742 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
743 PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
744
745 PINMUX_IPSR_DATA(IP1_19_18, A25),
746 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3),
747 PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
748
749 PINMUX_IPSR_DATA(IP1_22_20, D0),
750 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
751 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0),
752 PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
753 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0),
754
755 PINMUX_IPSR_DATA(IP1_25_23, D1),
756 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
757 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0),
758 PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
759 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0),
760
761 PINMUX_IPSR_DATA(IP1_28_26, D2),
762 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
763 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0),
764 PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
765 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0),
766
767 PINMUX_IPSR_DATA(IP1_31_29, D3),
768 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
769 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0),
770 PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
771 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0),
772
773 /* IPSR2 */
774 PINMUX_IPSR_DATA(IP2_2_0, D4),
775 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
776 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0),
777 PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
778 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0),
779
780 PINMUX_IPSR_DATA(IP2_4_3, D5),
781 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0),
783 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0),
784
785 PINMUX_IPSR_DATA(IP2_7_5, D6),
786 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0),
788 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
789 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0),
790
791 PINMUX_IPSR_DATA(IP2_10_8, D7),
792 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
793 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0),
794 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0),
795 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0),
796
797 PINMUX_IPSR_DATA(IP2_13_11, D8),
798 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
799 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
800 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0),
801 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0),
802 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
803
804 PINMUX_IPSR_DATA(IP2_16_14, D9),
805 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
806 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
807 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0),
808 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0),
809 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
810
811 PINMUX_IPSR_DATA(IP2_19_17, D10),
812 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
813 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
814 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0),
815 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
816
817 PINMUX_IPSR_DATA(IP2_22_20, D11),
818 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
819 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
820 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0),
821
822 PINMUX_IPSR_DATA(IP2_24_23, D12),
823 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0),
824 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
825
826 PINMUX_IPSR_DATA(IP2_27_25, D13),
827 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1),
828 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0),
829 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
830
831 PINMUX_IPSR_DATA(IP2_30_28, D14),
832 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1),
833 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0),
834 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
835
836 /* IPSR3 */
837 PINMUX_IPSR_DATA(IP3_1_0, D15),
838 PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1),
839
840 PINMUX_IPSR_DATA(IP3_2, CS1_A26),
841 PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1),
842
843 PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
844 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1),
845 PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
846 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1),
847 PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
848
849 PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
850 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1),
851 PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
852 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
853 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
854
855 PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
856 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
857 PINMUX_IPSR_DATA(IP3_11_9, ATARD),
858 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
859 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
860
861 PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
862 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
863 PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
864 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
865 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
866
867 PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
868 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
869 PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
870 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1),
871 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
872
873 PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
874 PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
875 PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
876 PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
877
878 PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
879 PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1),
880
881 PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
882 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
883 PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
884 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
885 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
886 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
887
888 PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
889 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
890 PINMUX_IPSR_DATA(IP3_26_24, DACK2),
891 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
892 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
893 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
894
895 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
896 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
897 PINMUX_IPSR_DATA(IP3_29_27, ATAG),
898 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0),
899 PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
900
901 /* IPSR4 */
902 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
903 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0),
904 PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
905 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
906 PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
907
908 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
909 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0),
910 PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
911 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
912 PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
913
914 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
915 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0),
916 PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
917 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
918 PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
919
920 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0),
921 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0),
922 PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
923 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
924 PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
925
926 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0),
927 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0),
928 PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
929 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
930 PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
931
932 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1),
933 PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
934 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
935 PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
936
937 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1),
938 PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
939 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
940
941 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1),
942 PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
943 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
944
945 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1),
946 PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
947 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
948
949 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1),
950 PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
951 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
952
953 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1),
954 PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
955
956 PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1),
957 PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
958
959 PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0),
960 PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
961
962 /* IPSR5 */
963 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
964 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0),
965 PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
966 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
967
968 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
969 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0),
970 PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
971 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
972
973 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
974 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0),
975 PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
976 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
977
978 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
979 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0),
980 PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
981 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
982
983 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
984 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0),
985 PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
986 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
987
988 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
989 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0),
990 PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
991 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
992
993 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
994 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0),
995 PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
996 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
997
998 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
999 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0),
1000 PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
1001
1002 PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
1003 PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
1004 PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2),
1005 PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
1006 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3),
1007 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
1008
1009 /* IPSR6 */
1010 PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
1011 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
1012 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0),
1014 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
1015 PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
1016
1017 PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3),
1020 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
1022 PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
1023
1024 PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
1025 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1),
1026 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
1027 PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
1028
1029 PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1),
1031 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
1032 PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
1033
1034 PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2),
1036 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1037 PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
1038
1039 PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
1040 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1041 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1042 PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
1043
1044 PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
1045 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1046 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1047 PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
1048
1049 PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
1050 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2),
1051 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1052 PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
1053
1054 PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
1055 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2),
1056 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1057 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1059 PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
1060
1061 PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
1062 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1063 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1064 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1065 PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
1066
1067 /* IPSR7 */
1068 PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
1069 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1070 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1071 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1072 PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
1073
1074 PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
1075 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1076 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1077 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1078 PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
1079
1080 PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
1081 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2),
1082 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1083 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1084 PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
1085
1086 PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1089 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1090 PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
1091
1092 PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2),
1094 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1096 PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
1097
1098 PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
1099 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2),
1100 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1101 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1102 PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
1103
1104 PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
1105 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2),
1106 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1107 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1108 PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
1109
1110 PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
1111 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2),
1112 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1113 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1114 PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
1115
1116 PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
1117 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1119 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1120
1121 PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
1122 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1),
1123 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1124 PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
1125
1126 PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
1127 PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
1128
1129 /* IPSR8 */
1130 PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
1131 PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
1132
1133 PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
1134 PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
1135
1136 PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1138 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1139
1140 PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1142 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1143
1144 PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1146 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1147
1148 PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1149 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1150 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1151
1152 PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1153 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1154 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1155
1156 PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1159 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1160
1161 PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
1162 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1163 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1164 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1165
1166 PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
1167 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1168 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1170
1171 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0),
1172 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1173 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4),
1174 PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
1175
1176 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0),
1177 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1178 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4),
1179 PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
1180
1181 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0),
1182 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1183 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1184 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1185
1186 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0),
1187 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1189 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1190
1191 /* IPSR9 */
1192 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1193 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1195
1196 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1197 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1),
1198 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1199
1200 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1203
1204 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1205 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1207
1208 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1209 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1211
1212 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1213 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1),
1214 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1215
1216 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1217 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1),
1218 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1219
1220 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1),
1222 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1223
1224 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1),
1226 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1227
1228 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1229 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1230 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1231
1232 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1233 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1234 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1235
1236 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1237 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1239 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1240
1241 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1243 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1244 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1245
1246 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1247 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1248 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1249
1250 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1251 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1252 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1253
1254 /* IPSE10 */
1255 PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1257 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1259 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1260
1261 PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
1262 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1263 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1265 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1),
1266 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1267
1268 PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1270 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1),
1272 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1273
1274 PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1276 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1277 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1279
1280 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1283 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1284 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1285
1286 PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1287 PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1288
1289 PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
1290 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1292 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1),
1293 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1294
1295 PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
1296 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1298 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1300
1301 PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1302 PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3),
1303
1304 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1305 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3),
1306 PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
1307
1308 PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1),
1310
1311 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1),
1313 PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
1314
1315 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2),
1317 PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
1318
1319 /* IPSR11 */
1320 PINMUX_IPSR_DATA(IP11_0, SCL1),
1321 PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1322
1323 PINMUX_IPSR_DATA(IP11_1, SDA1),
1324 PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4),
1325
1326 PINMUX_IPSR_DATA(IP11_2, SDA0),
1327 PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0),
1328
1329 PINMUX_IPSR_DATA(IP11_3, SDSELF),
1330 PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3),
1331
1332 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1334 PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
1335 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1336 PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
1337
1338 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1339 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1340 PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
1341 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1342 PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
1343
1344 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1346 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1347 PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
1348
1349 PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0),
1350 PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1351
1352 PINMUX_IPSR_DATA(IP11_15_13, PENC1),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3),
1354 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
1355 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3),
1356 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1),
1357
1358 PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3),
1360 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3),
1362 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1),
1363
1364 PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
1365 PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1366 PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
1367
1368 PINMUX_IPSR_DATA(IP11_22_21, DACK0),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1370 PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
1371
1372 PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1376 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1377
1378 PINMUX_IPSR_DATA(IP11_27_26, DACK1),
1379 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1),
1381 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1382
1383 PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
1384 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1385};
1386
1387static struct pinmux_gpio pinmux_gpios[] = {
1388 PINMUX_GPIO_GP_ALL(),
1389
1390 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1391 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1392 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
1393 GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
1394
1395 /* IPSR0 */
1396 GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
1397 GPIO_FN(TCLKA_C),
1398 GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
1399 GPIO_FN(TCLKB_C),
1400 GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
1401 GPIO_FN(TCLKC_C),
1402 GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
1403 GPIO_FN(TCLKD_C),
1404 GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
1405 GPIO_FN(TIOC0A_C),
1406 GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
1407 GPIO_FN(TIOC0B_C),
1408 GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
1409 GPIO_FN(TIOC0C_C),
1410 GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
1411 GPIO_FN(TIOC0D_C),
1412 GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
1413 GPIO_FN(TIOC1A_C),
1414 GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
1415 GPIO_FN(TIOC1B_C),
1416 GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
1417 GPIO_FN(TIOC2A_C),
1418 GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
1419 GPIO_FN(TIOC2B_C),
1420 GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
1421 GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
1422 GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
1423 GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
1424 GPIO_FN(TIOC3D_C),
1425
1426 /* IPSR1 */
1427 GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
1428 GPIO_FN(TIOC4A_C),
1429 GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
1430 GPIO_FN(TIOC4B_C),
1431 GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
1432 GPIO_FN(TIOC4C_C),
1433 GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
1434 GPIO_FN(TIOC4D_C),
1435 GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
1436 GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
1437 GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
1438 GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
1439 GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
1440 GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
1441 GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
1442 GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
1443 GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
1444 GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
1445 GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
1446 GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
1447 GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
1448 GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
1449
1450 /* IPSR2 */
1451 GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
1452 GPIO_FN(FD4_A),
1453 GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
1454 GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
1455 GPIO_FN(QSPCLK_A),
1456 GPIO_FN(FD6_A),
1457 GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
1458 GPIO_FN(FD7_A),
1459 GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
1460 GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
1461 GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
1462 GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
1463 GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
1464 GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
1465 GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
1466 GPIO_FN(ET0_ETXD3_B),
1467 GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
1468 GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
1469 GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
1470
1471 /* IPSR3 */
1472 GPIO_FN(D15), GPIO_FN(SCK2_B),
1473 GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
1474 GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
1475 GPIO_FN(ET0_ETXD0),
1476 GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
1477 GPIO_FN(ET0_GTX_CLK_A),
1478 GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
1479 GPIO_FN(ET0_ETXD1_A),
1480 GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
1481 GPIO_FN(ET0_ETXD2_A),
1482 GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1483 GPIO_FN(ET0_ETXD3_A),
1484 GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
1485 GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1486 GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1487 GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
1488 GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
1489 GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
1490 GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
1491 GPIO_FN(ET0_ETXD7),
1492
1493 /* IPSR4 */
1494 GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
1495 GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
1496 GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
1497 GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
1498 GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
1499 GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
1500 GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
1501 GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
1502 GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
1503 GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
1504 GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
1505 GPIO_FN(ET0_MDC),
1506 GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
1507 GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
1508 GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
1509 GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
1510 GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
1511 GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
1512 GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
1513
1514 /* IPSR5 */
1515 GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
1516 GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
1517 GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
1518 GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
1519 GPIO_FN(ET0_PHY_INT_B),
1520 GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
1521 GPIO_FN(ET0_MAGIC_B),
1522 GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
1523 GPIO_FN(ET0_LINK_B),
1524 GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
1525 GPIO_FN(ET0_MDIO_B),
1526 GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
1527 GPIO_FN(ET0_ERXD3_B),
1528 GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
1529 GPIO_FN(ET0_ERXD2_B),
1530 GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
1531 GPIO_FN(ET0_RX_CLK_B),
1532
1533 /* IPSR6 */
1534 GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
1535 GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
1536 GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
1537 GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
1538 GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
1539 GPIO_FN(HIFD07),
1540 GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
1541 GPIO_FN(HIFD06),
1542 GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
1543 GPIO_FN(HIFD05),
1544 GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
1545 GPIO_FN(HIFD04),
1546 GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
1547 GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
1548 GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
1549 GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
1550 GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
1551 GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
1552
1553 /* IPSR7 */
1554 GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
1555 GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
1556 GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
1557 GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
1558 GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
1559 GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
1560 GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
1561 GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
1562 GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
1563 GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
1564 GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
1565 GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
1566 GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
1567 GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
1568 GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
1569 GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
1570 GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
1571 GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
1572 GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
1573 GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
1574
1575 /* IPSR8 */
1576 GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
1577 GPIO_FN(ET0_ERXD3_A),
1578 GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
1579 GPIO_FN(ET0_ERXD2_A),
1580 GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
1581 GPIO_FN(ET0_ERXD1),
1582 GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
1583 GPIO_FN(ET0_ERXD0),
1584 GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
1585 GPIO_FN(LCD_VCPWC_B),
1586 GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
1587 GPIO_FN(AUDIO_CLKA_B),
1588 GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
1589 GPIO_FN(SSI_SDATA1_B),
1590 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
1591 GPIO_FN(SSI_WS1_B),
1592 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
1593 GPIO_FN(SSI_SCK1_B),
1594 GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
1595 GPIO_FN(SSI_SDATA0_B),
1596 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
1597 GPIO_FN(SSI_WS0_B),
1598 GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
1599 GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
1600 GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
1601
1602 /* IPSR9 */
1603 GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
1604 GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
1605 GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
1606 GPIO_FN(LCD_DATA12_B),
1607 GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
1608 GPIO_FN(LCD_DATA11_B),
1609 GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
1610 GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
1611 GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
1612 GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
1613 GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
1614 GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
1615 GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
1616 GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
1617 GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
1618 GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
1619 GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
1620
1621 /* IPSR10 */
1622 GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
1623 GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
1624 GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
1625 GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
1626 GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
1627 GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
1628 GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
1629 GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
1630 GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
1631 GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
1632 GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
1633 GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
1634 GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
1635 GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
1636 GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
1637 GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
1638 GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
1639 GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
1640 GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
1641 GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
1642
1643 /* IPSR11 */
1644 GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
1645 GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
1646 GPIO_FN(ET0_RX_CLK_A),
1647 GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
1648 GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
1649 GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
1650 GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
1651 GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
1652 GPIO_FN(RX5_D), GPIO_FN(IERX_B),
1653 GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
1654 GPIO_FN(TX5_D), GPIO_FN(IETX_B),
1655 GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
1656 GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
1657 GPIO_FN(ET0_ERXD6),
1658 GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
1659 GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
1660 GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
1661 GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
1662 GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
1663 GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
1664 GPIO_FN(SDA1), GPIO_FN(RX1_E),
1665 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1666};
1667
1668static struct pinmux_cfg_reg pinmux_config_regs[] = {
1669 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1670 GP_0_31_FN, FN_IP2_2_0,
1671 GP_0_30_FN, FN_IP1_31_29,
1672 GP_0_29_FN, FN_IP1_28_26,
1673 GP_0_28_FN, FN_IP1_25_23,
1674 GP_0_27_FN, FN_IP1_22_20,
1675 GP_0_26_FN, FN_IP1_19_18,
1676 GP_0_25_FN, FN_IP1_17_16,
1677 GP_0_24_FN, FN_IP0_5_4,
1678 GP_0_23_FN, FN_IP0_3_2,
1679 GP_0_22_FN, FN_IP0_1_0,
1680 GP_0_21_FN, FN_IP11_28,
1681 GP_0_20_FN, FN_IP1_7_6,
1682 GP_0_19_FN, FN_IP1_5_4,
1683 GP_0_18_FN, FN_IP1_3_2,
1684 GP_0_17_FN, FN_IP1_1_0,
1685 GP_0_16_FN, FN_IP0_31_30,
1686 GP_0_15_FN, FN_IP0_29_28,
1687 GP_0_14_FN, FN_IP0_27_26,
1688 GP_0_13_FN, FN_IP0_25_24,
1689 GP_0_12_FN, FN_IP0_23_22,
1690 GP_0_11_FN, FN_IP0_21_20,
1691 GP_0_10_FN, FN_IP0_19_18,
1692 GP_0_9_FN, FN_IP0_17_16,
1693 GP_0_8_FN, FN_IP0_15_14,
1694 GP_0_7_FN, FN_IP0_13_12,
1695 GP_0_6_FN, FN_IP0_11_10,
1696 GP_0_5_FN, FN_IP0_9_8,
1697 GP_0_4_FN, FN_IP0_7_6,
1698 GP_0_3_FN, FN_IP1_15_14,
1699 GP_0_2_FN, FN_IP1_13_12,
1700 GP_0_1_FN, FN_IP1_11_10,
1701 GP_0_0_FN, FN_IP1_9_8 }
1702 },
1703 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) {
1704 GP_1_31_FN, FN_IP11_25_23,
1705 GP_1_30_FN, FN_IP2_13_11,
1706 GP_1_29_FN, FN_IP2_10_8,
1707 GP_1_28_FN, FN_IP2_7_5,
1708 GP_1_27_FN, FN_IP3_26_24,
1709 GP_1_26_FN, FN_IP3_23_21,
1710 GP_1_25_FN, FN_IP2_4_3,
1711 GP_1_24_FN, FN_WE1,
1712 GP_1_23_FN, FN_WE0,
1713 GP_1_22_FN, FN_IP3_19_18,
1714 GP_1_21_FN, FN_RD,
1715 GP_1_20_FN, FN_IP3_17_15,
1716 GP_1_19_FN, FN_IP3_14_12,
1717 GP_1_18_FN, FN_IP3_11_9,
1718 GP_1_17_FN, FN_IP3_8_6,
1719 GP_1_16_FN, FN_IP3_5_3,
1720 GP_1_15_FN, FN_EX_CS0,
1721 GP_1_14_FN, FN_IP3_2,
1722 GP_1_13_FN, FN_CS0,
1723 GP_1_12_FN, FN_BS,
1724 GP_1_11_FN, FN_CLKOUT,
1725 GP_1_10_FN, FN_IP3_1_0,
1726 GP_1_9_FN, FN_IP2_30_28,
1727 GP_1_8_FN, FN_IP2_27_25,
1728 GP_1_7_FN, FN_IP2_24_23,
1729 GP_1_6_FN, FN_IP2_22_20,
1730 GP_1_5_FN, FN_IP2_19_17,
1731 GP_1_4_FN, FN_IP2_16_14,
1732 GP_1_3_FN, FN_IP11_22_21,
1733 GP_1_2_FN, FN_IP11_20_19,
1734 GP_1_1_FN, FN_IP3_29_27,
1735 GP_1_0_FN, FN_IP3_20 }
1736 },
1737 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) {
1738 GP_2_31_FN, FN_IP4_31_30,
1739 GP_2_30_FN, FN_IP5_2_0,
1740 GP_2_29_FN, FN_IP5_5_3,
1741 GP_2_28_FN, FN_IP5_8_6,
1742 GP_2_27_FN, FN_IP5_11_9,
1743 GP_2_26_FN, FN_IP5_14_12,
1744 GP_2_25_FN, FN_IP5_17_15,
1745 GP_2_24_FN, FN_IP5_20_18,
1746 GP_2_23_FN, FN_IP5_22_21,
1747 GP_2_22_FN, FN_IP5_24_23,
1748 GP_2_21_FN, FN_IP5_26_25,
1749 GP_2_20_FN, FN_IP4_29_28,
1750 GP_2_19_FN, FN_IP4_27_26,
1751 GP_2_18_FN, FN_IP4_25_24,
1752 GP_2_17_FN, FN_IP4_23_22,
1753 GP_2_16_FN, FN_IP4_21_20,
1754 GP_2_15_FN, FN_IP4_19_18,
1755 GP_2_14_FN, FN_IP4_17_15,
1756 GP_2_13_FN, FN_IP4_14_12,
1757 GP_2_12_FN, FN_IP4_11_9,
1758 GP_2_11_FN, FN_IP4_8_6,
1759 GP_2_10_FN, FN_IP4_5_3,
1760 GP_2_9_FN, FN_IP8_27_26,
1761 GP_2_8_FN, FN_IP11_12,
1762 GP_2_7_FN, FN_IP8_25_23,
1763 GP_2_6_FN, FN_IP8_22_20,
1764 GP_2_5_FN, FN_IP11_27_26,
1765 GP_2_4_FN, FN_IP8_29_28,
1766 GP_2_3_FN, FN_IP4_2_0,
1767 GP_2_2_FN, FN_IP11_11_10,
1768 GP_2_1_FN, FN_IP11_9_7,
1769 GP_2_0_FN, FN_IP11_6_4 }
1770 },
1771 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) {
1772 GP_3_31_FN, FN_IP9_1_0,
1773 GP_3_30_FN, FN_IP8_19_18,
1774 GP_3_29_FN, FN_IP8_17_16,
1775 GP_3_28_FN, FN_IP8_15_14,
1776 GP_3_27_FN, FN_IP8_13_12,
1777 GP_3_26_FN, FN_IP8_11_10,
1778 GP_3_25_FN, FN_IP8_9_8,
1779 GP_3_24_FN, FN_IP8_7_6,
1780 GP_3_23_FN, FN_IP8_5_4,
1781 GP_3_22_FN, FN_IP8_3_2,
1782 GP_3_21_FN, FN_IP8_1_0,
1783 GP_3_20_FN, FN_IP7_30_29,
1784 GP_3_19_FN, FN_IP7_28_27,
1785 GP_3_18_FN, FN_IP7_26_24,
1786 GP_3_17_FN, FN_IP7_23_21,
1787 GP_3_16_FN, FN_IP7_20_18,
1788 GP_3_15_FN, FN_IP7_17_15,
1789 GP_3_14_FN, FN_IP7_14_12,
1790 GP_3_13_FN, FN_IP7_11_9,
1791 GP_3_12_FN, FN_IP7_8_6,
1792 GP_3_11_FN, FN_IP7_5_3,
1793 GP_3_10_FN, FN_IP7_2_0,
1794 GP_3_9_FN, FN_IP6_23_21,
1795 GP_3_8_FN, FN_IP6_20_18,
1796 GP_3_7_FN, FN_IP6_17_16,
1797 GP_3_6_FN, FN_IP6_15_14,
1798 GP_3_5_FN, FN_IP6_13_12,
1799 GP_3_4_FN, FN_IP6_11_10,
1800 GP_3_3_FN, FN_IP6_9_8,
1801 GP_3_2_FN, FN_IP6_7_6,
1802 GP_3_1_FN, FN_IP6_5_3,
1803 GP_3_0_FN, FN_IP6_2_0 }
1804 },
1805
1806 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) {
1807 GP_4_31_FN, FN_IP10_24_23,
1808 GP_4_30_FN, FN_IP10_22,
1809 GP_4_29_FN, FN_IP11_18_16,
1810 GP_4_28_FN, FN_USB_OVC0,
1811 GP_4_27_FN, FN_IP11_15_13,
1812 GP_4_26_FN, FN_PENC0,
1813 GP_4_25_FN, FN_IP11_2,
1814 GP_4_24_FN, FN_SCL0,
1815 GP_4_23_FN, FN_IP11_1,
1816 GP_4_22_FN, FN_IP11_0,
1817 GP_4_21_FN, FN_IP10_21_19,
1818 GP_4_20_FN, FN_IP10_18_16,
1819 GP_4_19_FN, FN_IP10_15,
1820 GP_4_18_FN, FN_IP10_14_12,
1821 GP_4_17_FN, FN_IP10_11_9,
1822 GP_4_16_FN, FN_IP10_8_6,
1823 GP_4_15_FN, FN_IP10_5_3,
1824 GP_4_14_FN, FN_IP10_2_0,
1825 GP_4_13_FN, FN_IP9_29_28,
1826 GP_4_12_FN, FN_IP9_27_26,
1827 GP_4_11_FN, FN_IP9_9_8,
1828 GP_4_10_FN, FN_IP9_7_6,
1829 GP_4_9_FN, FN_IP9_5_4,
1830 GP_4_8_FN, FN_IP9_3_2,
1831 GP_4_7_FN, FN_IP9_17_16,
1832 GP_4_6_FN, FN_IP9_15_14,
1833 GP_4_5_FN, FN_IP9_13_12,
1834 GP_4_4_FN, FN_IP9_11_10,
1835 GP_4_3_FN, FN_IP9_25_24,
1836 GP_4_2_FN, FN_IP9_23_22,
1837 GP_4_1_FN, FN_IP9_21_20,
1838 GP_4_0_FN, FN_IP9_19_18 }
1839 },
1840 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) {
1841 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
1842 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
1843 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
1844 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
1845 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
1846 GP_5_11_FN, FN_IP10_29_28,
1847 GP_5_10_FN, FN_IP10_27_26,
1848 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
1849 0, 0, 0, 0, /* 5, 4 */
1850 GP_5_3_FN, FN_IRQ3_B,
1851 GP_5_2_FN, FN_IRQ2_B,
1852 GP_5_1_FN, FN_IP11_3,
1853 GP_5_0_FN, FN_IP10_25 }
1854 },
1855
1856 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1857 2, 2, 2, 2, 2, 2, 2, 2,
1858 2, 2, 2, 2, 2, 2, 2, 2) {
1859 /* IP0_31_30 [2] */
1860 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1861 FN_TIOC3D_C,
1862 /* IP0_29_28 [2] */
1863 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
1864 /* IP0_27_26 [2] */
1865 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
1866 /* IP0_25_24 [2] */
1867 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
1868 /* IP0_23_22 [2] */
1869 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
1870 /* IP0_21_20 [2] */
1871 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
1872 /* IP0_19_18 [2] */
1873 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
1874 /* IP0_17_16 [2] */
1875 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
1876 /* IP0_15_14 [2] */
1877 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
1878 /* IP0_13_12 [2] */
1879 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
1880 /* IP0_11_10 [2] */
1881 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
1882 /* IP0_9_8 [2] */
1883 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
1884 /* IP0_7_6 [2] */
1885 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
1886 /* IP0_5_4 [2] */
1887 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
1888 /* IP0_3_2 [2] */
1889 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1890 /* IP0_1_0 [2] */
1891 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C }
1892 },
1893 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1894 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
1895 /* IP1_31_29 [3] */
1896 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1897 FN_FD3_A, 0, 0, 0,
1898 /* IP1_28_26 [3] */
1899 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
1900 FN_FD2_A, 0, 0, 0,
1901 /* IP1_25_23 [3] */
1902 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
1903 FN_FD1_A, 0, 0, 0,
1904 /* IP1_22_20 [3] */
1905 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
1906 FN_FD0_A, 0, 0, 0,
1907 /* IP1_19_18 [2] */
1908 FN_A25, FN_TX2_D, FN_ST1_D2, 0,
1909 /* IP1_17_16 [2] */
1910 FN_A24, FN_RX2_D, FN_ST1_D1, 0,
1911 /* IP1_15_14 [2] */
1912 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
1913 /* IP1_13_12 [2] */
1914 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
1915 /* IP1_11_10 [2] */
1916 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
1917 /* IP1_9_8 [2] */
1918 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
1919 /* IP1_7_6 [2] */
1920 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
1921 /* IP1_5_4 [2] */
1922 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
1923 /* IP1_3_2 [2] */
1924 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
1925 /* IP1_1_0 [2] */
1926 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C }
1927 },
1928 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1929 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) {
1930 /* IP2_31 [1] */
1931 0, 0,
1932 /* IP2_30_28 [3] */
1933 FN_D14, FN_TX2_B, 0, FN_FSE_A,
1934 FN_ET0_TX_CLK_B, 0, 0, 0,
1935 /* IP2_27_25 [3] */
1936 FN_D13, FN_RX2_B, 0, FN_FRB_A,
1937 FN_ET0_ETXD6_B, 0, 0, 0,
1938 /* IP2_24_23 [2] */
1939 FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
1940 /* IP2_22_20 [3] */
1941 FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
1942 FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
1943 /* IP2_19_17 [3] */
1944 FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
1945 FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
1946 /* IP2_16_14 [3] */
1947 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
1948 FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
1949 /* IP2_13_11 [3] */
1950 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
1951 FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
1952 /* IP2_10_8 [3] */
1953 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
1954 FN_FD7_A, 0, 0, 0,
1955 /* IP2_7_5 [3] */
1956 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
1957 FN_FD6_A, 0, 0, 0,
1958 /* IP2_4_3 [2] */
1959 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1960 /* IP2_2_0 [3] */
1961 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1962 FN_FD4_A, 0, 0, 0 }
1963 },
1964 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1965 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) {
1966 /* IP3_31_30 [2] */
1967 0, 0, 0, 0,
1968 /* IP3_29_27 [3] */
1969 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
1970 FN_ET0_ETXD7, 0, 0, 0,
1971 /* IP3_26_24 [3] */
1972 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
1973 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
1974 /* IP3_23_21 [3] */
1975 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
1976 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
1977 /* IP3_20 [1] */
1978 FN_EX_WAIT0, FN_TCLK1_B,
1979 /* IP3_19_18 [2] */
1980 FN_RD_WR, FN_TCLK1_B, 0, 0,
1981 /* IP3_17_15 [3] */
1982 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1983 FN_ET0_ETXD3_A, 0, 0, 0,
1984 /* IP3_14_12 [3] */
1985 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
1986 FN_ET0_ETXD2_A, 0, 0, 0,
1987 /* IP3_11_9 [3] */
1988 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
1989 FN_ET0_ETXD1_A, 0, 0, 0,
1990 /* IP3_8_6 [3] */
1991 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
1992 FN_ET0_GTX_CLK_A, 0, 0, 0,
1993 /* IP3_5_3 [3] */
1994 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
1995 FN_ET0_ETXD0, 0, 0, 0,
1996 /* IP3_2 [1] */
1997 FN_CS1_A26, FN_QIO3_B,
1998 /* IP3_1_0 [2] */
1999 FN_D15, FN_SCK2_B, 0, 0 }
2000 },
2001 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2002 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) {
2003 /* IP4_31_30 [2] */
2004 0, FN_SCK2_A, FN_VI0_G3, 0,
2005 /* IP4_29_28 [2] */
2006 0, FN_RTS1_B, FN_VI0_G2, 0,
2007 /* IP4_27_26 [2] */
2008 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
2009 /* IP4_25_24 [2] */
2010 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
2011 /* IP4_23_22 [2] */
2012 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
2013 /* IP4_21_20 [2] */
2014 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
2015 /* IP4_19_18 [2] */
2016 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
2017 /* IP4_17_15 [3] */
2018 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
2019 FN_ET0_MDC, 0, 0, 0,
2020 /* IP4_14_12 [3] */
2021 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
2022 FN_ET0_COL, 0, 0, 0,
2023 /* IP4_11_9 [3] */
2024 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
2025 FN_ET0_CRS, 0, 0, 0,
2026 /* IP4_8_6 [3] */
2027 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
2028 FN_ET0_RX_ER, 0, 0, 0,
2029 /* IP4_5_3 [3] */
2030 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
2031 FN_ET0_RX_DV, 0, 0, 0,
2032 /* IP4_2_0 [3] */
2033 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2034 FN_ET0_ERXD7, 0, 0, 0 }
2035 },
2036 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2037 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) {
2038 /* IP5_31 [1] */
2039 0, 0,
2040 /* IP5_30 [1] */
2041 0, 0,
2042 /* IP5_29 [1] */
2043 0, 0,
2044 /* IP5_28 [1] */
2045 0, 0,
2046 /* IP5_27 [1] */
2047 0, 0,
2048 /* IP5_26_25 [2] */
2049 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
2050 /* IP5_24_23 [2] */
2051 FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
2052 /* IP5_22_21 [2] */
2053 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
2054 /* IP5_20_18 [3] */
2055 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
2056 0, 0, 0, FN_ET0_PHY_INT_B,
2057 /* IP5_17_15 [3] */
2058 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
2059 0, 0, 0, FN_ET0_MAGIC_B,
2060 /* IP5_14_12 [3] */
2061 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
2062 0, 0, 0, FN_ET0_LINK_B,
2063 /* IP5_11_9 [3] */
2064 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
2065 0, 0, 0, FN_ET0_MDIO_B,
2066 /* IP5_8_6 [3] */
2067 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
2068 0, 0, 0, FN_ET0_ERXD3_B,
2069 /* IP5_5_3 [3] */
2070 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
2071 0, 0, 0, FN_ET0_ERXD2_B,
2072 /* IP5_2_0 [3] */
2073 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2074 FN_ET0_RX_CLK_B, 0, 0, 0 }
2075 },
2076 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2077 1, 1, 1, 1, 1, 1, 1, 1,
2078 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) {
2079 /* IP5_31 [1] */
2080 0, 0,
2081 /* IP6_30 [1] */
2082 0, 0,
2083 /* IP6_29 [1] */
2084 0, 0,
2085 /* IP6_28 [1] */
2086 0, 0,
2087 /* IP6_27 [1] */
2088 0, 0,
2089 /* IP6_26 [1] */
2090 0, 0,
2091 /* IP6_25 [1] */
2092 0, 0,
2093 /* IP6_24 [1] */
2094 0, 0,
2095 /* IP6_23_21 [3] */
2096 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
2097 FN_HIFD09, 0, 0, 0,
2098 /* IP6_20_18 [3] */
2099 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
2100 FN_TIOC1A_A, FN_HIFD08, 0, 0,
2101 /* IP6_17_16 [2] */
2102 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
2103 /* IP6_15_14 [2] */
2104 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
2105 /* IP6_13_12 [2] */
2106 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
2107 /* IP6_11_10 [2] */
2108 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
2109 /* IP6_9_8 [2] */
2110 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
2111 /* IP6_7_6 [2] */
2112 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
2113 /* IP6_5_3 [3] */
2114 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
2115 FN_TCLKB_A, FN_HIFD01, 0, 0,
2116 /* IP6_2_0 [3] */
2117 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2118 FN_TCLKA_A, FN_HIFD00, 0, 0 }
2119 },
2120 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2121 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
2122 /* IP7_31 [1] */
2123 0, 0,
2124 /* IP7_30_29 [2] */
2125 FN_DU0_DB4, 0, FN_HIFINT, 0,
2126 /* IP7_28_27 [2] */
2127 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
2128 /* IP7_26_24 [3] */
2129 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
2130 FN_HIFWR, 0, 0, 0,
2131 /* IP7_23_21 [3] */
2132 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
2133 FN_HIFRS, 0, 0, 0,
2134 /* IP7_20_18 [3] */
2135 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
2136 FN_HIFCS, 0, 0, 0,
2137 /* IP7_17_15 [3] */
2138 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
2139 FN_HIFD15, 0, 0, 0,
2140 /* IP7_14_12 [3] */
2141 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
2142 FN_HIFD14, 0, 0, 0,
2143 /* IP7_11_9 [3] */
2144 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
2145 FN_HIFD13, 0, 0, 0,
2146 /* IP7_8_6 [3] */
2147 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
2148 FN_HIFD12, 0, 0, 0,
2149 /* IP7_5_3 [3] */
2150 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
2151 FN_HIFD11, 0, 0, 0,
2152 /* IP7_2_0 [3] */
2153 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2154 FN_HIFD10, 0, 0, 0 }
2155 },
2156 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2157 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
2158 /* IP9_31_30 [2] */
2159 0, 0, 0, 0,
2160 /* IP8_29_28 [2] */
2161 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
2162 /* IP8_27_26 [2] */
2163 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
2164 /* IP8_25_23 [3] */
2165 FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
2166 FN_ET0_ERXD1, 0, 0, 0,
2167 /* IP8_22_20 [3] */
2168 FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
2169 FN_ET0_ERXD0, 0, 0, 0,
2170 /* IP8_19_18 [2] */
2171 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
2172 /* IP8_17_16 [2] */
2173 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
2174 /* IP8_15_14 [2] */
2175 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
2176 FN_SSI_SDATA1_B,
2177 /* IP8_13_12 [2] */
2178 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
2179 /* IP8_11_10 [2] */
2180 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
2181 /* IP8_9_8 [2] */
2182 FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
2183 /* IP8_7_6 [2] */
2184 FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
2185 /* IP8_5_4 [2] */
2186 FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
2187 /* IP8_3_2 [2] */
2188 FN_DU0_DB6, 0, FN_HIFRDY, 0,
2189 /* IP8_1_0 [2] */
2190 FN_DU0_DB5, 0, FN_HIFDREQ, 0 }
2191 },
2192 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2193 2, 2, 2, 2, 2, 2, 2, 2,
2194 2, 2, 2, 2, 2, 2, 2, 2) {
2195 /* IP9_31_30 [2] */
2196 0, 0, 0, 0,
2197 /* IP9_29_28 [2] */
2198 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
2199 /* IP9_27_26 [2] */
2200 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
2201 /* IP9_25_24 [2] */
2202 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
2203 /* IP9_23_22 [2] */
2204 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
2205 /* IP9_21_20 [2] */
2206 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
2207 /* IP9_19_18 [2] */
2208 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
2209 /* IP9_17_16 [2] */
2210 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
2211 /* IP9_15_14 [2] */
2212 FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
2213 /* IP9_13_12 [2] */
2214 FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
2215 /* IP9_11_10 [2] */
2216 FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
2217 /* IP9_9_8 [2] */
2218 FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
2219 /* IP9_7_6 [2] */
2220 FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
2221 /* IP9_5_4 [2] */
2222 FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
2223 /* IP9_3_2 [2] */
2224 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2225 /* IP9_1_0 [2] */
2226 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B }
2227 },
2228 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2229 2, 2, 2, 1, 2, 1, 3,
2230 3, 1, 3, 3, 3, 3, 3) {
2231 /* IP9_31_30 [2] */
2232 0, 0, 0, 0,
2233 /* IP10_29_28 [2] */
2234 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
2235 /* IP10_27_26 [2] */
2236 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
2237 /* IP10_25 [1] */
2238 FN_CAN1_RX_A, FN_IRQ1_B,
2239 /* IP10_24_23 [2] */
2240 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
2241 /* IP10_22 [1] */
2242 FN_CAN_CLK_A, FN_RX4_D,
2243 /* IP10_21_19 [3] */
2244 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B,
2245 FN_LCD_M_DISP_B, 0, 0, 0,
2246 /* IP10_18_16 [3] */
2247 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B,
2248 FN_LCD_VEPWC_B, 0, 0, 0,
2249 /* IP10_15 [1] */
2250 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
2251 /* IP10_14_12 [3] */
2252 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
2253 FN_LCD_FLM_B, 0, 0, 0,
2254 /* IP10_11_9 [3] */
2255 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B,
2256 FN_LCD_CL2_B, 0, 0, 0,
2257 /* IP10_8_6 [3] */
2258 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B,
2259 FN_LCD_CL1_B, 0, 0, 0,
2260 /* IP10_5_3 [3] */
2261 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
2262 FN_LCD_DON_B, 0, 0, 0,
2263 /* IP10_2_0 [3] */
2264 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2265 FN_LCD_DATA15_B, 0, 0, 0 }
2266 },
2267 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2268 3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) {
2269 /* IP11_31_29 [3] */
2270 0, 0, 0, 0, 0, 0, 0, 0,
2271 /* IP11_28 [1] */
2272 FN_PRESETOUT, FN_ST_CLKOUT,
2273 /* IP11_27_26 [2] */
2274 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
2275 /* IP11_25_23 [3] */
2276 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
2277 FN_ET0_TX_CLK_A, 0, 0, 0,
2278 /* IP11_22_21 [2] */
2279 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
2280 /* IP11_20_19 [2] */
2281 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
2282 /* IP11_18_16 [3] */
2283 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
2284 FN_IERX_B, 0, 0, 0,
2285 /* IP11_15_13 [3] */
2286 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
2287 FN_IETX_B, 0, 0, 0,
2288 /* IP11_12 [1] */
2289 FN_TX0_A, FN_HSPI_TX_A,
2290 /* IP11_11_10 [2] */
2291 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
2292 /* IP11_9_7 [3] */
2293 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
2294 FN_ET0_ERXD5, 0, 0, 0,
2295 /* IP11_6_4 [3] */
2296 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
2297 FN_ET0_ERXD4, 0, 0, 0,
2298 /* IP11_3 [1] */
2299 FN_SDSELF, FN_RTS1_E,
2300 /* IP11_2 [1] */
2301 FN_SDA0, FN_HIFEBL_A,
2302 /* IP11_1 [1] */
2303 FN_SDA1, FN_RX1_E,
2304 /* IP11_0 [1] */
2305 FN_SCL1, FN_SCIF_CLK_C }
2306 },
2307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2308 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2,
2309 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
2310 /* SEL1_31_29 [3] */
2311 0, 0, 0, 0, 0, 0, 0, 0,
2312 /* SEL1_28 [1] */
2313 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
2314 /* SEL1_27 [1] */
2315 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
2316 /* SEL1_26 [1] */
2317 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
2318 /* SEL1_25 [1] */
2319 FN_SEL_HIF_0, FN_SEL_HIF_1,
2320 /* SEL1_24 [1] */
2321 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
2322 /* SEL1_23 [1] */
2323 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
2324 /* SEL1_22_21 [2] */
2325 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
2326 /* SEL1_20 [1] */
2327 FN_SEL_ET0_0, FN_SEL_ET0_1,
2328 /* SEL1_19 [1] */
2329 FN_SEL_RMII_0, FN_SEL_RMII_1,
2330 /* SEL1_18 [1] */
2331 FN_SEL_TMU_0, FN_SEL_TMU_1,
2332 /* SEL1_17_16 [2] */
2333 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
2334 /* SEL1_15_14 [2] */
2335 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
2336 /* SEL1_13 [1] */
2337 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
2338 /* SEL1_12_11 [2] */
2339 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
2340 /* SEL1_10 [1] */
2341 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
2342 /* SEL1_9 [1] */
2343 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
2344 /* SEL1_8 [1] */
2345 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
2346 /* SEL1_7 [1] */
2347 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
2348 /* SEL1_6 [1] */
2349 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
2350 /* SEL1_5 [1] */
2351 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
2352 /* SEL1_4 [1] */
2353 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
2354 /* SEL1_3 [1] */
2355 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
2356 /* SEL1_2 [1] */
2357 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
2358 /* SEL1_1 [1] */
2359 FN_SEL_MMC_0, FN_SEL_MMC_1,
2360 /* SEL1_0 [1] */
2361 FN_SEL_INTC_0, FN_SEL_INTC_1 }
2362 },
2363 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2364 1, 1, 1, 1, 1, 1, 1, 1,
2365 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) {
2366 /* SEL2_31 [1] */
2367 0, 0,
2368 /* SEL2_30 [1] */
2369 0, 0,
2370 /* SEL2_29 [1] */
2371 0, 0,
2372 /* SEL2_28 [1] */
2373 0, 0,
2374 /* SEL2_27 [1] */
2375 0, 0,
2376 /* SEL2_26 [1] */
2377 0, 0,
2378 /* SEL2_25 [1] */
2379 0, 0,
2380 /* SEL2_24 [1] */
2381 0, 0,
2382 /* SEL2_23 [1] */
2383 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
2384 /* SEL2_22 [1] */
2385 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
2386 /* SEL2_21 [1] */
2387 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
2388 /* SEL2_20_19 [2] */
2389 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
2390 /* SEL2_18_17 [2] */
2391 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
2392 /* SEL2_16 [1] */
2393 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
2394 /* SEL2_15_14 [2] */
2395 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2396 /* SEL2_13_12 [2] */
2397 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2398 /* SEL2_11_9 [3] */
2399 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2400 FN_SEL_SCIF3_4, 0, 0, 0,
2401 /* SEL2_8_7 [2] */
2402 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2403 /* SEL2_6_4 [3] */
2404 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
2405 FN_SEL_SCIF1_4, 0, 0, 0,
2406 /* SEL2_3_2 [2] */
2407 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2408 /* SEL2_1_0 [2] */
2409 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 }
2410 },
2411 /* GPIO 0 - 5*/
2412 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } },
2413 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } },
2414 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } },
2415 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } },
2416 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } },
2417 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) {
2418 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
2419 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
2420 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
2421 GP_5_11_IN, GP_5_11_OUT,
2422 GP_5_10_IN, GP_5_10_OUT,
2423 GP_5_9_IN, GP_5_9_OUT,
2424 GP_5_8_IN, GP_5_8_OUT,
2425 GP_5_7_IN, GP_5_7_OUT,
2426 GP_5_6_IN, GP_5_6_OUT,
2427 GP_5_5_IN, GP_5_5_OUT,
2428 GP_5_4_IN, GP_5_4_OUT,
2429 GP_5_3_IN, GP_5_3_OUT,
2430 GP_5_2_IN, GP_5_2_OUT,
2431 GP_5_1_IN, GP_5_1_OUT,
2432 GP_5_0_IN, GP_5_0_OUT }
2433 },
2434 { },
2435};
2436
2437static struct pinmux_data_reg pinmux_data_regs[] = {
2438 /* GPIO 0 - 5*/
2439 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
2440 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
2441 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } },
2442 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } },
2443 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } },
2444 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) {
2445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2446 0, 0, 0, 0,
2447 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2448 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2449 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
2450 },
2451 { },
2452};
2453
2454static struct resource sh7734_pfc_resources[] = {
2455 [0] = { /* PFC */
2456 .start = 0xFFFC0000,
2457 .end = 0xFFFC011C,
2458 .flags = IORESOURCE_MEM,
2459 },
2460 [1] = { /* GPIO */
2461 .start = 0xFFC40000,
2462 .end = 0xFFC4502B,
2463 .flags = IORESOURCE_MEM,
2464 }
2465};
2466
2467static struct pinmux_info sh7734_pinmux_info = {
2468 .name = "sh7734_pfc",
2469
2470 .resource = sh7734_pfc_resources,
2471 .num_resources = ARRAY_SIZE(sh7734_pfc_resources),
2472
2473 .unlock_reg = 0xFFFC0000,
2474
2475 .reserved_id = PINMUX_RESERVED,
2476 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2477 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2478 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2479 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2480 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2481
2482 .first_gpio = GPIO_GP_0_0,
2483 .last_gpio = GPIO_FN_ST_CLKOUT,
2484
2485 .gpios = pinmux_gpios,
2486 .cfg_regs = pinmux_config_regs,
2487 .data_regs = pinmux_data_regs,
2488
2489 .gpio_data = pinmux_data,
2490 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2491};
2492
2493static int __init plat_pinmux_setup(void)
2494{
2495 return register_pinmux(&sh7734_pinmux_info);
2496}
2497arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 1b8848317e9c..b91ea8300a3e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -13,6 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
16#include <asm/clock.h> 17#include <asm/clock.h>
17 18
18/* Serial */ 19/* Serial */
@@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_2, 24 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 25 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 26 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
26}; 27};
27 28
28static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
@@ -39,7 +40,7 @@ static struct plat_sci_port scif1_platform_data = {
39 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
40 .scbrr_algo_id = SCBRR_ALGO_2, 41 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF, 42 .type = PORT_SCIF,
42 .irqs = { 81, 81, 81, 81 }, 43 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
43}; 44};
44 45
45static struct platform_device scif1_device = { 46static struct platform_device scif1_device = {
@@ -56,7 +57,7 @@ static struct plat_sci_port scif2_platform_data = {
56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
57 .scbrr_algo_id = SCBRR_ALGO_2, 58 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 59 .type = PORT_SCIF,
59 .irqs = { 82, 82, 82, 82 }, 60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
60}; 61};
61 62
62static struct platform_device scif2_device = { 63static struct platform_device scif2_device = {
@@ -73,7 +74,7 @@ static struct plat_sci_port scif3_platform_data = {
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
74 .scbrr_algo_id = SCBRR_ALGO_2, 75 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF, 76 .type = PORT_SCIF,
76 .irqs = { 83, 83, 83, 83 }, 77 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)),
77}; 78};
78 79
79static struct platform_device scif3_device = { 80static struct platform_device scif3_device = {
@@ -92,8 +93,8 @@ static struct resource iic0_resources[] = {
92 .flags = IORESOURCE_MEM, 93 .flags = IORESOURCE_MEM,
93 }, 94 },
94 [1] = { 95 [1] = {
95 .start = 96, 96 .start = evt2irq(0xe00),
96 .end = 99, 97 .end = evt2irq(0xe60),
97 .flags = IORESOURCE_IRQ, 98 .flags = IORESOURCE_IRQ,
98 }, 99 },
99}; 100};
@@ -113,8 +114,8 @@ static struct resource iic1_resources[] = {
113 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
114 }, 115 },
115 [1] = { 116 [1] = {
116 .start = 44, 117 .start = evt2irq(0x780),
117 .end = 47, 118 .end = evt2irq(0x7e0),
118 .flags = IORESOURCE_IRQ, 119 .flags = IORESOURCE_IRQ,
119 }, 120 },
120}; 121};
@@ -129,7 +130,7 @@ static struct platform_device iic1_device = {
129static struct uio_info vpu_platform_data = { 130static struct uio_info vpu_platform_data = {
130 .name = "VPU4", 131 .name = "VPU4",
131 .version = "0", 132 .version = "0",
132 .irq = 60, 133 .irq = evt2irq(0x980),
133}; 134};
134 135
135static struct resource vpu_resources[] = { 136static struct resource vpu_resources[] = {
@@ -157,7 +158,7 @@ static struct platform_device vpu_device = {
157static struct uio_info veu_platform_data = { 158static struct uio_info veu_platform_data = {
158 .name = "VEU", 159 .name = "VEU",
159 .version = "0", 160 .version = "0",
160 .irq = 54, 161 .irq = evt2irq(0x8c0),
161}; 162};
162 163
163static struct resource veu_resources[] = { 164static struct resource veu_resources[] = {
@@ -185,7 +186,7 @@ static struct platform_device veu_device = {
185static struct uio_info jpu_platform_data = { 186static struct uio_info jpu_platform_data = {
186 .name = "JPU", 187 .name = "JPU",
187 .version = "0", 188 .version = "0",
188 .irq = 27, 189 .irq = evt2irq(0x560),
189}; 190};
190 191
191static struct resource jpu_resources[] = { 192static struct resource jpu_resources[] = {
@@ -224,7 +225,7 @@ static struct resource cmt_resources[] = {
224 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
225 }, 226 },
226 [1] = { 227 [1] = {
227 .start = 104, 228 .start = evt2irq(0xf00),
228 .flags = IORESOURCE_IRQ, 229 .flags = IORESOURCE_IRQ,
229 }, 230 },
230}; 231};
@@ -252,7 +253,7 @@ static struct resource tmu0_resources[] = {
252 .flags = IORESOURCE_MEM, 253 .flags = IORESOURCE_MEM,
253 }, 254 },
254 [1] = { 255 [1] = {
255 .start = 16, 256 .start = evt2irq(0x400),
256 .flags = IORESOURCE_IRQ, 257 .flags = IORESOURCE_IRQ,
257 }, 258 },
258}; 259};
@@ -280,7 +281,7 @@ static struct resource tmu1_resources[] = {
280 .flags = IORESOURCE_MEM, 281 .flags = IORESOURCE_MEM,
281 }, 282 },
282 [1] = { 283 [1] = {
283 .start = 17, 284 .start = evt2irq(0x420),
284 .flags = IORESOURCE_IRQ, 285 .flags = IORESOURCE_IRQ,
285 }, 286 },
286}; 287};
@@ -307,7 +308,7 @@ static struct resource tmu2_resources[] = {
307 .flags = IORESOURCE_MEM, 308 .flags = IORESOURCE_MEM,
308 }, 309 },
309 [1] = { 310 [1] = {
310 .start = 18, 311 .start = evt2irq(0x440),
311 .flags = IORESOURCE_IRQ, 312 .flags = IORESOURCE_IRQ,
312 }, 313 },
313}; 314};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 87773869a2f3..0bd09d51419f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -15,6 +15,7 @@
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
18#include <linux/usb/r8a66597.h> 19#include <linux/usb/r8a66597.h>
19#include <asm/clock.h> 20#include <asm/clock.h>
20 21
@@ -25,7 +26,7 @@ static struct plat_sci_port scif0_platform_data = {
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
26 .scbrr_algo_id = SCBRR_ALGO_2, 27 .scbrr_algo_id = SCBRR_ALGO_2,
27 .type = PORT_SCIF, 28 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 29 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
29}; 30};
30 31
31static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
@@ -44,8 +45,8 @@ static struct resource iic_resources[] = {
44 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
45 }, 46 },
46 [1] = { 47 [1] = {
47 .start = 96, 48 .start = evt2irq(0xe00),
48 .end = 99, 49 .end = evt2irq(0xe60),
49 .flags = IORESOURCE_IRQ, 50 .flags = IORESOURCE_IRQ,
50 }, 51 },
51}; 52};
@@ -68,8 +69,8 @@ static struct resource usb_host_resources[] = {
68 .flags = IORESOURCE_MEM, 69 .flags = IORESOURCE_MEM,
69 }, 70 },
70 [1] = { 71 [1] = {
71 .start = 65, 72 .start = evt2irq(0xa20),
72 .end = 65, 73 .end = evt2irq(0xa20),
73 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 74 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
74 }, 75 },
75}; 76};
@@ -89,7 +90,7 @@ static struct platform_device usb_host_device = {
89static struct uio_info vpu_platform_data = { 90static struct uio_info vpu_platform_data = {
90 .name = "VPU5", 91 .name = "VPU5",
91 .version = "0", 92 .version = "0",
92 .irq = 60, 93 .irq = evt2irq(0x980),
93}; 94};
94 95
95static struct resource vpu_resources[] = { 96static struct resource vpu_resources[] = {
@@ -117,7 +118,7 @@ static struct platform_device vpu_device = {
117static struct uio_info veu0_platform_data = { 118static struct uio_info veu0_platform_data = {
118 .name = "VEU", 119 .name = "VEU",
119 .version = "0", 120 .version = "0",
120 .irq = 54, 121 .irq = evt2irq(0x8c0),
121}; 122};
122 123
123static struct resource veu0_resources[] = { 124static struct resource veu0_resources[] = {
@@ -145,7 +146,7 @@ static struct platform_device veu0_device = {
145static struct uio_info veu1_platform_data = { 146static struct uio_info veu1_platform_data = {
146 .name = "VEU", 147 .name = "VEU",
147 .version = "0", 148 .version = "0",
148 .irq = 27, 149 .irq = evt2irq(0x560),
149}; 150};
150 151
151static struct resource veu1_resources[] = { 152static struct resource veu1_resources[] = {
@@ -184,7 +185,7 @@ static struct resource cmt_resources[] = {
184 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
185 }, 186 },
186 [1] = { 187 [1] = {
187 .start = 104, 188 .start = evt2irq(0xf00),
188 .flags = IORESOURCE_IRQ, 189 .flags = IORESOURCE_IRQ,
189 }, 190 },
190}; 191};
@@ -240,7 +241,7 @@ static struct resource tmu1_resources[] = {
240 .flags = IORESOURCE_MEM, 241 .flags = IORESOURCE_MEM,
241 }, 242 },
242 [1] = { 243 [1] = {
243 .start = 17, 244 .start = evt2irq(0x420),
244 .flags = IORESOURCE_IRQ, 245 .flags = IORESOURCE_IRQ,
245 }, 246 },
246}; 247};
@@ -267,7 +268,7 @@ static struct resource tmu2_resources[] = {
267 .flags = IORESOURCE_MEM, 268 .flags = IORESOURCE_MEM,
268 }, 269 },
269 [1] = { 270 [1] = {
270 .start = 18, 271 .start = evt2irq(0x440),
271 .flags = IORESOURCE_IRQ, 272 .flags = IORESOURCE_IRQ,
272 }, 273 },
273}; 274};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 8420d4bc8bfc..0f5a21907da6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,6 +13,7 @@
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
16#include <linux/uio_driver.h> 17#include <linux/uio_driver.h>
17#include <linux/usb/m66592.h> 18#include <linux/usb/m66592.h>
18 19
@@ -147,20 +148,20 @@ static struct resource sh7722_dmae_resources[] = {
147 }, 148 },
148 { 149 {
149 .name = "error_irq", 150 .name = "error_irq",
150 .start = 78, 151 .start = evt2irq(0xbc0),
151 .end = 78, 152 .end = evt2irq(0xbc0),
152 .flags = IORESOURCE_IRQ, 153 .flags = IORESOURCE_IRQ,
153 }, 154 },
154 { 155 {
155 /* IRQ for channels 0-3 */ 156 /* IRQ for channels 0-3 */
156 .start = 48, 157 .start = evt2irq(0x800),
157 .end = 51, 158 .end = evt2irq(0x860),
158 .flags = IORESOURCE_IRQ, 159 .flags = IORESOURCE_IRQ,
159 }, 160 },
160 { 161 {
161 /* IRQ for channels 4-5 */ 162 /* IRQ for channels 4-5 */
162 .start = 76, 163 .start = evt2irq(0xb80),
163 .end = 77, 164 .end = evt2irq(0xba0),
164 .flags = IORESOURCE_IRQ, 165 .flags = IORESOURCE_IRQ,
165 }, 166 },
166}; 167};
@@ -182,7 +183,7 @@ static struct plat_sci_port scif0_platform_data = {
182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
183 .scbrr_algo_id = SCBRR_ALGO_2, 184 .scbrr_algo_id = SCBRR_ALGO_2,
184 .type = PORT_SCIF, 185 .type = PORT_SCIF,
185 .irqs = { 80, 80, 80, 80 }, 186 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
186 .ops = &sh7722_sci_port_ops, 187 .ops = &sh7722_sci_port_ops,
187 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 188 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
188}; 189};
@@ -201,7 +202,7 @@ static struct plat_sci_port scif1_platform_data = {
201 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 202 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
202 .scbrr_algo_id = SCBRR_ALGO_2, 203 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF, 204 .type = PORT_SCIF,
204 .irqs = { 81, 81, 81, 81 }, 205 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
205 .ops = &sh7722_sci_port_ops, 206 .ops = &sh7722_sci_port_ops,
206 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 207 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
207}; 208};
@@ -220,7 +221,7 @@ static struct plat_sci_port scif2_platform_data = {
220 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 221 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
221 .scbrr_algo_id = SCBRR_ALGO_2, 222 .scbrr_algo_id = SCBRR_ALGO_2,
222 .type = PORT_SCIF, 223 .type = PORT_SCIF,
223 .irqs = { 82, 82, 82, 82 }, 224 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
224 .ops = &sh7722_sci_port_ops, 225 .ops = &sh7722_sci_port_ops,
225 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 226 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
226}; 227};
@@ -241,17 +242,17 @@ static struct resource rtc_resources[] = {
241 }, 242 },
242 [1] = { 243 [1] = {
243 /* Period IRQ */ 244 /* Period IRQ */
244 .start = 45, 245 .start = evt2irq(0x7a0),
245 .flags = IORESOURCE_IRQ, 246 .flags = IORESOURCE_IRQ,
246 }, 247 },
247 [2] = { 248 [2] = {
248 /* Carry IRQ */ 249 /* Carry IRQ */
249 .start = 46, 250 .start = evt2irq(0x7c0),
250 .flags = IORESOURCE_IRQ, 251 .flags = IORESOURCE_IRQ,
251 }, 252 },
252 [3] = { 253 [3] = {
253 /* Alarm IRQ */ 254 /* Alarm IRQ */
254 .start = 44, 255 .start = evt2irq(0x780),
255 .flags = IORESOURCE_IRQ, 256 .flags = IORESOURCE_IRQ,
256 }, 257 },
257}; 258};
@@ -275,8 +276,8 @@ static struct resource usbf_resources[] = {
275 .flags = IORESOURCE_MEM, 276 .flags = IORESOURCE_MEM,
276 }, 277 },
277 [1] = { 278 [1] = {
278 .start = 65, 279 .start = evt2irq(0xa20),
279 .end = 65, 280 .end = evt2irq(0xa20),
280 .flags = IORESOURCE_IRQ, 281 .flags = IORESOURCE_IRQ,
281 }, 282 },
282}; 283};
@@ -301,8 +302,8 @@ static struct resource iic_resources[] = {
301 .flags = IORESOURCE_MEM, 302 .flags = IORESOURCE_MEM,
302 }, 303 },
303 [1] = { 304 [1] = {
304 .start = 96, 305 .start = evt2irq(0xe00),
305 .end = 99, 306 .end = evt2irq(0xe60),
306 .flags = IORESOURCE_IRQ, 307 .flags = IORESOURCE_IRQ,
307 }, 308 },
308}; 309};
@@ -317,7 +318,7 @@ static struct platform_device iic_device = {
317static struct uio_info vpu_platform_data = { 318static struct uio_info vpu_platform_data = {
318 .name = "VPU4", 319 .name = "VPU4",
319 .version = "0", 320 .version = "0",
320 .irq = 60, 321 .irq = evt2irq(0x980),
321}; 322};
322 323
323static struct resource vpu_resources[] = { 324static struct resource vpu_resources[] = {
@@ -345,7 +346,7 @@ static struct platform_device vpu_device = {
345static struct uio_info veu_platform_data = { 346static struct uio_info veu_platform_data = {
346 .name = "VEU", 347 .name = "VEU",
347 .version = "0", 348 .version = "0",
348 .irq = 54, 349 .irq = evt2irq(0x8c0),
349}; 350};
350 351
351static struct resource veu_resources[] = { 352static struct resource veu_resources[] = {
@@ -373,7 +374,7 @@ static struct platform_device veu_device = {
373static struct uio_info jpu_platform_data = { 374static struct uio_info jpu_platform_data = {
374 .name = "JPU", 375 .name = "JPU",
375 .version = "0", 376 .version = "0",
376 .irq = 27, 377 .irq = evt2irq(0x560),
377}; 378};
378 379
379static struct resource jpu_resources[] = { 380static struct resource jpu_resources[] = {
@@ -412,7 +413,7 @@ static struct resource cmt_resources[] = {
412 .flags = IORESOURCE_MEM, 413 .flags = IORESOURCE_MEM,
413 }, 414 },
414 [1] = { 415 [1] = {
415 .start = 104, 416 .start = evt2irq(0xf00),
416 .flags = IORESOURCE_IRQ, 417 .flags = IORESOURCE_IRQ,
417 }, 418 },
418}; 419};
@@ -440,7 +441,7 @@ static struct resource tmu0_resources[] = {
440 .flags = IORESOURCE_MEM, 441 .flags = IORESOURCE_MEM,
441 }, 442 },
442 [1] = { 443 [1] = {
443 .start = 16, 444 .start = evt2irq(0x400),
444 .flags = IORESOURCE_IRQ, 445 .flags = IORESOURCE_IRQ,
445 }, 446 },
446}; 447};
@@ -468,7 +469,7 @@ static struct resource tmu1_resources[] = {
468 .flags = IORESOURCE_MEM, 469 .flags = IORESOURCE_MEM,
469 }, 470 },
470 [1] = { 471 [1] = {
471 .start = 17, 472 .start = evt2irq(0x420),
472 .flags = IORESOURCE_IRQ, 473 .flags = IORESOURCE_IRQ,
473 }, 474 },
474}; 475};
@@ -525,7 +526,7 @@ static struct resource siu_resources[] = {
525 .flags = IORESOURCE_MEM, 526 .flags = IORESOURCE_MEM,
526 }, 527 },
527 [1] = { 528 [1] = {
528 .start = 108, 529 .start = evt2irq(0xf80),
529 .flags = IORESOURCE_IRQ, 530 .flags = IORESOURCE_IRQ,
530 }, 531 },
531}; 532};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a188c9ea4393..28d6fd835fe0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -15,6 +15,7 @@
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/usb/r8a66597.h> 16#include <linux/usb/r8a66597.h>
17#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <asm/clock.h> 20#include <asm/clock.h>
20#include <asm/mmzone.h> 21#include <asm/mmzone.h>
@@ -28,7 +29,7 @@ static struct plat_sci_port scif0_platform_data = {
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2, 30 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF, 31 .type = PORT_SCIF,
31 .irqs = { 80, 80, 80, 80 }, 32 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 33 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
33}; 34};
34 35
@@ -47,7 +48,7 @@ static struct plat_sci_port scif1_platform_data = {
47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
48 .scbrr_algo_id = SCBRR_ALGO_2, 49 .scbrr_algo_id = SCBRR_ALGO_2,
49 .type = PORT_SCIF, 50 .type = PORT_SCIF,
50 .irqs = { 81, 81, 81, 81 }, 51 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 52 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
52}; 53};
53 54
@@ -66,7 +67,7 @@ static struct plat_sci_port scif2_platform_data = {
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2, 68 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 69 .type = PORT_SCIF,
69 .irqs = { 82, 82, 82, 82 }, 70 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 71 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
71}; 72};
72 73
@@ -85,7 +86,7 @@ static struct plat_sci_port scif3_platform_data = {
85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
86 .scbrr_algo_id = SCBRR_ALGO_3, 87 .scbrr_algo_id = SCBRR_ALGO_3,
87 .type = PORT_SCIFA, 88 .type = PORT_SCIFA,
88 .irqs = { 56, 56, 56, 56 }, 89 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
89}; 90};
90 91
91static struct platform_device scif3_device = { 92static struct platform_device scif3_device = {
@@ -103,7 +104,7 @@ static struct plat_sci_port scif4_platform_data = {
103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
104 .scbrr_algo_id = SCBRR_ALGO_3, 105 .scbrr_algo_id = SCBRR_ALGO_3,
105 .type = PORT_SCIFA, 106 .type = PORT_SCIFA,
106 .irqs = { 88, 88, 88, 88 }, 107 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)),
107}; 108};
108 109
109static struct platform_device scif4_device = { 110static struct platform_device scif4_device = {
@@ -121,7 +122,7 @@ static struct plat_sci_port scif5_platform_data = {
121 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
122 .scbrr_algo_id = SCBRR_ALGO_3, 123 .scbrr_algo_id = SCBRR_ALGO_3,
123 .type = PORT_SCIFA, 124 .type = PORT_SCIFA,
124 .irqs = { 109, 109, 109, 109 }, 125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
125}; 126};
126 127
127static struct platform_device scif5_device = { 128static struct platform_device scif5_device = {
@@ -135,7 +136,7 @@ static struct platform_device scif5_device = {
135static struct uio_info vpu_platform_data = { 136static struct uio_info vpu_platform_data = {
136 .name = "VPU5", 137 .name = "VPU5",
137 .version = "0", 138 .version = "0",
138 .irq = 60, 139 .irq = evt2irq(0x980),
139}; 140};
140 141
141static struct resource vpu_resources[] = { 142static struct resource vpu_resources[] = {
@@ -163,7 +164,7 @@ static struct platform_device vpu_device = {
163static struct uio_info veu0_platform_data = { 164static struct uio_info veu0_platform_data = {
164 .name = "VEU2H", 165 .name = "VEU2H",
165 .version = "0", 166 .version = "0",
166 .irq = 54, 167 .irq = evt2irq(0x8c0),
167}; 168};
168 169
169static struct resource veu0_resources[] = { 170static struct resource veu0_resources[] = {
@@ -191,7 +192,7 @@ static struct platform_device veu0_device = {
191static struct uio_info veu1_platform_data = { 192static struct uio_info veu1_platform_data = {
192 .name = "VEU2H", 193 .name = "VEU2H",
193 .version = "0", 194 .version = "0",
194 .irq = 27, 195 .irq = evt2irq(0x560),
195}; 196};
196 197
197static struct resource veu1_resources[] = { 198static struct resource veu1_resources[] = {
@@ -230,7 +231,7 @@ static struct resource cmt_resources[] = {
230 .flags = IORESOURCE_MEM, 231 .flags = IORESOURCE_MEM,
231 }, 232 },
232 [1] = { 233 [1] = {
233 .start = 104, 234 .start = evt2irq(0xf00),
234 .flags = IORESOURCE_IRQ, 235 .flags = IORESOURCE_IRQ,
235 }, 236 },
236}; 237};
@@ -258,7 +259,7 @@ static struct resource tmu0_resources[] = {
258 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
259 }, 260 },
260 [1] = { 261 [1] = {
261 .start = 16, 262 .start = evt2irq(0x400),
262 .flags = IORESOURCE_IRQ, 263 .flags = IORESOURCE_IRQ,
263 }, 264 },
264}; 265};
@@ -286,7 +287,7 @@ static struct resource tmu1_resources[] = {
286 .flags = IORESOURCE_MEM, 287 .flags = IORESOURCE_MEM,
287 }, 288 },
288 [1] = { 289 [1] = {
289 .start = 17, 290 .start = evt2irq(0x420),
290 .flags = IORESOURCE_IRQ, 291 .flags = IORESOURCE_IRQ,
291 }, 292 },
292}; 293};
@@ -313,7 +314,7 @@ static struct resource tmu2_resources[] = {
313 .flags = IORESOURCE_MEM, 314 .flags = IORESOURCE_MEM,
314 }, 315 },
315 [1] = { 316 [1] = {
316 .start = 18, 317 .start = evt2irq(0x440),
317 .flags = IORESOURCE_IRQ, 318 .flags = IORESOURCE_IRQ,
318 }, 319 },
319}; 320};
@@ -340,7 +341,7 @@ static struct resource tmu3_resources[] = {
340 .flags = IORESOURCE_MEM, 341 .flags = IORESOURCE_MEM,
341 }, 342 },
342 [1] = { 343 [1] = {
343 .start = 57, 344 .start = evt2irq(0x920),
344 .flags = IORESOURCE_IRQ, 345 .flags = IORESOURCE_IRQ,
345 }, 346 },
346}; 347};
@@ -367,7 +368,7 @@ static struct resource tmu4_resources[] = {
367 .flags = IORESOURCE_MEM, 368 .flags = IORESOURCE_MEM,
368 }, 369 },
369 [1] = { 370 [1] = {
370 .start = 58, 371 .start = evt2irq(0x940),
371 .flags = IORESOURCE_IRQ, 372 .flags = IORESOURCE_IRQ,
372 }, 373 },
373}; 374};
@@ -394,7 +395,7 @@ static struct resource tmu5_resources[] = {
394 .flags = IORESOURCE_MEM, 395 .flags = IORESOURCE_MEM,
395 }, 396 },
396 [1] = { 397 [1] = {
397 .start = 57, 398 .start = evt2irq(0x920),
398 .flags = IORESOURCE_IRQ, 399 .flags = IORESOURCE_IRQ,
399 }, 400 },
400}; 401};
@@ -417,17 +418,17 @@ static struct resource rtc_resources[] = {
417 }, 418 },
418 [1] = { 419 [1] = {
419 /* Period IRQ */ 420 /* Period IRQ */
420 .start = 69, 421 .start = evt2irq(0xaa0),
421 .flags = IORESOURCE_IRQ, 422 .flags = IORESOURCE_IRQ,
422 }, 423 },
423 [2] = { 424 [2] = {
424 /* Carry IRQ */ 425 /* Carry IRQ */
425 .start = 70, 426 .start = evt2irq(0xac0),
426 .flags = IORESOURCE_IRQ, 427 .flags = IORESOURCE_IRQ,
427 }, 428 },
428 [3] = { 429 [3] = {
429 /* Alarm IRQ */ 430 /* Alarm IRQ */
430 .start = 68, 431 .start = evt2irq(0xa80),
431 .flags = IORESOURCE_IRQ, 432 .flags = IORESOURCE_IRQ,
432 }, 433 },
433}; 434};
@@ -450,8 +451,8 @@ static struct resource sh7723_usb_host_resources[] = {
450 .flags = IORESOURCE_MEM, 451 .flags = IORESOURCE_MEM,
451 }, 452 },
452 [1] = { 453 [1] = {
453 .start = 65, 454 .start = evt2irq(0xa20),
454 .end = 65, 455 .end = evt2irq(0xa20),
455 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, 456 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
456 }, 457 },
457}; 458};
@@ -476,8 +477,8 @@ static struct resource iic_resources[] = {
476 .flags = IORESOURCE_MEM, 477 .flags = IORESOURCE_MEM,
477 }, 478 },
478 [1] = { 479 [1] = {
479 .start = 96, 480 .start = evt2irq(0xe00),
480 .end = 99, 481 .end = evt2irq(0xe60),
481 .flags = IORESOURCE_IRQ, 482 .flags = IORESOURCE_IRQ,
482 }, 483 },
483}; 484};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 4c671cfe68aa..26b74c2f9496 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -20,6 +20,7 @@
20#include <linux/uio_driver.h> 20#include <linux/uio_driver.h>
21#include <linux/sh_dma.h> 21#include <linux/sh_dma.h>
22#include <linux/sh_timer.h> 22#include <linux/sh_timer.h>
23#include <linux/sh_intc.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/notifier.h> 25#include <linux/notifier.h>
25 26
@@ -215,20 +216,20 @@ static struct resource sh7724_dmae0_resources[] = {
215 }, 216 },
216 { 217 {
217 .name = "error_irq", 218 .name = "error_irq",
218 .start = 78, 219 .start = evt2irq(0xbc0),
219 .end = 78, 220 .end = evt2irq(0xbc0),
220 .flags = IORESOURCE_IRQ, 221 .flags = IORESOURCE_IRQ,
221 }, 222 },
222 { 223 {
223 /* IRQ for channels 0-3 */ 224 /* IRQ for channels 0-3 */
224 .start = 48, 225 .start = evt2irq(0x800),
225 .end = 51, 226 .end = evt2irq(0x860),
226 .flags = IORESOURCE_IRQ, 227 .flags = IORESOURCE_IRQ,
227 }, 228 },
228 { 229 {
229 /* IRQ for channels 4-5 */ 230 /* IRQ for channels 4-5 */
230 .start = 76, 231 .start = evt2irq(0xb80),
231 .end = 77, 232 .end = evt2irq(0xba0),
232 .flags = IORESOURCE_IRQ, 233 .flags = IORESOURCE_IRQ,
233 }, 234 },
234}; 235};
@@ -249,20 +250,20 @@ static struct resource sh7724_dmae1_resources[] = {
249 }, 250 },
250 { 251 {
251 .name = "error_irq", 252 .name = "error_irq",
252 .start = 74, 253 .start = evt2irq(0xb40),
253 .end = 74, 254 .end = evt2irq(0xb40),
254 .flags = IORESOURCE_IRQ, 255 .flags = IORESOURCE_IRQ,
255 }, 256 },
256 { 257 {
257 /* IRQ for channels 0-3 */ 258 /* IRQ for channels 0-3 */
258 .start = 40, 259 .start = evt2irq(0x700),
259 .end = 43, 260 .end = evt2irq(0x760),
260 .flags = IORESOURCE_IRQ, 261 .flags = IORESOURCE_IRQ,
261 }, 262 },
262 { 263 {
263 /* IRQ for channels 4-5 */ 264 /* IRQ for channels 4-5 */
264 .start = 72, 265 .start = evt2irq(0xb00),
265 .end = 73, 266 .end = evt2irq(0xb20),
266 .flags = IORESOURCE_IRQ, 267 .flags = IORESOURCE_IRQ,
267 }, 268 },
268}; 269};
@@ -295,7 +296,7 @@ static struct plat_sci_port scif0_platform_data = {
295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
296 .scbrr_algo_id = SCBRR_ALGO_2, 297 .scbrr_algo_id = SCBRR_ALGO_2,
297 .type = PORT_SCIF, 298 .type = PORT_SCIF,
298 .irqs = { 80, 80, 80, 80 }, 299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
299 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
300}; 301};
301 302
@@ -314,7 +315,7 @@ static struct plat_sci_port scif1_platform_data = {
314 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
315 .scbrr_algo_id = SCBRR_ALGO_2, 316 .scbrr_algo_id = SCBRR_ALGO_2,
316 .type = PORT_SCIF, 317 .type = PORT_SCIF,
317 .irqs = { 81, 81, 81, 81 }, 318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
318 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
319}; 320};
320 321
@@ -333,7 +334,7 @@ static struct plat_sci_port scif2_platform_data = {
333 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
334 .scbrr_algo_id = SCBRR_ALGO_2, 335 .scbrr_algo_id = SCBRR_ALGO_2,
335 .type = PORT_SCIF, 336 .type = PORT_SCIF,
336 .irqs = { 82, 82, 82, 82 }, 337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
337 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
338}; 339};
339 340
@@ -352,7 +353,7 @@ static struct plat_sci_port scif3_platform_data = {
352 .scscr = SCSCR_RE | SCSCR_TE, 353 .scscr = SCSCR_RE | SCSCR_TE,
353 .scbrr_algo_id = SCBRR_ALGO_3, 354 .scbrr_algo_id = SCBRR_ALGO_3,
354 .type = PORT_SCIFA, 355 .type = PORT_SCIFA,
355 .irqs = { 56, 56, 56, 56 }, 356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
356}; 357};
357 358
358static struct platform_device scif3_device = { 359static struct platform_device scif3_device = {
@@ -370,7 +371,7 @@ static struct plat_sci_port scif4_platform_data = {
370 .scscr = SCSCR_RE | SCSCR_TE, 371 .scscr = SCSCR_RE | SCSCR_TE,
371 .scbrr_algo_id = SCBRR_ALGO_3, 372 .scbrr_algo_id = SCBRR_ALGO_3,
372 .type = PORT_SCIFA, 373 .type = PORT_SCIFA,
373 .irqs = { 88, 88, 88, 88 }, 374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)),
374}; 375};
375 376
376static struct platform_device scif4_device = { 377static struct platform_device scif4_device = {
@@ -388,7 +389,7 @@ static struct plat_sci_port scif5_platform_data = {
388 .scscr = SCSCR_RE | SCSCR_TE, 389 .scscr = SCSCR_RE | SCSCR_TE,
389 .scbrr_algo_id = SCBRR_ALGO_3, 390 .scbrr_algo_id = SCBRR_ALGO_3,
390 .type = PORT_SCIFA, 391 .type = PORT_SCIFA,
391 .irqs = { 109, 109, 109, 109 }, 392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)),
392}; 393};
393 394
394static struct platform_device scif5_device = { 395static struct platform_device scif5_device = {
@@ -408,17 +409,17 @@ static struct resource rtc_resources[] = {
408 }, 409 },
409 [1] = { 410 [1] = {
410 /* Period IRQ */ 411 /* Period IRQ */
411 .start = 69, 412 .start = evt2irq(0xaa0),
412 .flags = IORESOURCE_IRQ, 413 .flags = IORESOURCE_IRQ,
413 }, 414 },
414 [2] = { 415 [2] = {
415 /* Carry IRQ */ 416 /* Carry IRQ */
416 .start = 70, 417 .start = evt2irq(0xac0),
417 .flags = IORESOURCE_IRQ, 418 .flags = IORESOURCE_IRQ,
418 }, 419 },
419 [3] = { 420 [3] = {
420 /* Alarm IRQ */ 421 /* Alarm IRQ */
421 .start = 68, 422 .start = evt2irq(0xa80),
422 .flags = IORESOURCE_IRQ, 423 .flags = IORESOURCE_IRQ,
423 }, 424 },
424}; 425};
@@ -439,8 +440,8 @@ static struct resource iic0_resources[] = {
439 .flags = IORESOURCE_MEM, 440 .flags = IORESOURCE_MEM,
440 }, 441 },
441 [1] = { 442 [1] = {
442 .start = 96, 443 .start = evt2irq(0xe00),
443 .end = 99, 444 .end = evt2irq(0xe60),
444 .flags = IORESOURCE_IRQ, 445 .flags = IORESOURCE_IRQ,
445 }, 446 },
446}; 447};
@@ -461,8 +462,8 @@ static struct resource iic1_resources[] = {
461 .flags = IORESOURCE_MEM, 462 .flags = IORESOURCE_MEM,
462 }, 463 },
463 [1] = { 464 [1] = {
464 .start = 92, 465 .start = evt2irq(0xd80),
465 .end = 95, 466 .end = evt2irq(0xde0),
466 .flags = IORESOURCE_IRQ, 467 .flags = IORESOURCE_IRQ,
467 }, 468 },
468}; 469};
@@ -478,7 +479,7 @@ static struct platform_device iic1_device = {
478static struct uio_info vpu_platform_data = { 479static struct uio_info vpu_platform_data = {
479 .name = "VPU5F", 480 .name = "VPU5F",
480 .version = "0", 481 .version = "0",
481 .irq = 60, 482 .irq = evt2irq(0x980),
482}; 483};
483 484
484static struct resource vpu_resources[] = { 485static struct resource vpu_resources[] = {
@@ -507,7 +508,7 @@ static struct platform_device vpu_device = {
507static struct uio_info veu0_platform_data = { 508static struct uio_info veu0_platform_data = {
508 .name = "VEU3F0", 509 .name = "VEU3F0",
509 .version = "0", 510 .version = "0",
510 .irq = 83, 511 .irq = evt2irq(0xc60),
511}; 512};
512 513
513static struct resource veu0_resources[] = { 514static struct resource veu0_resources[] = {
@@ -536,7 +537,7 @@ static struct platform_device veu0_device = {
536static struct uio_info veu1_platform_data = { 537static struct uio_info veu1_platform_data = {
537 .name = "VEU3F1", 538 .name = "VEU3F1",
538 .version = "0", 539 .version = "0",
539 .irq = 54, 540 .irq = evt2irq(0x8c0),
540}; 541};
541 542
542static struct resource veu1_resources[] = { 543static struct resource veu1_resources[] = {
@@ -633,7 +634,7 @@ static struct resource cmt_resources[] = {
633 .flags = IORESOURCE_MEM, 634 .flags = IORESOURCE_MEM,
634 }, 635 },
635 [1] = { 636 [1] = {
636 .start = 104, 637 .start = evt2irq(0xf00),
637 .flags = IORESOURCE_IRQ, 638 .flags = IORESOURCE_IRQ,
638 }, 639 },
639}; 640};
@@ -661,7 +662,7 @@ static struct resource tmu0_resources[] = {
661 .flags = IORESOURCE_MEM, 662 .flags = IORESOURCE_MEM,
662 }, 663 },
663 [1] = { 664 [1] = {
664 .start = 16, 665 .start = evt2irq(0x400),
665 .flags = IORESOURCE_IRQ, 666 .flags = IORESOURCE_IRQ,
666 }, 667 },
667}; 668};
@@ -689,7 +690,7 @@ static struct resource tmu1_resources[] = {
689 .flags = IORESOURCE_MEM, 690 .flags = IORESOURCE_MEM,
690 }, 691 },
691 [1] = { 692 [1] = {
692 .start = 17, 693 .start = evt2irq(0x420),
693 .flags = IORESOURCE_IRQ, 694 .flags = IORESOURCE_IRQ,
694 }, 695 },
695}; 696};
@@ -716,7 +717,7 @@ static struct resource tmu2_resources[] = {
716 .flags = IORESOURCE_MEM, 717 .flags = IORESOURCE_MEM,
717 }, 718 },
718 [1] = { 719 [1] = {
719 .start = 18, 720 .start = evt2irq(0x440),
720 .flags = IORESOURCE_IRQ, 721 .flags = IORESOURCE_IRQ,
721 }, 722 },
722}; 723};
@@ -744,7 +745,7 @@ static struct resource tmu3_resources[] = {
744 .flags = IORESOURCE_MEM, 745 .flags = IORESOURCE_MEM,
745 }, 746 },
746 [1] = { 747 [1] = {
747 .start = 57, 748 .start = evt2irq(0x920),
748 .flags = IORESOURCE_IRQ, 749 .flags = IORESOURCE_IRQ,
749 }, 750 },
750}; 751};
@@ -771,7 +772,7 @@ static struct resource tmu4_resources[] = {
771 .flags = IORESOURCE_MEM, 772 .flags = IORESOURCE_MEM,
772 }, 773 },
773 [1] = { 774 [1] = {
774 .start = 58, 775 .start = evt2irq(0x940),
775 .flags = IORESOURCE_IRQ, 776 .flags = IORESOURCE_IRQ,
776 }, 777 },
777}; 778};
@@ -798,7 +799,7 @@ static struct resource tmu5_resources[] = {
798 .flags = IORESOURCE_MEM, 799 .flags = IORESOURCE_MEM,
799 }, 800 },
800 [1] = { 801 [1] = {
801 .start = 57, 802 .start = evt2irq(0x920),
802 .flags = IORESOURCE_IRQ, 803 .flags = IORESOURCE_IRQ,
803 }, 804 },
804}; 805};
@@ -817,7 +818,7 @@ static struct platform_device tmu5_device = {
817static struct uio_info jpu_platform_data = { 818static struct uio_info jpu_platform_data = {
818 .name = "JPU", 819 .name = "JPU",
819 .version = "0", 820 .version = "0",
820 .irq = 27, 821 .irq = evt2irq(0x560),
821}; 822};
822 823
823static struct resource jpu_resources[] = { 824static struct resource jpu_resources[] = {
@@ -846,7 +847,7 @@ static struct platform_device jpu_device = {
846static struct uio_info spu0_platform_data = { 847static struct uio_info spu0_platform_data = {
847 .name = "SPU2DSP0", 848 .name = "SPU2DSP0",
848 .version = "0", 849 .version = "0",
849 .irq = 86, 850 .irq = evt2irq(0xcc0),
850}; 851};
851 852
852static struct resource spu0_resources[] = { 853static struct resource spu0_resources[] = {
@@ -875,7 +876,7 @@ static struct platform_device spu0_device = {
875static struct uio_info spu1_platform_data = { 876static struct uio_info spu1_platform_data = {
876 .name = "SPU2DSP1", 877 .name = "SPU2DSP1",
877 .version = "0", 878 .version = "0",
878 .irq = 87, 879 .irq = evt2irq(0xce0),
879}; 880};
880 881
881static struct resource spu1_resources[] = { 882static struct resource spu1_resources[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
new file mode 100644
index 000000000000..f799971d453c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -0,0 +1,800 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/setup-sh7734.c
3
4 * SH7734 Setup
5 *
6 * Copyright (C) 2011,2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * Copyright (C) 2011,2012 Renesas Solutions Corp.
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/init.h>
16#include <linux/serial.h>
17#include <linux/mm.h>
18#include <linux/dma-mapping.h>
19#include <linux/serial_sci.h>
20#include <linux/sh_timer.h>
21#include <linux/io.h>
22#include <asm/clock.h>
23#include <asm/irq.h>
24#include <cpu/sh7734.h>
25
26/* SCIF */
27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE,
35};
36
37static struct platform_device scif0_device = {
38 .name = "sh-sci",
39 .id = 0,
40 .dev = {
41 .platform_data = &scif0_platform_data,
42 },
43};
44
45static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE,
53};
54
55static struct platform_device scif1_device = {
56 .name = "sh-sci",
57 .id = 1,
58 .dev = {
59 .platform_data = &scif1_platform_data,
60 },
61};
62
63static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE,
71};
72
73static struct platform_device scif2_device = {
74 .name = "sh-sci",
75 .id = 2,
76 .dev = {
77 .platform_data = &scif2_platform_data,
78 },
79};
80
81static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE,
89};
90
91static struct platform_device scif3_device = {
92 .name = "sh-sci",
93 .id = 3,
94 .dev = {
95 .platform_data = &scif3_platform_data,
96 },
97};
98
99static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE,
107};
108
109static struct platform_device scif4_device = {
110 .name = "sh-sci",
111 .id = 4,
112 .dev = {
113 .platform_data = &scif4_platform_data,
114 },
115};
116
117static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE,
125};
126
127static struct platform_device scif5_device = {
128 .name = "sh-sci",
129 .id = 5,
130 .dev = {
131 .platform_data = &scif5_platform_data,
132 },
133};
134
135/* RTC */
136static struct resource rtc_resources[] = {
137 [0] = {
138 .name = "rtc",
139 .start = 0xFFFC5000,
140 .end = 0xFFFC5000 + 0x26 - 1,
141 .flags = IORESOURCE_IO,
142 },
143 [1] = {
144 .start = evt2irq(0xC00),
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct platform_device rtc_device = {
150 .name = "sh-rtc",
151 .id = -1,
152 .num_resources = ARRAY_SIZE(rtc_resources),
153 .resource = rtc_resources,
154};
155
156/* I2C 0 */
157static struct resource i2c0_resources[] = {
158 [0] = {
159 .name = "IIC0",
160 .start = 0xFFC70000,
161 .end = 0xFFC7000A - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 [1] = {
165 .start = evt2irq(0x860),
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device i2c0_device = {
171 .name = "i2c-sh7734",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(i2c0_resources),
174 .resource = i2c0_resources,
175};
176
177/* TMU */
178static struct sh_timer_config tmu0_platform_data = {
179 .channel_offset = 0x04,
180 .timer_bit = 0,
181 .clockevent_rating = 200,
182};
183
184static struct resource tmu0_resources[] = {
185 [0] = {
186 .start = 0xFFD80008,
187 .end = 0xFFD80014 - 1,
188 .flags = IORESOURCE_MEM,
189 },
190 [1] = {
191 .start = evt2irq(0x400),
192 .flags = IORESOURCE_IRQ,
193 },
194};
195
196static struct platform_device tmu0_device = {
197 .name = "sh_tmu",
198 .id = 0,
199 .dev = {
200 .platform_data = &tmu0_platform_data,
201 },
202 .resource = tmu0_resources,
203 .num_resources = ARRAY_SIZE(tmu0_resources),
204};
205
206static struct sh_timer_config tmu1_platform_data = {
207 .channel_offset = 0x10,
208 .timer_bit = 1,
209 .clocksource_rating = 200,
210};
211
212static struct resource tmu1_resources[] = {
213 [0] = {
214 .start = 0xFFD80014,
215 .end = 0xFFD80020 - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = evt2irq(0x420),
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device tmu1_device = {
225 .name = "sh_tmu",
226 .id = 1,
227 .dev = {
228 .platform_data = &tmu1_platform_data,
229 },
230 .resource = tmu1_resources,
231 .num_resources = ARRAY_SIZE(tmu1_resources),
232};
233
234static struct sh_timer_config tmu2_platform_data = {
235 .channel_offset = 0x1c,
236 .timer_bit = 2,
237};
238
239static struct resource tmu2_resources[] = {
240 [0] = {
241 .start = 0xFFD80020,
242 .end = 0xFFD80030 - 1,
243 .flags = IORESOURCE_MEM,
244 },
245 [1] = {
246 .start = evt2irq(0x440),
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static struct platform_device tmu2_device = {
252 .name = "sh_tmu",
253 .id = 2,
254 .dev = {
255 .platform_data = &tmu2_platform_data,
256 },
257 .resource = tmu2_resources,
258 .num_resources = ARRAY_SIZE(tmu2_resources),
259};
260
261
262static struct sh_timer_config tmu3_platform_data = {
263 .channel_offset = 0x04,
264 .timer_bit = 0,
265};
266
267static struct resource tmu3_resources[] = {
268 [0] = {
269 .start = 0xFFD81008,
270 .end = 0xFFD81014 - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = evt2irq(0x480),
275 .flags = IORESOURCE_IRQ,
276 },
277};
278
279static struct platform_device tmu3_device = {
280 .name = "sh_tmu",
281 .id = 3,
282 .dev = {
283 .platform_data = &tmu3_platform_data,
284 },
285 .resource = tmu3_resources,
286 .num_resources = ARRAY_SIZE(tmu3_resources),
287};
288
289static struct sh_timer_config tmu4_platform_data = {
290 .channel_offset = 0x10,
291 .timer_bit = 1,
292};
293
294static struct resource tmu4_resources[] = {
295 [0] = {
296 .start = 0xFFD81014,
297 .end = 0xFFD81020 - 1,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = evt2irq(0x4A0),
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu4_device = {
307 .name = "sh_tmu",
308 .id = 4,
309 .dev = {
310 .platform_data = &tmu4_platform_data,
311 },
312 .resource = tmu4_resources,
313 .num_resources = ARRAY_SIZE(tmu4_resources),
314};
315
316static struct sh_timer_config tmu5_platform_data = {
317 .channel_offset = 0x1c,
318 .timer_bit = 2,
319};
320
321static struct resource tmu5_resources[] = {
322 [0] = {
323 .start = 0xFFD81020,
324 .end = 0xFFD81030 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = evt2irq(0x4C0),
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333static struct platform_device tmu5_device = {
334 .name = "sh_tmu",
335 .id = 5,
336 .dev = {
337 .platform_data = &tmu5_platform_data,
338 },
339 .resource = tmu5_resources,
340 .num_resources = ARRAY_SIZE(tmu5_resources),
341};
342
343static struct sh_timer_config tmu6_platform_data = {
344 .channel_offset = 0x4,
345 .timer_bit = 0,
346};
347
348static struct resource tmu6_resources[] = {
349 [0] = {
350 .start = 0xFFD82008,
351 .end = 0xFFD82014 - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 [1] = {
355 .start = evt2irq(0x500),
356 .flags = IORESOURCE_IRQ,
357 },
358};
359
360static struct platform_device tmu6_device = {
361 .name = "sh_tmu",
362 .id = 6,
363 .dev = {
364 .platform_data = &tmu6_platform_data,
365 },
366 .resource = tmu6_resources,
367 .num_resources = ARRAY_SIZE(tmu6_resources),
368};
369
370static struct sh_timer_config tmu7_platform_data = {
371 .channel_offset = 0x10,
372 .timer_bit = 1,
373};
374
375static struct resource tmu7_resources[] = {
376 [0] = {
377 .start = 0xFFD82014,
378 .end = 0xFFD82020 - 1,
379 .flags = IORESOURCE_MEM,
380 },
381 [1] = {
382 .start = evt2irq(0x520),
383 .flags = IORESOURCE_IRQ,
384 },
385};
386
387static struct platform_device tmu7_device = {
388 .name = "sh_tmu",
389 .id = 7,
390 .dev = {
391 .platform_data = &tmu7_platform_data,
392 },
393 .resource = tmu7_resources,
394 .num_resources = ARRAY_SIZE(tmu7_resources),
395};
396
397static struct sh_timer_config tmu8_platform_data = {
398 .channel_offset = 0x1c,
399 .timer_bit = 2,
400};
401
402static struct resource tmu8_resources[] = {
403 [0] = {
404 .start = 0xFFD82020,
405 .end = 0xFFD82030 - 1,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = evt2irq(0x540),
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu8_device = {
415 .name = "sh_tmu",
416 .id = 8,
417 .dev = {
418 .platform_data = &tmu8_platform_data,
419 },
420 .resource = tmu8_resources,
421 .num_resources = ARRAY_SIZE(tmu8_resources),
422};
423
424static struct platform_device *sh7734_devices[] __initdata = {
425 &scif0_device,
426 &scif1_device,
427 &scif2_device,
428 &scif3_device,
429 &scif4_device,
430 &scif5_device,
431 &tmu0_device,
432 &tmu1_device,
433 &tmu2_device,
434 &tmu3_device,
435 &tmu4_device,
436 &tmu5_device,
437 &tmu6_device,
438 &tmu7_device,
439 &tmu8_device,
440 &rtc_device,
441};
442
443static struct platform_device *sh7734_early_devices[] __initdata = {
444 &scif0_device,
445 &scif1_device,
446 &scif2_device,
447 &scif3_device,
448 &scif4_device,
449 &scif5_device,
450 &tmu0_device,
451 &tmu1_device,
452 &tmu2_device,
453 &tmu3_device,
454 &tmu4_device,
455 &tmu5_device,
456 &tmu6_device,
457 &tmu7_device,
458 &tmu8_device,
459};
460
461void __init plat_early_device_setup(void)
462{
463 early_platform_add_devices(sh7734_early_devices,
464 ARRAY_SIZE(sh7734_early_devices));
465}
466
467#define GROUP 0
468enum {
469 UNUSED = 0,
470
471 /* interrupt sources */
472
473 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
474 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
475 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
476 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
477
478 IRQ0, IRQ1, IRQ2, IRQ3,
479 DU,
480 TMU00, TMU10, TMU20, TMU21,
481 TMU30, TMU40, TMU50, TMU51,
482 TMU60, TMU70, TMU80,
483 RESET_WDT,
484 USB,
485 HUDI,
486 SHDMAC,
487 SSI0, SSI1, SSI2, SSI3,
488 VIN0,
489 RGPVG,
490 _2DG,
491 MMC,
492 HSPI,
493 LBSCATA,
494 I2C0,
495 RCAN0,
496 MIMLB,
497 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
498 LBSCDMAC0, LBSCDMAC1, LBSCDMAC2,
499 RCAN1,
500 SDHI0, SDHI1,
501 IEBUS,
502 HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22, HPBDMAC23_25_27_28,
503 RTC,
504 VIN1,
505 LCDC,
506 SRC0, SRC1,
507 GETHER,
508 SDHI2,
509 GPIO0_3, GPIO4_5,
510 STIF0, STIF1,
511 ADMAC,
512 HIF,
513 FLCTL,
514 ADC,
515 MTU2,
516 RSPI,
517 QSPI,
518 HSCIF,
519 VEU3F_VE3,
520
521 /* Group */
522 /* Mask */
523 STIF_M,
524 GPIO_M,
525 HPBDMAC_M,
526 LBSCDMAC_M,
527 RCAN_M,
528 SRC_M,
529 SCIF_M,
530 LCDC_M,
531 _2DG_M,
532 VIN_M,
533 TMU_3_M,
534 TMU_0_M,
535
536 /* Priority */
537 RCAN_P,
538 LBSCDMAC_P,
539
540 /* Common */
541 SDHI,
542 SSI,
543 SPI,
544};
545
546static struct intc_vect vectors[] __initdata = {
547 INTC_VECT(DU, 0x3E0),
548 INTC_VECT(TMU00, 0x400),
549 INTC_VECT(TMU10, 0x420),
550 INTC_VECT(TMU20, 0x440),
551 INTC_VECT(TMU30, 0x480),
552 INTC_VECT(TMU40, 0x4A0),
553 INTC_VECT(TMU50, 0x4C0),
554 INTC_VECT(TMU51, 0x4E0),
555 INTC_VECT(TMU60, 0x500),
556 INTC_VECT(TMU70, 0x520),
557 INTC_VECT(TMU80, 0x540),
558 INTC_VECT(RESET_WDT, 0x560),
559 INTC_VECT(USB, 0x580),
560 INTC_VECT(HUDI, 0x600),
561 INTC_VECT(SHDMAC, 0x620),
562 INTC_VECT(SSI0, 0x6C0),
563 INTC_VECT(SSI1, 0x6E0),
564 INTC_VECT(SSI2, 0x700),
565 INTC_VECT(SSI3, 0x720),
566 INTC_VECT(VIN0, 0x740),
567 INTC_VECT(RGPVG, 0x760),
568 INTC_VECT(_2DG, 0x780),
569 INTC_VECT(MMC, 0x7A0),
570 INTC_VECT(HSPI, 0x7E0),
571 INTC_VECT(LBSCATA, 0x840),
572 INTC_VECT(I2C0, 0x860),
573 INTC_VECT(RCAN0, 0x880),
574 INTC_VECT(SCIF0, 0x8A0),
575 INTC_VECT(SCIF1, 0x8C0),
576 INTC_VECT(SCIF2, 0x900),
577 INTC_VECT(SCIF3, 0x920),
578 INTC_VECT(SCIF4, 0x940),
579 INTC_VECT(SCIF5, 0x960),
580 INTC_VECT(LBSCDMAC0, 0x9E0),
581 INTC_VECT(LBSCDMAC1, 0xA00),
582 INTC_VECT(LBSCDMAC2, 0xA20),
583 INTC_VECT(RCAN1, 0xA60),
584 INTC_VECT(SDHI0, 0xAE0),
585 INTC_VECT(SDHI1, 0xB00),
586 INTC_VECT(IEBUS, 0xB20),
587 INTC_VECT(HPBDMAC0_3, 0xB60),
588 INTC_VECT(HPBDMAC4_10, 0xB80),
589 INTC_VECT(HPBDMAC11_18, 0xBA0),
590 INTC_VECT(HPBDMAC19_22, 0xBC0),
591 INTC_VECT(HPBDMAC23_25_27_28, 0xBE0),
592 INTC_VECT(RTC, 0xC00),
593 INTC_VECT(VIN1, 0xC20),
594 INTC_VECT(LCDC, 0xC40),
595 INTC_VECT(SRC0, 0xC60),
596 INTC_VECT(SRC1, 0xC80),
597 INTC_VECT(GETHER, 0xCA0),
598 INTC_VECT(SDHI2, 0xCC0),
599 INTC_VECT(GPIO0_3, 0xCE0),
600 INTC_VECT(GPIO4_5, 0xD00),
601 INTC_VECT(STIF0, 0xD20),
602 INTC_VECT(STIF1, 0xD40),
603 INTC_VECT(ADMAC, 0xDA0),
604 INTC_VECT(HIF, 0xDC0),
605 INTC_VECT(FLCTL, 0xDE0),
606 INTC_VECT(ADC, 0xE00),
607 INTC_VECT(MTU2, 0xE20),
608 INTC_VECT(RSPI, 0xE40),
609 INTC_VECT(QSPI, 0xE60),
610 INTC_VECT(HSCIF, 0xFC0),
611 INTC_VECT(VEU3F_VE3, 0xF40),
612};
613
614static struct intc_group groups[] __initdata = {
615 /* Common */
616 INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2),
617 INTC_GROUP(SPI, HSPI, RSPI, QSPI),
618 INTC_GROUP(SSI, SSI0, SSI1, SSI2, SSI3),
619
620 /* Mask group */
621 INTC_GROUP(STIF_M, STIF0, STIF1), /* 22 */
622 INTC_GROUP(GPIO_M, GPIO0_3, GPIO4_5), /* 21 */
623 INTC_GROUP(HPBDMAC_M, HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18,
624 HPBDMAC19_22, HPBDMAC23_25_27_28), /* 19 */
625 INTC_GROUP(LBSCDMAC_M, LBSCDMAC0, LBSCDMAC1, LBSCDMAC2), /* 18 */
626 INTC_GROUP(RCAN_M, RCAN0, RCAN1, IEBUS), /* 17 */
627 INTC_GROUP(SRC_M, SRC0, SRC1), /* 16 */
628 INTC_GROUP(SCIF_M, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5,
629 HSCIF), /* 14 */
630 INTC_GROUP(LCDC_M, LCDC, MIMLB), /* 13 */
631 INTC_GROUP(_2DG_M, _2DG, RGPVG), /* 12 */
632 INTC_GROUP(VIN_M, VIN0, VIN1), /* 10 */
633 INTC_GROUP(TMU_3_M, TMU30, TMU40, TMU50, TMU51,
634 TMU60, TMU60, TMU70, TMU80), /* 2 */
635 INTC_GROUP(TMU_0_M, TMU00, TMU10, TMU20, TMU21), /* 1 */
636
637 /* Priority group*/
638 INTC_GROUP(RCAN_P, RCAN0, RCAN1), /* INT2PRI5 */
639 INTC_GROUP(LBSCDMAC_P, LBSCDMAC0, LBSCDMAC1), /* INT2PRI5 */
640};
641
642static struct intc_mask_reg mask_registers[] __initdata = {
643 { 0xFF804040, 0xFF804044, 32, /* INT2MSKRG / INT2MSKCR */
644 { 0,
645 VEU3F_VE3,
646 SDHI, /* SDHI 0-2 */
647 ADMAC,
648 FLCTL,
649 RESET_WDT,
650 HIF,
651 ADC,
652 MTU2,
653 STIF_M, /* STIF 0,1 */
654 GPIO_M, /* GPIO 0-5*/
655 GETHER,
656 HPBDMAC_M, /* HPBDMAC 0_3 - 23_25_27_28 */
657 LBSCDMAC_M, /* LBSCDMAC 0 - 2 */
658 RCAN_M, /* RCAN, IEBUS */
659 SRC_M, /* SRC 0,1 */
660 LBSCATA,
661 SCIF_M, /* SCIF 0-5, HSCIF */
662 LCDC_M, /* LCDC, MIMLB */
663 _2DG_M, /* 2DG, RGPVG */
664 SPI, /* HSPI, RSPI, QSPI */
665 VIN_M, /* VIN0, 1 */
666 SSI, /* SSI 0-3 */
667 USB,
668 SHDMAC,
669 HUDI,
670 MMC,
671 RTC,
672 I2C0, /* I2C */ /* I2C 0, 1*/
673 TMU_3_M, /* TMU30 - TMU80 */
674 TMU_0_M, /* TMU00 - TMU21 */
675 DU } },
676};
677
678static struct intc_prio_reg prio_registers[] __initdata = {
679 { 0xFF804000, 0, 32, 8, /* INT2PRI0 */
680 { DU, TMU00, TMU10, TMU20 } },
681 { 0xFF804004, 0, 32, 8, /* INT2PRI1 */
682 { TMU30, TMU60, RTC, SDHI } },
683 { 0xFF804008, 0, 32, 8, /* INT2PRI2 */
684 { HUDI, SHDMAC, USB, SSI } },
685 { 0xFF80400C, 0, 32, 8, /* INT2PRI3 */
686 { VIN0, SPI, _2DG, LBSCATA } },
687 { 0xFF804010, 0, 32, 8, /* INT2PRI4 */
688 { SCIF0, SCIF3, HSCIF, LCDC } },
689 { 0xFF804014, 0, 32, 8, /* INT2PRI5 */
690 { RCAN_P, LBSCDMAC_P, LBSCDMAC2, MMC } },
691 { 0xFF804018, 0, 32, 8, /* INT2PRI6 */
692 { HPBDMAC0_3, HPBDMAC4_10, HPBDMAC11_18, HPBDMAC19_22 } },
693 { 0xFF80401C, 0, 32, 8, /* INT2PRI7 */
694 { HPBDMAC23_25_27_28, I2C0, SRC0, SRC1 } },
695 { 0xFF804020, 0, 32, 8, /* INT2PRI8 */
696 { 0 /* ADIF */, VIN1, RESET_WDT, HIF } },
697 { 0xFF804024, 0, 32, 8, /* INT2PRI9 */
698 { ADMAC, FLCTL, GPIO0_3, GPIO4_5 } },
699 { 0xFF804028, 0, 32, 8, /* INT2PRI10 */
700 { STIF0, STIF1, VEU3F_VE3, GETHER } },
701 { 0xFF80402C, 0, 32, 8, /* INT2PRI11 */
702 { MTU2, RGPVG, MIMLB, IEBUS } },
703};
704
705static DECLARE_INTC_DESC(intc_desc, "sh7734", vectors, groups,
706 mask_registers, prio_registers, NULL);
707
708/* Support for external interrupt pins in IRQ mode */
709
710static struct intc_vect irq3210_vectors[] __initdata = {
711 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
712 INTC_VECT(IRQ2, 0x2C0), INTC_VECT(IRQ3, 0x300),
713};
714
715static struct intc_sense_reg irq3210_sense_registers[] __initdata = {
716 { 0xFF80201C, 32, 2, /* ICR1 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, } },
718};
719
720static struct intc_mask_reg irq3210_ack_registers[] __initdata = {
721 { 0xFF802024, 0, 32, /* INTREQ */
722 { IRQ0, IRQ1, IRQ2, IRQ3, } },
723};
724
725static struct intc_mask_reg irq3210_mask_registers[] __initdata = {
726 { 0xFF802044, 0xFF802064, 32, /* INTMSK0 / INTMSKCLR0 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, } },
728};
729
730static struct intc_prio_reg irq3210_prio_registers[] __initdata = {
731 { 0xFF802010, 0, 32, 4, /* INTPRI */
732 { IRQ0, IRQ1, IRQ2, IRQ3, } },
733};
734
735static DECLARE_INTC_DESC_ACK(intc_desc_irq3210, "sh7734-irq3210",
736 irq3210_vectors, NULL,
737 irq3210_mask_registers, irq3210_prio_registers,
738 irq3210_sense_registers, irq3210_ack_registers);
739
740/* External interrupt pins in IRL mode */
741
742static struct intc_vect vectors_irl3210[] __initdata = {
743 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
744 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
745 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
746 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
747 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
748 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
749 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
750 INTC_VECT(IRL0_HHHL, 0x3c0),
751};
752
753static DECLARE_INTC_DESC(intc_desc_irl3210, "sh7734-irl3210",
754 vectors_irl3210, NULL, mask_registers, NULL, NULL);
755
756#define INTC_ICR0 0xFF802000
757#define INTC_INTMSK0 0xFF802044
758#define INTC_INTMSK1 0xFF802048
759#define INTC_INTMSKCLR0 0xFF802064
760#define INTC_INTMSKCLR1 0xFF802068
761
762void __init plat_irq_setup(void)
763{
764 /* disable IRQ3-0 */
765 __raw_writel(0xF0000000, INTC_INTMSK0);
766
767 /* disable IRL3-0 */
768 __raw_writel(0x80000000, INTC_INTMSK1);
769
770 /* select IRL mode for IRL3-0 */
771 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0);
772
773 /* disable holding function, ie enable "SH-4 Mode (LVLMODE)" */
774 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
775
776 register_intc_controller(&intc_desc);
777}
778
779void __init plat_irq_setup_pins(int mode)
780{
781 switch (mode) {
782 case IRQ_MODE_IRQ3210:
783 /* select IRQ mode for IRL3-0 */
784 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
785 register_intc_controller(&intc_desc_irq3210);
786 break;
787 case IRQ_MODE_IRL3210:
788 /* enable IRL0-3 but don't provide any masking */
789 __raw_writel(0x80000000, INTC_INTMSKCLR1);
790 __raw_writel(0xf0000000, INTC_INTMSKCLR0);
791 break;
792 case IRQ_MODE_IRL3210_MASK:
793 /* enable IRL0-3 and mask using cpu intc controller */
794 __raw_writel(0x80000000, INTC_INTMSKCLR0);
795 register_intc_controller(&intc_desc_irl3210);
796 break;
797 default:
798 BUG();
799 }
800}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index c8836cffa216..a7708425afa9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -18,7 +18,7 @@
18#include <linux/dma-mapping.h> 18#include <linux/dma-mapping.h>
19#include <linux/sh_timer.h> 19#include <linux/sh_timer.h>
20#include <linux/sh_dma.h> 20#include <linux/sh_dma.h>
21 21#include <linux/sh_intc.h>
22#include <cpu/dma-register.h> 22#include <cpu/dma-register.h>
23#include <cpu/sh7757.h> 23#include <cpu/sh7757.h>
24 24
@@ -28,7 +28,7 @@ static struct plat_sci_port scif2_platform_data = {
28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
30 .type = PORT_SCIF, 30 .type = PORT_SCIF,
31 .irqs = { 40, 40, 40, 40 }, 31 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
32}; 32};
33 33
34static struct platform_device scif2_device = { 34static struct platform_device scif2_device = {
@@ -45,7 +45,7 @@ static struct plat_sci_port scif3_platform_data = {
45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
46 .scbrr_algo_id = SCBRR_ALGO_2, 46 .scbrr_algo_id = SCBRR_ALGO_2,
47 .type = PORT_SCIF, 47 .type = PORT_SCIF,
48 .irqs = { 76, 76, 76, 76 }, 48 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
49}; 49};
50 50
51static struct platform_device scif3_device = { 51static struct platform_device scif3_device = {
@@ -62,7 +62,7 @@ static struct plat_sci_port scif4_platform_data = {
62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 62 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2, 63 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 64 .type = PORT_SCIF,
65 .irqs = { 104, 104, 104, 104 }, 65 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)),
66}; 66};
67 67
68static struct platform_device scif4_device = { 68static struct platform_device scif4_device = {
@@ -86,7 +86,7 @@ static struct resource tmu0_resources[] = {
86 .flags = IORESOURCE_MEM, 86 .flags = IORESOURCE_MEM,
87 }, 87 },
88 [1] = { 88 [1] = {
89 .start = 28, 89 .start = evt2irq(0x580),
90 .flags = IORESOURCE_IRQ, 90 .flags = IORESOURCE_IRQ,
91 }, 91 },
92}; 92};
@@ -114,7 +114,7 @@ static struct resource tmu1_resources[] = {
114 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
115 }, 115 },
116 [1] = { 116 [1] = {
117 .start = 29, 117 .start = evt2irq(0x5a0),
118 .flags = IORESOURCE_IRQ, 118 .flags = IORESOURCE_IRQ,
119 }, 119 },
120}; 120};
@@ -136,7 +136,7 @@ static struct resource spi0_resources[] = {
136 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, 136 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
137 }, 137 },
138 [1] = { 138 [1] = {
139 .start = 86, 139 .start = evt2irq(0xcc0),
140 .flags = IORESOURCE_IRQ, 140 .flags = IORESOURCE_IRQ,
141 }, 141 },
142}; 142};
@@ -466,8 +466,8 @@ static struct resource sh7757_dmae0_resources[] = {
466 }, 466 },
467 { 467 {
468 .name = "error_irq", 468 .name = "error_irq",
469 .start = 34, 469 .start = evt2irq(0x640),
470 .end = 34, 470 .end = evt2irq(0x640),
471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 471 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
472 }, 472 },
473}; 473};
@@ -488,56 +488,56 @@ static struct resource sh7757_dmae1_resources[] = {
488 }, 488 },
489 { 489 {
490 .name = "error_irq", 490 .name = "error_irq",
491 .start = 34, 491 .start = evt2irq(0x640),
492 .end = 34, 492 .end = evt2irq(0x640),
493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 493 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
494 }, 494 },
495 { 495 {
496 /* IRQ for channels 4 */ 496 /* IRQ for channels 4 */
497 .start = 46, 497 .start = evt2irq(0x7c0),
498 .end = 46, 498 .end = evt2irq(0x7c0),
499 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 499 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
500 }, 500 },
501 { 501 {
502 /* IRQ for channels 5 */ 502 /* IRQ for channels 5 */
503 .start = 46, 503 .start = evt2irq(0x7c0),
504 .end = 46, 504 .end = evt2irq(0x7c0),
505 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 505 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
506 }, 506 },
507 { 507 {
508 /* IRQ for channels 6 */ 508 /* IRQ for channels 6 */
509 .start = 88, 509 .start = evt2irq(0xd00),
510 .end = 88, 510 .end = evt2irq(0xd00),
511 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 511 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
512 }, 512 },
513 { 513 {
514 /* IRQ for channels 7 */ 514 /* IRQ for channels 7 */
515 .start = 88, 515 .start = evt2irq(0xd00),
516 .end = 88, 516 .end = evt2irq(0xd00),
517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
518 }, 518 },
519 { 519 {
520 /* IRQ for channels 8 */ 520 /* IRQ for channels 8 */
521 .start = 88, 521 .start = evt2irq(0xd00),
522 .end = 88, 522 .end = evt2irq(0xd00),
523 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 523 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
524 }, 524 },
525 { 525 {
526 /* IRQ for channels 9 */ 526 /* IRQ for channels 9 */
527 .start = 88, 527 .start = evt2irq(0xd00),
528 .end = 88, 528 .end = evt2irq(0xd00),
529 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 529 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
530 }, 530 },
531 { 531 {
532 /* IRQ for channels 10 */ 532 /* IRQ for channels 10 */
533 .start = 88, 533 .start = evt2irq(0xd00),
534 .end = 88, 534 .end = evt2irq(0xd00),
535 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 535 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
536 }, 536 },
537 { 537 {
538 /* IRQ for channels 11 */ 538 /* IRQ for channels 11 */
539 .start = 88, 539 .start = evt2irq(0xd00),
540 .end = 88, 540 .end = evt2irq(0xd00),
541 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 541 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
542 }, 542 },
543}; 543};
@@ -558,20 +558,20 @@ static struct resource sh7757_dmae2_resources[] = {
558 }, 558 },
559 { 559 {
560 .name = "error_irq", 560 .name = "error_irq",
561 .start = 323, 561 .start = evt2irq(0x2a60),
562 .end = 323, 562 .end = evt2irq(0x2a60),
563 .flags = IORESOURCE_IRQ, 563 .flags = IORESOURCE_IRQ,
564 }, 564 },
565 { 565 {
566 /* IRQ for channels 12 to 16 */ 566 /* IRQ for channels 12 to 16 */
567 .start = 272, 567 .start = evt2irq(0x2400),
568 .end = 276, 568 .end = evt2irq(0x2480),
569 .flags = IORESOURCE_IRQ, 569 .flags = IORESOURCE_IRQ,
570 }, 570 },
571 { 571 {
572 /* IRQ for channel 17 */ 572 /* IRQ for channel 17 */
573 .start = 279, 573 .start = evt2irq(0x24e0),
574 .end = 279, 574 .end = evt2irq(0x24e0),
575 .flags = IORESOURCE_IRQ, 575 .flags = IORESOURCE_IRQ,
576 }, 576 },
577}; 577};
@@ -592,20 +592,20 @@ static struct resource sh7757_dmae3_resources[] = {
592 }, 592 },
593 { 593 {
594 .name = "error_irq", 594 .name = "error_irq",
595 .start = 324, 595 .start = evt2irq(0x2a80),
596 .end = 324, 596 .end = evt2irq(0x2a80),
597 .flags = IORESOURCE_IRQ, 597 .flags = IORESOURCE_IRQ,
598 }, 598 },
599 { 599 {
600 /* IRQ for channels 18 to 22 */ 600 /* IRQ for channels 18 to 22 */
601 .start = 280, 601 .start = evt2irq(0x2500),
602 .end = 284, 602 .end = evt2irq(0x2580),
603 .flags = IORESOURCE_IRQ, 603 .flags = IORESOURCE_IRQ,
604 }, 604 },
605 { 605 {
606 /* IRQ for channel 23 */ 606 /* IRQ for channel 23 */
607 .start = 288, 607 .start = evt2irq(0x2600),
608 .end = 288, 608 .end = evt2irq(0x2600),
609 .flags = IORESOURCE_IRQ, 609 .flags = IORESOURCE_IRQ,
610 }, 610 },
611}; 611};
@@ -668,7 +668,7 @@ static struct resource spi1_resources[] = {
668 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, 668 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
669 }, 669 },
670 { 670 {
671 .start = 54, 671 .start = evt2irq(0x8c0),
672 .flags = IORESOURCE_IRQ, 672 .flags = IORESOURCE_IRQ,
673 }, 673 },
674}; 674};
@@ -687,7 +687,7 @@ static struct resource rspi_resources[] = {
687 .flags = IORESOURCE_MEM, 687 .flags = IORESOURCE_MEM,
688 }, 688 },
689 { 689 {
690 .start = 220, 690 .start = evt2irq(0x1d80),
691 .flags = IORESOURCE_IRQ, 691 .flags = IORESOURCE_IRQ,
692 }, 692 },
693}; 693};
@@ -706,8 +706,8 @@ static struct resource usb_ehci_resources[] = {
706 .flags = IORESOURCE_MEM, 706 .flags = IORESOURCE_MEM,
707 }, 707 },
708 [1] = { 708 [1] = {
709 .start = 57, 709 .start = evt2irq(0x920),
710 .end = 57, 710 .end = evt2irq(0x920),
711 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
712 }, 712 },
713}; 713};
@@ -730,8 +730,8 @@ static struct resource usb_ohci_resources[] = {
730 .flags = IORESOURCE_MEM, 730 .flags = IORESOURCE_MEM,
731 }, 731 },
732 [1] = { 732 [1] = {
733 .start = 57, 733 .start = evt2irq(0x920),
734 .end = 57, 734 .end = evt2irq(0x920),
735 .flags = IORESOURCE_IRQ, 735 .flags = IORESOURCE_IRQ,
736 }, 736 },
737}; 737};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 00113515f233..bd0a8fbe610f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/sh_timer.h> 15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/serial_sci.h> 18#include <linux/serial_sci.h>
18 19
@@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2, 24 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 25 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 }, 26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27}; 28};
28 29
@@ -40,7 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
41 .scbrr_algo_id = SCBRR_ALGO_2, 42 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 43 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 }, 44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
45}; 46};
46 47
@@ -58,7 +59,7 @@ static struct plat_sci_port scif2_platform_data = {
58 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 59 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
59 .scbrr_algo_id = SCBRR_ALGO_2, 60 .scbrr_algo_id = SCBRR_ALGO_2,
60 .type = PORT_SCIF, 61 .type = PORT_SCIF,
61 .irqs = { 104, 104, 104, 104 }, 62 .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)),
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 63 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
63}; 64};
64 65
@@ -78,7 +79,7 @@ static struct resource rtc_resources[] = {
78 }, 79 },
79 [1] = { 80 [1] = {
80 /* Shared Period/Carry/Alarm IRQ */ 81 /* Shared Period/Carry/Alarm IRQ */
81 .start = 20, 82 .start = evt2irq(0x480),
82 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
83 }, 84 },
84}; 85};
@@ -97,13 +98,14 @@ static struct resource usb_ohci_resources[] = {
97 .flags = IORESOURCE_MEM, 98 .flags = IORESOURCE_MEM,
98 }, 99 },
99 [1] = { 100 [1] = {
100 .start = 83, 101 .start = evt2irq(0xc60),
101 .end = 83, 102 .end = evt2irq(0xc60),
102 .flags = IORESOURCE_IRQ, 103 .flags = IORESOURCE_IRQ,
103 }, 104 },
104}; 105};
105 106
106static u64 usb_ohci_dma_mask = 0xffffffffUL; 107static u64 usb_ohci_dma_mask = 0xffffffffUL;
108
107static struct platform_device usb_ohci_device = { 109static struct platform_device usb_ohci_device = {
108 .name = "sh_ohci", 110 .name = "sh_ohci",
109 .id = -1, 111 .id = -1,
@@ -122,8 +124,8 @@ static struct resource usbf_resources[] = {
122 .flags = IORESOURCE_MEM, 124 .flags = IORESOURCE_MEM,
123 }, 125 },
124 [1] = { 126 [1] = {
125 .start = 84, 127 .start = evt2irq(0xc80),
126 .end = 84, 128 .end = evt2irq(0xc80),
127 .flags = IORESOURCE_IRQ, 129 .flags = IORESOURCE_IRQ,
128 }, 130 },
129}; 131};
@@ -152,7 +154,7 @@ static struct resource tmu0_resources[] = {
152 .flags = IORESOURCE_MEM, 154 .flags = IORESOURCE_MEM,
153 }, 155 },
154 [1] = { 156 [1] = {
155 .start = 28, 157 .start = evt2irq(0x580),
156 .flags = IORESOURCE_IRQ, 158 .flags = IORESOURCE_IRQ,
157 }, 159 },
158}; 160};
@@ -180,7 +182,7 @@ static struct resource tmu1_resources[] = {
180 .flags = IORESOURCE_MEM, 182 .flags = IORESOURCE_MEM,
181 }, 183 },
182 [1] = { 184 [1] = {
183 .start = 29, 185 .start = evt2irq(0x5a0),
184 .flags = IORESOURCE_IRQ, 186 .flags = IORESOURCE_IRQ,
185 }, 187 },
186}; 188};
@@ -207,7 +209,7 @@ static struct resource tmu2_resources[] = {
207 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
208 }, 210 },
209 [1] = { 211 [1] = {
210 .start = 30, 212 .start = evt2irq(0x5c0),
211 .flags = IORESOURCE_IRQ, 213 .flags = IORESOURCE_IRQ,
212 }, 214 },
213}; 215};
@@ -234,7 +236,7 @@ static struct resource tmu3_resources[] = {
234 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
235 }, 237 },
236 [1] = { 238 [1] = {
237 .start = 96, 239 .start = evt2irq(0xe00),
238 .flags = IORESOURCE_IRQ, 240 .flags = IORESOURCE_IRQ,
239 }, 241 },
240}; 242};
@@ -261,7 +263,7 @@ static struct resource tmu4_resources[] = {
261 .flags = IORESOURCE_MEM, 263 .flags = IORESOURCE_MEM,
262 }, 264 },
263 [1] = { 265 [1] = {
264 .start = 97, 266 .start = evt2irq(0xe20),
265 .flags = IORESOURCE_IRQ, 267 .flags = IORESOURCE_IRQ,
266 }, 268 },
267}; 269};
@@ -288,7 +290,7 @@ static struct resource tmu5_resources[] = {
288 .flags = IORESOURCE_MEM, 290 .flags = IORESOURCE_MEM,
289 }, 291 },
290 [1] = { 292 [1] = {
291 .start = 98, 293 .start = evt2irq(0xe40),
292 .flags = IORESOURCE_IRQ, 294 .flags = IORESOURCE_IRQ,
293 }, 295 },
294}; 296};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 2c6aa22cf5f6..256ea7a45164 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h> 14#include <linux/sh_timer.h>
15#include <linux/sh_intc.h>
15#include <linux/io.h> 16#include <linux/io.h>
16 17
17static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
@@ -20,7 +21,7 @@ static struct plat_sci_port scif0_platform_data = {
20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
21 .scbrr_algo_id = SCBRR_ALGO_2, 22 .scbrr_algo_id = SCBRR_ALGO_2,
22 .type = PORT_SCIF, 23 .type = PORT_SCIF,
23 .irqs = { 61, 61, 61, 61 }, 24 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
24}; 25};
25 26
26static struct platform_device scif0_device = { 27static struct platform_device scif0_device = {
@@ -37,7 +38,7 @@ static struct plat_sci_port scif1_platform_data = {
37 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 38 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
38 .scbrr_algo_id = SCBRR_ALGO_2, 39 .scbrr_algo_id = SCBRR_ALGO_2,
39 .type = PORT_SCIF, 40 .type = PORT_SCIF,
40 .irqs = { 62, 62, 62, 62 }, 41 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
41}; 42};
42 43
43static struct platform_device scif1_device = { 44static struct platform_device scif1_device = {
@@ -54,7 +55,7 @@ static struct plat_sci_port scif2_platform_data = {
54 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
55 .scbrr_algo_id = SCBRR_ALGO_2, 56 .scbrr_algo_id = SCBRR_ALGO_2,
56 .type = PORT_SCIF, 57 .type = PORT_SCIF,
57 .irqs = { 63, 63, 63, 63 }, 58 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
58}; 59};
59 60
60static struct platform_device scif2_device = { 61static struct platform_device scif2_device = {
@@ -71,7 +72,7 @@ static struct plat_sci_port scif3_platform_data = {
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
72 .scbrr_algo_id = SCBRR_ALGO_2, 73 .scbrr_algo_id = SCBRR_ALGO_2,
73 .type = PORT_SCIF, 74 .type = PORT_SCIF,
74 .irqs = { 64, 64, 64, 64 }, 75 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)),
75}; 76};
76 77
77static struct platform_device scif3_device = { 78static struct platform_device scif3_device = {
@@ -88,7 +89,7 @@ static struct plat_sci_port scif4_platform_data = {
88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
89 .scbrr_algo_id = SCBRR_ALGO_2, 90 .scbrr_algo_id = SCBRR_ALGO_2,
90 .type = PORT_SCIF, 91 .type = PORT_SCIF,
91 .irqs = { 65, 65, 65, 65 }, 92 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)),
92}; 93};
93 94
94static struct platform_device scif4_device = { 95static struct platform_device scif4_device = {
@@ -105,7 +106,7 @@ static struct plat_sci_port scif5_platform_data = {
105 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 106 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
106 .scbrr_algo_id = SCBRR_ALGO_2, 107 .scbrr_algo_id = SCBRR_ALGO_2,
107 .type = PORT_SCIF, 108 .type = PORT_SCIF,
108 .irqs = { 66, 66, 66, 66 }, 109 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)),
109}; 110};
110 111
111static struct platform_device scif5_device = { 112static struct platform_device scif5_device = {
@@ -122,7 +123,7 @@ static struct plat_sci_port scif6_platform_data = {
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 123 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
123 .scbrr_algo_id = SCBRR_ALGO_2, 124 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 125 .type = PORT_SCIF,
125 .irqs = { 67, 67, 67, 67 }, 126 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)),
126}; 127};
127 128
128static struct platform_device scif6_device = { 129static struct platform_device scif6_device = {
@@ -139,7 +140,7 @@ static struct plat_sci_port scif7_platform_data = {
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
140 .scbrr_algo_id = SCBRR_ALGO_2, 141 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 142 .type = PORT_SCIF,
142 .irqs = { 68, 68, 68, 68 }, 143 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)),
143}; 144};
144 145
145static struct platform_device scif7_device = { 146static struct platform_device scif7_device = {
@@ -156,7 +157,7 @@ static struct plat_sci_port scif8_platform_data = {
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
157 .scbrr_algo_id = SCBRR_ALGO_2, 158 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 159 .type = PORT_SCIF,
159 .irqs = { 69, 69, 69, 69 }, 160 .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)),
160}; 161};
161 162
162static struct platform_device scif8_device = { 163static struct platform_device scif8_device = {
@@ -173,7 +174,7 @@ static struct plat_sci_port scif9_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 174 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
174 .scbrr_algo_id = SCBRR_ALGO_2, 175 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 176 .type = PORT_SCIF,
176 .irqs = { 70, 70, 70, 70 }, 177 .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)),
177}; 178};
178 179
179static struct platform_device scif9_device = { 180static struct platform_device scif9_device = {
@@ -197,7 +198,7 @@ static struct resource tmu0_resources[] = {
197 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
198 }, 199 },
199 [1] = { 200 [1] = {
200 .start = 16, 201 .start = evt2irq(0x400),
201 .flags = IORESOURCE_IRQ, 202 .flags = IORESOURCE_IRQ,
202 }, 203 },
203}; 204};
@@ -225,7 +226,7 @@ static struct resource tmu1_resources[] = {
225 .flags = IORESOURCE_MEM, 226 .flags = IORESOURCE_MEM,
226 }, 227 },
227 [1] = { 228 [1] = {
228 .start = 17, 229 .start = evt2irq(0x420),
229 .flags = IORESOURCE_IRQ, 230 .flags = IORESOURCE_IRQ,
230 }, 231 },
231}; 232};
@@ -252,7 +253,7 @@ static struct resource tmu2_resources[] = {
252 .flags = IORESOURCE_MEM, 253 .flags = IORESOURCE_MEM,
253 }, 254 },
254 [1] = { 255 [1] = {
255 .start = 18, 256 .start = evt2irq(0x440),
256 .flags = IORESOURCE_IRQ, 257 .flags = IORESOURCE_IRQ,
257 }, 258 },
258}; 259};
@@ -279,7 +280,7 @@ static struct resource tmu3_resources[] = {
279 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
280 }, 281 },
281 [1] = { 282 [1] = {
282 .start = 19, 283 .start = evt2irq(0x460),
283 .flags = IORESOURCE_IRQ, 284 .flags = IORESOURCE_IRQ,
284 }, 285 },
285}; 286};
@@ -306,7 +307,7 @@ static struct resource tmu4_resources[] = {
306 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
307 }, 308 },
308 [1] = { 309 [1] = {
309 .start = 20, 310 .start = evt2irq(0x480),
310 .flags = IORESOURCE_IRQ, 311 .flags = IORESOURCE_IRQ,
311 }, 312 },
312}; 313};
@@ -333,7 +334,7 @@ static struct resource tmu5_resources[] = {
333 .flags = IORESOURCE_MEM, 334 .flags = IORESOURCE_MEM,
334 }, 335 },
335 [1] = { 336 [1] = {
336 .start = 21, 337 .start = evt2irq(0x4a0),
337 .flags = IORESOURCE_IRQ, 338 .flags = IORESOURCE_IRQ,
338 }, 339 },
339}; 340};
@@ -360,7 +361,7 @@ static struct resource tmu6_resources[] = {
360 .flags = IORESOURCE_MEM, 361 .flags = IORESOURCE_MEM,
361 }, 362 },
362 [1] = { 363 [1] = {
363 .start = 22, 364 .start = evt2irq(0x4c0),
364 .flags = IORESOURCE_IRQ, 365 .flags = IORESOURCE_IRQ,
365 }, 366 },
366}; 367};
@@ -387,7 +388,7 @@ static struct resource tmu7_resources[] = {
387 .flags = IORESOURCE_MEM, 388 .flags = IORESOURCE_MEM,
388 }, 389 },
389 [1] = { 390 [1] = {
390 .start = 23, 391 .start = evt2irq(0x4e0),
391 .flags = IORESOURCE_IRQ, 392 .flags = IORESOURCE_IRQ,
392 }, 393 },
393}; 394};
@@ -414,7 +415,7 @@ static struct resource tmu8_resources[] = {
414 .flags = IORESOURCE_MEM, 415 .flags = IORESOURCE_MEM,
415 }, 416 },
416 [1] = { 417 [1] = {
417 .start = 24, 418 .start = evt2irq(0x500),
418 .flags = IORESOURCE_IRQ, 419 .flags = IORESOURCE_IRQ,
419 }, 420 },
420}; 421};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index d431b0052d0c..de45b704687a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -14,6 +14,7 @@
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h> 15#include <linux/sh_dma.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
17#include <cpu/dma-register.h> 18#include <cpu/dma-register.h>
18 19
19static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
@@ -22,7 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
23 .scbrr_algo_id = SCBRR_ALGO_1, 24 .scbrr_algo_id = SCBRR_ALGO_1,
24 .type = PORT_SCIF, 25 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 }, 26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27}; 28};
28 29
@@ -40,7 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_1, 42 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF, 43 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 }, 44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
45}; 46};
46 47
@@ -65,7 +66,7 @@ static struct resource tmu0_resources[] = {
65 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
66 }, 67 },
67 [1] = { 68 [1] = {
68 .start = 28, 69 .start = evt2irq(0x580),
69 .flags = IORESOURCE_IRQ, 70 .flags = IORESOURCE_IRQ,
70 }, 71 },
71}; 72};
@@ -93,7 +94,7 @@ static struct resource tmu1_resources[] = {
93 .flags = IORESOURCE_MEM, 94 .flags = IORESOURCE_MEM,
94 }, 95 },
95 [1] = { 96 [1] = {
96 .start = 29, 97 .start = evt2irq(0x5a0),
97 .flags = IORESOURCE_IRQ, 98 .flags = IORESOURCE_IRQ,
98 }, 99 },
99}; 100};
@@ -120,7 +121,7 @@ static struct resource tmu2_resources[] = {
120 .flags = IORESOURCE_MEM, 121 .flags = IORESOURCE_MEM,
121 }, 122 },
122 [1] = { 123 [1] = {
123 .start = 30, 124 .start = evt2irq(0x5c0),
124 .flags = IORESOURCE_IRQ, 125 .flags = IORESOURCE_IRQ,
125 }, 126 },
126}; 127};
@@ -147,7 +148,7 @@ static struct resource tmu3_resources[] = {
147 .flags = IORESOURCE_MEM, 148 .flags = IORESOURCE_MEM,
148 }, 149 },
149 [1] = { 150 [1] = {
150 .start = 96, 151 .start = evt2irq(0xe00),
151 .flags = IORESOURCE_IRQ, 152 .flags = IORESOURCE_IRQ,
152 }, 153 },
153}; 154};
@@ -174,7 +175,7 @@ static struct resource tmu4_resources[] = {
174 .flags = IORESOURCE_MEM, 175 .flags = IORESOURCE_MEM,
175 }, 176 },
176 [1] = { 177 [1] = {
177 .start = 97, 178 .start = evt2irq(0xe20),
178 .flags = IORESOURCE_IRQ, 179 .flags = IORESOURCE_IRQ,
179 }, 180 },
180}; 181};
@@ -201,7 +202,7 @@ static struct resource tmu5_resources[] = {
201 .flags = IORESOURCE_MEM, 202 .flags = IORESOURCE_MEM,
202 }, 203 },
203 [1] = { 204 [1] = {
204 .start = 98, 205 .start = evt2irq(0xe40),
205 .flags = IORESOURCE_IRQ, 206 .flags = IORESOURCE_IRQ,
206 }, 207 },
207}; 208};
@@ -224,7 +225,7 @@ static struct resource rtc_resources[] = {
224 }, 225 },
225 [1] = { 226 [1] = {
226 /* Shared Period/Carry/Alarm IRQ */ 227 /* Shared Period/Carry/Alarm IRQ */
227 .start = 20, 228 .start = evt2irq(0x480),
228 .flags = IORESOURCE_IRQ, 229 .flags = IORESOURCE_IRQ,
229 }, 230 },
230}; 231};
@@ -321,10 +322,13 @@ static struct resource sh7780_dmae0_resources[] = {
321 .flags = IORESOURCE_MEM, 322 .flags = IORESOURCE_MEM,
322 }, 323 },
323 { 324 {
324 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */ 325 /*
326 * Real DMA error vector is 0x6c0, and channel
327 * vectors are 0x640-0x6a0, 0x780-0x7a0
328 */
325 .name = "error_irq", 329 .name = "error_irq",
326 .start = 34, 330 .start = evt2irq(0x640),
327 .end = 34, 331 .end = evt2irq(0x640),
328 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 332 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
329 }, 333 },
330}; 334};
@@ -338,10 +342,13 @@ static struct resource sh7780_dmae1_resources[] = {
338 }, 342 },
339 /* DMAC1 has no DMARS */ 343 /* DMAC1 has no DMARS */
340 { 344 {
341 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */ 345 /*
346 * Real DMA error vector is 0x6c0, and channel
347 * vectors are 0x7c0-0x7e0, 0xd80-0xde0
348 */
342 .name = "error_irq", 349 .name = "error_irq",
343 .start = 46, 350 .start = evt2irq(0x7c0),
344 .end = 46, 351 .end = evt2irq(0x7c0),
345 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 352 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
346 }, 353 },
347}; 354};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 81588ef15a6c..0968ecb962e6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -15,6 +15,7 @@
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_dma.h> 16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18#include <linux/sh_intc.h>
18#include <asm/mmzone.h> 19#include <asm/mmzone.h>
19#include <cpu/dma-register.h> 20#include <cpu/dma-register.h>
20 21
@@ -24,7 +25,7 @@ static struct plat_sci_port scif0_platform_data = {
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
25 .scbrr_algo_id = SCBRR_ALGO_1, 26 .scbrr_algo_id = SCBRR_ALGO_1,
26 .type = PORT_SCIF, 27 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 28 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 29 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29}; 30};
30 31
@@ -42,7 +43,7 @@ static struct plat_sci_port scif1_platform_data = {
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
43 .scbrr_algo_id = SCBRR_ALGO_1, 44 .scbrr_algo_id = SCBRR_ALGO_1,
44 .type = PORT_SCIF, 45 .type = PORT_SCIF,
45 .irqs = { 44, 44, 44, 44 }, 46 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 48};
48 49
@@ -60,7 +61,7 @@ static struct plat_sci_port scif2_platform_data = {
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
61 .scbrr_algo_id = SCBRR_ALGO_1, 62 .scbrr_algo_id = SCBRR_ALGO_1,
62 .type = PORT_SCIF, 63 .type = PORT_SCIF,
63 .irqs = { 60, 60, 60, 60 }, 64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65}; 66};
66 67
@@ -78,7 +79,7 @@ static struct plat_sci_port scif3_platform_data = {
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 79 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
79 .scbrr_algo_id = SCBRR_ALGO_1, 80 .scbrr_algo_id = SCBRR_ALGO_1,
80 .type = PORT_SCIF, 81 .type = PORT_SCIF,
81 .irqs = { 61, 61, 61, 61 }, 82 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 83 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
83}; 84};
84 85
@@ -96,7 +97,7 @@ static struct plat_sci_port scif4_platform_data = {
96 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
97 .scbrr_algo_id = SCBRR_ALGO_1, 98 .scbrr_algo_id = SCBRR_ALGO_1,
98 .type = PORT_SCIF, 99 .type = PORT_SCIF,
99 .irqs = { 62, 62, 62, 62 }, 100 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 101 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
101}; 102};
102 103
@@ -114,7 +115,7 @@ static struct plat_sci_port scif5_platform_data = {
114 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 115 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
115 .scbrr_algo_id = SCBRR_ALGO_1, 116 .scbrr_algo_id = SCBRR_ALGO_1,
116 .type = PORT_SCIF, 117 .type = PORT_SCIF,
117 .irqs = { 63, 63, 63, 63 }, 118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
119}; 120};
120 121
@@ -139,7 +140,7 @@ static struct resource tmu0_resources[] = {
139 .flags = IORESOURCE_MEM, 140 .flags = IORESOURCE_MEM,
140 }, 141 },
141 [1] = { 142 [1] = {
142 .start = 28, 143 .start = evt2irq(0x580),
143 .flags = IORESOURCE_IRQ, 144 .flags = IORESOURCE_IRQ,
144 }, 145 },
145}; 146};
@@ -167,7 +168,7 @@ static struct resource tmu1_resources[] = {
167 .flags = IORESOURCE_MEM, 168 .flags = IORESOURCE_MEM,
168 }, 169 },
169 [1] = { 170 [1] = {
170 .start = 29, 171 .start = evt2irq(0x5a0),
171 .flags = IORESOURCE_IRQ, 172 .flags = IORESOURCE_IRQ,
172 }, 173 },
173}; 174};
@@ -194,7 +195,7 @@ static struct resource tmu2_resources[] = {
194 .flags = IORESOURCE_MEM, 195 .flags = IORESOURCE_MEM,
195 }, 196 },
196 [1] = { 197 [1] = {
197 .start = 30, 198 .start = evt2irq(0x5c0),
198 .flags = IORESOURCE_IRQ, 199 .flags = IORESOURCE_IRQ,
199 }, 200 },
200}; 201};
@@ -221,7 +222,7 @@ static struct resource tmu3_resources[] = {
221 .flags = IORESOURCE_MEM, 222 .flags = IORESOURCE_MEM,
222 }, 223 },
223 [1] = { 224 [1] = {
224 .start = 96, 225 .start = evt2irq(0xe00),
225 .flags = IORESOURCE_IRQ, 226 .flags = IORESOURCE_IRQ,
226 }, 227 },
227}; 228};
@@ -248,7 +249,7 @@ static struct resource tmu4_resources[] = {
248 .flags = IORESOURCE_MEM, 249 .flags = IORESOURCE_MEM,
249 }, 250 },
250 [1] = { 251 [1] = {
251 .start = 97, 252 .start = evt2irq(0xe20),
252 .flags = IORESOURCE_IRQ, 253 .flags = IORESOURCE_IRQ,
253 }, 254 },
254}; 255};
@@ -275,7 +276,7 @@ static struct resource tmu5_resources[] = {
275 .flags = IORESOURCE_MEM, 276 .flags = IORESOURCE_MEM,
276 }, 277 },
277 [1] = { 278 [1] = {
278 .start = 98, 279 .start = evt2irq(0xe40),
279 .flags = IORESOURCE_IRQ, 280 .flags = IORESOURCE_IRQ,
280 }, 281 },
281}; 282};
@@ -375,10 +376,13 @@ static struct resource sh7785_dmae0_resources[] = {
375 .flags = IORESOURCE_MEM, 376 .flags = IORESOURCE_MEM,
376 }, 377 },
377 { 378 {
378 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */ 379 /*
380 * Real DMA error vector is 0x6e0, and channel
381 * vectors are 0x620-0x6c0
382 */
379 .name = "error_irq", 383 .name = "error_irq",
380 .start = 33, 384 .start = evt2irq(0x620),
381 .end = 33, 385 .end = evt2irq(0x620),
382 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
383 }, 387 },
384}; 388};
@@ -392,10 +396,13 @@ static struct resource sh7785_dmae1_resources[] = {
392 }, 396 },
393 /* DMAC1 has no DMARS */ 397 /* DMAC1 has no DMARS */
394 { 398 {
395 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */ 399 /*
400 * Real DMA error vector is 0x940, and channel
401 * vectors are 0x880-0x920
402 */
396 .name = "error_irq", 403 .name = "error_irq",
397 .start = 52, 404 .start = evt2irq(0x880),
398 .end = 52, 405 .end = evt2irq(0x880),
399 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE, 406 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
400 }, 407 },
401}; 408};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 599022d73b28..2e6952f87848 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -32,7 +32,10 @@ static struct plat_sci_port scif0_platform_data = {
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
33 .scbrr_algo_id = SCBRR_ALGO_1, 33 .scbrr_algo_id = SCBRR_ALGO_1,
34 .type = PORT_SCIF, 34 .type = PORT_SCIF,
35 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { evt2irq(0x700),
36 evt2irq(0x720),
37 evt2irq(0x760),
38 evt2irq(0x740) },
36 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 39 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
37}; 40};
38 41
@@ -53,7 +56,7 @@ static struct plat_sci_port scif1_platform_data = {
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 56 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
54 .scbrr_algo_id = SCBRR_ALGO_1, 57 .scbrr_algo_id = SCBRR_ALGO_1,
55 .type = PORT_SCIF, 58 .type = PORT_SCIF,
56 .irqs = { 44, 44, 44, 44 }, 59 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 60 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
58}; 61};
59 62
@@ -71,7 +74,7 @@ static struct plat_sci_port scif2_platform_data = {
71 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
72 .scbrr_algo_id = SCBRR_ALGO_1, 75 .scbrr_algo_id = SCBRR_ALGO_1,
73 .type = PORT_SCIF, 76 .type = PORT_SCIF,
74 .irqs = { 50, 50, 50, 50 }, 77 .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)),
75 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 78 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
76}; 79};
77 80
@@ -89,7 +92,7 @@ static struct plat_sci_port scif3_platform_data = {
89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 92 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
90 .scbrr_algo_id = SCBRR_ALGO_1, 93 .scbrr_algo_id = SCBRR_ALGO_1,
91 .type = PORT_SCIF, 94 .type = PORT_SCIF,
92 .irqs = { 51, 51, 51, 51 }, 95 .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)),
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 96 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
94}; 97};
95 98
@@ -107,7 +110,7 @@ static struct plat_sci_port scif4_platform_data = {
107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 110 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
108 .scbrr_algo_id = SCBRR_ALGO_1, 111 .scbrr_algo_id = SCBRR_ALGO_1,
109 .type = PORT_SCIF, 112 .type = PORT_SCIF,
110 .irqs = { 52, 52, 52, 52 }, 113 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 114 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
112}; 115};
113 116
@@ -125,7 +128,7 @@ static struct plat_sci_port scif5_platform_data = {
125 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 128 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
126 .scbrr_algo_id = SCBRR_ALGO_1, 129 .scbrr_algo_id = SCBRR_ALGO_1,
127 .type = PORT_SCIF, 130 .type = PORT_SCIF,
128 .irqs = { 53, 53, 53, 53 }, 131 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 132 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
130}; 133};
131 134
@@ -150,7 +153,7 @@ static struct resource tmu0_resources[] = {
150 .flags = IORESOURCE_MEM, 153 .flags = IORESOURCE_MEM,
151 }, 154 },
152 [1] = { 155 [1] = {
153 .start = 16, 156 .start = evt2irq(0x400),
154 .flags = IORESOURCE_IRQ, 157 .flags = IORESOURCE_IRQ,
155 }, 158 },
156}; 159};
@@ -178,7 +181,7 @@ static struct resource tmu1_resources[] = {
178 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
179 }, 182 },
180 [1] = { 183 [1] = {
181 .start = 17, 184 .start = evt2irq(0x420),
182 .flags = IORESOURCE_IRQ, 185 .flags = IORESOURCE_IRQ,
183 }, 186 },
184}; 187};
@@ -205,7 +208,7 @@ static struct resource tmu2_resources[] = {
205 .flags = IORESOURCE_MEM, 208 .flags = IORESOURCE_MEM,
206 }, 209 },
207 [1] = { 210 [1] = {
208 .start = 18, 211 .start = evt2irq(0x440),
209 .flags = IORESOURCE_IRQ, 212 .flags = IORESOURCE_IRQ,
210 }, 213 },
211}; 214};
@@ -232,7 +235,7 @@ static struct resource tmu3_resources[] = {
232 .flags = IORESOURCE_MEM, 235 .flags = IORESOURCE_MEM,
233 }, 236 },
234 [1] = { 237 [1] = {
235 .start = 20, 238 .start = evt2irq(0x480),
236 .flags = IORESOURCE_IRQ, 239 .flags = IORESOURCE_IRQ,
237 }, 240 },
238}; 241};
@@ -259,7 +262,7 @@ static struct resource tmu4_resources[] = {
259 .flags = IORESOURCE_MEM, 262 .flags = IORESOURCE_MEM,
260 }, 263 },
261 [1] = { 264 [1] = {
262 .start = 21, 265 .start = evt2irq(0x4a0),
263 .flags = IORESOURCE_IRQ, 266 .flags = IORESOURCE_IRQ,
264 }, 267 },
265}; 268};
@@ -286,7 +289,7 @@ static struct resource tmu5_resources[] = {
286 .flags = IORESOURCE_MEM, 289 .flags = IORESOURCE_MEM,
287 }, 290 },
288 [1] = { 291 [1] = {
289 .start = 22, 292 .start = evt2irq(0x4c0),
290 .flags = IORESOURCE_IRQ, 293 .flags = IORESOURCE_IRQ,
291 }, 294 },
292}; 295};
@@ -313,7 +316,7 @@ static struct resource tmu6_resources[] = {
313 .flags = IORESOURCE_MEM, 316 .flags = IORESOURCE_MEM,
314 }, 317 },
315 [1] = { 318 [1] = {
316 .start = 45, 319 .start = evt2irq(0x7a0),
317 .flags = IORESOURCE_IRQ, 320 .flags = IORESOURCE_IRQ,
318 }, 321 },
319}; 322};
@@ -340,7 +343,7 @@ static struct resource tmu7_resources[] = {
340 .flags = IORESOURCE_MEM, 343 .flags = IORESOURCE_MEM,
341 }, 344 },
342 [1] = { 345 [1] = {
343 .start = 45, 346 .start = evt2irq(0x7a0),
344 .flags = IORESOURCE_IRQ, 347 .flags = IORESOURCE_IRQ,
345 }, 348 },
346}; 349};
@@ -367,7 +370,7 @@ static struct resource tmu8_resources[] = {
367 .flags = IORESOURCE_MEM, 370 .flags = IORESOURCE_MEM,
368 }, 371 },
369 [1] = { 372 [1] = {
370 .start = 45, 373 .start = evt2irq(0x7a0),
371 .flags = IORESOURCE_IRQ, 374 .flags = IORESOURCE_IRQ,
372 }, 375 },
373}; 376};
@@ -394,7 +397,7 @@ static struct resource tmu9_resources[] = {
394 .flags = IORESOURCE_MEM, 397 .flags = IORESOURCE_MEM,
395 }, 398 },
396 [1] = { 399 [1] = {
397 .start = 46, 400 .start = evt2irq(0x7c0),
398 .flags = IORESOURCE_IRQ, 401 .flags = IORESOURCE_IRQ,
399 }, 402 },
400}; 403};
@@ -421,7 +424,7 @@ static struct resource tmu10_resources[] = {
421 .flags = IORESOURCE_MEM, 424 .flags = IORESOURCE_MEM,
422 }, 425 },
423 [1] = { 426 [1] = {
424 .start = 46, 427 .start = evt2irq(0x7c0),
425 .flags = IORESOURCE_IRQ, 428 .flags = IORESOURCE_IRQ,
426 }, 429 },
427}; 430};
@@ -448,7 +451,7 @@ static struct resource tmu11_resources[] = {
448 .flags = IORESOURCE_MEM, 451 .flags = IORESOURCE_MEM,
449 }, 452 },
450 [1] = { 453 [1] = {
451 .start = 46, 454 .start = evt2irq(0x7c0),
452 .flags = IORESOURCE_IRQ, 455 .flags = IORESOURCE_IRQ,
453 }, 456 },
454}; 457};
@@ -550,8 +553,8 @@ static struct resource usb_ehci_resources[] = {
550 .flags = IORESOURCE_MEM, 553 .flags = IORESOURCE_MEM,
551 }, 554 },
552 [1] = { 555 [1] = {
553 .start = 77, 556 .start = evt2irq(0xba0),
554 .end = 77, 557 .end = evt2irq(0xba0),
555 .flags = IORESOURCE_IRQ, 558 .flags = IORESOURCE_IRQ,
556 }, 559 },
557}; 560};
@@ -574,8 +577,8 @@ static struct resource usb_ohci_resources[] = {
574 .flags = IORESOURCE_MEM, 577 .flags = IORESOURCE_MEM,
575 }, 578 },
576 [1] = { 579 [1] = {
577 .start = 77, 580 .start = evt2irq(0xba0),
578 .end = 77, 581 .end = evt2irq(0xba0),
579 .flags = IORESOURCE_IRQ, 582 .flags = IORESOURCE_IRQ,
580 }, 583 },
581}; 584};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index bb208806dc1a..688f7ed1bab1 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <linux/sh_intc.h>
17#include <cpu/shx3.h> 18#include <cpu/shx3.h>
18#include <asm/mmzone.h> 19#include <asm/mmzone.h>
19 20
@@ -32,7 +33,10 @@ static struct plat_sci_port scif0_platform_data = {
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
33 .scbrr_algo_id = SCBRR_ALGO_2, 34 .scbrr_algo_id = SCBRR_ALGO_2,
34 .type = PORT_SCIF, 35 .type = PORT_SCIF,
35 .irqs = { 40, 41, 43, 42 }, 36 .irqs = { evt2irq(0x700),
37 evt2irq(0x720),
38 evt2irq(0x760),
39 evt2irq(0x740) },
36}; 40};
37 41
38static struct platform_device scif0_device = { 42static struct platform_device scif0_device = {
@@ -49,7 +53,10 @@ static struct plat_sci_port scif1_platform_data = {
49 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
50 .scbrr_algo_id = SCBRR_ALGO_2, 54 .scbrr_algo_id = SCBRR_ALGO_2,
51 .type = PORT_SCIF, 55 .type = PORT_SCIF,
52 .irqs = { 44, 45, 47, 46 }, 56 .irqs = { evt2irq(0x780),
57 evt2irq(0x7a0),
58 evt2irq(0x7e0),
59 evt2irq(0x7c0) },
53}; 60};
54 61
55static struct platform_device scif1_device = { 62static struct platform_device scif1_device = {
@@ -66,7 +73,10 @@ static struct plat_sci_port scif2_platform_data = {
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2, 74 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 75 .type = PORT_SCIF,
69 .irqs = { 52, 53, 55, 54 }, 76 .irqs = { evt2irq(0x880),
77 evt2irq(0x8a0),
78 evt2irq(0x8e0),
79 evt2irq(0x8c0) },
70}; 80};
71 81
72static struct platform_device scif2_device = { 82static struct platform_device scif2_device = {
@@ -90,7 +100,7 @@ static struct resource tmu0_resources[] = {
90 .flags = IORESOURCE_MEM, 100 .flags = IORESOURCE_MEM,
91 }, 101 },
92 [1] = { 102 [1] = {
93 .start = 16, 103 .start = evt2irq(0x400),
94 .flags = IORESOURCE_IRQ, 104 .flags = IORESOURCE_IRQ,
95 }, 105 },
96}; 106};
@@ -118,7 +128,7 @@ static struct resource tmu1_resources[] = {
118 .flags = IORESOURCE_MEM, 128 .flags = IORESOURCE_MEM,
119 }, 129 },
120 [1] = { 130 [1] = {
121 .start = 17, 131 .start = evt2irq(0x420),
122 .flags = IORESOURCE_IRQ, 132 .flags = IORESOURCE_IRQ,
123 }, 133 },
124}; 134};
@@ -145,7 +155,7 @@ static struct resource tmu2_resources[] = {
145 .flags = IORESOURCE_MEM, 155 .flags = IORESOURCE_MEM,
146 }, 156 },
147 [1] = { 157 [1] = {
148 .start = 18, 158 .start = evt2irq(0x440),
149 .flags = IORESOURCE_IRQ, 159 .flags = IORESOURCE_IRQ,
150 }, 160 },
151}; 161};
@@ -172,7 +182,7 @@ static struct resource tmu3_resources[] = {
172 .flags = IORESOURCE_MEM, 182 .flags = IORESOURCE_MEM,
173 }, 183 },
174 [1] = { 184 [1] = {
175 .start = 19, 185 .start = evt2irq(0x460),
176 .flags = IORESOURCE_IRQ, 186 .flags = IORESOURCE_IRQ,
177 }, 187 },
178}; 188};
@@ -199,7 +209,7 @@ static struct resource tmu4_resources[] = {
199 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
200 }, 210 },
201 [1] = { 211 [1] = {
202 .start = 20, 212 .start = evt2irq(0x480),
203 .flags = IORESOURCE_IRQ, 213 .flags = IORESOURCE_IRQ,
204 }, 214 },
205}; 215};
@@ -226,7 +236,7 @@ static struct resource tmu5_resources[] = {
226 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
227 }, 237 },
228 [1] = { 238 [1] = {
229 .start = 21, 239 .start = evt2irq(0x4a0),
230 .flags = IORESOURCE_IRQ, 240 .flags = IORESOURCE_IRQ,
231 }, 241 },
232}; 242};
@@ -484,9 +494,6 @@ void __init plat_irq_setup_pins(int mode)
484 494
485void __init plat_irq_setup(void) 495void __init plat_irq_setup(void)
486{ 496{
487 reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
488 reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
489
490 register_intc_controller(&intc_desc); 497 register_intc_controller(&intc_desc);
491} 498}
492 499
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 6b80295dd7a4..ff1f0e6e9bec 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -335,7 +335,7 @@ tlb_miss:
335 /* If the fast path handler fixed the fault, just drop through quickly 335 /* If the fast path handler fixed the fault, just drop through quickly
336 to the restore code right away to return to the excepting context. 336 to the restore code right away to return to the excepting context.
337 */ 337 */
338 beqi/u r2, 0, tr1 338 bnei/u r2, 0, tr1
339 339
340fast_tlb_miss_restore: 340fast_tlb_miss_restore:
341 ld.q SP, SAVED_TR0, r2 341 ld.q SP, SAVED_TR0, r2
@@ -1079,9 +1079,8 @@ restore_all:
1079 * 1079 *
1080 * Kernel TLB fault handlers will get a slightly different interface. 1080 * Kernel TLB fault handlers will get a slightly different interface.
1081 * (r2) struct pt_regs *, original register's frame pointer 1081 * (r2) struct pt_regs *, original register's frame pointer
1082 * (r3) writeaccess, whether it's a store fault as opposed to load fault 1082 * (r3) page fault error code (see asm/thread_info.h)
1083 * (r4) execaccess, whether it's a ITLB fault as opposed to DTLB fault 1083 * (r4) Effective Address of fault
1084 * (r5) Effective Address of fault
1085 * (LINK) return address 1084 * (LINK) return address
1086 * (SP) = r2 1085 * (SP) = r2
1087 * 1086 *
@@ -1092,26 +1091,25 @@ restore_all:
1092tlb_miss_load: 1091tlb_miss_load:
1093 or SP, ZERO, r2 1092 or SP, ZERO, r2
1094 or ZERO, ZERO, r3 /* Read */ 1093 or ZERO, ZERO, r3 /* Read */
1095 or ZERO, ZERO, r4 /* Data */ 1094 getcon TEA, r4
1096 getcon TEA, r5
1097 pta call_do_page_fault, tr0 1095 pta call_do_page_fault, tr0
1098 beq ZERO, ZERO, tr0 1096 beq ZERO, ZERO, tr0
1099 1097
1100tlb_miss_store: 1098tlb_miss_store:
1101 or SP, ZERO, r2 1099 or SP, ZERO, r2
1102 movi 1, r3 /* Write */ 1100 movi FAULT_CODE_WRITE, r3 /* Write */
1103 or ZERO, ZERO, r4 /* Data */ 1101 getcon TEA, r4
1104 getcon TEA, r5
1105 pta call_do_page_fault, tr0 1102 pta call_do_page_fault, tr0
1106 beq ZERO, ZERO, tr0 1103 beq ZERO, ZERO, tr0
1107 1104
1108itlb_miss_or_IRQ: 1105itlb_miss_or_IRQ:
1109 pta its_IRQ, tr0 1106 pta its_IRQ, tr0
1110 beqi/u r4, EVENT_INTERRUPT, tr0 1107 beqi/u r4, EVENT_INTERRUPT, tr0
1108
1109 /* ITLB miss */
1111 or SP, ZERO, r2 1110 or SP, ZERO, r2
1112 or ZERO, ZERO, r3 /* Read */ 1111 movi FAULT_CODE_ITLB, r3
1113 movi 1, r4 /* Text */ 1112 getcon TEA, r4
1114 getcon TEA, r5
1115 /* Fall through */ 1113 /* Fall through */
1116 1114
1117call_do_page_fault: 1115call_do_page_fault:
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index 4b3bb35e99f3..9f8713aa7184 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -107,8 +107,5 @@ asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs)
107 107
108 regs->pc += 4; 108 regs->pc += 4;
109 109
110 tsk->thread.trap_no = 11;
111 tsk->thread.error_code = 0;
112
113 force_sig(SIGFPE, tsk); 110 force_sig(SIGFPE, tsk);
114} 111}
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index a3ee91971129..dadce735f746 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -234,8 +234,10 @@ void __init init_IRQ(void)
234#ifdef CONFIG_SPARSE_IRQ 234#ifdef CONFIG_SPARSE_IRQ
235int __init arch_probe_nr_irqs(void) 235int __init arch_probe_nr_irqs(void)
236{ 236{
237 nr_irqs = sh_mv.mv_nr_irqs; 237 /*
238 return NR_IRQS_LEGACY; 238 * No pre-allocated IRQs.
239 */
240 return 0;
239} 241}
240#endif 242#endif
241 243
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index b117781bfea2..38b313909ac9 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SuperH KGDB support 2 * SuperH KGDB support
3 * 3 *
4 * Copyright (C) 2008 - 2009 Paul Mundt 4 * Copyright (C) 2008 - 2012 Paul Mundt
5 * 5 *
6 * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel. 6 * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel.
7 * 7 *
@@ -164,42 +164,89 @@ static void undo_single_step(struct pt_regs *linux_regs)
164 stepped_opcode = 0; 164 stepped_opcode = 0;
165} 165}
166 166
167void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) 167struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
168{ 168 { "r0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[0]) },
169 int i; 169 { "r1", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[1]) },
170 { "r2", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[2]) },
171 { "r3", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[3]) },
172 { "r4", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[4]) },
173 { "r5", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[5]) },
174 { "r6", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[6]) },
175 { "r7", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[7]) },
176 { "r8", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[8]) },
177 { "r9", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[9]) },
178 { "r10", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[10]) },
179 { "r11", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[11]) },
180 { "r12", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[12]) },
181 { "r13", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[13]) },
182 { "r14", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[14]) },
183 { "r15", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[15]) },
184 { "pc", GDB_SIZEOF_REG, offsetof(struct pt_regs, pc) },
185 { "pr", GDB_SIZEOF_REG, offsetof(struct pt_regs, pr) },
186 { "sr", GDB_SIZEOF_REG, offsetof(struct pt_regs, sr) },
187 { "gbr", GDB_SIZEOF_REG, offsetof(struct pt_regs, gbr) },
188 { "mach", GDB_SIZEOF_REG, offsetof(struct pt_regs, mach) },
189 { "macl", GDB_SIZEOF_REG, offsetof(struct pt_regs, macl) },
190 { "vbr", GDB_SIZEOF_REG, -1 },
191};
170 192
171 for (i = 0; i < 16; i++) 193int dbg_set_reg(int regno, void *mem, struct pt_regs *regs)
172 gdb_regs[GDB_R0 + i] = regs->regs[i]; 194{
195 if (regno < 0 || regno >= DBG_MAX_REG_NUM)
196 return -EINVAL;
173 197
174 gdb_regs[GDB_PC] = regs->pc; 198 if (dbg_reg_def[regno].offset != -1)
175 gdb_regs[GDB_PR] = regs->pr; 199 memcpy((void *)regs + dbg_reg_def[regno].offset, mem,
176 gdb_regs[GDB_SR] = regs->sr; 200 dbg_reg_def[regno].size);
177 gdb_regs[GDB_GBR] = regs->gbr;
178 gdb_regs[GDB_MACH] = regs->mach;
179 gdb_regs[GDB_MACL] = regs->macl;
180 201
181 __asm__ __volatile__ ("stc vbr, %0" : "=r" (gdb_regs[GDB_VBR])); 202 return 0;
182} 203}
183 204
184void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) 205char *dbg_get_reg(int regno, void *mem, struct pt_regs *regs)
185{ 206{
186 int i; 207 if (regno >= DBG_MAX_REG_NUM || regno < 0)
208 return NULL;
187 209
188 for (i = 0; i < 16; i++) 210 if (dbg_reg_def[regno].size != -1)
189 regs->regs[GDB_R0 + i] = gdb_regs[GDB_R0 + i]; 211 memcpy(mem, (void *)regs + dbg_reg_def[regno].offset,
212 dbg_reg_def[regno].size);
213
214 switch (regno) {
215 case GDB_VBR:
216 __asm__ __volatile__ ("stc vbr, %0" : "=r" (mem));
217 break;
218 }
190 219
191 regs->pc = gdb_regs[GDB_PC]; 220 return dbg_reg_def[regno].name;
192 regs->pr = gdb_regs[GDB_PR];
193 regs->sr = gdb_regs[GDB_SR];
194 regs->gbr = gdb_regs[GDB_GBR];
195 regs->mach = gdb_regs[GDB_MACH];
196 regs->macl = gdb_regs[GDB_MACL];
197} 221}
198 222
199void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p) 223void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
200{ 224{
225 struct pt_regs *thread_regs = task_pt_regs(p);
226 int reg;
227
228 /* Initialize to zero */
229 for (reg = 0; reg < DBG_MAX_REG_NUM; reg++)
230 gdb_regs[reg] = 0;
231
232 /*
233 * Copy out GP regs 8 to 14.
234 *
235 * switch_to() relies on SR.RB toggling, so regs 0->7 are banked
236 * and need privileged instructions to get to. The r15 value we
237 * fetch from the thread info directly.
238 */
239 for (reg = GDB_R8; reg < GDB_R15; reg++)
240 gdb_regs[reg] = thread_regs->regs[reg];
241
201 gdb_regs[GDB_R15] = p->thread.sp; 242 gdb_regs[GDB_R15] = p->thread.sp;
202 gdb_regs[GDB_PC] = p->thread.pc; 243 gdb_regs[GDB_PC] = p->thread.pc;
244
245 /*
246 * Additional registers we have context for
247 */
248 gdb_regs[GDB_PR] = thread_regs->pr;
249 gdb_regs[GDB_GBR] = thread_regs->gbr;
203} 250}
204 251
205int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, 252int kgdb_arch_handle_exception(int e_vector, int signo, int err_code,
@@ -264,6 +311,18 @@ BUILD_TRAP_HANDLER(singlestep)
264 local_irq_restore(flags); 311 local_irq_restore(flags);
265} 312}
266 313
314static void kgdb_call_nmi_hook(void *ignored)
315{
316 kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
317}
318
319void kgdb_roundup_cpus(unsigned long flags)
320{
321 local_irq_enable();
322 smp_call_function(kgdb_call_nmi_hook, NULL, 0);
323 local_irq_disable();
324}
325
267static int __kgdb_notify(struct die_args *args, unsigned long cmd) 326static int __kgdb_notify(struct die_args *args, unsigned long cmd)
268{ 327{
269 int ret; 328 int ret;
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 3d722e49db08..ec05f491c347 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -121,7 +121,4 @@ void __init sh_mv_setup(void)
121 mv_set(irq_demux); 121 mv_set(irq_demux);
122 mv_set(mode_pins); 122 mv_set(mode_pins);
123 mv_set(mem_init); 123 mv_set(mem_init);
124
125 if (!sh_mv.mv_nr_irqs)
126 sh_mv.mv_nr_irqs = NR_IRQS;
127} 124}
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index f2621abdf01d..e77feaf117ab 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -2,10 +2,17 @@
2#include <linux/kernel.h> 2#include <linux/kernel.h>
3#include <linux/slab.h> 3#include <linux/slab.h>
4#include <linux/sched.h> 4#include <linux/sched.h>
5#include <linux/export.h>
6#include <linux/stackprotector.h>
5 7
6struct kmem_cache *task_xstate_cachep = NULL; 8struct kmem_cache *task_xstate_cachep = NULL;
7unsigned int xstate_size; 9unsigned int xstate_size;
8 10
11#ifdef CONFIG_CC_STACKPROTECTOR
12unsigned long __stack_chk_guard __read_mostly;
13EXPORT_SYMBOL(__stack_chk_guard);
14#endif
15
9int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) 16int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
10{ 17{
11 *dst = *src; 18 *dst = *src;
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 94273aaf78c1..f78cc421e665 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -22,6 +22,7 @@
22#include <linux/ftrace.h> 22#include <linux/ftrace.h>
23#include <linux/hw_breakpoint.h> 23#include <linux/hw_breakpoint.h>
24#include <linux/prefetch.h> 24#include <linux/prefetch.h>
25#include <linux/stackprotector.h>
25#include <asm/uaccess.h> 26#include <asm/uaccess.h>
26#include <asm/mmu_context.h> 27#include <asm/mmu_context.h>
27#include <asm/fpu.h> 28#include <asm/fpu.h>
@@ -220,6 +221,10 @@ __switch_to(struct task_struct *prev, struct task_struct *next)
220{ 221{
221 struct thread_struct *next_t = &next->thread; 222 struct thread_struct *next_t = &next->thread;
222 223
224#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
225 __stack_chk_guard = next->stack_canary;
226#endif
227
223 unlazy_fpu(prev, task_pt_regs(prev)); 228 unlazy_fpu(prev, task_pt_regs(prev));
224 229
225 /* we're going to use this soon, after a few expensive things */ 230 /* we're going to use this soon, after a few expensive things */
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index 6c0486094e48..8dae93ed8aff 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -283,8 +283,6 @@ static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_na
283 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk) 283 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
284{ 284{
285 show_excp_regs(fn_name, trapnr, signr, regs); 285 show_excp_regs(fn_name, trapnr, signr, regs);
286 tsk->thread.error_code = error_code;
287 tsk->thread.trap_no = trapnr;
288 286
289 if (user_mode(regs)) 287 if (user_mode(regs))
290 force_sig(signr, tsk); 288 force_sig(signr, tsk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-13 05:01:45 -0500