diff options
author | David S. Miller <davem@davemloft.net> | 2010-12-27 01:37:05 -0500 |
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committer | David S. Miller <davem@davemloft.net> | 2010-12-27 01:37:05 -0500 |
commit | 17f7f4d9fcce8f1b75b5f735569309dee7665968 (patch) | |
tree | 14d7e49ca0053a0fcab3c33b5023bf3f90c5c08a /arch/sh/kernel/cpu | |
parent | 041110a439e21cd40709ead4ffbfa8034619ad77 (diff) | |
parent | d7c1255a3a21e98bdc64df8ccf005a174d7e6289 (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
net/ipv4/fib_frontend.c
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r-- | arch/sh/kernel/cpu/sh4/clock-sh4-202.c | 2 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 44 |
2 files changed, 40 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c index 4eabc68cd753..b601fa3978d1 100644 --- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c | |||
@@ -110,7 +110,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) | |||
110 | return 0; | 110 | return 0; |
111 | } | 111 | } |
112 | 112 | ||
113 | static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) | 113 | static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) |
114 | { | 114 | { |
115 | unsigned long frqcr3; | 115 | unsigned long frqcr3; |
116 | unsigned int tmp; | 116 | unsigned int tmp; |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 0fe2e9329cb2..271c0b325a9a 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c | |||
@@ -111,12 +111,21 @@ static struct clk div3_clk = { | |||
111 | .parent = &pll_clk, | 111 | .parent = &pll_clk, |
112 | }; | 112 | }; |
113 | 113 | ||
114 | /* External input clock (pin name: FSIMCKA/FSIMCKB ) */ | ||
115 | struct clk sh7724_fsimcka_clk = { | ||
116 | }; | ||
117 | |||
118 | struct clk sh7724_fsimckb_clk = { | ||
119 | }; | ||
120 | |||
114 | static struct clk *main_clks[] = { | 121 | static struct clk *main_clks[] = { |
115 | &r_clk, | 122 | &r_clk, |
116 | &extal_clk, | 123 | &extal_clk, |
117 | &fll_clk, | 124 | &fll_clk, |
118 | &pll_clk, | 125 | &pll_clk, |
119 | &div3_clk, | 126 | &div3_clk, |
127 | &sh7724_fsimcka_clk, | ||
128 | &sh7724_fsimckb_clk, | ||
120 | }; | 129 | }; |
121 | 130 | ||
122 | static void div4_kick(struct clk *clk) | 131 | static void div4_kick(struct clk *clk) |
@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = { | |||
154 | [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), | 163 | [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), |
155 | }; | 164 | }; |
156 | 165 | ||
157 | enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; | 166 | enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR }; |
158 | 167 | ||
159 | static struct clk div6_clks[DIV6_NR] = { | 168 | static struct clk div6_clks[DIV6_NR] = { |
160 | [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), | 169 | [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), |
161 | [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), | ||
162 | [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), | ||
163 | [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), | 170 | [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0), |
164 | [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), | 171 | [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), |
165 | }; | 172 | }; |
166 | 173 | ||
174 | enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR }; | ||
175 | |||
176 | /* Indices are important - they are the actual src selecting values */ | ||
177 | static struct clk *fclkacr_parent[] = { | ||
178 | [0] = &div3_clk, | ||
179 | [1] = NULL, | ||
180 | [2] = &sh7724_fsimcka_clk, | ||
181 | [3] = NULL, | ||
182 | }; | ||
183 | |||
184 | static struct clk *fclkbcr_parent[] = { | ||
185 | [0] = &div3_clk, | ||
186 | [1] = NULL, | ||
187 | [2] = &sh7724_fsimckb_clk, | ||
188 | [3] = NULL, | ||
189 | }; | ||
190 | |||
191 | static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { | ||
192 | [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0, | ||
193 | fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), | ||
194 | [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0, | ||
195 | fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), | ||
196 | }; | ||
197 | |||
167 | static struct clk mstp_clks[HWBLK_NR] = { | 198 | static struct clk mstp_clks[HWBLK_NR] = { |
168 | SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), | 199 | SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), |
169 | SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), | 200 | SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT), |
@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = { | |||
240 | 271 | ||
241 | /* DIV6 clocks */ | 272 | /* DIV6 clocks */ |
242 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | 273 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), |
243 | CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), | 274 | CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]), |
244 | CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), | 275 | CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]), |
245 | CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), | 276 | CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), |
246 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), | 277 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), |
247 | 278 | ||
@@ -376,6 +407,9 @@ int __init arch_clk_init(void) | |||
376 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); | 407 | ret = sh_clk_div6_register(div6_clks, DIV6_NR); |
377 | 408 | ||
378 | if (!ret) | 409 | if (!ret) |
410 | ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR); | ||
411 | |||
412 | if (!ret) | ||
379 | ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); | 413 | ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR); |
380 | 414 | ||
381 | return ret; | 415 | return ret; |