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authorPaul Mundt <lethal@linux-sh.org>2009-05-11 16:59:27 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-05-11 16:59:27 -0400
commitf5c84cf50812c80133e64683d0500b2416d55cb3 (patch)
treeeb116c797a5b56d96deeca62f5122d0de197f601 /arch/sh/kernel/cpu/sh4
parentaa87aa343f2cd236b5eccd643abd4df918ed5c4f (diff)
sh: clkfwk: Tidy up on-chip clock registration and rate propagation.
This tidies up the set_rate hack that the on-chip clocks were abusing to trigger rate propagation, which is now handled generically. Additionally, now that CLK_ENABLE_ON_INIT is wired up where it needs to be for these clocks, the clk_enable() can go away. In some cases this was bumping up the refcount higher than it should have been. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4')
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c19
1 files changed, 4 insertions, 15 deletions
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 0caca9f99fe8..435f4f12ffb8 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -127,7 +127,7 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
127 frqcr3 |= tmp << 6; 127 frqcr3 |= tmp << 6;
128 ctrl_outl(frqcr3, CPG2_FRQCR3); 128 ctrl_outl(frqcr3, CPG2_FRQCR3);
129 129
130 return clk->parent->rate / frqcr3_divisors[tmp]; 130 clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
131 131
132 return 0; 132 return 0;
133} 133}
@@ -153,28 +153,17 @@ static struct clk *sh4202_onchip_clocks[] = {
153static int __init sh4202_clk_init(void) 153static int __init sh4202_clk_init(void)
154{ 154{
155 struct clk *clk = clk_get(NULL, "master_clk"); 155 struct clk *clk = clk_get(NULL, "master_clk");
156 int i; 156 int i, ret = 0;
157 157
158 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { 158 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
159 struct clk *clkp = sh4202_onchip_clocks[i]; 159 struct clk *clkp = sh4202_onchip_clocks[i];
160 160
161 clkp->parent = clk; 161 clkp->parent = clk;
162 clk_register(clkp); 162 ret |= clk_register(clkp);
163 clk_enable(clkp);
164 } 163 }
165 164
166 /*
167 * Now that we have the rest of the clocks registered, we need to
168 * force the parent clock to propagate so that these clocks will
169 * automatically figure out their rate. We cheat by handing the
170 * parent clock its current rate and forcing child propagation.
171 */
172 clk_set_rate(clk, clk_get_rate(clk));
173
174 clk_put(clk); 165 clk_put(clk);
175 166
176 return 0; 167 return ret;
177} 168}
178
179arch_initcall(sh4202_clk_init); 169arch_initcall(sh4202_clk_init);
180