diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-18 09:31:43 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-03-18 09:31:43 -0400 |
commit | 0a95d92c0054e74fb79607ac2df958b7bf295706 (patch) | |
tree | e2c5f836e799dcfd72904949be47595af91432e7 /arch/powerpc | |
parent | 08351fc6a75731226e1112fc7254542bd3a2912e (diff) | |
parent | 831532035b12a5f7b600515a6f4da0b207b82d6e (diff) |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (62 commits)
powerpc/85xx: Fix signedness bug in cache-sram
powerpc/fsl: 85xx: document cache sram bindings
powerpc/fsl: define binding for fsl mpic interrupt controllers
powerpc/fsl_msi: Handle msi-available-ranges better
drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak
powerpc/85xx: Fix SPE float to integer conversion failure
powerpc/85xx: Update sata controller compatible for p1022ds board
ATA: Add FSL sata v2 controller support
powerpc/mpc8xxx_gpio: simplify searching for 'fsl, qoriq-gpio' compatiable
powerpc/8xx: remove obsolete mgsuvd board
powerpc/82xx: rename and update mgcoge board support
powerpc/83xx: rename and update kmeter1
powerpc/85xx: Workaroudn e500 CPU erratum A005
powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x
powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e
powerpc/pseries: Disable MSI using new interface if possible
powerpc: Enable GENERIC_HARDIRQS_NO_DEPRECATED.
powerpc: core irq_data conversion.
powerpc: sysdev/xilinx_intc irq_data conversion.
powerpc: sysdev/uic irq_data conversion.
...
Fix up conflicts in arch/powerpc/sysdev/fsl_msi.c (due to getting rid of
of_platform_driver in arch/powerpc)
Diffstat (limited to 'arch/powerpc')
93 files changed, 2097 insertions, 1280 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 7d69e9bf5e64..71ba04721beb 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig | |||
@@ -134,6 +134,7 @@ config PPC | |||
134 | select HAVE_GENERIC_HARDIRQS | 134 | select HAVE_GENERIC_HARDIRQS |
135 | select HAVE_SPARSE_IRQ | 135 | select HAVE_SPARSE_IRQ |
136 | select IRQ_PER_CPU | 136 | select IRQ_PER_CPU |
137 | select GENERIC_HARDIRQS_NO_DEPRECATED | ||
137 | 138 | ||
138 | config EARLY_PRINTK | 139 | config EARLY_PRINTK |
139 | bool | 140 | bool |
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 5b27a4b74b79..2779f08313a5 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts | |||
@@ -172,6 +172,19 @@ | |||
172 | interrupts = <0x1e 4>; | 172 | interrupts = <0x1e 4>; |
173 | }; | 173 | }; |
174 | 174 | ||
175 | USBOTG0: usbotg@bff80000 { | ||
176 | compatible = "amcc,dwc-otg"; | ||
177 | reg = <0x4 0xbff80000 0x10000>; | ||
178 | interrupt-parent = <&USBOTG0>; | ||
179 | #interrupt-cells = <1>; | ||
180 | #address-cells = <0>; | ||
181 | #size-cells = <0>; | ||
182 | interrupts = <0x0 0x1 0x2>; | ||
183 | interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4 | ||
184 | /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8 | ||
185 | /* DMA */ 0x2 &UIC0 0xc 0x4>; | ||
186 | }; | ||
187 | |||
175 | SATA0: sata@bffd1000 { | 188 | SATA0: sata@bffd1000 { |
176 | compatible = "amcc,sata-460ex"; | 189 | compatible = "amcc,sata-460ex"; |
177 | reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; | 190 | reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>; |
@@ -233,6 +246,11 @@ | |||
233 | }; | 246 | }; |
234 | }; | 247 | }; |
235 | 248 | ||
249 | cpld@2,0 { | ||
250 | compatible = "amcc,ppc460ex-bcsr"; | ||
251 | reg = <2 0x0 0x9>; | ||
252 | }; | ||
253 | |||
236 | ndfc@3,0 { | 254 | ndfc@3,0 { |
237 | compatible = "ibm,ndfc"; | 255 | compatible = "ibm,ndfc"; |
238 | reg = <0x00000003 0x00000000 0x00002000>; | 256 | reg = <0x00000003 0x00000000 0x00002000>; |
@@ -307,6 +325,12 @@ | |||
307 | interrupts = <0x3 0x4>; | 325 | interrupts = <0x3 0x4>; |
308 | }; | 326 | }; |
309 | 327 | ||
328 | GPIO0: gpio@ef600b00 { | ||
329 | compatible = "ibm,ppc4xx-gpio"; | ||
330 | reg = <0xef600b00 0x00000048>; | ||
331 | gpio-controller; | ||
332 | }; | ||
333 | |||
310 | ZMII0: emac-zmii@ef600d00 { | 334 | ZMII0: emac-zmii@ef600d00 { |
311 | compatible = "ibm,zmii-460ex", "ibm,zmii"; | 335 | compatible = "ibm,zmii-460ex", "ibm,zmii"; |
312 | reg = <0xef600d00 0x0000000c>; | 336 | reg = <0xef600d00 0x0000000c>; |
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts index d8b5d12fb663..d16bae1230f7 100644 --- a/arch/powerpc/boot/dts/kmeter1.dts +++ b/arch/powerpc/boot/dts/kmeter1.dts | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Keymile KMETER1 Device Tree Source | 2 | * Keymile KMETER1 Device Tree Source |
3 | * | 3 | * |
4 | * 2008 DENX Software Engineering GmbH | 4 | * 2008-2011 DENX Software Engineering GmbH |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the | 7 | * under the terms of the GNU General Public License as published by the |
@@ -70,11 +70,11 @@ | |||
70 | #address-cells = <1>; | 70 | #address-cells = <1>; |
71 | #size-cells = <0>; | 71 | #size-cells = <0>; |
72 | cell-index = <0>; | 72 | cell-index = <0>; |
73 | compatible = "fsl-i2c"; | 73 | compatible = "fsl,mpc8313-i2c","fsl-i2c"; |
74 | reg = <0x3000 0x100>; | 74 | reg = <0x3000 0x100>; |
75 | interrupts = <14 0x8>; | 75 | interrupts = <14 0x8>; |
76 | interrupt-parent = <&ipic>; | 76 | interrupt-parent = <&ipic>; |
77 | dfsrr; | 77 | clock-frequency = <400000>; |
78 | }; | 78 | }; |
79 | 79 | ||
80 | serial0: serial@4500 { | 80 | serial0: serial@4500 { |
@@ -137,6 +137,13 @@ | |||
137 | compatible = "fsl,mpc8360-par_io"; | 137 | compatible = "fsl,mpc8360-par_io"; |
138 | num-ports = <7>; | 138 | num-ports = <7>; |
139 | 139 | ||
140 | qe_pio_c: gpio-controller@30 { | ||
141 | #gpio-cells = <2>; | ||
142 | compatible = "fsl,mpc8360-qe-pario-bank", | ||
143 | "fsl,mpc8323-qe-pario-bank"; | ||
144 | reg = <0x1430 0x18>; | ||
145 | gpio-controller; | ||
146 | }; | ||
140 | pio_ucc1: ucc_pin@0 { | 147 | pio_ucc1: ucc_pin@0 { |
141 | reg = <0>; | 148 | reg = <0>; |
142 | 149 | ||
@@ -472,7 +479,17 @@ | |||
472 | #address-cells = <0>; | 479 | #address-cells = <0>; |
473 | #interrupt-cells = <1>; | 480 | #interrupt-cells = <1>; |
474 | reg = <0x80 0x80>; | 481 | reg = <0x80 0x80>; |
475 | interrupts = <32 8 33 8>; | 482 | big-endian; |
483 | interrupts = < | ||
484 | 32 0x8 | ||
485 | 33 0x8 | ||
486 | 34 0x8 | ||
487 | 35 0x8 | ||
488 | 40 0x8 | ||
489 | 41 0x8 | ||
490 | 42 0x8 | ||
491 | 43 0x8 | ||
492 | >; | ||
476 | interrupt-parent = <&ipic>; | 493 | interrupt-parent = <&ipic>; |
477 | }; | 494 | }; |
478 | }; | 495 | }; |
@@ -484,43 +501,31 @@ | |||
484 | compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", | 501 | compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", |
485 | "simple-bus"; | 502 | "simple-bus"; |
486 | reg = <0xe0005000 0xd8>; | 503 | reg = <0xe0005000 0xd8>; |
487 | ranges = <0 0 0xf0000000 0x04000000>; /* Filled in by U-Boot */ | 504 | ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ |
505 | 1 0 0xe8000000 0x01000000 /* LB 1 */ | ||
506 | 3 0 0xa0000000 0x10000000>; /* LB 3 */ | ||
488 | 507 | ||
489 | flash@f0000000,0 { | 508 | flash@0,0 { |
490 | compatible = "cfi-flash"; | 509 | compatible = "cfi-flash"; |
491 | /* | 510 | reg = <0 0 0x04000000>; |
492 | * The Intel P30 chip has 2 non-identical chips on | ||
493 | * one die, so we need to define 2 separate regions | ||
494 | * that are scanned by physmap_of independantly. | ||
495 | */ | ||
496 | reg = <0 0x00000000 0x02000000 | ||
497 | 0 0x02000000 0x02000000>; /* Filled in by U-Boot */ | ||
498 | bank-width = <2>; | ||
499 | #address-cells = <1>; | 511 | #address-cells = <1>; |
500 | #size-cells = <1>; | 512 | #size-cells = <1>; |
501 | partition@0 { | 513 | bank-width = <2>; |
514 | partition@0 { /* 768KB */ | ||
502 | label = "u-boot"; | 515 | label = "u-boot"; |
503 | reg = <0 0x40000>; | 516 | reg = <0 0xC0000>; |
504 | }; | 517 | }; |
505 | partition@40000 { | 518 | partition@c0000 { /* 128KB */ |
506 | label = "env"; | 519 | label = "env"; |
507 | reg = <0x40000 0x40000>; | 520 | reg = <0xC0000 0x20000>; |
508 | }; | ||
509 | partition@80000 { | ||
510 | label = "dtb"; | ||
511 | reg = <0x80000 0x20000>; | ||
512 | }; | ||
513 | partition@a0000 { | ||
514 | label = "kernel"; | ||
515 | reg = <0xa0000 0x300000>; | ||
516 | }; | 521 | }; |
517 | partition@3a0000 { | 522 | partition@e0000 { /* 128KB */ |
518 | label = "ramdisk"; | 523 | label = "envred"; |
519 | reg = <0x3a0000 0x800000>; | 524 | reg = <0xE0000 0x20000>; |
520 | }; | 525 | }; |
521 | partition@ba0000 { | 526 | partition@100000 { /* 64512KB */ |
522 | label = "user"; | 527 | label = "ubi0"; |
523 | reg = <0xba0000 0x3460000>; | 528 | reg = <0x100000 0x3F00000>; |
524 | }; | 529 | }; |
525 | }; | 530 | }; |
526 | }; | 531 | }; |
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts index 0ce96644176d..1360d2f69024 100644 --- a/arch/powerpc/boot/dts/mgcoge.dts +++ b/arch/powerpc/boot/dts/mgcoge.dts | |||
@@ -13,7 +13,7 @@ | |||
13 | /dts-v1/; | 13 | /dts-v1/; |
14 | / { | 14 | / { |
15 | model = "MGCOGE"; | 15 | model = "MGCOGE"; |
16 | compatible = "keymile,mgcoge"; | 16 | compatible = "keymile,km82xx"; |
17 | #address-cells = <1>; | 17 | #address-cells = <1>; |
18 | #size-cells = <1>; | 18 | #size-cells = <1>; |
19 | 19 | ||
@@ -48,8 +48,10 @@ | |||
48 | reg = <0xf0010100 0x40>; | 48 | reg = <0xf0010100 0x40>; |
49 | 49 | ||
50 | ranges = <0 0 0xfe000000 0x00400000 | 50 | ranges = <0 0 0xfe000000 0x00400000 |
51 | 5 0 0x50000000 0x20000000 | 51 | 1 0 0x30000000 0x00010000 |
52 | >; /* Filled in by U-Boot */ | 52 | 2 0 0x40000000 0x00010000 |
53 | 5 0 0x50000000 0x04000000 | ||
54 | >; | ||
53 | 55 | ||
54 | flash@0,0 { | 56 | flash@0,0 { |
55 | compatible = "cfi-flash"; | 57 | compatible = "cfi-flash"; |
@@ -60,36 +62,32 @@ | |||
60 | device-width = <1>; | 62 | device-width = <1>; |
61 | partition@0 { | 63 | partition@0 { |
62 | label = "u-boot"; | 64 | label = "u-boot"; |
63 | reg = <0 0x40000>; | 65 | reg = <0x00000 0xC0000>; |
64 | }; | 66 | }; |
65 | partition@40000 { | 67 | partition@1 { |
66 | label = "env"; | 68 | label = "env"; |
67 | reg = <0x40000 0x20000>; | 69 | reg = <0xC0000 0x20000>; |
68 | }; | 70 | }; |
69 | partition@60000 { | 71 | partition@2 { |
70 | label = "kernel"; | 72 | label = "envred"; |
71 | reg = <0x60000 0x220000>; | 73 | reg = <0xE0000 0x20000>; |
72 | }; | 74 | }; |
73 | partition@280000 { | 75 | partition@3 { |
74 | label = "dtb"; | 76 | label = "free"; |
75 | reg = <0x280000 0x20000>; | 77 | reg = <0x100000 0x300000>; |
76 | }; | 78 | }; |
77 | }; | 79 | }; |
78 | 80 | ||
79 | flash@5,0 { | 81 | flash@5,0 { |
80 | compatible = "cfi-flash"; | 82 | compatible = "cfi-flash"; |
81 | reg = <5 0x0 0x2000000>; | 83 | reg = <5 0x00000000 0x02000000 |
84 | 5 0x02000000 0x02000000>; | ||
82 | #address-cells = <1>; | 85 | #address-cells = <1>; |
83 | #size-cells = <1>; | 86 | #size-cells = <1>; |
84 | bank-width = <2>; | 87 | bank-width = <2>; |
85 | device-width = <2>; | 88 | partition@app { /* 64 MBytes */ |
86 | partition@0 { | 89 | label = "ubi0"; |
87 | label = "ramdisk"; | 90 | reg = <0x00000000 0x04000000>; |
88 | reg = <0 0x7a0000>; | ||
89 | }; | ||
90 | partition@7a0000 { | ||
91 | label = "user"; | ||
92 | reg = <0x7a0000 0x1860000>; | ||
93 | }; | 91 | }; |
94 | }; | 92 | }; |
95 | }; | 93 | }; |
@@ -217,6 +215,13 @@ | |||
217 | }; | 215 | }; |
218 | }; | 216 | }; |
219 | 217 | ||
218 | cpm2_pio_c: gpio-controller@10d40 { | ||
219 | #gpio-cells = <2>; | ||
220 | compatible = "fsl,cpm2-pario-bank"; | ||
221 | reg = <0x10d40 0x14>; | ||
222 | gpio-controller; | ||
223 | }; | ||
224 | |||
220 | PIC: interrupt-controller@10c00 { | 225 | PIC: interrupt-controller@10c00 { |
221 | #interrupt-cells = <2>; | 226 | #interrupt-cells = <2>; |
222 | interrupt-controller; | 227 | interrupt-controller; |
diff --git a/arch/powerpc/boot/dts/mgsuvd.dts b/arch/powerpc/boot/dts/mgsuvd.dts deleted file mode 100644 index e4fc53ab42bd..000000000000 --- a/arch/powerpc/boot/dts/mgsuvd.dts +++ /dev/null | |||
@@ -1,163 +0,0 @@ | |||
1 | /* | ||
2 | * MGSUVD Device Tree Source | ||
3 | * | ||
4 | * Copyright 2008 DENX Software Engineering GmbH | ||
5 | * Heiko Schocher <hs@denx.de> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | */ | ||
12 | |||
13 | /dts-v1/; | ||
14 | / { | ||
15 | model = "MGSUVD"; | ||
16 | compatible = "keymile,mgsuvd"; | ||
17 | #address-cells = <1>; | ||
18 | #size-cells = <1>; | ||
19 | |||
20 | cpus { | ||
21 | #address-cells = <1>; | ||
22 | #size-cells = <0>; | ||
23 | |||
24 | PowerPC,852@0 { | ||
25 | device_type = "cpu"; | ||
26 | reg = <0>; | ||
27 | d-cache-line-size = <16>; | ||
28 | i-cache-line-size = <16>; | ||
29 | d-cache-size = <8192>; | ||
30 | i-cache-size = <8192>; | ||
31 | timebase-frequency = <0>; /* Filled in by u-boot */ | ||
32 | bus-frequency = <0>; /* Filled in by u-boot */ | ||
33 | clock-frequency = <0>; /* Filled in by u-boot */ | ||
34 | interrupts = <15 2>; /* decrementer interrupt */ | ||
35 | interrupt-parent = <&PIC>; | ||
36 | }; | ||
37 | }; | ||
38 | |||
39 | memory { | ||
40 | device_type = "memory"; | ||
41 | reg = <00000000 0x4000000>; /* Filled in by u-boot */ | ||
42 | }; | ||
43 | |||
44 | localbus@fff00100 { | ||
45 | compatible = "fsl,mpc852-localbus", "fsl,pq1-localbus", "simple-bus"; | ||
46 | #address-cells = <2>; | ||
47 | #size-cells = <1>; | ||
48 | reg = <0xfff00100 0x40>; | ||
49 | |||
50 | ranges = <0 0 0xf0000000 0x01000000>; /* Filled in by u-boot */ | ||
51 | |||
52 | flash@0,0 { | ||
53 | compatible = "cfi-flash"; | ||
54 | reg = <0 0 0x1000000>; | ||
55 | #address-cells = <1>; | ||
56 | #size-cells = <1>; | ||
57 | bank-width = <1>; | ||
58 | device-width = <1>; | ||
59 | partition@0 { | ||
60 | label = "u-boot"; | ||
61 | reg = <0 0x80000>; | ||
62 | }; | ||
63 | partition@80000 { | ||
64 | label = "env"; | ||
65 | reg = <0x80000 0x20000>; | ||
66 | }; | ||
67 | partition@a0000 { | ||
68 | label = "kernel"; | ||
69 | reg = <0xa0000 0x1e0000>; | ||
70 | }; | ||
71 | partition@280000 { | ||
72 | label = "dtb"; | ||
73 | reg = <0x280000 0x20000>; | ||
74 | }; | ||
75 | partition@2a0000 { | ||
76 | label = "root"; | ||
77 | reg = <0x2a0000 0x500000>; | ||
78 | }; | ||
79 | partition@7a0000 { | ||
80 | label = "user"; | ||
81 | reg = <0x7a0000 0x860000>; | ||
82 | }; | ||
83 | }; | ||
84 | }; | ||
85 | |||
86 | soc@fff00000 { | ||
87 | compatible = "fsl,mpc852", "fsl,pq1-soc", "simple-bus"; | ||
88 | #address-cells = <1>; | ||
89 | #size-cells = <1>; | ||
90 | device_type = "soc"; | ||
91 | ranges = <0 0xfff00000 0x00004000>; | ||
92 | |||
93 | PIC: interrupt-controller@0 { | ||
94 | interrupt-controller; | ||
95 | #interrupt-cells = <2>; | ||
96 | reg = <0 24>; | ||
97 | compatible = "fsl,mpc852-pic", "fsl,pq1-pic"; | ||
98 | }; | ||
99 | |||
100 | cpm@9c0 { | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <1>; | ||
103 | compatible = "fsl,mpc852-cpm", "fsl,cpm1", "simple-bus"; | ||
104 | interrupts = <0>; /* cpm error interrupt */ | ||
105 | interrupt-parent = <&CPM_PIC>; | ||
106 | reg = <0x9c0 10>; | ||
107 | ranges; | ||
108 | |||
109 | muram@2000 { | ||
110 | compatible = "fsl,cpm-muram"; | ||
111 | #address-cells = <1>; | ||
112 | #size-cells = <1>; | ||
113 | ranges = <0 0x2000 0x2000>; | ||
114 | |||
115 | data@0 { | ||
116 | compatible = "fsl,cpm-muram-data"; | ||
117 | reg = <0x800 0x1800>; | ||
118 | }; | ||
119 | }; | ||
120 | |||
121 | brg@9f0 { | ||
122 | compatible = "fsl,mpc852-brg", | ||
123 | "fsl,cpm1-brg", | ||
124 | "fsl,cpm-brg"; | ||
125 | reg = <0x9f0 0x10>; | ||
126 | clock-frequency = <0>; /* Filled in by u-boot */ | ||
127 | }; | ||
128 | |||
129 | CPM_PIC: interrupt-controller@930 { | ||
130 | interrupt-controller; | ||
131 | #interrupt-cells = <1>; | ||
132 | interrupts = <5 2 0 2>; | ||
133 | interrupt-parent = <&PIC>; | ||
134 | reg = <0x930 0x20>; | ||
135 | compatible = "fsl,cpm1-pic"; | ||
136 | }; | ||
137 | |||
138 | /* MON-1 */ | ||
139 | serial@a80 { | ||
140 | device_type = "serial"; | ||
141 | compatible = "fsl,cpm1-smc-uart"; | ||
142 | reg = <0xa80 0x10 0x3fc0 0x40>; | ||
143 | interrupts = <4>; | ||
144 | interrupt-parent = <&CPM_PIC>; | ||
145 | fsl,cpm-brg = <1>; | ||
146 | fsl,cpm-command = <0x0090>; | ||
147 | current-speed = <0>; /* Filled in by u-boot */ | ||
148 | }; | ||
149 | |||
150 | ethernet@a40 { | ||
151 | device_type = "network"; | ||
152 | compatible = "fsl,mpc866-scc-enet", | ||
153 | "fsl,cpm1-scc-enet"; | ||
154 | reg = <0xa40 0x18 0x3e00 0x100>; | ||
155 | local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by u-boot */ | ||
156 | interrupts = <28>; | ||
157 | interrupt-parent = <&CPM_PIC>; | ||
158 | fsl,cpm-command = <0x80>; | ||
159 | fixed-link = <0 0 10 0 0>; | ||
160 | }; | ||
161 | }; | ||
162 | }; | ||
163 | }; | ||
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts index 69422eb24d97..59ef405c1c91 100644 --- a/arch/powerpc/boot/dts/p1022ds.dts +++ b/arch/powerpc/boot/dts/p1022ds.dts | |||
@@ -475,14 +475,14 @@ | |||
475 | }; | 475 | }; |
476 | 476 | ||
477 | sata@18000 { | 477 | sata@18000 { |
478 | compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; | 478 | compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; |
479 | reg = <0x18000 0x1000>; | 479 | reg = <0x18000 0x1000>; |
480 | cell-index = <1>; | 480 | cell-index = <1>; |
481 | interrupts = <74 0x2>; | 481 | interrupts = <74 0x2>; |
482 | }; | 482 | }; |
483 | 483 | ||
484 | sata@19000 { | 484 | sata@19000 { |
485 | compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; | 485 | compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; |
486 | reg = <0x19000 0x1000>; | 486 | reg = <0x19000 0x1000>; |
487 | cell-index = <2>; | 487 | cell-index = <2>; |
488 | interrupts = <41 0x2>; | 488 | interrupts = <41 0x2>; |
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig index 7a7b731c5735..07e1bbadebfe 100644 --- a/arch/powerpc/configs/83xx/kmeter1_defconfig +++ b/arch/powerpc/configs/83xx/kmeter1_defconfig | |||
@@ -2,6 +2,7 @@ CONFIG_EXPERIMENTAL=y | |||
2 | # CONFIG_SWAP is not set | 2 | # CONFIG_SWAP is not set |
3 | CONFIG_SYSVIPC=y | 3 | CONFIG_SYSVIPC=y |
4 | CONFIG_POSIX_MQUEUE=y | 4 | CONFIG_POSIX_MQUEUE=y |
5 | CONFIG_SPARSE_IRQ=y | ||
5 | CONFIG_LOG_BUF_SHIFT=14 | 6 | CONFIG_LOG_BUF_SHIFT=14 |
6 | CONFIG_EXPERT=y | 7 | CONFIG_EXPERT=y |
7 | # CONFIG_HOTPLUG is not set | 8 | # CONFIG_HOTPLUG is not set |
@@ -18,7 +19,6 @@ CONFIG_KMETER1=y | |||
18 | CONFIG_NO_HZ=y | 19 | CONFIG_NO_HZ=y |
19 | CONFIG_HIGH_RES_TIMERS=y | 20 | CONFIG_HIGH_RES_TIMERS=y |
20 | CONFIG_PREEMPT=y | 21 | CONFIG_PREEMPT=y |
21 | CONFIG_SPARSE_IRQ=y | ||
22 | # CONFIG_SECCOMP is not set | 22 | # CONFIG_SECCOMP is not set |
23 | CONFIG_NET=y | 23 | CONFIG_NET=y |
24 | CONFIG_PACKET=y | 24 | CONFIG_PACKET=y |
@@ -37,7 +37,6 @@ CONFIG_MTD=y | |||
37 | CONFIG_MTD_CONCAT=y | 37 | CONFIG_MTD_CONCAT=y |
38 | CONFIG_MTD_PARTITIONS=y | 38 | CONFIG_MTD_PARTITIONS=y |
39 | CONFIG_MTD_CMDLINE_PARTS=y | 39 | CONFIG_MTD_CMDLINE_PARTS=y |
40 | CONFIG_MTD_OF_PARTS=y | ||
41 | CONFIG_MTD_CHAR=y | 40 | CONFIG_MTD_CHAR=y |
42 | CONFIG_MTD_BLOCK=y | 41 | CONFIG_MTD_BLOCK=y |
43 | CONFIG_MTD_CFI=y | 42 | CONFIG_MTD_CFI=y |
@@ -49,13 +48,12 @@ CONFIG_MTD_UBI=y | |||
49 | CONFIG_MTD_UBI_GLUEBI=y | 48 | CONFIG_MTD_UBI_GLUEBI=y |
50 | CONFIG_MTD_UBI_DEBUG=y | 49 | CONFIG_MTD_UBI_DEBUG=y |
51 | CONFIG_PROC_DEVICETREE=y | 50 | CONFIG_PROC_DEVICETREE=y |
52 | # CONFIG_MISC_DEVICES is not set | ||
53 | CONFIG_NETDEVICES=y | 51 | CONFIG_NETDEVICES=y |
54 | CONFIG_DUMMY=y | 52 | CONFIG_DUMMY=y |
55 | CONFIG_TUN=y | 53 | CONFIG_TUN=y |
54 | CONFIG_MII=y | ||
56 | CONFIG_MARVELL_PHY=y | 55 | CONFIG_MARVELL_PHY=y |
57 | CONFIG_NET_ETHERNET=y | 56 | CONFIG_NET_ETHERNET=y |
58 | CONFIG_MII=y | ||
59 | CONFIG_UCC_GETH=y | 57 | CONFIG_UCC_GETH=y |
60 | # CONFIG_NETDEV_10000 is not set | 58 | # CONFIG_NETDEV_10000 is not set |
61 | CONFIG_WAN=y | 59 | CONFIG_WAN=y |
@@ -77,7 +75,6 @@ CONFIG_I2C_MPC=y | |||
77 | # CONFIG_USB_SUPPORT is not set | 75 | # CONFIG_USB_SUPPORT is not set |
78 | CONFIG_UIO=y | 76 | CONFIG_UIO=y |
79 | # CONFIG_DNOTIFY is not set | 77 | # CONFIG_DNOTIFY is not set |
80 | CONFIG_INOTIFY=y | ||
81 | CONFIG_TMPFS=y | 78 | CONFIG_TMPFS=y |
82 | CONFIG_JFFS2_FS=y | 79 | CONFIG_JFFS2_FS=y |
83 | CONFIG_NFS_FS=y | 80 | CONFIG_NFS_FS=y |
diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig index 39518e91822f..6cb588a7d425 100644 --- a/arch/powerpc/configs/mgcoge_defconfig +++ b/arch/powerpc/configs/mgcoge_defconfig | |||
@@ -1,4 +1,5 @@ | |||
1 | CONFIG_SYSVIPC=y | 1 | CONFIG_SYSVIPC=y |
2 | CONFIG_SPARSE_IRQ=y | ||
2 | CONFIG_IKCONFIG=y | 3 | CONFIG_IKCONFIG=y |
3 | CONFIG_IKCONFIG_PROC=y | 4 | CONFIG_IKCONFIG_PROC=y |
4 | CONFIG_LOG_BUF_SHIFT=14 | 5 | CONFIG_LOG_BUF_SHIFT=14 |
@@ -10,7 +11,6 @@ CONFIG_SLAB=y | |||
10 | CONFIG_PPC_82xx=y | 11 | CONFIG_PPC_82xx=y |
11 | CONFIG_MGCOGE=y | 12 | CONFIG_MGCOGE=y |
12 | CONFIG_BINFMT_MISC=y | 13 | CONFIG_BINFMT_MISC=y |
13 | CONFIG_SPARSE_IRQ=y | ||
14 | # CONFIG_SECCOMP is not set | 14 | # CONFIG_SECCOMP is not set |
15 | CONFIG_NET=y | 15 | CONFIG_NET=y |
16 | CONFIG_PACKET=y | 16 | CONFIG_PACKET=y |
@@ -30,7 +30,6 @@ CONFIG_MTD=y | |||
30 | CONFIG_MTD_CONCAT=y | 30 | CONFIG_MTD_CONCAT=y |
31 | CONFIG_MTD_PARTITIONS=y | 31 | CONFIG_MTD_PARTITIONS=y |
32 | CONFIG_MTD_CMDLINE_PARTS=y | 32 | CONFIG_MTD_CMDLINE_PARTS=y |
33 | CONFIG_MTD_OF_PARTS=y | ||
34 | CONFIG_MTD_CHAR=y | 33 | CONFIG_MTD_CHAR=y |
35 | CONFIG_MTD_BLKDEVS=y | 34 | CONFIG_MTD_BLKDEVS=y |
36 | CONFIG_MTD_CFI=y | 35 | CONFIG_MTD_CFI=y |
@@ -43,7 +42,6 @@ CONFIG_MTD_PHYSMAP_OF=y | |||
43 | CONFIG_PROC_DEVICETREE=y | 42 | CONFIG_PROC_DEVICETREE=y |
44 | CONFIG_BLK_DEV_LOOP=y | 43 | CONFIG_BLK_DEV_LOOP=y |
45 | CONFIG_BLK_DEV_RAM=y | 44 | CONFIG_BLK_DEV_RAM=y |
46 | # CONFIG_MISC_DEVICES is not set | ||
47 | # CONFIG_MACINTOSH_DRIVERS is not set | 45 | # CONFIG_MACINTOSH_DRIVERS is not set |
48 | CONFIG_NETDEVICES=y | 46 | CONFIG_NETDEVICES=y |
49 | CONFIG_FIXED_PHY=y | 47 | CONFIG_FIXED_PHY=y |
@@ -67,7 +65,6 @@ CONFIG_EXT2_FS=y | |||
67 | CONFIG_EXT3_FS=y | 65 | CONFIG_EXT3_FS=y |
68 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | 66 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set |
69 | # CONFIG_EXT3_FS_XATTR is not set | 67 | # CONFIG_EXT3_FS_XATTR is not set |
70 | CONFIG_INOTIFY=y | ||
71 | CONFIG_AUTOFS4_FS=y | 68 | CONFIG_AUTOFS4_FS=y |
72 | CONFIG_PROC_KCORE=y | 69 | CONFIG_PROC_KCORE=y |
73 | CONFIG_TMPFS=y | 70 | CONFIG_TMPFS=y |
@@ -88,13 +85,9 @@ CONFIG_DEBUG_FS=y | |||
88 | CONFIG_DEBUG_KERNEL=y | 85 | CONFIG_DEBUG_KERNEL=y |
89 | # CONFIG_SCHED_DEBUG is not set | 86 | # CONFIG_SCHED_DEBUG is not set |
90 | CONFIG_DEBUG_INFO=y | 87 | CONFIG_DEBUG_INFO=y |
91 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
92 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 88 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
93 | CONFIG_BDI_SWITCH=y | 89 | CONFIG_BDI_SWITCH=y |
94 | CONFIG_CRYPTO_CBC=y | ||
95 | CONFIG_CRYPTO_ECB=y | 90 | CONFIG_CRYPTO_ECB=y |
96 | CONFIG_CRYPTO_PCBC=y | 91 | CONFIG_CRYPTO_PCBC=y |
97 | CONFIG_CRYPTO_MD5=y | ||
98 | CONFIG_CRYPTO_DES=y | ||
99 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | 92 | # CONFIG_CRYPTO_ANSI_CPRNG is not set |
100 | # CONFIG_CRYPTO_HW is not set | 93 | # CONFIG_CRYPTO_HW is not set |
diff --git a/arch/powerpc/configs/mgsuvd_defconfig b/arch/powerpc/configs/mgsuvd_defconfig deleted file mode 100644 index 2a490626015c..000000000000 --- a/arch/powerpc/configs/mgsuvd_defconfig +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | CONFIG_PPC_8xx=y | ||
2 | CONFIG_EXPERIMENTAL=y | ||
3 | # CONFIG_SWAP is not set | ||
4 | CONFIG_SYSVIPC=y | ||
5 | CONFIG_BLK_DEV_INITRD=y | ||
6 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | ||
7 | CONFIG_EXPERT=y | ||
8 | # CONFIG_SYSCTL_SYSCALL is not set | ||
9 | # CONFIG_HOTPLUG is not set | ||
10 | # CONFIG_BUG is not set | ||
11 | # CONFIG_BASE_FULL is not set | ||
12 | # CONFIG_EPOLL is not set | ||
13 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
14 | CONFIG_SLAB=y | ||
15 | # CONFIG_BLK_DEV_BSG is not set | ||
16 | CONFIG_PPC_MGSUVD=y | ||
17 | CONFIG_8xx_COPYBACK=y | ||
18 | CONFIG_8xx_CPU6=y | ||
19 | CONFIG_I2C_SPI_SMC1_UCODE_PATCH=y | ||
20 | CONFIG_HZ_1000=y | ||
21 | CONFIG_MATH_EMULATION=y | ||
22 | CONFIG_SPARSE_IRQ=y | ||
23 | # CONFIG_SECCOMP is not set | ||
24 | CONFIG_NET=y | ||
25 | CONFIG_PACKET=y | ||
26 | CONFIG_UNIX=y | ||
27 | CONFIG_INET=y | ||
28 | CONFIG_IP_MULTICAST=y | ||
29 | CONFIG_IP_PNP=y | ||
30 | CONFIG_SYN_COOKIES=y | ||
31 | # CONFIG_INET_LRO is not set | ||
32 | # CONFIG_IPV6 is not set | ||
33 | CONFIG_MTD=y | ||
34 | CONFIG_MTD_PARTITIONS=y | ||
35 | CONFIG_MTD_CMDLINE_PARTS=y | ||
36 | CONFIG_MTD_OF_PARTS=y | ||
37 | CONFIG_MTD_CHAR=y | ||
38 | CONFIG_MTD_BLOCK=y | ||
39 | CONFIG_MTD_CFI=y | ||
40 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
41 | CONFIG_MTD_CFI_GEOMETRY=y | ||
42 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | ||
43 | CONFIG_MTD_CFI_INTELEXT=y | ||
44 | CONFIG_MTD_CFI_AMDSTD=y | ||
45 | CONFIG_MTD_CFI_STAA=y | ||
46 | CONFIG_MTD_PHYSMAP_OF=y | ||
47 | CONFIG_BLK_DEV_LOOP=y | ||
48 | CONFIG_BLK_DEV_RAM=y | ||
49 | # CONFIG_MISC_DEVICES is not set | ||
50 | CONFIG_NETDEVICES=y | ||
51 | CONFIG_FIXED_PHY=y | ||
52 | CONFIG_NET_ETHERNET=y | ||
53 | CONFIG_FS_ENET=y | ||
54 | # CONFIG_FS_ENET_HAS_FEC is not set | ||
55 | # CONFIG_NETDEV_1000 is not set | ||
56 | # CONFIG_NETDEV_10000 is not set | ||
57 | # CONFIG_INPUT is not set | ||
58 | # CONFIG_SERIO is not set | ||
59 | # CONFIG_VT is not set | ||
60 | CONFIG_SERIAL_CPM=y | ||
61 | CONFIG_SERIAL_CPM_CONSOLE=y | ||
62 | # CONFIG_LEGACY_PTYS is not set | ||
63 | CONFIG_GEN_RTC=y | ||
64 | # CONFIG_HWMON is not set | ||
65 | # CONFIG_USB_SUPPORT is not set | ||
66 | CONFIG_EXT2_FS=y | ||
67 | CONFIG_EXT2_FS_XATTR=y | ||
68 | CONFIG_EXT3_FS=y | ||
69 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
70 | CONFIG_INOTIFY=y | ||
71 | CONFIG_TMPFS=y | ||
72 | CONFIG_JFFS2_FS=y | ||
73 | CONFIG_CRAMFS=y | ||
74 | CONFIG_NFS_FS=y | ||
75 | CONFIG_NFS_V3=y | ||
76 | CONFIG_ROOT_NFS=y | ||
77 | CONFIG_PARTITION_ADVANCED=y | ||
78 | CONFIG_CRC_CCITT=y | ||
79 | CONFIG_DEBUG_FS=y | ||
80 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
81 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index f0a211d96923..be3cdf9134ce 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h | |||
@@ -154,6 +154,7 @@ extern const char *powerpc_base_platform; | |||
154 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) | 154 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) |
155 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) | 155 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) |
156 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) | 156 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) |
157 | #define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000) | ||
157 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | 158 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) |
158 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 159 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
159 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 160 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
@@ -465,7 +466,7 @@ enum { | |||
465 | CPU_FTRS_44X | CPU_FTRS_440x6 | | 466 | CPU_FTRS_44X | CPU_FTRS_440x6 | |
466 | #endif | 467 | #endif |
467 | #ifdef CONFIG_PPC_47x | 468 | #ifdef CONFIG_PPC_47x |
468 | CPU_FTRS_47X | | 469 | CPU_FTRS_47X | CPU_FTR_476_DD2 | |
469 | #endif | 470 | #endif |
470 | #ifdef CONFIG_E200 | 471 | #ifdef CONFIG_E200 |
471 | CPU_FTRS_E200 | | 472 | CPU_FTRS_E200 | |
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index ff08b70b36d4..bb712c9488b3 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h | |||
@@ -141,6 +141,8 @@ static inline bool arch_irqs_disabled(void) | |||
141 | 141 | ||
142 | #endif /* CONFIG_PPC64 */ | 142 | #endif /* CONFIG_PPC64 */ |
143 | 143 | ||
144 | #define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST | ||
145 | |||
144 | /* | 146 | /* |
145 | * interrupt-retrigger: should we handle this via lost interrupts and IPIs | 147 | * interrupt-retrigger: should we handle this via lost interrupts and IPIs |
146 | * or should we not care like we do now ? --BenH. | 148 | * or should we not care like we do now ? --BenH. |
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index e000cce8f6dd..946ec4947da2 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h | |||
@@ -467,11 +467,11 @@ extern void mpic_request_ipis(void); | |||
467 | void smp_mpic_message_pass(int target, int msg); | 467 | void smp_mpic_message_pass(int target, int msg); |
468 | 468 | ||
469 | /* Unmask a specific virq */ | 469 | /* Unmask a specific virq */ |
470 | extern void mpic_unmask_irq(unsigned int irq); | 470 | extern void mpic_unmask_irq(struct irq_data *d); |
471 | /* Mask a specific virq */ | 471 | /* Mask a specific virq */ |
472 | extern void mpic_mask_irq(unsigned int irq); | 472 | extern void mpic_mask_irq(struct irq_data *d); |
473 | /* EOI a specific virq */ | 473 | /* EOI a specific virq */ |
474 | extern void mpic_end_irq(unsigned int irq); | 474 | extern void mpic_end_irq(struct irq_data *d); |
475 | 475 | ||
476 | /* Fetch interrupt from a given mpic */ | 476 | /* Fetch interrupt from a given mpic */ |
477 | extern unsigned int mpic_get_one_irq(struct mpic *mpic); | 477 | extern unsigned int mpic_get_one_irq(struct mpic *mpic); |
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h index 92efe67d1c57..9d1aafe607c7 100644 --- a/arch/powerpc/include/asm/nvram.h +++ b/arch/powerpc/include/asm/nvram.h | |||
@@ -51,7 +51,8 @@ static inline int mmio_nvram_init(void) | |||
51 | extern int __init nvram_scan_partitions(void); | 51 | extern int __init nvram_scan_partitions(void); |
52 | extern loff_t nvram_create_partition(const char *name, int sig, | 52 | extern loff_t nvram_create_partition(const char *name, int sig, |
53 | int req_size, int min_size); | 53 | int req_size, int min_size); |
54 | extern int nvram_remove_partition(const char *name, int sig); | 54 | extern int nvram_remove_partition(const char *name, int sig, |
55 | const char *exceptions[]); | ||
55 | extern int nvram_get_partition_size(loff_t data_index); | 56 | extern int nvram_get_partition_size(loff_t data_index); |
56 | extern loff_t nvram_find_partition(const char *name, int sig, int *out_size); | 57 | extern loff_t nvram_find_partition(const char *name, int sig, int *out_size); |
57 | 58 | ||
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h index 89f158731ce3..88b0bd925a8b 100644 --- a/arch/powerpc/include/asm/pgtable.h +++ b/arch/powerpc/include/asm/pgtable.h | |||
@@ -170,6 +170,7 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre | |||
170 | #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ | 170 | #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ |
171 | _PAGE_COHERENT | _PAGE_WRITETHRU)) | 171 | _PAGE_COHERENT | _PAGE_WRITETHRU)) |
172 | 172 | ||
173 | #define pgprot_writecombine pgprot_noncached_wc | ||
173 | 174 | ||
174 | struct file; | 175 | struct file; |
175 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | 176 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h index cf519663a791..9e2cb2019161 100644 --- a/arch/powerpc/include/asm/qe_ic.h +++ b/arch/powerpc/include/asm/qe_ic.h | |||
@@ -81,7 +81,7 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); | |||
81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, | 81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, |
82 | struct irq_desc *desc) | 82 | struct irq_desc *desc) |
83 | { | 83 | { |
84 | struct qe_ic *qe_ic = desc->handler_data; | 84 | struct qe_ic *qe_ic = get_irq_desc_data(desc); |
85 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | 85 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); |
86 | 86 | ||
87 | if (cascade_irq != NO_IRQ) | 87 | if (cascade_irq != NO_IRQ) |
@@ -91,7 +91,7 @@ static inline void qe_ic_cascade_low_ipic(unsigned int irq, | |||
91 | static inline void qe_ic_cascade_high_ipic(unsigned int irq, | 91 | static inline void qe_ic_cascade_high_ipic(unsigned int irq, |
92 | struct irq_desc *desc) | 92 | struct irq_desc *desc) |
93 | { | 93 | { |
94 | struct qe_ic *qe_ic = desc->handler_data; | 94 | struct qe_ic *qe_ic = get_irq_desc_data(desc); |
95 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | 95 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); |
96 | 96 | ||
97 | if (cascade_irq != NO_IRQ) | 97 | if (cascade_irq != NO_IRQ) |
@@ -101,32 +101,35 @@ static inline void qe_ic_cascade_high_ipic(unsigned int irq, | |||
101 | static inline void qe_ic_cascade_low_mpic(unsigned int irq, | 101 | static inline void qe_ic_cascade_low_mpic(unsigned int irq, |
102 | struct irq_desc *desc) | 102 | struct irq_desc *desc) |
103 | { | 103 | { |
104 | struct qe_ic *qe_ic = desc->handler_data; | 104 | struct qe_ic *qe_ic = get_irq_desc_data(desc); |
105 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); | 105 | unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic); |
106 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
106 | 107 | ||
107 | if (cascade_irq != NO_IRQ) | 108 | if (cascade_irq != NO_IRQ) |
108 | generic_handle_irq(cascade_irq); | 109 | generic_handle_irq(cascade_irq); |
109 | 110 | ||
110 | desc->chip->eoi(irq); | 111 | chip->irq_eoi(&desc->irq_data); |
111 | } | 112 | } |
112 | 113 | ||
113 | static inline void qe_ic_cascade_high_mpic(unsigned int irq, | 114 | static inline void qe_ic_cascade_high_mpic(unsigned int irq, |
114 | struct irq_desc *desc) | 115 | struct irq_desc *desc) |
115 | { | 116 | { |
116 | struct qe_ic *qe_ic = desc->handler_data; | 117 | struct qe_ic *qe_ic = get_irq_desc_data(desc); |
117 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); | 118 | unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic); |
119 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
118 | 120 | ||
119 | if (cascade_irq != NO_IRQ) | 121 | if (cascade_irq != NO_IRQ) |
120 | generic_handle_irq(cascade_irq); | 122 | generic_handle_irq(cascade_irq); |
121 | 123 | ||
122 | desc->chip->eoi(irq); | 124 | chip->irq_eoi(&desc->irq_data); |
123 | } | 125 | } |
124 | 126 | ||
125 | static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, | 127 | static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, |
126 | struct irq_desc *desc) | 128 | struct irq_desc *desc) |
127 | { | 129 | { |
128 | struct qe_ic *qe_ic = desc->handler_data; | 130 | struct qe_ic *qe_ic = get_irq_desc_data(desc); |
129 | unsigned int cascade_irq; | 131 | unsigned int cascade_irq; |
132 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
130 | 133 | ||
131 | cascade_irq = qe_ic_get_high_irq(qe_ic); | 134 | cascade_irq = qe_ic_get_high_irq(qe_ic); |
132 | if (cascade_irq == NO_IRQ) | 135 | if (cascade_irq == NO_IRQ) |
@@ -135,7 +138,7 @@ static inline void qe_ic_cascade_muxed_mpic(unsigned int irq, | |||
135 | if (cascade_irq != NO_IRQ) | 138 | if (cascade_irq != NO_IRQ) |
136 | generic_handle_irq(cascade_irq); | 139 | generic_handle_irq(cascade_irq); |
137 | 140 | ||
138 | desc->chip->eoi(irq); | 141 | chip->irq_eoi(&desc->irq_data); |
139 | } | 142 | } |
140 | 143 | ||
141 | #endif /* _ASM_POWERPC_QE_IC_H */ | 144 | #endif /* _ASM_POWERPC_QE_IC_H */ |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 125fc1ad665d..1bc6a12f3725 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -170,6 +170,16 @@ | |||
170 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ | 170 | #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ |
171 | 171 | ||
172 | /* Special Purpose Registers (SPRNs)*/ | 172 | /* Special Purpose Registers (SPRNs)*/ |
173 | |||
174 | #ifdef CONFIG_40x | ||
175 | #define SPRN_PID 0x3B1 /* Process ID */ | ||
176 | #else | ||
177 | #define SPRN_PID 0x030 /* Process ID */ | ||
178 | #ifdef CONFIG_BOOKE | ||
179 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | ||
180 | #endif | ||
181 | #endif | ||
182 | |||
173 | #define SPRN_CTR 0x009 /* Count Register */ | 183 | #define SPRN_CTR 0x009 /* Count Register */ |
174 | #define SPRN_DSCR 0x11 | 184 | #define SPRN_DSCR 0x11 |
175 | #define SPRN_CTRLF 0x088 | 185 | #define SPRN_CTRLF 0x088 |
@@ -852,6 +862,8 @@ | |||
852 | #define PVR_7450 0x80000000 | 862 | #define PVR_7450 0x80000000 |
853 | #define PVR_8540 0x80200000 | 863 | #define PVR_8540 0x80200000 |
854 | #define PVR_8560 0x80200000 | 864 | #define PVR_8560 0x80200000 |
865 | #define PVR_VER_E500V1 0x8020 | ||
866 | #define PVR_VER_E500V2 0x8021 | ||
855 | /* | 867 | /* |
856 | * For the 8xx processors, all of them report the same PVR family for | 868 | * For the 8xx processors, all of them report the same PVR family for |
857 | * the PowerPC core. The various versions of these processors must be | 869 | * the PowerPC core. The various versions of these processors must be |
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index e68c69bf741a..86ad8128963a 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
@@ -150,8 +150,6 @@ | |||
150 | * or IBM 40x. | 150 | * or IBM 40x. |
151 | */ | 151 | */ |
152 | #ifdef CONFIG_BOOKE | 152 | #ifdef CONFIG_BOOKE |
153 | #define SPRN_PID 0x030 /* Process ID */ | ||
154 | #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ | ||
155 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ | 153 | #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ |
156 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ | 154 | #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ |
157 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ | 155 | #define SPRN_DEAR 0x03D /* Data Error Address Register */ |
@@ -168,7 +166,6 @@ | |||
168 | #define SPRN_TCR 0x154 /* Timer Control Register */ | 166 | #define SPRN_TCR 0x154 /* Timer Control Register */ |
169 | #endif /* Book E */ | 167 | #endif /* Book E */ |
170 | #ifdef CONFIG_40x | 168 | #ifdef CONFIG_40x |
171 | #define SPRN_PID 0x3B1 /* Process ID */ | ||
172 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ | 169 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ |
173 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ | 170 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ |
174 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ | 171 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ |
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index e8e915ce3d8d..c9b68d07ac4f 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
@@ -1811,11 +1811,11 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1811 | .machine_check = machine_check_440A, | 1811 | .machine_check = machine_check_440A, |
1812 | .platform = "ppc440", | 1812 | .platform = "ppc440", |
1813 | }, | 1813 | }, |
1814 | { /* 476 core */ | 1814 | { /* 476 DD2 core */ |
1815 | .pvr_mask = 0xffff0000, | 1815 | .pvr_mask = 0xffffffff, |
1816 | .pvr_value = 0x11a50000, | 1816 | .pvr_value = 0x11a52080, |
1817 | .cpu_name = "476", | 1817 | .cpu_name = "476", |
1818 | .cpu_features = CPU_FTRS_47X, | 1818 | .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2, |
1819 | .cpu_user_features = COMMON_USER_BOOKE | | 1819 | .cpu_user_features = COMMON_USER_BOOKE | |
1820 | PPC_FEATURE_HAS_FPU, | 1820 | PPC_FEATURE_HAS_FPU, |
1821 | .mmu_features = MMU_FTR_TYPE_47x | | 1821 | .mmu_features = MMU_FTR_TYPE_47x | |
@@ -1839,6 +1839,20 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1839 | .machine_check = machine_check_47x, | 1839 | .machine_check = machine_check_47x, |
1840 | .platform = "ppc470", | 1840 | .platform = "ppc470", |
1841 | }, | 1841 | }, |
1842 | { /* 476 others */ | ||
1843 | .pvr_mask = 0xffff0000, | ||
1844 | .pvr_value = 0x11a50000, | ||
1845 | .cpu_name = "476", | ||
1846 | .cpu_features = CPU_FTRS_47X, | ||
1847 | .cpu_user_features = COMMON_USER_BOOKE | | ||
1848 | PPC_FEATURE_HAS_FPU, | ||
1849 | .mmu_features = MMU_FTR_TYPE_47x | | ||
1850 | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL, | ||
1851 | .icache_bsize = 32, | ||
1852 | .dcache_bsize = 128, | ||
1853 | .machine_check = machine_check_47x, | ||
1854 | .platform = "ppc470", | ||
1855 | }, | ||
1842 | { /* default match */ | 1856 | { /* default match */ |
1843 | .pvr_mask = 0x00000000, | 1857 | .pvr_mask = 0x00000000, |
1844 | .pvr_value = 0x00000000, | 1858 | .pvr_value = 0x00000000, |
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index ce557f6f00fc..0a5570338b96 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
@@ -237,6 +237,7 @@ int show_interrupts(struct seq_file *p, void *v) | |||
237 | int i = *(loff_t *) v, j, prec; | 237 | int i = *(loff_t *) v, j, prec; |
238 | struct irqaction *action; | 238 | struct irqaction *action; |
239 | struct irq_desc *desc; | 239 | struct irq_desc *desc; |
240 | struct irq_chip *chip; | ||
240 | 241 | ||
241 | if (i > nr_irqs) | 242 | if (i > nr_irqs) |
242 | return 0; | 243 | return 0; |
@@ -270,8 +271,9 @@ int show_interrupts(struct seq_file *p, void *v) | |||
270 | for_each_online_cpu(j) | 271 | for_each_online_cpu(j) |
271 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | 272 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); |
272 | 273 | ||
273 | if (desc->chip) | 274 | chip = get_irq_desc_chip(desc); |
274 | seq_printf(p, " %-16s", desc->chip->name); | 275 | if (chip) |
276 | seq_printf(p, " %-16s", chip->name); | ||
275 | else | 277 | else |
276 | seq_printf(p, " %-16s", "None"); | 278 | seq_printf(p, " %-16s", "None"); |
277 | seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge"); | 279 | seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge"); |
@@ -313,6 +315,8 @@ void fixup_irqs(const struct cpumask *map) | |||
313 | alloc_cpumask_var(&mask, GFP_KERNEL); | 315 | alloc_cpumask_var(&mask, GFP_KERNEL); |
314 | 316 | ||
315 | for_each_irq(irq) { | 317 | for_each_irq(irq) { |
318 | struct irq_chip *chip; | ||
319 | |||
316 | desc = irq_to_desc(irq); | 320 | desc = irq_to_desc(irq); |
317 | if (!desc) | 321 | if (!desc) |
318 | continue; | 322 | continue; |
@@ -320,13 +324,15 @@ void fixup_irqs(const struct cpumask *map) | |||
320 | if (desc->status & IRQ_PER_CPU) | 324 | if (desc->status & IRQ_PER_CPU) |
321 | continue; | 325 | continue; |
322 | 326 | ||
323 | cpumask_and(mask, desc->affinity, map); | 327 | chip = get_irq_desc_chip(desc); |
328 | |||
329 | cpumask_and(mask, desc->irq_data.affinity, map); | ||
324 | if (cpumask_any(mask) >= nr_cpu_ids) { | 330 | if (cpumask_any(mask) >= nr_cpu_ids) { |
325 | printk("Breaking affinity for irq %i\n", irq); | 331 | printk("Breaking affinity for irq %i\n", irq); |
326 | cpumask_copy(mask, map); | 332 | cpumask_copy(mask, map); |
327 | } | 333 | } |
328 | if (desc->chip->set_affinity) | 334 | if (chip->irq_set_affinity) |
329 | desc->chip->set_affinity(irq, mask); | 335 | chip->irq_set_affinity(&desc->irq_data, mask, true); |
330 | else if (desc->action && !(warned++)) | 336 | else if (desc->action && !(warned++)) |
331 | printk("Cannot set affinity for irq %i\n", irq); | 337 | printk("Cannot set affinity for irq %i\n", irq); |
332 | } | 338 | } |
@@ -678,16 +684,15 @@ void irq_set_virq_count(unsigned int count) | |||
678 | static int irq_setup_virq(struct irq_host *host, unsigned int virq, | 684 | static int irq_setup_virq(struct irq_host *host, unsigned int virq, |
679 | irq_hw_number_t hwirq) | 685 | irq_hw_number_t hwirq) |
680 | { | 686 | { |
681 | struct irq_desc *desc; | 687 | int res; |
682 | 688 | ||
683 | desc = irq_to_desc_alloc_node(virq, 0); | 689 | res = irq_alloc_desc_at(virq, 0); |
684 | if (!desc) { | 690 | if (res != virq) { |
685 | pr_debug("irq: -> allocating desc failed\n"); | 691 | pr_debug("irq: -> allocating desc failed\n"); |
686 | goto error; | 692 | goto error; |
687 | } | 693 | } |
688 | 694 | ||
689 | /* Clear IRQ_NOREQUEST flag */ | 695 | irq_clear_status_flags(virq, IRQ_NOREQUEST); |
690 | desc->status &= ~IRQ_NOREQUEST; | ||
691 | 696 | ||
692 | /* map it */ | 697 | /* map it */ |
693 | smp_wmb(); | 698 | smp_wmb(); |
@@ -696,11 +701,13 @@ static int irq_setup_virq(struct irq_host *host, unsigned int virq, | |||
696 | 701 | ||
697 | if (host->ops->map(host, virq, hwirq)) { | 702 | if (host->ops->map(host, virq, hwirq)) { |
698 | pr_debug("irq: -> mapping failed, freeing\n"); | 703 | pr_debug("irq: -> mapping failed, freeing\n"); |
699 | goto error; | 704 | goto errdesc; |
700 | } | 705 | } |
701 | 706 | ||
702 | return 0; | 707 | return 0; |
703 | 708 | ||
709 | errdesc: | ||
710 | irq_free_descs(virq, 1); | ||
704 | error: | 711 | error: |
705 | irq_free_virt(virq, 1); | 712 | irq_free_virt(virq, 1); |
706 | return -1; | 713 | return -1; |
@@ -879,9 +886,9 @@ void irq_dispose_mapping(unsigned int virq) | |||
879 | smp_mb(); | 886 | smp_mb(); |
880 | irq_map[virq].hwirq = host->inval_irq; | 887 | irq_map[virq].hwirq = host->inval_irq; |
881 | 888 | ||
882 | /* Set some flags */ | 889 | irq_set_status_flags(virq, IRQ_NOREQUEST); |
883 | irq_to_desc(virq)->status |= IRQ_NOREQUEST; | ||
884 | 890 | ||
891 | irq_free_descs(virq, 1); | ||
885 | /* Free it */ | 892 | /* Free it */ |
886 | irq_free_virt(virq, 1); | 893 | irq_free_virt(virq, 1); |
887 | } | 894 | } |
@@ -1074,21 +1081,6 @@ void irq_free_virt(unsigned int virq, unsigned int count) | |||
1074 | 1081 | ||
1075 | int arch_early_irq_init(void) | 1082 | int arch_early_irq_init(void) |
1076 | { | 1083 | { |
1077 | struct irq_desc *desc; | ||
1078 | int i; | ||
1079 | |||
1080 | for (i = 0; i < NR_IRQS; i++) { | ||
1081 | desc = irq_to_desc(i); | ||
1082 | if (desc) | ||
1083 | desc->status |= IRQ_NOREQUEST; | ||
1084 | } | ||
1085 | |||
1086 | return 0; | ||
1087 | } | ||
1088 | |||
1089 | int arch_init_chip_data(struct irq_desc *desc, int node) | ||
1090 | { | ||
1091 | desc->status |= IRQ_NOREQUEST; | ||
1092 | return 0; | 1084 | return 0; |
1093 | } | 1085 | } |
1094 | 1086 | ||
@@ -1159,11 +1151,14 @@ static int virq_debug_show(struct seq_file *m, void *private) | |||
1159 | raw_spin_lock_irqsave(&desc->lock, flags); | 1151 | raw_spin_lock_irqsave(&desc->lock, flags); |
1160 | 1152 | ||
1161 | if (desc->action && desc->action->handler) { | 1153 | if (desc->action && desc->action->handler) { |
1154 | struct irq_chip *chip; | ||
1155 | |||
1162 | seq_printf(m, "%5d ", i); | 1156 | seq_printf(m, "%5d ", i); |
1163 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); | 1157 | seq_printf(m, "0x%05lx ", virq_to_hw(i)); |
1164 | 1158 | ||
1165 | if (desc->chip && desc->chip->name) | 1159 | chip = get_irq_desc_chip(desc); |
1166 | p = desc->chip->name; | 1160 | if (chip && chip->name) |
1161 | p = chip->name; | ||
1167 | else | 1162 | else |
1168 | p = none; | 1163 | p = none; |
1169 | seq_printf(m, "%-15s ", p); | 1164 | seq_printf(m, "%-15s ", p); |
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index a5f8672eeff3..bd1e1ff17b2d 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c | |||
@@ -26,20 +26,23 @@ void machine_kexec_mask_interrupts(void) { | |||
26 | 26 | ||
27 | for_each_irq(i) { | 27 | for_each_irq(i) { |
28 | struct irq_desc *desc = irq_to_desc(i); | 28 | struct irq_desc *desc = irq_to_desc(i); |
29 | struct irq_chip *chip; | ||
29 | 30 | ||
30 | if (!desc || !desc->chip) | 31 | if (!desc) |
31 | continue; | 32 | continue; |
32 | 33 | ||
33 | if (desc->chip->eoi && | 34 | chip = get_irq_desc_chip(desc); |
34 | desc->status & IRQ_INPROGRESS) | 35 | if (!chip) |
35 | desc->chip->eoi(i); | 36 | continue; |
37 | |||
38 | if (chip->irq_eoi && desc->status & IRQ_INPROGRESS) | ||
39 | chip->irq_eoi(&desc->irq_data); | ||
36 | 40 | ||
37 | if (desc->chip->mask) | 41 | if (chip->irq_mask) |
38 | desc->chip->mask(i); | 42 | chip->irq_mask(&desc->irq_data); |
39 | 43 | ||
40 | if (desc->chip->disable && | 44 | if (chip->irq_disable && !(desc->status & IRQ_DISABLED)) |
41 | !(desc->status & IRQ_DISABLED)) | 45 | chip->irq_disable(&desc->irq_data); |
42 | desc->chip->disable(i); | ||
43 | } | 46 | } |
44 | } | 47 | } |
45 | 48 | ||
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c index bb12b3248f13..bec1e930ed73 100644 --- a/arch/powerpc/kernel/nvram_64.c +++ b/arch/powerpc/kernel/nvram_64.c | |||
@@ -237,22 +237,45 @@ static unsigned char __init nvram_checksum(struct nvram_header *p) | |||
237 | return c_sum; | 237 | return c_sum; |
238 | } | 238 | } |
239 | 239 | ||
240 | /* | ||
241 | * Per the criteria passed via nvram_remove_partition(), should this | ||
242 | * partition be removed? 1=remove, 0=keep | ||
243 | */ | ||
244 | static int nvram_can_remove_partition(struct nvram_partition *part, | ||
245 | const char *name, int sig, const char *exceptions[]) | ||
246 | { | ||
247 | if (part->header.signature != sig) | ||
248 | return 0; | ||
249 | if (name) { | ||
250 | if (strncmp(name, part->header.name, 12)) | ||
251 | return 0; | ||
252 | } else if (exceptions) { | ||
253 | const char **except; | ||
254 | for (except = exceptions; *except; except++) { | ||
255 | if (!strncmp(*except, part->header.name, 12)) | ||
256 | return 0; | ||
257 | } | ||
258 | } | ||
259 | return 1; | ||
260 | } | ||
261 | |||
240 | /** | 262 | /** |
241 | * nvram_remove_partition - Remove one or more partitions in nvram | 263 | * nvram_remove_partition - Remove one or more partitions in nvram |
242 | * @name: name of the partition to remove, or NULL for a | 264 | * @name: name of the partition to remove, or NULL for a |
243 | * signature only match | 265 | * signature only match |
244 | * @sig: signature of the partition(s) to remove | 266 | * @sig: signature of the partition(s) to remove |
267 | * @exceptions: When removing all partitions with a matching signature, | ||
268 | * leave these alone. | ||
245 | */ | 269 | */ |
246 | 270 | ||
247 | int __init nvram_remove_partition(const char *name, int sig) | 271 | int __init nvram_remove_partition(const char *name, int sig, |
272 | const char *exceptions[]) | ||
248 | { | 273 | { |
249 | struct nvram_partition *part, *prev, *tmp; | 274 | struct nvram_partition *part, *prev, *tmp; |
250 | int rc; | 275 | int rc; |
251 | 276 | ||
252 | list_for_each_entry(part, &nvram_partitions, partition) { | 277 | list_for_each_entry(part, &nvram_partitions, partition) { |
253 | if (part->header.signature != sig) | 278 | if (!nvram_can_remove_partition(part, name, sig, exceptions)) |
254 | continue; | ||
255 | if (name && strncmp(name, part->header.name, 12)) | ||
256 | continue; | 279 | continue; |
257 | 280 | ||
258 | /* Make partition a free partition */ | 281 | /* Make partition a free partition */ |
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 7185f0da7dc3..05b7139d6a27 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c | |||
@@ -97,7 +97,7 @@ static void __init move_device_tree(void) | |||
97 | start = __pa(initial_boot_params); | 97 | start = __pa(initial_boot_params); |
98 | size = be32_to_cpu(initial_boot_params->totalsize); | 98 | size = be32_to_cpu(initial_boot_params->totalsize); |
99 | 99 | ||
100 | if ((memory_limit && (start + size) > memory_limit) || | 100 | if ((memory_limit && (start + size) > PHYSICAL_START + memory_limit) || |
101 | overlaps_crashkernel(start, size)) { | 101 | overlaps_crashkernel(start, size)) { |
102 | p = __va(memblock_alloc(size, PAGE_SIZE)); | 102 | p = __va(memblock_alloc(size, PAGE_SIZE)); |
103 | memcpy(p, initial_boot_params, size); | 103 | memcpy(p, initial_boot_params, size); |
diff --git a/arch/powerpc/kernel/rtasd.c b/arch/powerpc/kernel/rtasd.c index 049dbecb5dbc..7980ec0e1e1a 100644 --- a/arch/powerpc/kernel/rtasd.c +++ b/arch/powerpc/kernel/rtasd.c | |||
@@ -412,7 +412,8 @@ static void rtas_event_scan(struct work_struct *w) | |||
412 | 412 | ||
413 | get_online_cpus(); | 413 | get_online_cpus(); |
414 | 414 | ||
415 | cpu = cpumask_next(smp_processor_id(), cpu_online_mask); | 415 | /* raw_ OK because just using CPU as starting point. */ |
416 | cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask); | ||
416 | if (cpu >= nr_cpu_ids) { | 417 | if (cpu >= nr_cpu_ids) { |
417 | cpu = cpumask_first(cpu_online_mask); | 418 | cpu = cpumask_first(cpu_online_mask); |
418 | 419 | ||
diff --git a/arch/powerpc/math-emu/math_efp.c b/arch/powerpc/math-emu/math_efp.c index 41f4ef30e480..62279200d965 100644 --- a/arch/powerpc/math-emu/math_efp.c +++ b/arch/powerpc/math-emu/math_efp.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * arch/powerpc/math-emu/math_efp.c | 2 | * arch/powerpc/math-emu/math_efp.c |
3 | * | 3 | * |
4 | * Copyright (C) 2006-2008 Freescale Semiconductor, Inc. All rights reserved. | 4 | * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc. |
5 | * | 5 | * |
6 | * Author: Ebony Zhu, <ebony.zhu@freescale.com> | 6 | * Author: Ebony Zhu, <ebony.zhu@freescale.com> |
7 | * Yu Liu, <yu.liu@freescale.com> | 7 | * Yu Liu, <yu.liu@freescale.com> |
@@ -104,6 +104,8 @@ | |||
104 | #define FP_EX_MASK (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \ | 104 | #define FP_EX_MASK (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \ |
105 | FP_EX_UNDERFLOW | FP_EX_OVERFLOW) | 105 | FP_EX_UNDERFLOW | FP_EX_OVERFLOW) |
106 | 106 | ||
107 | static int have_e500_cpu_a005_erratum; | ||
108 | |||
107 | union dw_union { | 109 | union dw_union { |
108 | u64 dp[1]; | 110 | u64 dp[1]; |
109 | u32 wp[2]; | 111 | u32 wp[2]; |
@@ -320,7 +322,8 @@ int do_spe_mathemu(struct pt_regs *regs) | |||
320 | } else { | 322 | } else { |
321 | _FP_ROUND_ZERO(1, SB); | 323 | _FP_ROUND_ZERO(1, SB); |
322 | } | 324 | } |
323 | FP_TO_INT_S(vc.wp[1], SB, 32, ((func & 0x3) != 0)); | 325 | FP_TO_INT_S(vc.wp[1], SB, 32, |
326 | (((func & 0x3) != 0) || SB_s)); | ||
324 | goto update_regs; | 327 | goto update_regs; |
325 | 328 | ||
326 | default: | 329 | default: |
@@ -458,7 +461,8 @@ cmp_s: | |||
458 | } else { | 461 | } else { |
459 | _FP_ROUND_ZERO(2, DB); | 462 | _FP_ROUND_ZERO(2, DB); |
460 | } | 463 | } |
461 | FP_TO_INT_D(vc.wp[1], DB, 32, ((func & 0x3) != 0)); | 464 | FP_TO_INT_D(vc.wp[1], DB, 32, |
465 | (((func & 0x3) != 0) || DB_s)); | ||
462 | goto update_regs; | 466 | goto update_regs; |
463 | 467 | ||
464 | default: | 468 | default: |
@@ -589,8 +593,10 @@ cmp_d: | |||
589 | _FP_ROUND_ZERO(1, SB0); | 593 | _FP_ROUND_ZERO(1, SB0); |
590 | _FP_ROUND_ZERO(1, SB1); | 594 | _FP_ROUND_ZERO(1, SB1); |
591 | } | 595 | } |
592 | FP_TO_INT_S(vc.wp[0], SB0, 32, ((func & 0x3) != 0)); | 596 | FP_TO_INT_S(vc.wp[0], SB0, 32, |
593 | FP_TO_INT_S(vc.wp[1], SB1, 32, ((func & 0x3) != 0)); | 597 | (((func & 0x3) != 0) || SB0_s)); |
598 | FP_TO_INT_S(vc.wp[1], SB1, 32, | ||
599 | (((func & 0x3) != 0) || SB1_s)); | ||
594 | goto update_regs; | 600 | goto update_regs; |
595 | 601 | ||
596 | default: | 602 | default: |
@@ -652,6 +658,15 @@ update_regs: | |||
652 | return 0; | 658 | return 0; |
653 | 659 | ||
654 | illegal: | 660 | illegal: |
661 | if (have_e500_cpu_a005_erratum) { | ||
662 | /* according to e500 cpu a005 erratum, reissue efp inst */ | ||
663 | regs->nip -= 4; | ||
664 | #ifdef DEBUG | ||
665 | printk(KERN_DEBUG "re-issue efp inst: %08lx\n", speinsn); | ||
666 | #endif | ||
667 | return 0; | ||
668 | } | ||
669 | |||
655 | printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn); | 670 | printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn); |
656 | return -ENOSYS; | 671 | return -ENOSYS; |
657 | } | 672 | } |
@@ -718,3 +733,43 @@ int speround_handler(struct pt_regs *regs) | |||
718 | 733 | ||
719 | return 0; | 734 | return 0; |
720 | } | 735 | } |
736 | |||
737 | int __init spe_mathemu_init(void) | ||
738 | { | ||
739 | u32 pvr, maj, min; | ||
740 | |||
741 | pvr = mfspr(SPRN_PVR); | ||
742 | |||
743 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || | ||
744 | (PVR_VER(pvr) == PVR_VER_E500V2)) { | ||
745 | maj = PVR_MAJ(pvr); | ||
746 | min = PVR_MIN(pvr); | ||
747 | |||
748 | /* | ||
749 | * E500 revision below 1.1, 2.3, 3.1, 4.1, 5.1 | ||
750 | * need cpu a005 errata workaround | ||
751 | */ | ||
752 | switch (maj) { | ||
753 | case 1: | ||
754 | if (min < 1) | ||
755 | have_e500_cpu_a005_erratum = 1; | ||
756 | break; | ||
757 | case 2: | ||
758 | if (min < 3) | ||
759 | have_e500_cpu_a005_erratum = 1; | ||
760 | break; | ||
761 | case 3: | ||
762 | case 4: | ||
763 | case 5: | ||
764 | if (min < 1) | ||
765 | have_e500_cpu_a005_erratum = 1; | ||
766 | break; | ||
767 | default: | ||
768 | break; | ||
769 | } | ||
770 | } | ||
771 | |||
772 | return 0; | ||
773 | } | ||
774 | |||
775 | module_init(spe_mathemu_init); | ||
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 742da43b4ab6..d65b591e5556 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c | |||
@@ -148,7 +148,7 @@ void __init MMU_init(void) | |||
148 | lowmem_end_addr = memstart_addr + total_lowmem; | 148 | lowmem_end_addr = memstart_addr + total_lowmem; |
149 | #ifndef CONFIG_HIGHMEM | 149 | #ifndef CONFIG_HIGHMEM |
150 | total_memory = total_lowmem; | 150 | total_memory = total_lowmem; |
151 | memblock_enforce_memory_limit(lowmem_end_addr); | 151 | memblock_enforce_memory_limit(total_lowmem); |
152 | memblock_analyze(); | 152 | memblock_analyze(); |
153 | #endif /* CONFIG_HIGHMEM */ | 153 | #endif /* CONFIG_HIGHMEM */ |
154 | } | 154 | } |
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index af405eefe48d..7c63c0ed4f1b 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S | |||
@@ -189,6 +189,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) | |||
189 | blr | 189 | blr |
190 | 190 | ||
191 | #ifdef CONFIG_PPC_47x | 191 | #ifdef CONFIG_PPC_47x |
192 | |||
193 | /* | ||
194 | * 47x variant of icbt | ||
195 | */ | ||
196 | # define ICBT(CT,RA,RB) \ | ||
197 | .long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11) | ||
198 | |||
192 | /* | 199 | /* |
193 | * _tlbivax_bcast is only on 47x. We don't bother doing a runtime | 200 | * _tlbivax_bcast is only on 47x. We don't bother doing a runtime |
194 | * check though, it will blow up soon enough if we mistakenly try | 201 | * check though, it will blow up soon enough if we mistakenly try |
@@ -206,7 +213,35 @@ _GLOBAL(_tlbivax_bcast) | |||
206 | isync | 213 | isync |
207 | eieio | 214 | eieio |
208 | tlbsync | 215 | tlbsync |
216 | BEGIN_FTR_SECTION | ||
217 | b 1f | ||
218 | END_FTR_SECTION_IFSET(CPU_FTR_476_DD2) | ||
219 | sync | ||
220 | wrtee r10 | ||
221 | blr | ||
222 | /* | ||
223 | * DD2 HW could hang if in instruction fetch happens before msync completes. | ||
224 | * Touch enough instruction cache lines to ensure cache hits | ||
225 | */ | ||
226 | 1: mflr r9 | ||
227 | bl 2f | ||
228 | 2: mflr r6 | ||
229 | li r7,32 | ||
230 | ICBT(0,r6,r7) /* touch next cache line */ | ||
231 | add r6,r6,r7 | ||
232 | ICBT(0,r6,r7) /* touch next cache line */ | ||
233 | add r6,r6,r7 | ||
234 | ICBT(0,r6,r7) /* touch next cache line */ | ||
209 | sync | 235 | sync |
236 | nop | ||
237 | nop | ||
238 | nop | ||
239 | nop | ||
240 | nop | ||
241 | nop | ||
242 | nop | ||
243 | nop | ||
244 | mtlr r9 | ||
210 | wrtee r10 | 245 | wrtee r10 |
211 | blr | 246 | blr |
212 | #endif /* CONFIG_PPC_47x */ | 247 | #endif /* CONFIG_PPC_47x */ |
diff --git a/arch/powerpc/platforms/44x/44x.h b/arch/powerpc/platforms/44x/44x.h index dbc4d2b4301a..63f703ecd23c 100644 --- a/arch/powerpc/platforms/44x/44x.h +++ b/arch/powerpc/platforms/44x/44x.h | |||
@@ -4,4 +4,8 @@ | |||
4 | extern u8 as1_readb(volatile u8 __iomem *addr); | 4 | extern u8 as1_readb(volatile u8 __iomem *addr); |
5 | extern void as1_writeb(u8 data, volatile u8 __iomem *addr); | 5 | extern void as1_writeb(u8 data, volatile u8 __iomem *addr); |
6 | 6 | ||
7 | #define GPIO0_OSRH 0xC | ||
8 | #define GPIO0_TSRH 0x14 | ||
9 | #define GPIO0_ISR1H 0x34 | ||
10 | |||
7 | #endif /* __POWERPC_PLATFORMS_44X_44X_H */ | 11 | #endif /* __POWERPC_PLATFORMS_44X_44X_H */ |
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig index 0f979c5c756b..f485fc5f6d5e 100644 --- a/arch/powerpc/platforms/44x/Kconfig +++ b/arch/powerpc/platforms/44x/Kconfig | |||
@@ -115,7 +115,6 @@ config CANYONLANDS | |||
115 | bool "Canyonlands" | 115 | bool "Canyonlands" |
116 | depends on 44x | 116 | depends on 44x |
117 | default n | 117 | default n |
118 | select PPC44x_SIMPLE | ||
119 | select 460EX | 118 | select 460EX |
120 | select PCI | 119 | select PCI |
121 | select PPC4xx_PCI_EXPRESS | 120 | select PPC4xx_PCI_EXPRESS |
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile index c04d16df8488..553db6007217 100644 --- a/arch/powerpc/platforms/44x/Makefile +++ b/arch/powerpc/platforms/44x/Makefile | |||
@@ -9,3 +9,4 @@ obj-$(CONFIG_WARP) += warp.o | |||
9 | obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o | 9 | obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o |
10 | obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o | 10 | obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o |
11 | obj-$(CONFIG_ISS4xx) += iss4xx.o | 11 | obj-$(CONFIG_ISS4xx) += iss4xx.o |
12 | obj-$(CONFIG_CANYONLANDS)+= canyonlands.o | ||
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c new file mode 100644 index 000000000000..afc5e8ea3775 --- /dev/null +++ b/arch/powerpc/platforms/44x/canyonlands.c | |||
@@ -0,0 +1,134 @@ | |||
1 | /* | ||
2 | * This contain platform specific code for APM PPC460EX based Canyonlands | ||
3 | * board. | ||
4 | * | ||
5 | * Copyright (c) 2010, Applied Micro Circuits Corporation | ||
6 | * Author: Rupjyoti Sarmah <rsarmah@apm.com> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or | ||
9 | * modify it under the terms of the GNU General Public License as | ||
10 | * published by the Free Software Foundation; either version 2 of | ||
11 | * the License, or (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | ||
21 | * MA 02111-1307 USA | ||
22 | * | ||
23 | */ | ||
24 | #include <linux/kernel.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <asm/pci-bridge.h> | ||
27 | #include <asm/ppc4xx.h> | ||
28 | #include <asm/udbg.h> | ||
29 | #include <asm/uic.h> | ||
30 | #include <linux/of_platform.h> | ||
31 | #include <linux/delay.h> | ||
32 | #include "44x.h" | ||
33 | |||
34 | #define BCSR_USB_EN 0x11 | ||
35 | |||
36 | static __initdata struct of_device_id ppc460ex_of_bus[] = { | ||
37 | { .compatible = "ibm,plb4", }, | ||
38 | { .compatible = "ibm,opb", }, | ||
39 | { .compatible = "ibm,ebc", }, | ||
40 | { .compatible = "simple-bus", }, | ||
41 | {}, | ||
42 | }; | ||
43 | |||
44 | static int __init ppc460ex_device_probe(void) | ||
45 | { | ||
46 | of_platform_bus_probe(NULL, ppc460ex_of_bus, NULL); | ||
47 | |||
48 | return 0; | ||
49 | } | ||
50 | machine_device_initcall(canyonlands, ppc460ex_device_probe); | ||
51 | |||
52 | /* Using this code only for the Canyonlands board. */ | ||
53 | |||
54 | static int __init ppc460ex_probe(void) | ||
55 | { | ||
56 | unsigned long root = of_get_flat_dt_root(); | ||
57 | if (of_flat_dt_is_compatible(root, "amcc,canyonlands")) { | ||
58 | ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC); | ||
59 | return 1; | ||
60 | } | ||
61 | return 0; | ||
62 | } | ||
63 | |||
64 | /* USB PHY fixup code on Canyonlands kit. */ | ||
65 | |||
66 | static int __init ppc460ex_canyonlands_fixup(void) | ||
67 | { | ||
68 | u8 __iomem *bcsr ; | ||
69 | void __iomem *vaddr; | ||
70 | struct device_node *np; | ||
71 | int ret = 0; | ||
72 | |||
73 | np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-bcsr"); | ||
74 | if (!np) { | ||
75 | printk(KERN_ERR "failed did not find amcc, ppc460ex bcsr node\n"); | ||
76 | return -ENODEV; | ||
77 | } | ||
78 | |||
79 | bcsr = of_iomap(np, 0); | ||
80 | of_node_put(np); | ||
81 | |||
82 | if (!bcsr) { | ||
83 | printk(KERN_CRIT "Could not remap bcsr\n"); | ||
84 | ret = -ENODEV; | ||
85 | goto err_bcsr; | ||
86 | } | ||
87 | |||
88 | np = of_find_compatible_node(NULL, NULL, "ibm,ppc4xx-gpio"); | ||
89 | if (!np) { | ||
90 | printk(KERN_ERR "failed did not find ibm,ppc4xx-gpio node\n"); | ||
91 | return -ENODEV; | ||
92 | } | ||
93 | |||
94 | vaddr = of_iomap(np, 0); | ||
95 | of_node_put(np); | ||
96 | |||
97 | if (!vaddr) { | ||
98 | printk(KERN_CRIT "Could not get gpio node address\n"); | ||
99 | ret = -ENODEV; | ||
100 | goto err_gpio; | ||
101 | } | ||
102 | /* Disable USB, through the BCSR7 bits */ | ||
103 | setbits8(&bcsr[7], BCSR_USB_EN); | ||
104 | |||
105 | /* Wait for a while after reset */ | ||
106 | msleep(100); | ||
107 | |||
108 | /* Enable USB here */ | ||
109 | clrbits8(&bcsr[7], BCSR_USB_EN); | ||
110 | |||
111 | /* | ||
112 | * Configure multiplexed gpio16 and gpio19 as alternate1 output | ||
113 | * source after USB reset. In this configuration gpio16 will be | ||
114 | * USB2HStop and gpio19 will be USB2DStop. For more details refer to | ||
115 | * table 34-7 of PPC460EX user manual. | ||
116 | */ | ||
117 | setbits32((vaddr + GPIO0_OSRH), 0x42000000); | ||
118 | setbits32((vaddr + GPIO0_TSRH), 0x42000000); | ||
119 | err_gpio: | ||
120 | iounmap(vaddr); | ||
121 | err_bcsr: | ||
122 | iounmap(bcsr); | ||
123 | return ret; | ||
124 | } | ||
125 | machine_device_initcall(canyonlands, ppc460ex_canyonlands_fixup); | ||
126 | define_machine(canyonlands) { | ||
127 | .name = "Canyonlands", | ||
128 | .probe = ppc460ex_probe, | ||
129 | .progress = udbg_progress, | ||
130 | .init_IRQ = uic_init_tree, | ||
131 | .get_irq = uic_get_irq, | ||
132 | .restart = ppc4xx_reset_system, | ||
133 | .calibrate_decr = generic_calibrate_decr, | ||
134 | }; | ||
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c index 7ddcba3b9397..c81c19c0b3d4 100644 --- a/arch/powerpc/platforms/44x/ppc44x_simple.c +++ b/arch/powerpc/platforms/44x/ppc44x_simple.c | |||
@@ -53,7 +53,6 @@ static char *board[] __initdata = { | |||
53 | "amcc,arches", | 53 | "amcc,arches", |
54 | "amcc,bamboo", | 54 | "amcc,bamboo", |
55 | "amcc,bluestone", | 55 | "amcc,bluestone", |
56 | "amcc,canyonlands", | ||
57 | "amcc,glacier", | 56 | "amcc,glacier", |
58 | "ibm,ebony", | 57 | "ibm,ebony", |
59 | "amcc,eiger", | 58 | "amcc,eiger", |
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c index 4ecf4cf9a51b..fde0ea50c97d 100644 --- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c +++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c | |||
@@ -59,9 +59,9 @@ irq_to_pic_bit(unsigned int irq) | |||
59 | } | 59 | } |
60 | 60 | ||
61 | static void | 61 | static void |
62 | cpld_mask_irq(unsigned int irq) | 62 | cpld_mask_irq(struct irq_data *d) |
63 | { | 63 | { |
64 | unsigned int cpld_irq = (unsigned int)irq_map[irq].hwirq; | 64 | unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq; |
65 | void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); | 65 | void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); |
66 | 66 | ||
67 | out_8(pic_mask, | 67 | out_8(pic_mask, |
@@ -69,9 +69,9 @@ cpld_mask_irq(unsigned int irq) | |||
69 | } | 69 | } |
70 | 70 | ||
71 | static void | 71 | static void |
72 | cpld_unmask_irq(unsigned int irq) | 72 | cpld_unmask_irq(struct irq_data *d) |
73 | { | 73 | { |
74 | unsigned int cpld_irq = (unsigned int)irq_map[irq].hwirq; | 74 | unsigned int cpld_irq = (unsigned int)irq_map[d->irq].hwirq; |
75 | void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); | 75 | void __iomem *pic_mask = irq_to_pic_mask(cpld_irq); |
76 | 76 | ||
77 | out_8(pic_mask, | 77 | out_8(pic_mask, |
@@ -80,9 +80,9 @@ cpld_unmask_irq(unsigned int irq) | |||
80 | 80 | ||
81 | static struct irq_chip cpld_pic = { | 81 | static struct irq_chip cpld_pic = { |
82 | .name = "CPLD PIC", | 82 | .name = "CPLD PIC", |
83 | .mask = cpld_mask_irq, | 83 | .irq_mask = cpld_mask_irq, |
84 | .ack = cpld_mask_irq, | 84 | .irq_ack = cpld_mask_irq, |
85 | .unmask = cpld_unmask_irq, | 85 | .irq_unmask = cpld_unmask_irq, |
86 | }; | 86 | }; |
87 | 87 | ||
88 | static int | 88 | static int |
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c index 2c7780cb68e5..2bd1e6cf1f58 100644 --- a/arch/powerpc/platforms/52xx/media5200.c +++ b/arch/powerpc/platforms/52xx/media5200.c | |||
@@ -49,45 +49,46 @@ struct media5200_irq { | |||
49 | }; | 49 | }; |
50 | struct media5200_irq media5200_irq; | 50 | struct media5200_irq media5200_irq; |
51 | 51 | ||
52 | static void media5200_irq_unmask(unsigned int virq) | 52 | static void media5200_irq_unmask(struct irq_data *d) |
53 | { | 53 | { |
54 | unsigned long flags; | 54 | unsigned long flags; |
55 | u32 val; | 55 | u32 val; |
56 | 56 | ||
57 | spin_lock_irqsave(&media5200_irq.lock, flags); | 57 | spin_lock_irqsave(&media5200_irq.lock, flags); |
58 | val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); | 58 | val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); |
59 | val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq); | 59 | val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq); |
60 | out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); | 60 | out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); |
61 | spin_unlock_irqrestore(&media5200_irq.lock, flags); | 61 | spin_unlock_irqrestore(&media5200_irq.lock, flags); |
62 | } | 62 | } |
63 | 63 | ||
64 | static void media5200_irq_mask(unsigned int virq) | 64 | static void media5200_irq_mask(struct irq_data *d) |
65 | { | 65 | { |
66 | unsigned long flags; | 66 | unsigned long flags; |
67 | u32 val; | 67 | u32 val; |
68 | 68 | ||
69 | spin_lock_irqsave(&media5200_irq.lock, flags); | 69 | spin_lock_irqsave(&media5200_irq.lock, flags); |
70 | val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); | 70 | val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); |
71 | val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq)); | 71 | val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq)); |
72 | out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); | 72 | out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); |
73 | spin_unlock_irqrestore(&media5200_irq.lock, flags); | 73 | spin_unlock_irqrestore(&media5200_irq.lock, flags); |
74 | } | 74 | } |
75 | 75 | ||
76 | static struct irq_chip media5200_irq_chip = { | 76 | static struct irq_chip media5200_irq_chip = { |
77 | .name = "Media5200 FPGA", | 77 | .name = "Media5200 FPGA", |
78 | .unmask = media5200_irq_unmask, | 78 | .irq_unmask = media5200_irq_unmask, |
79 | .mask = media5200_irq_mask, | 79 | .irq_mask = media5200_irq_mask, |
80 | .mask_ack = media5200_irq_mask, | 80 | .irq_mask_ack = media5200_irq_mask, |
81 | }; | 81 | }; |
82 | 82 | ||
83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | 83 | void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) |
84 | { | 84 | { |
85 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
85 | int sub_virq, val; | 86 | int sub_virq, val; |
86 | u32 status, enable; | 87 | u32 status, enable; |
87 | 88 | ||
88 | /* Mask off the cascaded IRQ */ | 89 | /* Mask off the cascaded IRQ */ |
89 | raw_spin_lock(&desc->lock); | 90 | raw_spin_lock(&desc->lock); |
90 | desc->chip->mask(virq); | 91 | chip->irq_mask(&desc->irq_data); |
91 | raw_spin_unlock(&desc->lock); | 92 | raw_spin_unlock(&desc->lock); |
92 | 93 | ||
93 | /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs | 94 | /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs |
@@ -105,9 +106,9 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
105 | 106 | ||
106 | /* Processing done; can reenable the cascade now */ | 107 | /* Processing done; can reenable the cascade now */ |
107 | raw_spin_lock(&desc->lock); | 108 | raw_spin_lock(&desc->lock); |
108 | desc->chip->ack(virq); | 109 | chip->irq_ack(&desc->irq_data); |
109 | if (!(desc->status & IRQ_DISABLED)) | 110 | if (!(desc->status & IRQ_DISABLED)) |
110 | desc->chip->unmask(virq); | 111 | chip->irq_unmask(&desc->irq_data); |
111 | raw_spin_unlock(&desc->lock); | 112 | raw_spin_unlock(&desc->lock); |
112 | } | 113 | } |
113 | 114 | ||
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c index 859abf1c6d4b..6da44f0f2934 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c | |||
@@ -135,9 +135,9 @@ DEFINE_MUTEX(mpc52xx_gpt_list_mutex); | |||
135 | * Cascaded interrupt controller hooks | 135 | * Cascaded interrupt controller hooks |
136 | */ | 136 | */ |
137 | 137 | ||
138 | static void mpc52xx_gpt_irq_unmask(unsigned int virq) | 138 | static void mpc52xx_gpt_irq_unmask(struct irq_data *d) |
139 | { | 139 | { |
140 | struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); | 140 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
141 | unsigned long flags; | 141 | unsigned long flags; |
142 | 142 | ||
143 | spin_lock_irqsave(&gpt->lock, flags); | 143 | spin_lock_irqsave(&gpt->lock, flags); |
@@ -145,9 +145,9 @@ static void mpc52xx_gpt_irq_unmask(unsigned int virq) | |||
145 | spin_unlock_irqrestore(&gpt->lock, flags); | 145 | spin_unlock_irqrestore(&gpt->lock, flags); |
146 | } | 146 | } |
147 | 147 | ||
148 | static void mpc52xx_gpt_irq_mask(unsigned int virq) | 148 | static void mpc52xx_gpt_irq_mask(struct irq_data *d) |
149 | { | 149 | { |
150 | struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); | 150 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
151 | unsigned long flags; | 151 | unsigned long flags; |
152 | 152 | ||
153 | spin_lock_irqsave(&gpt->lock, flags); | 153 | spin_lock_irqsave(&gpt->lock, flags); |
@@ -155,20 +155,20 @@ static void mpc52xx_gpt_irq_mask(unsigned int virq) | |||
155 | spin_unlock_irqrestore(&gpt->lock, flags); | 155 | spin_unlock_irqrestore(&gpt->lock, flags); |
156 | } | 156 | } |
157 | 157 | ||
158 | static void mpc52xx_gpt_irq_ack(unsigned int virq) | 158 | static void mpc52xx_gpt_irq_ack(struct irq_data *d) |
159 | { | 159 | { |
160 | struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); | 160 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
161 | 161 | ||
162 | out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); | 162 | out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); |
163 | } | 163 | } |
164 | 164 | ||
165 | static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type) | 165 | static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type) |
166 | { | 166 | { |
167 | struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq); | 167 | struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); |
168 | unsigned long flags; | 168 | unsigned long flags; |
169 | u32 reg; | 169 | u32 reg; |
170 | 170 | ||
171 | dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type); | 171 | dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type); |
172 | 172 | ||
173 | spin_lock_irqsave(&gpt->lock, flags); | 173 | spin_lock_irqsave(&gpt->lock, flags); |
174 | reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; | 174 | reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; |
@@ -184,10 +184,10 @@ static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type) | |||
184 | 184 | ||
185 | static struct irq_chip mpc52xx_gpt_irq_chip = { | 185 | static struct irq_chip mpc52xx_gpt_irq_chip = { |
186 | .name = "MPC52xx GPT", | 186 | .name = "MPC52xx GPT", |
187 | .unmask = mpc52xx_gpt_irq_unmask, | 187 | .irq_unmask = mpc52xx_gpt_irq_unmask, |
188 | .mask = mpc52xx_gpt_irq_mask, | 188 | .irq_mask = mpc52xx_gpt_irq_mask, |
189 | .ack = mpc52xx_gpt_irq_ack, | 189 | .irq_ack = mpc52xx_gpt_irq_ack, |
190 | .set_type = mpc52xx_gpt_irq_set_type, | 190 | .irq_set_type = mpc52xx_gpt_irq_set_type, |
191 | }; | 191 | }; |
192 | 192 | ||
193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) | 193 | void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) |
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index 4bf4bf7b063e..9f3ed582d082 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c | |||
@@ -155,47 +155,47 @@ static inline void io_be_clrbit(u32 __iomem *addr, int bitno) | |||
155 | /* | 155 | /* |
156 | * IRQ[0-3] interrupt irq_chip | 156 | * IRQ[0-3] interrupt irq_chip |
157 | */ | 157 | */ |
158 | static void mpc52xx_extirq_mask(unsigned int virq) | 158 | static void mpc52xx_extirq_mask(struct irq_data *d) |
159 | { | 159 | { |
160 | int irq; | 160 | int irq; |
161 | int l2irq; | 161 | int l2irq; |
162 | 162 | ||
163 | irq = irq_map[virq].hwirq; | 163 | irq = irq_map[d->irq].hwirq; |
164 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 164 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
165 | 165 | ||
166 | io_be_clrbit(&intr->ctrl, 11 - l2irq); | 166 | io_be_clrbit(&intr->ctrl, 11 - l2irq); |
167 | } | 167 | } |
168 | 168 | ||
169 | static void mpc52xx_extirq_unmask(unsigned int virq) | 169 | static void mpc52xx_extirq_unmask(struct irq_data *d) |
170 | { | 170 | { |
171 | int irq; | 171 | int irq; |
172 | int l2irq; | 172 | int l2irq; |
173 | 173 | ||
174 | irq = irq_map[virq].hwirq; | 174 | irq = irq_map[d->irq].hwirq; |
175 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 175 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
176 | 176 | ||
177 | io_be_setbit(&intr->ctrl, 11 - l2irq); | 177 | io_be_setbit(&intr->ctrl, 11 - l2irq); |
178 | } | 178 | } |
179 | 179 | ||
180 | static void mpc52xx_extirq_ack(unsigned int virq) | 180 | static void mpc52xx_extirq_ack(struct irq_data *d) |
181 | { | 181 | { |
182 | int irq; | 182 | int irq; |
183 | int l2irq; | 183 | int l2irq; |
184 | 184 | ||
185 | irq = irq_map[virq].hwirq; | 185 | irq = irq_map[d->irq].hwirq; |
186 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 186 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
187 | 187 | ||
188 | io_be_setbit(&intr->ctrl, 27-l2irq); | 188 | io_be_setbit(&intr->ctrl, 27-l2irq); |
189 | } | 189 | } |
190 | 190 | ||
191 | static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) | 191 | static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type) |
192 | { | 192 | { |
193 | u32 ctrl_reg, type; | 193 | u32 ctrl_reg, type; |
194 | int irq; | 194 | int irq; |
195 | int l2irq; | 195 | int l2irq; |
196 | void *handler = handle_level_irq; | 196 | void *handler = handle_level_irq; |
197 | 197 | ||
198 | irq = irq_map[virq].hwirq; | 198 | irq = irq_map[d->irq].hwirq; |
199 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 199 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
200 | 200 | ||
201 | pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); | 201 | pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); |
@@ -214,44 +214,44 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) | |||
214 | ctrl_reg |= (type << (22 - (l2irq * 2))); | 214 | ctrl_reg |= (type << (22 - (l2irq * 2))); |
215 | out_be32(&intr->ctrl, ctrl_reg); | 215 | out_be32(&intr->ctrl, ctrl_reg); |
216 | 216 | ||
217 | __set_irq_handler_unlocked(virq, handler); | 217 | __set_irq_handler_unlocked(d->irq, handler); |
218 | 218 | ||
219 | return 0; | 219 | return 0; |
220 | } | 220 | } |
221 | 221 | ||
222 | static struct irq_chip mpc52xx_extirq_irqchip = { | 222 | static struct irq_chip mpc52xx_extirq_irqchip = { |
223 | .name = "MPC52xx External", | 223 | .name = "MPC52xx External", |
224 | .mask = mpc52xx_extirq_mask, | 224 | .irq_mask = mpc52xx_extirq_mask, |
225 | .unmask = mpc52xx_extirq_unmask, | 225 | .irq_unmask = mpc52xx_extirq_unmask, |
226 | .ack = mpc52xx_extirq_ack, | 226 | .irq_ack = mpc52xx_extirq_ack, |
227 | .set_type = mpc52xx_extirq_set_type, | 227 | .irq_set_type = mpc52xx_extirq_set_type, |
228 | }; | 228 | }; |
229 | 229 | ||
230 | /* | 230 | /* |
231 | * Main interrupt irq_chip | 231 | * Main interrupt irq_chip |
232 | */ | 232 | */ |
233 | static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type) | 233 | static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type) |
234 | { | 234 | { |
235 | return 0; /* Do nothing so that the sense mask will get updated */ | 235 | return 0; /* Do nothing so that the sense mask will get updated */ |
236 | } | 236 | } |
237 | 237 | ||
238 | static void mpc52xx_main_mask(unsigned int virq) | 238 | static void mpc52xx_main_mask(struct irq_data *d) |
239 | { | 239 | { |
240 | int irq; | 240 | int irq; |
241 | int l2irq; | 241 | int l2irq; |
242 | 242 | ||
243 | irq = irq_map[virq].hwirq; | 243 | irq = irq_map[d->irq].hwirq; |
244 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 244 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
245 | 245 | ||
246 | io_be_setbit(&intr->main_mask, 16 - l2irq); | 246 | io_be_setbit(&intr->main_mask, 16 - l2irq); |
247 | } | 247 | } |
248 | 248 | ||
249 | static void mpc52xx_main_unmask(unsigned int virq) | 249 | static void mpc52xx_main_unmask(struct irq_data *d) |
250 | { | 250 | { |
251 | int irq; | 251 | int irq; |
252 | int l2irq; | 252 | int l2irq; |
253 | 253 | ||
254 | irq = irq_map[virq].hwirq; | 254 | irq = irq_map[d->irq].hwirq; |
255 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 255 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
256 | 256 | ||
257 | io_be_clrbit(&intr->main_mask, 16 - l2irq); | 257 | io_be_clrbit(&intr->main_mask, 16 - l2irq); |
@@ -259,32 +259,32 @@ static void mpc52xx_main_unmask(unsigned int virq) | |||
259 | 259 | ||
260 | static struct irq_chip mpc52xx_main_irqchip = { | 260 | static struct irq_chip mpc52xx_main_irqchip = { |
261 | .name = "MPC52xx Main", | 261 | .name = "MPC52xx Main", |
262 | .mask = mpc52xx_main_mask, | 262 | .irq_mask = mpc52xx_main_mask, |
263 | .mask_ack = mpc52xx_main_mask, | 263 | .irq_mask_ack = mpc52xx_main_mask, |
264 | .unmask = mpc52xx_main_unmask, | 264 | .irq_unmask = mpc52xx_main_unmask, |
265 | .set_type = mpc52xx_null_set_type, | 265 | .irq_set_type = mpc52xx_null_set_type, |
266 | }; | 266 | }; |
267 | 267 | ||
268 | /* | 268 | /* |
269 | * Peripherals interrupt irq_chip | 269 | * Peripherals interrupt irq_chip |
270 | */ | 270 | */ |
271 | static void mpc52xx_periph_mask(unsigned int virq) | 271 | static void mpc52xx_periph_mask(struct irq_data *d) |
272 | { | 272 | { |
273 | int irq; | 273 | int irq; |
274 | int l2irq; | 274 | int l2irq; |
275 | 275 | ||
276 | irq = irq_map[virq].hwirq; | 276 | irq = irq_map[d->irq].hwirq; |
277 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 277 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
278 | 278 | ||
279 | io_be_setbit(&intr->per_mask, 31 - l2irq); | 279 | io_be_setbit(&intr->per_mask, 31 - l2irq); |
280 | } | 280 | } |
281 | 281 | ||
282 | static void mpc52xx_periph_unmask(unsigned int virq) | 282 | static void mpc52xx_periph_unmask(struct irq_data *d) |
283 | { | 283 | { |
284 | int irq; | 284 | int irq; |
285 | int l2irq; | 285 | int l2irq; |
286 | 286 | ||
287 | irq = irq_map[virq].hwirq; | 287 | irq = irq_map[d->irq].hwirq; |
288 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 288 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
289 | 289 | ||
290 | io_be_clrbit(&intr->per_mask, 31 - l2irq); | 290 | io_be_clrbit(&intr->per_mask, 31 - l2irq); |
@@ -292,43 +292,43 @@ static void mpc52xx_periph_unmask(unsigned int virq) | |||
292 | 292 | ||
293 | static struct irq_chip mpc52xx_periph_irqchip = { | 293 | static struct irq_chip mpc52xx_periph_irqchip = { |
294 | .name = "MPC52xx Peripherals", | 294 | .name = "MPC52xx Peripherals", |
295 | .mask = mpc52xx_periph_mask, | 295 | .irq_mask = mpc52xx_periph_mask, |
296 | .mask_ack = mpc52xx_periph_mask, | 296 | .irq_mask_ack = mpc52xx_periph_mask, |
297 | .unmask = mpc52xx_periph_unmask, | 297 | .irq_unmask = mpc52xx_periph_unmask, |
298 | .set_type = mpc52xx_null_set_type, | 298 | .irq_set_type = mpc52xx_null_set_type, |
299 | }; | 299 | }; |
300 | 300 | ||
301 | /* | 301 | /* |
302 | * SDMA interrupt irq_chip | 302 | * SDMA interrupt irq_chip |
303 | */ | 303 | */ |
304 | static void mpc52xx_sdma_mask(unsigned int virq) | 304 | static void mpc52xx_sdma_mask(struct irq_data *d) |
305 | { | 305 | { |
306 | int irq; | 306 | int irq; |
307 | int l2irq; | 307 | int l2irq; |
308 | 308 | ||
309 | irq = irq_map[virq].hwirq; | 309 | irq = irq_map[d->irq].hwirq; |
310 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 310 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
311 | 311 | ||
312 | io_be_setbit(&sdma->IntMask, l2irq); | 312 | io_be_setbit(&sdma->IntMask, l2irq); |
313 | } | 313 | } |
314 | 314 | ||
315 | static void mpc52xx_sdma_unmask(unsigned int virq) | 315 | static void mpc52xx_sdma_unmask(struct irq_data *d) |
316 | { | 316 | { |
317 | int irq; | 317 | int irq; |
318 | int l2irq; | 318 | int l2irq; |
319 | 319 | ||
320 | irq = irq_map[virq].hwirq; | 320 | irq = irq_map[d->irq].hwirq; |
321 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 321 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
322 | 322 | ||
323 | io_be_clrbit(&sdma->IntMask, l2irq); | 323 | io_be_clrbit(&sdma->IntMask, l2irq); |
324 | } | 324 | } |
325 | 325 | ||
326 | static void mpc52xx_sdma_ack(unsigned int virq) | 326 | static void mpc52xx_sdma_ack(struct irq_data *d) |
327 | { | 327 | { |
328 | int irq; | 328 | int irq; |
329 | int l2irq; | 329 | int l2irq; |
330 | 330 | ||
331 | irq = irq_map[virq].hwirq; | 331 | irq = irq_map[d->irq].hwirq; |
332 | l2irq = irq & MPC52xx_IRQ_L2_MASK; | 332 | l2irq = irq & MPC52xx_IRQ_L2_MASK; |
333 | 333 | ||
334 | out_be32(&sdma->IntPend, 1 << l2irq); | 334 | out_be32(&sdma->IntPend, 1 << l2irq); |
@@ -336,10 +336,10 @@ static void mpc52xx_sdma_ack(unsigned int virq) | |||
336 | 336 | ||
337 | static struct irq_chip mpc52xx_sdma_irqchip = { | 337 | static struct irq_chip mpc52xx_sdma_irqchip = { |
338 | .name = "MPC52xx SDMA", | 338 | .name = "MPC52xx SDMA", |
339 | .mask = mpc52xx_sdma_mask, | 339 | .irq_mask = mpc52xx_sdma_mask, |
340 | .unmask = mpc52xx_sdma_unmask, | 340 | .irq_unmask = mpc52xx_sdma_unmask, |
341 | .ack = mpc52xx_sdma_ack, | 341 | .irq_ack = mpc52xx_sdma_ack, |
342 | .set_type = mpc52xx_null_set_type, | 342 | .irq_set_type = mpc52xx_null_set_type, |
343 | }; | 343 | }; |
344 | 344 | ||
345 | /** | 345 | /** |
diff --git a/arch/powerpc/platforms/82xx/Makefile b/arch/powerpc/platforms/82xx/Makefile index d982793f4dbd..455fe21e37c4 100644 --- a/arch/powerpc/platforms/82xx/Makefile +++ b/arch/powerpc/platforms/82xx/Makefile | |||
@@ -6,4 +6,4 @@ obj-$(CONFIG_CPM2) += pq2.o | |||
6 | obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o | 6 | obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o |
7 | obj-$(CONFIG_PQ2FADS) += pq2fads.o | 7 | obj-$(CONFIG_PQ2FADS) += pq2fads.o |
8 | obj-$(CONFIG_EP8248E) += ep8248e.o | 8 | obj-$(CONFIG_EP8248E) += ep8248e.o |
9 | obj-$(CONFIG_MGCOGE) += mgcoge.o | 9 | obj-$(CONFIG_MGCOGE) += km82xx.o |
diff --git a/arch/powerpc/platforms/82xx/mgcoge.c b/arch/powerpc/platforms/82xx/km82xx.c index 7a5de9eb3c73..428c5e0a0e75 100644 --- a/arch/powerpc/platforms/82xx/mgcoge.c +++ b/arch/powerpc/platforms/82xx/km82xx.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Keymile mgcoge support | 2 | * Keymile km82xx support |
3 | * Copyright 2008 DENX Software Engineering GmbH | 3 | * Copyright 2008-2011 DENX Software Engineering GmbH |
4 | * Author: Heiko Schocher <hs@denx.de> | 4 | * Author: Heiko Schocher <hs@denx.de> |
5 | * | 5 | * |
6 | * based on code from: | 6 | * based on code from: |
@@ -31,9 +31,10 @@ | |||
31 | 31 | ||
32 | #include "pq2.h" | 32 | #include "pq2.h" |
33 | 33 | ||
34 | static void __init mgcoge_pic_init(void) | 34 | static void __init km82xx_pic_init(void) |
35 | { | 35 | { |
36 | struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); | 36 | struct device_node *np = of_find_compatible_node(NULL, NULL, |
37 | "fsl,pq2-pic"); | ||
37 | if (!np) { | 38 | if (!np) { |
38 | printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); | 39 | printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); |
39 | return; | 40 | return; |
@@ -47,12 +48,18 @@ struct cpm_pin { | |||
47 | int port, pin, flags; | 48 | int port, pin, flags; |
48 | }; | 49 | }; |
49 | 50 | ||
50 | static __initdata struct cpm_pin mgcoge_pins[] = { | 51 | static __initdata struct cpm_pin km82xx_pins[] = { |
51 | 52 | ||
52 | /* SMC2 */ | 53 | /* SMC2 */ |
53 | {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | 54 | {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
54 | {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, | 55 | {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
55 | 56 | ||
57 | /* SCC1 */ | ||
58 | {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | ||
59 | {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | ||
60 | {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | ||
61 | {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, | ||
62 | |||
56 | /* SCC4 */ | 63 | /* SCC4 */ |
57 | {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | 64 | {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
58 | {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, | 65 | {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
@@ -107,30 +114,49 @@ static __initdata struct cpm_pin mgcoge_pins[] = { | |||
107 | {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, | 114 | {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, |
108 | {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, | 115 | {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, |
109 | #endif | 116 | #endif |
117 | |||
118 | /* USB */ | ||
119 | {0, 10, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /* FULL_SPEED */ | ||
120 | {0, 11, CPM_PIN_OUTPUT | CPM_PIN_GPIO}, /*/SLAVE */ | ||
121 | {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXN */ | ||
122 | {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXP */ | ||
123 | {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* /OE */ | ||
124 | {2, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXCLK */ | ||
125 | {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */ | ||
126 | {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */ | ||
127 | {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* RXD */ | ||
110 | }; | 128 | }; |
111 | 129 | ||
112 | static void __init init_ioports(void) | 130 | static void __init init_ioports(void) |
113 | { | 131 | { |
114 | int i; | 132 | int i; |
115 | 133 | ||
116 | for (i = 0; i < ARRAY_SIZE(mgcoge_pins); i++) { | 134 | for (i = 0; i < ARRAY_SIZE(km82xx_pins); i++) { |
117 | const struct cpm_pin *pin = &mgcoge_pins[i]; | 135 | const struct cpm_pin *pin = &km82xx_pins[i]; |
118 | cpm2_set_pin(pin->port, pin->pin, pin->flags); | 136 | cpm2_set_pin(pin->port, pin->pin, pin->flags); |
119 | } | 137 | } |
120 | 138 | ||
121 | cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8); | 139 | cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8); |
140 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_RX); | ||
141 | cpm2_clk_setup(CPM_CLK_SCC1, CPM_CLK11, CPM_CLK_TX); | ||
142 | cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RTX); | ||
122 | cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX); | 143 | cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX); |
123 | cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX); | 144 | cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX); |
124 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX); | 145 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX); |
125 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_TX); | 146 | cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_TX); |
126 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); | 147 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); |
127 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); | 148 | cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); |
149 | |||
150 | /* Force USB FULL SPEED bit to '1' */ | ||
151 | setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); | ||
152 | /* clear USB_SLAVE */ | ||
153 | clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); | ||
128 | } | 154 | } |
129 | 155 | ||
130 | static void __init mgcoge_setup_arch(void) | 156 | static void __init km82xx_setup_arch(void) |
131 | { | 157 | { |
132 | if (ppc_md.progress) | 158 | if (ppc_md.progress) |
133 | ppc_md.progress("mgcoge_setup_arch()", 0); | 159 | ppc_md.progress("km82xx_setup_arch()", 0); |
134 | 160 | ||
135 | cpm2_reset(); | 161 | cpm2_reset(); |
136 | 162 | ||
@@ -142,7 +168,7 @@ static void __init mgcoge_setup_arch(void) | |||
142 | init_ioports(); | 168 | init_ioports(); |
143 | 169 | ||
144 | if (ppc_md.progress) | 170 | if (ppc_md.progress) |
145 | ppc_md.progress("mgcoge_setup_arch(), finish", 0); | 171 | ppc_md.progress("km82xx_setup_arch(), finish", 0); |
146 | } | 172 | } |
147 | 173 | ||
148 | static __initdata struct of_device_id of_bus_ids[] = { | 174 | static __initdata struct of_device_id of_bus_ids[] = { |
@@ -156,23 +182,23 @@ static int __init declare_of_platform_devices(void) | |||
156 | 182 | ||
157 | return 0; | 183 | return 0; |
158 | } | 184 | } |
159 | machine_device_initcall(mgcoge, declare_of_platform_devices); | 185 | machine_device_initcall(km82xx, declare_of_platform_devices); |
160 | 186 | ||
161 | /* | 187 | /* |
162 | * Called very early, device-tree isn't unflattened | 188 | * Called very early, device-tree isn't unflattened |
163 | */ | 189 | */ |
164 | static int __init mgcoge_probe(void) | 190 | static int __init km82xx_probe(void) |
165 | { | 191 | { |
166 | unsigned long root = of_get_flat_dt_root(); | 192 | unsigned long root = of_get_flat_dt_root(); |
167 | return of_flat_dt_is_compatible(root, "keymile,mgcoge"); | 193 | return of_flat_dt_is_compatible(root, "keymile,km82xx"); |
168 | } | 194 | } |
169 | 195 | ||
170 | define_machine(mgcoge) | 196 | define_machine(km82xx) |
171 | { | 197 | { |
172 | .name = "Keymile MGCOGE", | 198 | .name = "Keymile km82xx", |
173 | .probe = mgcoge_probe, | 199 | .probe = km82xx_probe, |
174 | .setup_arch = mgcoge_setup_arch, | 200 | .setup_arch = km82xx_setup_arch, |
175 | .init_IRQ = mgcoge_pic_init, | 201 | .init_IRQ = km82xx_pic_init, |
176 | .get_irq = cpm2_get_irq, | 202 | .get_irq = cpm2_get_irq, |
177 | .calibrate_decr = generic_calibrate_decr, | 203 | .calibrate_decr = generic_calibrate_decr, |
178 | .restart = pq2_restart, | 204 | .restart = pq2_restart, |
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 5a55d87d6bd6..926dfdaaf57a 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | |||
@@ -39,10 +39,10 @@ struct pq2ads_pci_pic { | |||
39 | 39 | ||
40 | #define NUM_IRQS 32 | 40 | #define NUM_IRQS 32 |
41 | 41 | ||
42 | static void pq2ads_pci_mask_irq(unsigned int virq) | 42 | static void pq2ads_pci_mask_irq(struct irq_data *d) |
43 | { | 43 | { |
44 | struct pq2ads_pci_pic *priv = get_irq_chip_data(virq); | 44 | struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d); |
45 | int irq = NUM_IRQS - virq_to_hw(virq) - 1; | 45 | int irq = NUM_IRQS - virq_to_hw(d->irq) - 1; |
46 | 46 | ||
47 | if (irq != -1) { | 47 | if (irq != -1) { |
48 | unsigned long flags; | 48 | unsigned long flags; |
@@ -55,10 +55,10 @@ static void pq2ads_pci_mask_irq(unsigned int virq) | |||
55 | } | 55 | } |
56 | } | 56 | } |
57 | 57 | ||
58 | static void pq2ads_pci_unmask_irq(unsigned int virq) | 58 | static void pq2ads_pci_unmask_irq(struct irq_data *d) |
59 | { | 59 | { |
60 | struct pq2ads_pci_pic *priv = get_irq_chip_data(virq); | 60 | struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d); |
61 | int irq = NUM_IRQS - virq_to_hw(virq) - 1; | 61 | int irq = NUM_IRQS - virq_to_hw(d->irq) - 1; |
62 | 62 | ||
63 | if (irq != -1) { | 63 | if (irq != -1) { |
64 | unsigned long flags; | 64 | unsigned long flags; |
@@ -71,18 +71,17 @@ static void pq2ads_pci_unmask_irq(unsigned int virq) | |||
71 | 71 | ||
72 | static struct irq_chip pq2ads_pci_ic = { | 72 | static struct irq_chip pq2ads_pci_ic = { |
73 | .name = "PQ2 ADS PCI", | 73 | .name = "PQ2 ADS PCI", |
74 | .end = pq2ads_pci_unmask_irq, | 74 | .irq_mask = pq2ads_pci_mask_irq, |
75 | .mask = pq2ads_pci_mask_irq, | 75 | .irq_mask_ack = pq2ads_pci_mask_irq, |
76 | .mask_ack = pq2ads_pci_mask_irq, | 76 | .irq_ack = pq2ads_pci_mask_irq, |
77 | .ack = pq2ads_pci_mask_irq, | 77 | .irq_unmask = pq2ads_pci_unmask_irq, |
78 | .unmask = pq2ads_pci_unmask_irq, | 78 | .irq_enable = pq2ads_pci_unmask_irq, |
79 | .enable = pq2ads_pci_unmask_irq, | 79 | .irq_disable = pq2ads_pci_mask_irq |
80 | .disable = pq2ads_pci_mask_irq | ||
81 | }; | 80 | }; |
82 | 81 | ||
83 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) | 82 | static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc) |
84 | { | 83 | { |
85 | struct pq2ads_pci_pic *priv = desc->handler_data; | 84 | struct pq2ads_pci_pic *priv = get_irq_desc_data(desc); |
86 | u32 stat, mask, pend; | 85 | u32 stat, mask, pend; |
87 | int bit; | 86 | int bit; |
88 | 87 | ||
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile index 6e8bbbbcfdf8..ed95bfcbcbff 100644 --- a/arch/powerpc/platforms/83xx/Makefile +++ b/arch/powerpc/platforms/83xx/Makefile | |||
@@ -16,4 +16,4 @@ obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o | |||
16 | obj-$(CONFIG_SBC834x) += sbc834x.o | 16 | obj-$(CONFIG_SBC834x) += sbc834x.o |
17 | obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o | 17 | obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o |
18 | obj-$(CONFIG_ASP834x) += asp834x.o | 18 | obj-$(CONFIG_ASP834x) += asp834x.o |
19 | obj-$(CONFIG_KMETER1) += kmeter1.o | 19 | obj-$(CONFIG_KMETER1) += km83xx.o |
diff --git a/arch/powerpc/platforms/83xx/kmeter1.c b/arch/powerpc/platforms/83xx/km83xx.c index 903acfd851ac..a2b9b9ef1240 100644 --- a/arch/powerpc/platforms/83xx/kmeter1.c +++ b/arch/powerpc/platforms/83xx/km83xx.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2008 DENX Software Engineering GmbH | 2 | * Copyright 2008-2011 DENX Software Engineering GmbH |
3 | * Author: Heiko Schocher <hs@denx.de> | 3 | * Author: Heiko Schocher <hs@denx.de> |
4 | * | 4 | * |
5 | * Description: | 5 | * Description: |
@@ -49,12 +49,12 @@ | |||
49 | * Setup the architecture | 49 | * Setup the architecture |
50 | * | 50 | * |
51 | */ | 51 | */ |
52 | static void __init kmeter1_setup_arch(void) | 52 | static void __init mpc83xx_km_setup_arch(void) |
53 | { | 53 | { |
54 | struct device_node *np; | 54 | struct device_node *np; |
55 | 55 | ||
56 | if (ppc_md.progress) | 56 | if (ppc_md.progress) |
57 | ppc_md.progress("kmeter1_setup_arch()", 0); | 57 | ppc_md.progress("kmpbec83xx_setup_arch()", 0); |
58 | 58 | ||
59 | #ifdef CONFIG_PCI | 59 | #ifdef CONFIG_PCI |
60 | for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") | 60 | for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") |
@@ -69,6 +69,9 @@ static void __init kmeter1_setup_arch(void) | |||
69 | par_io_init(np); | 69 | par_io_init(np); |
70 | of_node_put(np); | 70 | of_node_put(np); |
71 | 71 | ||
72 | for_each_node_by_name(np, "spi") | ||
73 | par_io_of_config(np); | ||
74 | |||
72 | for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) | 75 | for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;) |
73 | par_io_of_config(np); | 76 | par_io_of_config(np); |
74 | } | 77 | } |
@@ -119,7 +122,7 @@ static void __init kmeter1_setup_arch(void) | |||
119 | #endif /* CONFIG_QUICC_ENGINE */ | 122 | #endif /* CONFIG_QUICC_ENGINE */ |
120 | } | 123 | } |
121 | 124 | ||
122 | static struct of_device_id kmeter_ids[] = { | 125 | static struct of_device_id kmpbec83xx_ids[] = { |
123 | { .type = "soc", }, | 126 | { .type = "soc", }, |
124 | { .compatible = "soc", }, | 127 | { .compatible = "soc", }, |
125 | { .compatible = "simple-bus", }, | 128 | { .compatible = "simple-bus", }, |
@@ -131,13 +134,13 @@ static struct of_device_id kmeter_ids[] = { | |||
131 | static int __init kmeter_declare_of_platform_devices(void) | 134 | static int __init kmeter_declare_of_platform_devices(void) |
132 | { | 135 | { |
133 | /* Publish the QE devices */ | 136 | /* Publish the QE devices */ |
134 | of_platform_bus_probe(NULL, kmeter_ids, NULL); | 137 | of_platform_bus_probe(NULL, kmpbec83xx_ids, NULL); |
135 | 138 | ||
136 | return 0; | 139 | return 0; |
137 | } | 140 | } |
138 | machine_device_initcall(kmeter1, kmeter_declare_of_platform_devices); | 141 | machine_device_initcall(mpc83xx_km, kmeter_declare_of_platform_devices); |
139 | 142 | ||
140 | static void __init kmeter1_init_IRQ(void) | 143 | static void __init mpc83xx_km_init_IRQ(void) |
141 | { | 144 | { |
142 | struct device_node *np; | 145 | struct device_node *np; |
143 | 146 | ||
@@ -168,21 +171,34 @@ static void __init kmeter1_init_IRQ(void) | |||
168 | #endif /* CONFIG_QUICC_ENGINE */ | 171 | #endif /* CONFIG_QUICC_ENGINE */ |
169 | } | 172 | } |
170 | 173 | ||
174 | /* list of the supported boards */ | ||
175 | static char *board[] __initdata = { | ||
176 | "Keymile,KMETER1", | ||
177 | "Keymile,kmpbec8321", | ||
178 | NULL | ||
179 | }; | ||
180 | |||
171 | /* | 181 | /* |
172 | * Called very early, MMU is off, device-tree isn't unflattened | 182 | * Called very early, MMU is off, device-tree isn't unflattened |
173 | */ | 183 | */ |
174 | static int __init kmeter1_probe(void) | 184 | static int __init mpc83xx_km_probe(void) |
175 | { | 185 | { |
176 | unsigned long root = of_get_flat_dt_root(); | 186 | unsigned long node = of_get_flat_dt_root(); |
187 | int i = 0; | ||
177 | 188 | ||
178 | return of_flat_dt_is_compatible(root, "keymile,KMETER1"); | 189 | while (board[i]) { |
190 | if (of_flat_dt_is_compatible(node, board[i])) | ||
191 | break; | ||
192 | i++; | ||
193 | } | ||
194 | return (board[i] != NULL); | ||
179 | } | 195 | } |
180 | 196 | ||
181 | define_machine(kmeter1) { | 197 | define_machine(mpc83xx_km) { |
182 | .name = "KMETER1", | 198 | .name = "mpc83xx-km-platform", |
183 | .probe = kmeter1_probe, | 199 | .probe = mpc83xx_km_probe, |
184 | .setup_arch = kmeter1_setup_arch, | 200 | .setup_arch = mpc83xx_km_setup_arch, |
185 | .init_IRQ = kmeter1_init_IRQ, | 201 | .init_IRQ = mpc83xx_km_init_IRQ, |
186 | .get_irq = ipic_get_irq, | 202 | .get_irq = ipic_get_irq, |
187 | .restart = mpc83xx_restart, | 203 | .restart = mpc83xx_restart, |
188 | .time_init = mpc83xx_time_init, | 204 | .time_init = mpc83xx_time_init, |
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c index f4d36b5a2e00..64447e48f3d5 100644 --- a/arch/powerpc/platforms/85xx/ksi8560.c +++ b/arch/powerpc/platforms/85xx/ksi8560.c | |||
@@ -56,12 +56,13 @@ static void machine_restart(char *cmd) | |||
56 | 56 | ||
57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 57 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
58 | { | 58 | { |
59 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
59 | int cascade_irq; | 60 | int cascade_irq; |
60 | 61 | ||
61 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 62 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
62 | generic_handle_irq(cascade_irq); | 63 | generic_handle_irq(cascade_irq); |
63 | 64 | ||
64 | desc->chip->eoi(irq); | 65 | chip->irq_eoi(&desc->irq_data); |
65 | } | 66 | } |
66 | 67 | ||
67 | static void __init ksi8560_pic_init(void) | 68 | static void __init ksi8560_pic_init(void) |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c index 9438a892afc4..1352d1107bfd 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c | |||
@@ -50,12 +50,13 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, | |||
50 | 50 | ||
51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 51 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
52 | { | 52 | { |
53 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
53 | int cascade_irq; | 54 | int cascade_irq; |
54 | 55 | ||
55 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 56 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
56 | generic_handle_irq(cascade_irq); | 57 | generic_handle_irq(cascade_irq); |
57 | 58 | ||
58 | desc->chip->eoi(irq); | 59 | chip->irq_eoi(&desc->irq_data); |
59 | } | 60 | } |
60 | 61 | ||
61 | #endif /* CONFIG_CPM2 */ | 62 | #endif /* CONFIG_CPM2 */ |
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c index 8190bc25bf27..793ead7993ab 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c | |||
@@ -47,12 +47,13 @@ | |||
47 | #ifdef CONFIG_PPC_I8259 | 47 | #ifdef CONFIG_PPC_I8259 |
48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 48 | static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
49 | { | 49 | { |
50 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
50 | unsigned int cascade_irq = i8259_irq(); | 51 | unsigned int cascade_irq = i8259_irq(); |
51 | 52 | ||
52 | if (cascade_irq != NO_IRQ) { | 53 | if (cascade_irq != NO_IRQ) { |
53 | generic_handle_irq(cascade_irq); | 54 | generic_handle_irq(cascade_irq); |
54 | } | 55 | } |
55 | desc->chip->eoi(irq); | 56 | chip->irq_eoi(&desc->irq_data); |
56 | } | 57 | } |
57 | #endif /* CONFIG_PPC_I8259 */ | 58 | #endif /* CONFIG_PPC_I8259 */ |
58 | 59 | ||
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c index a5ad1c7794bf..d7e28ec3e072 100644 --- a/arch/powerpc/platforms/85xx/sbc8560.c +++ b/arch/powerpc/platforms/85xx/sbc8560.c | |||
@@ -41,12 +41,13 @@ | |||
41 | 41 | ||
42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 42 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
43 | { | 43 | { |
44 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
44 | int cascade_irq; | 45 | int cascade_irq; |
45 | 46 | ||
46 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 47 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
47 | generic_handle_irq(cascade_irq); | 48 | generic_handle_irq(cascade_irq); |
48 | 49 | ||
49 | desc->chip->eoi(irq); | 50 | chip->irq_eoi(&desc->irq_data); |
50 | } | 51 | } |
51 | 52 | ||
52 | #endif /* CONFIG_CPM2 */ | 53 | #endif /* CONFIG_CPM2 */ |
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 5c91a992f02b..0d00ff9d05a0 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c | |||
@@ -91,10 +91,14 @@ smp_85xx_kick_cpu(int nr) | |||
91 | while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) | 91 | while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) |
92 | mdelay(1); | 92 | mdelay(1); |
93 | #else | 93 | #else |
94 | smp_generic_kick_cpu(nr); | ||
95 | |||
94 | out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER), | 96 | out_be64((u64 *)(bptr_vaddr + BOOT_ENTRY_ADDR_UPPER), |
95 | __pa((u64)*((unsigned long long *) generic_secondary_smp_init))); | 97 | __pa((u64)*((unsigned long long *) generic_secondary_smp_init))); |
96 | 98 | ||
97 | smp_generic_kick_cpu(nr); | 99 | if (!ioremappable) |
100 | flush_dcache_range((ulong)bptr_vaddr, | ||
101 | (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); | ||
98 | #endif | 102 | #endif |
99 | 103 | ||
100 | local_irq_restore(flags); | 104 | local_irq_restore(flags); |
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c index d48527ffc425..79d85aca4767 100644 --- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c +++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c | |||
@@ -93,6 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq) | |||
93 | 93 | ||
94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) | 94 | void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
96 | unsigned int cascade_irq; | 97 | unsigned int cascade_irq; |
97 | 98 | ||
98 | /* | 99 | /* |
@@ -103,17 +104,16 @@ void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc) | |||
103 | 104 | ||
104 | if (cascade_irq != NO_IRQ) | 105 | if (cascade_irq != NO_IRQ) |
105 | generic_handle_irq(cascade_irq); | 106 | generic_handle_irq(cascade_irq); |
106 | desc->chip->eoi(irq); | 107 | chip->irq_eoi(&desc->irq_data); |
107 | |||
108 | } | 108 | } |
109 | 109 | ||
110 | static void socrates_fpga_pic_ack(unsigned int virq) | 110 | static void socrates_fpga_pic_ack(struct irq_data *d) |
111 | { | 111 | { |
112 | unsigned long flags; | 112 | unsigned long flags; |
113 | unsigned int hwirq, irq_line; | 113 | unsigned int hwirq, irq_line; |
114 | uint32_t mask; | 114 | uint32_t mask; |
115 | 115 | ||
116 | hwirq = socrates_fpga_irq_to_hw(virq); | 116 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
117 | 117 | ||
118 | irq_line = fpga_irqs[hwirq].irq_line; | 118 | irq_line = fpga_irqs[hwirq].irq_line; |
119 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); | 119 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); |
@@ -124,14 +124,14 @@ static void socrates_fpga_pic_ack(unsigned int virq) | |||
124 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); | 124 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); |
125 | } | 125 | } |
126 | 126 | ||
127 | static void socrates_fpga_pic_mask(unsigned int virq) | 127 | static void socrates_fpga_pic_mask(struct irq_data *d) |
128 | { | 128 | { |
129 | unsigned long flags; | 129 | unsigned long flags; |
130 | unsigned int hwirq; | 130 | unsigned int hwirq; |
131 | int irq_line; | 131 | int irq_line; |
132 | u32 mask; | 132 | u32 mask; |
133 | 133 | ||
134 | hwirq = socrates_fpga_irq_to_hw(virq); | 134 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
135 | 135 | ||
136 | irq_line = fpga_irqs[hwirq].irq_line; | 136 | irq_line = fpga_irqs[hwirq].irq_line; |
137 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); | 137 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); |
@@ -142,14 +142,14 @@ static void socrates_fpga_pic_mask(unsigned int virq) | |||
142 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); | 142 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); |
143 | } | 143 | } |
144 | 144 | ||
145 | static void socrates_fpga_pic_mask_ack(unsigned int virq) | 145 | static void socrates_fpga_pic_mask_ack(struct irq_data *d) |
146 | { | 146 | { |
147 | unsigned long flags; | 147 | unsigned long flags; |
148 | unsigned int hwirq; | 148 | unsigned int hwirq; |
149 | int irq_line; | 149 | int irq_line; |
150 | u32 mask; | 150 | u32 mask; |
151 | 151 | ||
152 | hwirq = socrates_fpga_irq_to_hw(virq); | 152 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
153 | 153 | ||
154 | irq_line = fpga_irqs[hwirq].irq_line; | 154 | irq_line = fpga_irqs[hwirq].irq_line; |
155 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); | 155 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); |
@@ -161,14 +161,14 @@ static void socrates_fpga_pic_mask_ack(unsigned int virq) | |||
161 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); | 161 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); |
162 | } | 162 | } |
163 | 163 | ||
164 | static void socrates_fpga_pic_unmask(unsigned int virq) | 164 | static void socrates_fpga_pic_unmask(struct irq_data *d) |
165 | { | 165 | { |
166 | unsigned long flags; | 166 | unsigned long flags; |
167 | unsigned int hwirq; | 167 | unsigned int hwirq; |
168 | int irq_line; | 168 | int irq_line; |
169 | u32 mask; | 169 | u32 mask; |
170 | 170 | ||
171 | hwirq = socrates_fpga_irq_to_hw(virq); | 171 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
172 | 172 | ||
173 | irq_line = fpga_irqs[hwirq].irq_line; | 173 | irq_line = fpga_irqs[hwirq].irq_line; |
174 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); | 174 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); |
@@ -179,14 +179,14 @@ static void socrates_fpga_pic_unmask(unsigned int virq) | |||
179 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); | 179 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); |
180 | } | 180 | } |
181 | 181 | ||
182 | static void socrates_fpga_pic_eoi(unsigned int virq) | 182 | static void socrates_fpga_pic_eoi(struct irq_data *d) |
183 | { | 183 | { |
184 | unsigned long flags; | 184 | unsigned long flags; |
185 | unsigned int hwirq; | 185 | unsigned int hwirq; |
186 | int irq_line; | 186 | int irq_line; |
187 | u32 mask; | 187 | u32 mask; |
188 | 188 | ||
189 | hwirq = socrates_fpga_irq_to_hw(virq); | 189 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
190 | 190 | ||
191 | irq_line = fpga_irqs[hwirq].irq_line; | 191 | irq_line = fpga_irqs[hwirq].irq_line; |
192 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); | 192 | raw_spin_lock_irqsave(&socrates_fpga_pic_lock, flags); |
@@ -197,7 +197,7 @@ static void socrates_fpga_pic_eoi(unsigned int virq) | |||
197 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); | 197 | raw_spin_unlock_irqrestore(&socrates_fpga_pic_lock, flags); |
198 | } | 198 | } |
199 | 199 | ||
200 | static int socrates_fpga_pic_set_type(unsigned int virq, | 200 | static int socrates_fpga_pic_set_type(struct irq_data *d, |
201 | unsigned int flow_type) | 201 | unsigned int flow_type) |
202 | { | 202 | { |
203 | unsigned long flags; | 203 | unsigned long flags; |
@@ -205,7 +205,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq, | |||
205 | int polarity; | 205 | int polarity; |
206 | u32 mask; | 206 | u32 mask; |
207 | 207 | ||
208 | hwirq = socrates_fpga_irq_to_hw(virq); | 208 | hwirq = socrates_fpga_irq_to_hw(d->irq); |
209 | 209 | ||
210 | if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE) | 210 | if (fpga_irqs[hwirq].type != IRQ_TYPE_NONE) |
211 | return -EINVAL; | 211 | return -EINVAL; |
@@ -233,12 +233,12 @@ static int socrates_fpga_pic_set_type(unsigned int virq, | |||
233 | 233 | ||
234 | static struct irq_chip socrates_fpga_pic_chip = { | 234 | static struct irq_chip socrates_fpga_pic_chip = { |
235 | .name = "FPGA-PIC", | 235 | .name = "FPGA-PIC", |
236 | .ack = socrates_fpga_pic_ack, | 236 | .irq_ack = socrates_fpga_pic_ack, |
237 | .mask = socrates_fpga_pic_mask, | 237 | .irq_mask = socrates_fpga_pic_mask, |
238 | .mask_ack = socrates_fpga_pic_mask_ack, | 238 | .irq_mask_ack = socrates_fpga_pic_mask_ack, |
239 | .unmask = socrates_fpga_pic_unmask, | 239 | .irq_unmask = socrates_fpga_pic_unmask, |
240 | .eoi = socrates_fpga_pic_eoi, | 240 | .irq_eoi = socrates_fpga_pic_eoi, |
241 | .set_type = socrates_fpga_pic_set_type, | 241 | .irq_set_type = socrates_fpga_pic_set_type, |
242 | }; | 242 | }; |
243 | 243 | ||
244 | static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, | 244 | static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq, |
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c index bc33d1859ae7..2b62b064eac7 100644 --- a/arch/powerpc/platforms/85xx/stx_gp3.c +++ b/arch/powerpc/platforms/85xx/stx_gp3.c | |||
@@ -46,12 +46,13 @@ | |||
46 | 46 | ||
47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 47 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
48 | { | 48 | { |
49 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
49 | int cascade_irq; | 50 | int cascade_irq; |
50 | 51 | ||
51 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 52 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
52 | generic_handle_irq(cascade_irq); | 53 | generic_handle_irq(cascade_irq); |
53 | 54 | ||
54 | desc->chip->eoi(irq); | 55 | chip->irq_eoi(&desc->irq_data); |
55 | } | 56 | } |
56 | #endif /* CONFIG_CPM2 */ | 57 | #endif /* CONFIG_CPM2 */ |
57 | 58 | ||
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c index 5e847d0b47c8..2265b68e3279 100644 --- a/arch/powerpc/platforms/85xx/tqm85xx.c +++ b/arch/powerpc/platforms/85xx/tqm85xx.c | |||
@@ -44,12 +44,13 @@ | |||
44 | 44 | ||
45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) | 45 | static void cpm2_cascade(unsigned int irq, struct irq_desc *desc) |
46 | { | 46 | { |
47 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
47 | int cascade_irq; | 48 | int cascade_irq; |
48 | 49 | ||
49 | while ((cascade_irq = cpm2_get_irq()) >= 0) | 50 | while ((cascade_irq = cpm2_get_irq()) >= 0) |
50 | generic_handle_irq(cascade_irq); | 51 | generic_handle_irq(cascade_irq); |
51 | 52 | ||
52 | desc->chip->eoi(irq); | 53 | chip->irq_eoi(&desc->irq_data); |
53 | } | 54 | } |
54 | #endif /* CONFIG_CPM2 */ | 55 | #endif /* CONFIG_CPM2 */ |
55 | 56 | ||
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c index 6df9e2561c06..0adfe3b740cd 100644 --- a/arch/powerpc/platforms/86xx/gef_pic.c +++ b/arch/powerpc/platforms/86xx/gef_pic.c | |||
@@ -95,6 +95,7 @@ static int gef_pic_cascade_irq; | |||
95 | 95 | ||
96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) | 96 | void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) |
97 | { | 97 | { |
98 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
98 | unsigned int cascade_irq; | 99 | unsigned int cascade_irq; |
99 | 100 | ||
100 | /* | 101 | /* |
@@ -106,17 +107,16 @@ void gef_pic_cascade(unsigned int irq, struct irq_desc *desc) | |||
106 | if (cascade_irq != NO_IRQ) | 107 | if (cascade_irq != NO_IRQ) |
107 | generic_handle_irq(cascade_irq); | 108 | generic_handle_irq(cascade_irq); |
108 | 109 | ||
109 | desc->chip->eoi(irq); | 110 | chip->irq_eoi(&desc->irq_data); |
110 | |||
111 | } | 111 | } |
112 | 112 | ||
113 | static void gef_pic_mask(unsigned int virq) | 113 | static void gef_pic_mask(struct irq_data *d) |
114 | { | 114 | { |
115 | unsigned long flags; | 115 | unsigned long flags; |
116 | unsigned int hwirq; | 116 | unsigned int hwirq; |
117 | u32 mask; | 117 | u32 mask; |
118 | 118 | ||
119 | hwirq = gef_irq_to_hw(virq); | 119 | hwirq = gef_irq_to_hw(d->irq); |
120 | 120 | ||
121 | raw_spin_lock_irqsave(&gef_pic_lock, flags); | 121 | raw_spin_lock_irqsave(&gef_pic_lock, flags); |
122 | mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); | 122 | mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); |
@@ -125,21 +125,21 @@ static void gef_pic_mask(unsigned int virq) | |||
125 | raw_spin_unlock_irqrestore(&gef_pic_lock, flags); | 125 | raw_spin_unlock_irqrestore(&gef_pic_lock, flags); |
126 | } | 126 | } |
127 | 127 | ||
128 | static void gef_pic_mask_ack(unsigned int virq) | 128 | static void gef_pic_mask_ack(struct irq_data *d) |
129 | { | 129 | { |
130 | /* Don't think we actually have to do anything to ack an interrupt, | 130 | /* Don't think we actually have to do anything to ack an interrupt, |
131 | * we just need to clear down the devices interrupt and it will go away | 131 | * we just need to clear down the devices interrupt and it will go away |
132 | */ | 132 | */ |
133 | gef_pic_mask(virq); | 133 | gef_pic_mask(d); |
134 | } | 134 | } |
135 | 135 | ||
136 | static void gef_pic_unmask(unsigned int virq) | 136 | static void gef_pic_unmask(struct irq_data *d) |
137 | { | 137 | { |
138 | unsigned long flags; | 138 | unsigned long flags; |
139 | unsigned int hwirq; | 139 | unsigned int hwirq; |
140 | u32 mask; | 140 | u32 mask; |
141 | 141 | ||
142 | hwirq = gef_irq_to_hw(virq); | 142 | hwirq = gef_irq_to_hw(d->irq); |
143 | 143 | ||
144 | raw_spin_lock_irqsave(&gef_pic_lock, flags); | 144 | raw_spin_lock_irqsave(&gef_pic_lock, flags); |
145 | mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); | 145 | mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0)); |
@@ -150,9 +150,9 @@ static void gef_pic_unmask(unsigned int virq) | |||
150 | 150 | ||
151 | static struct irq_chip gef_pic_chip = { | 151 | static struct irq_chip gef_pic_chip = { |
152 | .name = "gefp", | 152 | .name = "gefp", |
153 | .mask = gef_pic_mask, | 153 | .irq_mask = gef_pic_mask, |
154 | .mask_ack = gef_pic_mask_ack, | 154 | .irq_mask_ack = gef_pic_mask_ack, |
155 | .unmask = gef_pic_unmask, | 155 | .irq_unmask = gef_pic_unmask, |
156 | }; | 156 | }; |
157 | 157 | ||
158 | 158 | ||
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c index 668275d9e668..cbe33639b478 100644 --- a/arch/powerpc/platforms/86xx/pic.c +++ b/arch/powerpc/platforms/86xx/pic.c | |||
@@ -19,10 +19,13 @@ | |||
19 | #ifdef CONFIG_PPC_I8259 | 19 | #ifdef CONFIG_PPC_I8259 |
20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) | 20 | static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc) |
21 | { | 21 | { |
22 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
22 | unsigned int cascade_irq = i8259_irq(); | 23 | unsigned int cascade_irq = i8259_irq(); |
24 | |||
23 | if (cascade_irq != NO_IRQ) | 25 | if (cascade_irq != NO_IRQ) |
24 | generic_handle_irq(cascade_irq); | 26 | generic_handle_irq(cascade_irq); |
25 | desc->chip->eoi(irq); | 27 | |
28 | chip->irq_eoi(&desc->irq_data); | ||
26 | } | 29 | } |
27 | #endif /* CONFIG_PPC_I8259 */ | 30 | #endif /* CONFIG_PPC_I8259 */ |
28 | 31 | ||
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig index dd35ce081cff..ee56a9ea6a79 100644 --- a/arch/powerpc/platforms/8xx/Kconfig +++ b/arch/powerpc/platforms/8xx/Kconfig | |||
@@ -49,12 +49,6 @@ config PPC_ADDER875 | |||
49 | This enables support for the Analogue & Micro Adder 875 | 49 | This enables support for the Analogue & Micro Adder 875 |
50 | board. | 50 | board. |
51 | 51 | ||
52 | config PPC_MGSUVD | ||
53 | bool "MGSUVD" | ||
54 | select CPM1 | ||
55 | help | ||
56 | This enables support for the Keymile MGSUVD board. | ||
57 | |||
58 | config TQM8XX | 52 | config TQM8XX |
59 | bool "TQM8XX" | 53 | bool "TQM8XX" |
60 | select CPM1 | 54 | select CPM1 |
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile index a491fe6b94fc..76a81c3350a8 100644 --- a/arch/powerpc/platforms/8xx/Makefile +++ b/arch/powerpc/platforms/8xx/Makefile | |||
@@ -6,5 +6,4 @@ obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o | |||
6 | obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o | 6 | obj-$(CONFIG_MPC86XADS) += mpc86xads_setup.o |
7 | obj-$(CONFIG_PPC_EP88XC) += ep88xc.o | 7 | obj-$(CONFIG_PPC_EP88XC) += ep88xc.o |
8 | obj-$(CONFIG_PPC_ADDER875) += adder875.o | 8 | obj-$(CONFIG_PPC_ADDER875) += adder875.o |
9 | obj-$(CONFIG_PPC_MGSUVD) += mgsuvd.o | ||
10 | obj-$(CONFIG_TQM8XX) += tqm8xx_setup.o | 9 | obj-$(CONFIG_TQM8XX) += tqm8xx_setup.o |
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index 60168c1f98fe..fabb108e8744 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c | |||
@@ -218,15 +218,20 @@ void mpc8xx_restart(char *cmd) | |||
218 | 218 | ||
219 | static void cpm_cascade(unsigned int irq, struct irq_desc *desc) | 219 | static void cpm_cascade(unsigned int irq, struct irq_desc *desc) |
220 | { | 220 | { |
221 | struct irq_chip *chip; | ||
221 | int cascade_irq; | 222 | int cascade_irq; |
222 | 223 | ||
223 | if ((cascade_irq = cpm_get_irq()) >= 0) { | 224 | if ((cascade_irq = cpm_get_irq()) >= 0) { |
224 | struct irq_desc *cdesc = irq_to_desc(cascade_irq); | 225 | struct irq_desc *cdesc = irq_to_desc(cascade_irq); |
225 | 226 | ||
226 | generic_handle_irq(cascade_irq); | 227 | generic_handle_irq(cascade_irq); |
227 | cdesc->chip->eoi(cascade_irq); | 228 | |
229 | chip = get_irq_desc_chip(cdesc); | ||
230 | chip->irq_eoi(&cdesc->irq_data); | ||
228 | } | 231 | } |
229 | desc->chip->eoi(irq); | 232 | |
233 | chip = get_irq_desc_chip(desc); | ||
234 | chip->irq_eoi(&desc->irq_data); | ||
230 | } | 235 | } |
231 | 236 | ||
232 | /* Initialize the internal interrupt controllers. The number of | 237 | /* Initialize the internal interrupt controllers. The number of |
diff --git a/arch/powerpc/platforms/8xx/mgsuvd.c b/arch/powerpc/platforms/8xx/mgsuvd.c deleted file mode 100644 index ca3cb071772c..000000000000 --- a/arch/powerpc/platforms/8xx/mgsuvd.c +++ /dev/null | |||
@@ -1,92 +0,0 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Platform setup for the Keymile mgsuvd board | ||
4 | * | ||
5 | * Heiko Schocher <hs@denx.de> | ||
6 | * | ||
7 | * Copyright 2008 DENX Software Engineering GmbH | ||
8 | * | ||
9 | * This file is licensed under the terms of the GNU General Public License | ||
10 | * version 2. This program is licensed "as is" without any warranty of any | ||
11 | * kind, whether express or implied. | ||
12 | */ | ||
13 | |||
14 | #include <linux/ioport.h> | ||
15 | #include <linux/of_platform.h> | ||
16 | |||
17 | #include <asm/io.h> | ||
18 | #include <asm/machdep.h> | ||
19 | #include <asm/processor.h> | ||
20 | #include <asm/cpm1.h> | ||
21 | #include <asm/prom.h> | ||
22 | #include <asm/fs_pd.h> | ||
23 | |||
24 | #include "mpc8xx.h" | ||
25 | |||
26 | struct cpm_pin { | ||
27 | int port, pin, flags; | ||
28 | }; | ||
29 | |||
30 | static __initdata struct cpm_pin mgsuvd_pins[] = { | ||
31 | /* SMC1 */ | ||
32 | {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */ | ||
33 | {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */ | ||
34 | |||
35 | /* SCC3 */ | ||
36 | {CPM_PORTA, 10, CPM_PIN_INPUT}, | ||
37 | {CPM_PORTA, 11, CPM_PIN_INPUT}, | ||
38 | {CPM_PORTA, 3, CPM_PIN_INPUT}, | ||
39 | {CPM_PORTA, 2, CPM_PIN_INPUT}, | ||
40 | {CPM_PORTC, 13, CPM_PIN_INPUT}, | ||
41 | }; | ||
42 | |||
43 | static void __init init_ioports(void) | ||
44 | { | ||
45 | int i; | ||
46 | |||
47 | for (i = 0; i < ARRAY_SIZE(mgsuvd_pins); i++) { | ||
48 | struct cpm_pin *pin = &mgsuvd_pins[i]; | ||
49 | cpm1_set_pin(pin->port, pin->pin, pin->flags); | ||
50 | } | ||
51 | |||
52 | setbits16(&mpc8xx_immr->im_ioport.iop_pcso, 0x300); | ||
53 | cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_RX); | ||
54 | cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_TX); | ||
55 | cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); | ||
56 | } | ||
57 | |||
58 | static void __init mgsuvd_setup_arch(void) | ||
59 | { | ||
60 | cpm_reset(); | ||
61 | init_ioports(); | ||
62 | } | ||
63 | |||
64 | static __initdata struct of_device_id of_bus_ids[] = { | ||
65 | { .compatible = "simple-bus" }, | ||
66 | {}, | ||
67 | }; | ||
68 | |||
69 | static int __init declare_of_platform_devices(void) | ||
70 | { | ||
71 | of_platform_bus_probe(NULL, of_bus_ids, NULL); | ||
72 | return 0; | ||
73 | } | ||
74 | machine_device_initcall(mgsuvd, declare_of_platform_devices); | ||
75 | |||
76 | static int __init mgsuvd_probe(void) | ||
77 | { | ||
78 | unsigned long root = of_get_flat_dt_root(); | ||
79 | return of_flat_dt_is_compatible(root, "keymile,mgsuvd"); | ||
80 | } | ||
81 | |||
82 | define_machine(mgsuvd) { | ||
83 | .name = "MGSUVD", | ||
84 | .probe = mgsuvd_probe, | ||
85 | .setup_arch = mgsuvd_setup_arch, | ||
86 | .init_IRQ = mpc8xx_pics_init, | ||
87 | .get_irq = mpc8xx_get_irq, | ||
88 | .restart = mpc8xx_restart, | ||
89 | .calibrate_decr = mpc8xx_calibrate_decr, | ||
90 | .set_rtc_time = mpc8xx_set_rtc_time, | ||
91 | .get_rtc_time = mpc8xx_get_rtc_time, | ||
92 | }; | ||
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index c35099af340e..c48b66a67e42 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
@@ -93,6 +93,7 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) | |||
93 | 93 | ||
94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | 94 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
95 | { | 95 | { |
96 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
96 | struct axon_msic *msic = get_irq_data(irq); | 97 | struct axon_msic *msic = get_irq_data(irq); |
97 | u32 write_offset, msi; | 98 | u32 write_offset, msi; |
98 | int idx; | 99 | int idx; |
@@ -145,7 +146,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
145 | msic->read_offset &= MSIC_FIFO_SIZE_MASK; | 146 | msic->read_offset &= MSIC_FIFO_SIZE_MASK; |
146 | } | 147 | } |
147 | 148 | ||
148 | desc->chip->eoi(irq); | 149 | chip->irq_eoi(&desc->irq_data); |
149 | } | 150 | } |
150 | 151 | ||
151 | static struct axon_msic *find_msi_translator(struct pci_dev *dev) | 152 | static struct axon_msic *find_msi_translator(struct pci_dev *dev) |
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c index 682af97321a8..0b8f7d7135c5 100644 --- a/arch/powerpc/platforms/cell/beat_interrupt.c +++ b/arch/powerpc/platforms/cell/beat_interrupt.c | |||
@@ -61,59 +61,59 @@ static inline void beatic_update_irq_mask(unsigned int irq_plug) | |||
61 | panic("Failed to set mask IRQ!"); | 61 | panic("Failed to set mask IRQ!"); |
62 | } | 62 | } |
63 | 63 | ||
64 | static void beatic_mask_irq(unsigned int irq_plug) | 64 | static void beatic_mask_irq(struct irq_data *d) |
65 | { | 65 | { |
66 | unsigned long flags; | 66 | unsigned long flags; |
67 | 67 | ||
68 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); | 68 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
69 | beatic_irq_mask_enable[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64))); | 69 | beatic_irq_mask_enable[d->irq/64] &= ~(1UL << (63 - (d->irq%64))); |
70 | beatic_update_irq_mask(irq_plug); | 70 | beatic_update_irq_mask(d->irq); |
71 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); | 71 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
72 | } | 72 | } |
73 | 73 | ||
74 | static void beatic_unmask_irq(unsigned int irq_plug) | 74 | static void beatic_unmask_irq(struct irq_data *d) |
75 | { | 75 | { |
76 | unsigned long flags; | 76 | unsigned long flags; |
77 | 77 | ||
78 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); | 78 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
79 | beatic_irq_mask_enable[irq_plug/64] |= 1UL << (63 - (irq_plug%64)); | 79 | beatic_irq_mask_enable[d->irq/64] |= 1UL << (63 - (d->irq%64)); |
80 | beatic_update_irq_mask(irq_plug); | 80 | beatic_update_irq_mask(d->irq); |
81 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); | 81 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
82 | } | 82 | } |
83 | 83 | ||
84 | static void beatic_ack_irq(unsigned int irq_plug) | 84 | static void beatic_ack_irq(struct irq_data *d) |
85 | { | 85 | { |
86 | unsigned long flags; | 86 | unsigned long flags; |
87 | 87 | ||
88 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); | 88 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
89 | beatic_irq_mask_ack[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64))); | 89 | beatic_irq_mask_ack[d->irq/64] &= ~(1UL << (63 - (d->irq%64))); |
90 | beatic_update_irq_mask(irq_plug); | 90 | beatic_update_irq_mask(d->irq); |
91 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); | 91 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
92 | } | 92 | } |
93 | 93 | ||
94 | static void beatic_end_irq(unsigned int irq_plug) | 94 | static void beatic_end_irq(struct irq_data *d) |
95 | { | 95 | { |
96 | s64 err; | 96 | s64 err; |
97 | unsigned long flags; | 97 | unsigned long flags; |
98 | 98 | ||
99 | err = beat_downcount_of_interrupt(irq_plug); | 99 | err = beat_downcount_of_interrupt(d->irq); |
100 | if (err != 0) { | 100 | if (err != 0) { |
101 | if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */ | 101 | if ((err & 0xFFFFFFFF) != 0xFFFFFFF5) /* -11: wrong state */ |
102 | panic("Failed to downcount IRQ! Error = %16llx", err); | 102 | panic("Failed to downcount IRQ! Error = %16llx", err); |
103 | 103 | ||
104 | printk(KERN_ERR "IRQ over-downcounted, plug %d\n", irq_plug); | 104 | printk(KERN_ERR "IRQ over-downcounted, plug %d\n", d->irq); |
105 | } | 105 | } |
106 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); | 106 | raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags); |
107 | beatic_irq_mask_ack[irq_plug/64] |= 1UL << (63 - (irq_plug%64)); | 107 | beatic_irq_mask_ack[d->irq/64] |= 1UL << (63 - (d->irq%64)); |
108 | beatic_update_irq_mask(irq_plug); | 108 | beatic_update_irq_mask(d->irq); |
109 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); | 109 | raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags); |
110 | } | 110 | } |
111 | 111 | ||
112 | static struct irq_chip beatic_pic = { | 112 | static struct irq_chip beatic_pic = { |
113 | .name = "CELL-BEAT", | 113 | .name = "CELL-BEAT", |
114 | .unmask = beatic_unmask_irq, | 114 | .irq_unmask = beatic_unmask_irq, |
115 | .mask = beatic_mask_irq, | 115 | .irq_mask = beatic_mask_irq, |
116 | .eoi = beatic_end_irq, | 116 | .irq_eoi = beatic_end_irq, |
117 | }; | 117 | }; |
118 | 118 | ||
119 | /* | 119 | /* |
@@ -232,7 +232,7 @@ unsigned int beatic_get_irq(void) | |||
232 | 232 | ||
233 | ret = beatic_get_irq_plug(); | 233 | ret = beatic_get_irq_plug(); |
234 | if (ret != NO_IRQ) | 234 | if (ret != NO_IRQ) |
235 | beatic_ack_irq(ret); | 235 | beatic_ack_irq(irq_get_irq_data(ret)); |
236 | return ret; | 236 | return ret; |
237 | } | 237 | } |
238 | 238 | ||
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c index 10eb1a443626..624d26e72f1d 100644 --- a/arch/powerpc/platforms/cell/interrupt.c +++ b/arch/powerpc/platforms/cell/interrupt.c | |||
@@ -72,15 +72,15 @@ static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits) | |||
72 | return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit; | 72 | return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit; |
73 | } | 73 | } |
74 | 74 | ||
75 | static void iic_mask(unsigned int irq) | 75 | static void iic_mask(struct irq_data *d) |
76 | { | 76 | { |
77 | } | 77 | } |
78 | 78 | ||
79 | static void iic_unmask(unsigned int irq) | 79 | static void iic_unmask(struct irq_data *d) |
80 | { | 80 | { |
81 | } | 81 | } |
82 | 82 | ||
83 | static void iic_eoi(unsigned int irq) | 83 | static void iic_eoi(struct irq_data *d) |
84 | { | 84 | { |
85 | struct iic *iic = &__get_cpu_var(cpu_iic); | 85 | struct iic *iic = &__get_cpu_var(cpu_iic); |
86 | out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); | 86 | out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); |
@@ -89,19 +89,21 @@ static void iic_eoi(unsigned int irq) | |||
89 | 89 | ||
90 | static struct irq_chip iic_chip = { | 90 | static struct irq_chip iic_chip = { |
91 | .name = "CELL-IIC", | 91 | .name = "CELL-IIC", |
92 | .mask = iic_mask, | 92 | .irq_mask = iic_mask, |
93 | .unmask = iic_unmask, | 93 | .irq_unmask = iic_unmask, |
94 | .eoi = iic_eoi, | 94 | .irq_eoi = iic_eoi, |
95 | }; | 95 | }; |
96 | 96 | ||
97 | 97 | ||
98 | static void iic_ioexc_eoi(unsigned int irq) | 98 | static void iic_ioexc_eoi(struct irq_data *d) |
99 | { | 99 | { |
100 | } | 100 | } |
101 | 101 | ||
102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) | 102 | static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) |
103 | { | 103 | { |
104 | struct cbe_iic_regs __iomem *node_iic = (void __iomem *)desc->handler_data; | 104 | struct irq_chip *chip = get_irq_desc_chip(desc); |
105 | struct cbe_iic_regs __iomem *node_iic = | ||
106 | (void __iomem *)get_irq_desc_data(desc); | ||
105 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; | 107 | unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; |
106 | unsigned long bits, ack; | 108 | unsigned long bits, ack; |
107 | int cascade; | 109 | int cascade; |
@@ -128,15 +130,15 @@ static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) | |||
128 | if (ack) | 130 | if (ack) |
129 | out_be64(&node_iic->iic_is, ack); | 131 | out_be64(&node_iic->iic_is, ack); |
130 | } | 132 | } |
131 | desc->chip->eoi(irq); | 133 | chip->irq_eoi(&desc->irq_data); |
132 | } | 134 | } |
133 | 135 | ||
134 | 136 | ||
135 | static struct irq_chip iic_ioexc_chip = { | 137 | static struct irq_chip iic_ioexc_chip = { |
136 | .name = "CELL-IOEX", | 138 | .name = "CELL-IOEX", |
137 | .mask = iic_mask, | 139 | .irq_mask = iic_mask, |
138 | .unmask = iic_unmask, | 140 | .irq_unmask = iic_unmask, |
139 | .eoi = iic_ioexc_eoi, | 141 | .irq_eoi = iic_ioexc_eoi, |
140 | }; | 142 | }; |
141 | 143 | ||
142 | /* Get an IRQ number from the pending state register of the IIC */ | 144 | /* Get an IRQ number from the pending state register of the IIC */ |
@@ -237,6 +239,8 @@ extern int noirqdebug; | |||
237 | 239 | ||
238 | static void handle_iic_irq(unsigned int irq, struct irq_desc *desc) | 240 | static void handle_iic_irq(unsigned int irq, struct irq_desc *desc) |
239 | { | 241 | { |
242 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
243 | |||
240 | raw_spin_lock(&desc->lock); | 244 | raw_spin_lock(&desc->lock); |
241 | 245 | ||
242 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | 246 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
@@ -275,7 +279,7 @@ static void handle_iic_irq(unsigned int irq, struct irq_desc *desc) | |||
275 | 279 | ||
276 | desc->status &= ~IRQ_INPROGRESS; | 280 | desc->status &= ~IRQ_INPROGRESS; |
277 | out_eoi: | 281 | out_eoi: |
278 | desc->chip->eoi(irq); | 282 | chip->irq_eoi(&desc->irq_data); |
279 | raw_spin_unlock(&desc->lock); | 283 | raw_spin_unlock(&desc->lock); |
280 | } | 284 | } |
281 | 285 | ||
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index 691995761b3d..6a28d027d959 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c | |||
@@ -187,13 +187,15 @@ machine_subsys_initcall(cell, cell_publish_devices); | |||
187 | 187 | ||
188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) | 188 | static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) |
189 | { | 189 | { |
190 | struct mpic *mpic = desc->handler_data; | 190 | struct irq_chip *chip = get_irq_desc_chip(desc); |
191 | struct mpic *mpic = get_irq_desc_data(desc); | ||
191 | unsigned int virq; | 192 | unsigned int virq; |
192 | 193 | ||
193 | virq = mpic_get_one_irq(mpic); | 194 | virq = mpic_get_one_irq(mpic); |
194 | if (virq != NO_IRQ) | 195 | if (virq != NO_IRQ) |
195 | generic_handle_irq(virq); | 196 | generic_handle_irq(virq); |
196 | desc->chip->eoi(irq); | 197 | |
198 | chip->irq_eoi(&desc->irq_data); | ||
197 | } | 199 | } |
198 | 200 | ||
199 | static void __init mpic_init_IRQ(void) | 201 | static void __init mpic_init_IRQ(void) |
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c index 3f2e557344a3..b38cdfc1deb8 100644 --- a/arch/powerpc/platforms/cell/spider-pic.c +++ b/arch/powerpc/platforms/cell/spider-pic.c | |||
@@ -79,30 +79,30 @@ static void __iomem *spider_get_irq_config(struct spider_pic *pic, | |||
79 | return pic->regs + TIR_CFGA + 8 * src; | 79 | return pic->regs + TIR_CFGA + 8 * src; |
80 | } | 80 | } |
81 | 81 | ||
82 | static void spider_unmask_irq(unsigned int virq) | 82 | static void spider_unmask_irq(struct irq_data *d) |
83 | { | 83 | { |
84 | struct spider_pic *pic = spider_virq_to_pic(virq); | 84 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
85 | void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); | 85 | void __iomem *cfg = spider_get_irq_config(pic, irq_map[d->irq].hwirq); |
86 | 86 | ||
87 | out_be32(cfg, in_be32(cfg) | 0x30000000u); | 87 | out_be32(cfg, in_be32(cfg) | 0x30000000u); |
88 | } | 88 | } |
89 | 89 | ||
90 | static void spider_mask_irq(unsigned int virq) | 90 | static void spider_mask_irq(struct irq_data *d) |
91 | { | 91 | { |
92 | struct spider_pic *pic = spider_virq_to_pic(virq); | 92 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
93 | void __iomem *cfg = spider_get_irq_config(pic, irq_map[virq].hwirq); | 93 | void __iomem *cfg = spider_get_irq_config(pic, irq_map[d->irq].hwirq); |
94 | 94 | ||
95 | out_be32(cfg, in_be32(cfg) & ~0x30000000u); | 95 | out_be32(cfg, in_be32(cfg) & ~0x30000000u); |
96 | } | 96 | } |
97 | 97 | ||
98 | static void spider_ack_irq(unsigned int virq) | 98 | static void spider_ack_irq(struct irq_data *d) |
99 | { | 99 | { |
100 | struct spider_pic *pic = spider_virq_to_pic(virq); | 100 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
101 | unsigned int src = irq_map[virq].hwirq; | 101 | unsigned int src = irq_map[d->irq].hwirq; |
102 | 102 | ||
103 | /* Reset edge detection logic if necessary | 103 | /* Reset edge detection logic if necessary |
104 | */ | 104 | */ |
105 | if (irq_to_desc(virq)->status & IRQ_LEVEL) | 105 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
106 | return; | 106 | return; |
107 | 107 | ||
108 | /* Only interrupts 47 to 50 can be set to edge */ | 108 | /* Only interrupts 47 to 50 can be set to edge */ |
@@ -113,13 +113,13 @@ static void spider_ack_irq(unsigned int virq) | |||
113 | out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); | 113 | out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); |
114 | } | 114 | } |
115 | 115 | ||
116 | static int spider_set_irq_type(unsigned int virq, unsigned int type) | 116 | static int spider_set_irq_type(struct irq_data *d, unsigned int type) |
117 | { | 117 | { |
118 | unsigned int sense = type & IRQ_TYPE_SENSE_MASK; | 118 | unsigned int sense = type & IRQ_TYPE_SENSE_MASK; |
119 | struct spider_pic *pic = spider_virq_to_pic(virq); | 119 | struct spider_pic *pic = spider_virq_to_pic(d->irq); |
120 | unsigned int hw = irq_map[virq].hwirq; | 120 | unsigned int hw = irq_map[d->irq].hwirq; |
121 | void __iomem *cfg = spider_get_irq_config(pic, hw); | 121 | void __iomem *cfg = spider_get_irq_config(pic, hw); |
122 | struct irq_desc *desc = irq_to_desc(virq); | 122 | struct irq_desc *desc = irq_to_desc(d->irq); |
123 | u32 old_mask; | 123 | u32 old_mask; |
124 | u32 ic; | 124 | u32 ic; |
125 | 125 | ||
@@ -169,10 +169,10 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type) | |||
169 | 169 | ||
170 | static struct irq_chip spider_pic = { | 170 | static struct irq_chip spider_pic = { |
171 | .name = "SPIDER", | 171 | .name = "SPIDER", |
172 | .unmask = spider_unmask_irq, | 172 | .irq_unmask = spider_unmask_irq, |
173 | .mask = spider_mask_irq, | 173 | .irq_mask = spider_mask_irq, |
174 | .ack = spider_ack_irq, | 174 | .irq_ack = spider_ack_irq, |
175 | .set_type = spider_set_irq_type, | 175 | .irq_set_type = spider_set_irq_type, |
176 | }; | 176 | }; |
177 | 177 | ||
178 | static int spider_host_map(struct irq_host *h, unsigned int virq, | 178 | static int spider_host_map(struct irq_host *h, unsigned int virq, |
@@ -207,7 +207,8 @@ static struct irq_host_ops spider_host_ops = { | |||
207 | 207 | ||
208 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) | 208 | static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) |
209 | { | 209 | { |
210 | struct spider_pic *pic = desc->handler_data; | 210 | struct irq_chip *chip = get_irq_desc_chip(desc); |
211 | struct spider_pic *pic = get_irq_desc_data(desc); | ||
211 | unsigned int cs, virq; | 212 | unsigned int cs, virq; |
212 | 213 | ||
213 | cs = in_be32(pic->regs + TIR_CS) >> 24; | 214 | cs = in_be32(pic->regs + TIR_CS) >> 24; |
@@ -215,9 +216,11 @@ static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc) | |||
215 | virq = NO_IRQ; | 216 | virq = NO_IRQ; |
216 | else | 217 | else |
217 | virq = irq_linear_revmap(pic->host, cs); | 218 | virq = irq_linear_revmap(pic->host, cs); |
219 | |||
218 | if (virq != NO_IRQ) | 220 | if (virq != NO_IRQ) |
219 | generic_handle_irq(virq); | 221 | generic_handle_irq(virq); |
220 | desc->chip->eoi(irq); | 222 | |
223 | chip->irq_eoi(&desc->irq_data); | ||
221 | } | 224 | } |
222 | 225 | ||
223 | /* For hooking up the cascace we have a problem. Our device-tree is | 226 | /* For hooking up the cascace we have a problem. Our device-tree is |
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c index 8553cc49e0d6..4c1288451a21 100644 --- a/arch/powerpc/platforms/chrp/setup.c +++ b/arch/powerpc/platforms/chrp/setup.c | |||
@@ -365,10 +365,13 @@ void __init chrp_setup_arch(void) | |||
365 | 365 | ||
366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) | 366 | static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) |
367 | { | 367 | { |
368 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
368 | unsigned int cascade_irq = i8259_irq(); | 369 | unsigned int cascade_irq = i8259_irq(); |
370 | |||
369 | if (cascade_irq != NO_IRQ) | 371 | if (cascade_irq != NO_IRQ) |
370 | generic_handle_irq(cascade_irq); | 372 | generic_handle_irq(cascade_irq); |
371 | desc->chip->eoi(irq); | 373 | |
374 | chip->irq_eoi(&desc->irq_data); | ||
372 | } | 375 | } |
373 | 376 | ||
374 | /* | 377 | /* |
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index c278bd3a8fec..0aca0e28a8e5 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c | |||
@@ -46,10 +46,10 @@ | |||
46 | * | 46 | * |
47 | */ | 47 | */ |
48 | 48 | ||
49 | static void flipper_pic_mask_and_ack(unsigned int virq) | 49 | static void flipper_pic_mask_and_ack(struct irq_data *d) |
50 | { | 50 | { |
51 | int irq = virq_to_hw(virq); | 51 | int irq = virq_to_hw(d->irq); |
52 | void __iomem *io_base = get_irq_chip_data(virq); | 52 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
53 | u32 mask = 1 << irq; | 53 | u32 mask = 1 << irq; |
54 | 54 | ||
55 | clrbits32(io_base + FLIPPER_IMR, mask); | 55 | clrbits32(io_base + FLIPPER_IMR, mask); |
@@ -57,27 +57,27 @@ static void flipper_pic_mask_and_ack(unsigned int virq) | |||
57 | out_be32(io_base + FLIPPER_ICR, mask); | 57 | out_be32(io_base + FLIPPER_ICR, mask); |
58 | } | 58 | } |
59 | 59 | ||
60 | static void flipper_pic_ack(unsigned int virq) | 60 | static void flipper_pic_ack(struct irq_data *d) |
61 | { | 61 | { |
62 | int irq = virq_to_hw(virq); | 62 | int irq = virq_to_hw(d->irq); |
63 | void __iomem *io_base = get_irq_chip_data(virq); | 63 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
64 | 64 | ||
65 | /* this is at least needed for RSW */ | 65 | /* this is at least needed for RSW */ |
66 | out_be32(io_base + FLIPPER_ICR, 1 << irq); | 66 | out_be32(io_base + FLIPPER_ICR, 1 << irq); |
67 | } | 67 | } |
68 | 68 | ||
69 | static void flipper_pic_mask(unsigned int virq) | 69 | static void flipper_pic_mask(struct irq_data *d) |
70 | { | 70 | { |
71 | int irq = virq_to_hw(virq); | 71 | int irq = virq_to_hw(d->irq); |
72 | void __iomem *io_base = get_irq_chip_data(virq); | 72 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
73 | 73 | ||
74 | clrbits32(io_base + FLIPPER_IMR, 1 << irq); | 74 | clrbits32(io_base + FLIPPER_IMR, 1 << irq); |
75 | } | 75 | } |
76 | 76 | ||
77 | static void flipper_pic_unmask(unsigned int virq) | 77 | static void flipper_pic_unmask(struct irq_data *d) |
78 | { | 78 | { |
79 | int irq = virq_to_hw(virq); | 79 | int irq = virq_to_hw(d->irq); |
80 | void __iomem *io_base = get_irq_chip_data(virq); | 80 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
81 | 81 | ||
82 | setbits32(io_base + FLIPPER_IMR, 1 << irq); | 82 | setbits32(io_base + FLIPPER_IMR, 1 << irq); |
83 | } | 83 | } |
@@ -85,10 +85,10 @@ static void flipper_pic_unmask(unsigned int virq) | |||
85 | 85 | ||
86 | static struct irq_chip flipper_pic = { | 86 | static struct irq_chip flipper_pic = { |
87 | .name = "flipper-pic", | 87 | .name = "flipper-pic", |
88 | .ack = flipper_pic_ack, | 88 | .irq_ack = flipper_pic_ack, |
89 | .mask_ack = flipper_pic_mask_and_ack, | 89 | .irq_mask_ack = flipper_pic_mask_and_ack, |
90 | .mask = flipper_pic_mask, | 90 | .irq_mask = flipper_pic_mask, |
91 | .unmask = flipper_pic_unmask, | 91 | .irq_unmask = flipper_pic_unmask, |
92 | }; | 92 | }; |
93 | 93 | ||
94 | /* | 94 | /* |
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index a771f91e215b..35e448bd8479 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c | |||
@@ -41,36 +41,36 @@ | |||
41 | * | 41 | * |
42 | */ | 42 | */ |
43 | 43 | ||
44 | static void hlwd_pic_mask_and_ack(unsigned int virq) | 44 | static void hlwd_pic_mask_and_ack(struct irq_data *d) |
45 | { | 45 | { |
46 | int irq = virq_to_hw(virq); | 46 | int irq = virq_to_hw(d->irq); |
47 | void __iomem *io_base = get_irq_chip_data(virq); | 47 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
48 | u32 mask = 1 << irq; | 48 | u32 mask = 1 << irq; |
49 | 49 | ||
50 | clrbits32(io_base + HW_BROADWAY_IMR, mask); | 50 | clrbits32(io_base + HW_BROADWAY_IMR, mask); |
51 | out_be32(io_base + HW_BROADWAY_ICR, mask); | 51 | out_be32(io_base + HW_BROADWAY_ICR, mask); |
52 | } | 52 | } |
53 | 53 | ||
54 | static void hlwd_pic_ack(unsigned int virq) | 54 | static void hlwd_pic_ack(struct irq_data *d) |
55 | { | 55 | { |
56 | int irq = virq_to_hw(virq); | 56 | int irq = virq_to_hw(d->irq); |
57 | void __iomem *io_base = get_irq_chip_data(virq); | 57 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
58 | 58 | ||
59 | out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); | 59 | out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); |
60 | } | 60 | } |
61 | 61 | ||
62 | static void hlwd_pic_mask(unsigned int virq) | 62 | static void hlwd_pic_mask(struct irq_data *d) |
63 | { | 63 | { |
64 | int irq = virq_to_hw(virq); | 64 | int irq = virq_to_hw(d->irq); |
65 | void __iomem *io_base = get_irq_chip_data(virq); | 65 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
66 | 66 | ||
67 | clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); | 67 | clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); |
68 | } | 68 | } |
69 | 69 | ||
70 | static void hlwd_pic_unmask(unsigned int virq) | 70 | static void hlwd_pic_unmask(struct irq_data *d) |
71 | { | 71 | { |
72 | int irq = virq_to_hw(virq); | 72 | int irq = virq_to_hw(d->irq); |
73 | void __iomem *io_base = get_irq_chip_data(virq); | 73 | void __iomem *io_base = irq_data_get_irq_chip_data(d); |
74 | 74 | ||
75 | setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); | 75 | setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); |
76 | } | 76 | } |
@@ -78,10 +78,10 @@ static void hlwd_pic_unmask(unsigned int virq) | |||
78 | 78 | ||
79 | static struct irq_chip hlwd_pic = { | 79 | static struct irq_chip hlwd_pic = { |
80 | .name = "hlwd-pic", | 80 | .name = "hlwd-pic", |
81 | .ack = hlwd_pic_ack, | 81 | .irq_ack = hlwd_pic_ack, |
82 | .mask_ack = hlwd_pic_mask_and_ack, | 82 | .irq_mask_ack = hlwd_pic_mask_and_ack, |
83 | .mask = hlwd_pic_mask, | 83 | .irq_mask = hlwd_pic_mask, |
84 | .unmask = hlwd_pic_unmask, | 84 | .irq_unmask = hlwd_pic_unmask, |
85 | }; | 85 | }; |
86 | 86 | ||
87 | /* | 87 | /* |
@@ -129,11 +129,12 @@ static unsigned int __hlwd_pic_get_irq(struct irq_host *h) | |||
129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | 129 | static void hlwd_pic_irq_cascade(unsigned int cascade_virq, |
130 | struct irq_desc *desc) | 130 | struct irq_desc *desc) |
131 | { | 131 | { |
132 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
132 | struct irq_host *irq_host = get_irq_data(cascade_virq); | 133 | struct irq_host *irq_host = get_irq_data(cascade_virq); |
133 | unsigned int virq; | 134 | unsigned int virq; |
134 | 135 | ||
135 | raw_spin_lock(&desc->lock); | 136 | raw_spin_lock(&desc->lock); |
136 | desc->chip->mask(cascade_virq); /* IRQ_LEVEL */ | 137 | chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */ |
137 | raw_spin_unlock(&desc->lock); | 138 | raw_spin_unlock(&desc->lock); |
138 | 139 | ||
139 | virq = __hlwd_pic_get_irq(irq_host); | 140 | virq = __hlwd_pic_get_irq(irq_host); |
@@ -143,9 +144,9 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq, | |||
143 | pr_err("spurious interrupt!\n"); | 144 | pr_err("spurious interrupt!\n"); |
144 | 145 | ||
145 | raw_spin_lock(&desc->lock); | 146 | raw_spin_lock(&desc->lock); |
146 | desc->chip->ack(cascade_virq); /* IRQ_LEVEL */ | 147 | chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ |
147 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | 148 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) |
148 | desc->chip->unmask(cascade_virq); | 149 | chip->irq_unmask(&desc->irq_data); |
149 | raw_spin_unlock(&desc->lock); | 150 | raw_spin_unlock(&desc->lock); |
150 | } | 151 | } |
151 | 152 | ||
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c index ba446bf355a9..4fb96f0b2df6 100644 --- a/arch/powerpc/platforms/iseries/irq.c +++ b/arch/powerpc/platforms/iseries/irq.c | |||
@@ -167,11 +167,11 @@ static void pci_event_handler(struct HvLpEvent *event) | |||
167 | * This will be called by device drivers (via enable_IRQ) | 167 | * This will be called by device drivers (via enable_IRQ) |
168 | * to enable INTA in the bridge interrupt status register. | 168 | * to enable INTA in the bridge interrupt status register. |
169 | */ | 169 | */ |
170 | static void iseries_enable_IRQ(unsigned int irq) | 170 | static void iseries_enable_IRQ(struct irq_data *d) |
171 | { | 171 | { |
172 | u32 bus, dev_id, function, mask; | 172 | u32 bus, dev_id, function, mask; |
173 | const u32 sub_bus = 0; | 173 | const u32 sub_bus = 0; |
174 | unsigned int rirq = (unsigned int)irq_map[irq].hwirq; | 174 | unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; |
175 | 175 | ||
176 | /* The IRQ has already been locked by the caller */ | 176 | /* The IRQ has already been locked by the caller */ |
177 | bus = REAL_IRQ_TO_BUS(rirq); | 177 | bus = REAL_IRQ_TO_BUS(rirq); |
@@ -184,23 +184,23 @@ static void iseries_enable_IRQ(unsigned int irq) | |||
184 | } | 184 | } |
185 | 185 | ||
186 | /* This is called by iseries_activate_IRQs */ | 186 | /* This is called by iseries_activate_IRQs */ |
187 | static unsigned int iseries_startup_IRQ(unsigned int irq) | 187 | static unsigned int iseries_startup_IRQ(struct irq_data *d) |
188 | { | 188 | { |
189 | u32 bus, dev_id, function, mask; | 189 | u32 bus, dev_id, function, mask; |
190 | const u32 sub_bus = 0; | 190 | const u32 sub_bus = 0; |
191 | unsigned int rirq = (unsigned int)irq_map[irq].hwirq; | 191 | unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; |
192 | 192 | ||
193 | bus = REAL_IRQ_TO_BUS(rirq); | 193 | bus = REAL_IRQ_TO_BUS(rirq); |
194 | function = REAL_IRQ_TO_FUNC(rirq); | 194 | function = REAL_IRQ_TO_FUNC(rirq); |
195 | dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function; | 195 | dev_id = (REAL_IRQ_TO_IDSEL(rirq) << 4) + function; |
196 | 196 | ||
197 | /* Link the IRQ number to the bridge */ | 197 | /* Link the IRQ number to the bridge */ |
198 | HvCallXm_connectBusUnit(bus, sub_bus, dev_id, irq); | 198 | HvCallXm_connectBusUnit(bus, sub_bus, dev_id, d->irq); |
199 | 199 | ||
200 | /* Unmask bridge interrupts in the FISR */ | 200 | /* Unmask bridge interrupts in the FISR */ |
201 | mask = 0x01010000 << function; | 201 | mask = 0x01010000 << function; |
202 | HvCallPci_unmaskFisr(bus, sub_bus, dev_id, mask); | 202 | HvCallPci_unmaskFisr(bus, sub_bus, dev_id, mask); |
203 | iseries_enable_IRQ(irq); | 203 | iseries_enable_IRQ(d); |
204 | return 0; | 204 | return 0; |
205 | } | 205 | } |
206 | 206 | ||
@@ -215,21 +215,26 @@ void __init iSeries_activate_IRQs() | |||
215 | 215 | ||
216 | for_each_irq (irq) { | 216 | for_each_irq (irq) { |
217 | struct irq_desc *desc = irq_to_desc(irq); | 217 | struct irq_desc *desc = irq_to_desc(irq); |
218 | struct irq_chip *chip; | ||
218 | 219 | ||
219 | if (desc && desc->chip && desc->chip->startup) { | 220 | if (!desc) |
221 | continue; | ||
222 | |||
223 | chip = get_irq_desc_chip(desc); | ||
224 | if (chip && chip->irq_startup) { | ||
220 | raw_spin_lock_irqsave(&desc->lock, flags); | 225 | raw_spin_lock_irqsave(&desc->lock, flags); |
221 | desc->chip->startup(irq); | 226 | chip->irq_startup(&desc->irq_data); |
222 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 227 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
223 | } | 228 | } |
224 | } | 229 | } |
225 | } | 230 | } |
226 | 231 | ||
227 | /* this is not called anywhere currently */ | 232 | /* this is not called anywhere currently */ |
228 | static void iseries_shutdown_IRQ(unsigned int irq) | 233 | static void iseries_shutdown_IRQ(struct irq_data *d) |
229 | { | 234 | { |
230 | u32 bus, dev_id, function, mask; | 235 | u32 bus, dev_id, function, mask; |
231 | const u32 sub_bus = 0; | 236 | const u32 sub_bus = 0; |
232 | unsigned int rirq = (unsigned int)irq_map[irq].hwirq; | 237 | unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; |
233 | 238 | ||
234 | /* irq should be locked by the caller */ | 239 | /* irq should be locked by the caller */ |
235 | bus = REAL_IRQ_TO_BUS(rirq); | 240 | bus = REAL_IRQ_TO_BUS(rirq); |
@@ -248,11 +253,11 @@ static void iseries_shutdown_IRQ(unsigned int irq) | |||
248 | * This will be called by device drivers (via disable_IRQ) | 253 | * This will be called by device drivers (via disable_IRQ) |
249 | * to disable INTA in the bridge interrupt status register. | 254 | * to disable INTA in the bridge interrupt status register. |
250 | */ | 255 | */ |
251 | static void iseries_disable_IRQ(unsigned int irq) | 256 | static void iseries_disable_IRQ(struct irq_data *d) |
252 | { | 257 | { |
253 | u32 bus, dev_id, function, mask; | 258 | u32 bus, dev_id, function, mask; |
254 | const u32 sub_bus = 0; | 259 | const u32 sub_bus = 0; |
255 | unsigned int rirq = (unsigned int)irq_map[irq].hwirq; | 260 | unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; |
256 | 261 | ||
257 | /* The IRQ has already been locked by the caller */ | 262 | /* The IRQ has already been locked by the caller */ |
258 | bus = REAL_IRQ_TO_BUS(rirq); | 263 | bus = REAL_IRQ_TO_BUS(rirq); |
@@ -264,9 +269,9 @@ static void iseries_disable_IRQ(unsigned int irq) | |||
264 | HvCallPci_maskInterrupts(bus, sub_bus, dev_id, mask); | 269 | HvCallPci_maskInterrupts(bus, sub_bus, dev_id, mask); |
265 | } | 270 | } |
266 | 271 | ||
267 | static void iseries_end_IRQ(unsigned int irq) | 272 | static void iseries_end_IRQ(struct irq_data *d) |
268 | { | 273 | { |
269 | unsigned int rirq = (unsigned int)irq_map[irq].hwirq; | 274 | unsigned int rirq = (unsigned int)irq_map[d->irq].hwirq; |
270 | 275 | ||
271 | HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq), | 276 | HvCallPci_eoi(REAL_IRQ_TO_BUS(rirq), REAL_IRQ_TO_SUBBUS(rirq), |
272 | (REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq)); | 277 | (REAL_IRQ_TO_IDSEL(rirq) << 4) + REAL_IRQ_TO_FUNC(rirq)); |
@@ -274,11 +279,11 @@ static void iseries_end_IRQ(unsigned int irq) | |||
274 | 279 | ||
275 | static struct irq_chip iseries_pic = { | 280 | static struct irq_chip iseries_pic = { |
276 | .name = "iSeries", | 281 | .name = "iSeries", |
277 | .startup = iseries_startup_IRQ, | 282 | .irq_startup = iseries_startup_IRQ, |
278 | .shutdown = iseries_shutdown_IRQ, | 283 | .irq_shutdown = iseries_shutdown_IRQ, |
279 | .unmask = iseries_enable_IRQ, | 284 | .irq_unmask = iseries_enable_IRQ, |
280 | .mask = iseries_disable_IRQ, | 285 | .irq_mask = iseries_disable_IRQ, |
281 | .eoi = iseries_end_IRQ | 286 | .irq_eoi = iseries_end_IRQ |
282 | }; | 287 | }; |
283 | 288 | ||
284 | /* | 289 | /* |
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c index f372ec1691a3..a6067b38d2ca 100644 --- a/arch/powerpc/platforms/pasemi/setup.c +++ b/arch/powerpc/platforms/pasemi/setup.c | |||
@@ -240,7 +240,7 @@ static __init void pas_init_IRQ(void) | |||
240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); | 240 | nmi_virq = irq_create_mapping(NULL, *nmiprop); |
241 | mpic_irq_set_priority(nmi_virq, 15); | 241 | mpic_irq_set_priority(nmi_virq, 15); |
242 | set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); | 242 | set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); |
243 | mpic_unmask_irq(nmi_virq); | 243 | mpic_unmask_irq(irq_get_irq_data(nmi_virq)); |
244 | } | 244 | } |
245 | 245 | ||
246 | of_node_put(mpic_node); | 246 | of_node_put(mpic_node); |
@@ -266,7 +266,7 @@ static int pas_machine_check_handler(struct pt_regs *regs) | |||
266 | if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) { | 266 | if (nmi_virq != NO_IRQ && mpic_get_mcirq() == nmi_virq) { |
267 | printk(KERN_ERR "NMI delivered\n"); | 267 | printk(KERN_ERR "NMI delivered\n"); |
268 | debugger(regs); | 268 | debugger(regs); |
269 | mpic_end_irq(nmi_virq); | 269 | mpic_end_irq(irq_get_irq_data(nmi_virq)); |
270 | goto out; | 270 | goto out; |
271 | } | 271 | } |
272 | 272 | ||
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c index 890d5f72b198..c55812bb6a51 100644 --- a/arch/powerpc/platforms/powermac/pic.c +++ b/arch/powerpc/platforms/powermac/pic.c | |||
@@ -82,9 +82,9 @@ static void __pmac_retrigger(unsigned int irq_nr) | |||
82 | } | 82 | } |
83 | } | 83 | } |
84 | 84 | ||
85 | static void pmac_mask_and_ack_irq(unsigned int virq) | 85 | static void pmac_mask_and_ack_irq(struct irq_data *d) |
86 | { | 86 | { |
87 | unsigned int src = irq_map[virq].hwirq; | 87 | unsigned int src = irq_map[d->irq].hwirq; |
88 | unsigned long bit = 1UL << (src & 0x1f); | 88 | unsigned long bit = 1UL << (src & 0x1f); |
89 | int i = src >> 5; | 89 | int i = src >> 5; |
90 | unsigned long flags; | 90 | unsigned long flags; |
@@ -104,9 +104,9 @@ static void pmac_mask_and_ack_irq(unsigned int virq) | |||
104 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); | 104 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
105 | } | 105 | } |
106 | 106 | ||
107 | static void pmac_ack_irq(unsigned int virq) | 107 | static void pmac_ack_irq(struct irq_data *d) |
108 | { | 108 | { |
109 | unsigned int src = irq_map[virq].hwirq; | 109 | unsigned int src = irq_map[d->irq].hwirq; |
110 | unsigned long bit = 1UL << (src & 0x1f); | 110 | unsigned long bit = 1UL << (src & 0x1f); |
111 | int i = src >> 5; | 111 | int i = src >> 5; |
112 | unsigned long flags; | 112 | unsigned long flags; |
@@ -149,15 +149,15 @@ static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) | |||
149 | /* When an irq gets requested for the first client, if it's an | 149 | /* When an irq gets requested for the first client, if it's an |
150 | * edge interrupt, we clear any previous one on the controller | 150 | * edge interrupt, we clear any previous one on the controller |
151 | */ | 151 | */ |
152 | static unsigned int pmac_startup_irq(unsigned int virq) | 152 | static unsigned int pmac_startup_irq(struct irq_data *d) |
153 | { | 153 | { |
154 | unsigned long flags; | 154 | unsigned long flags; |
155 | unsigned int src = irq_map[virq].hwirq; | 155 | unsigned int src = irq_map[d->irq].hwirq; |
156 | unsigned long bit = 1UL << (src & 0x1f); | 156 | unsigned long bit = 1UL << (src & 0x1f); |
157 | int i = src >> 5; | 157 | int i = src >> 5; |
158 | 158 | ||
159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 159 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
160 | if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0) | 160 | if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0) |
161 | out_le32(&pmac_irq_hw[i]->ack, bit); | 161 | out_le32(&pmac_irq_hw[i]->ack, bit); |
162 | __set_bit(src, ppc_cached_irq_mask); | 162 | __set_bit(src, ppc_cached_irq_mask); |
163 | __pmac_set_irq_mask(src, 0); | 163 | __pmac_set_irq_mask(src, 0); |
@@ -166,10 +166,10 @@ static unsigned int pmac_startup_irq(unsigned int virq) | |||
166 | return 0; | 166 | return 0; |
167 | } | 167 | } |
168 | 168 | ||
169 | static void pmac_mask_irq(unsigned int virq) | 169 | static void pmac_mask_irq(struct irq_data *d) |
170 | { | 170 | { |
171 | unsigned long flags; | 171 | unsigned long flags; |
172 | unsigned int src = irq_map[virq].hwirq; | 172 | unsigned int src = irq_map[d->irq].hwirq; |
173 | 173 | ||
174 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 174 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
175 | __clear_bit(src, ppc_cached_irq_mask); | 175 | __clear_bit(src, ppc_cached_irq_mask); |
@@ -177,10 +177,10 @@ static void pmac_mask_irq(unsigned int virq) | |||
177 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); | 177 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
178 | } | 178 | } |
179 | 179 | ||
180 | static void pmac_unmask_irq(unsigned int virq) | 180 | static void pmac_unmask_irq(struct irq_data *d) |
181 | { | 181 | { |
182 | unsigned long flags; | 182 | unsigned long flags; |
183 | unsigned int src = irq_map[virq].hwirq; | 183 | unsigned int src = irq_map[d->irq].hwirq; |
184 | 184 | ||
185 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 185 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
186 | __set_bit(src, ppc_cached_irq_mask); | 186 | __set_bit(src, ppc_cached_irq_mask); |
@@ -188,24 +188,24 @@ static void pmac_unmask_irq(unsigned int virq) | |||
188 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); | 188 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
189 | } | 189 | } |
190 | 190 | ||
191 | static int pmac_retrigger(unsigned int virq) | 191 | static int pmac_retrigger(struct irq_data *d) |
192 | { | 192 | { |
193 | unsigned long flags; | 193 | unsigned long flags; |
194 | 194 | ||
195 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); | 195 | raw_spin_lock_irqsave(&pmac_pic_lock, flags); |
196 | __pmac_retrigger(irq_map[virq].hwirq); | 196 | __pmac_retrigger(irq_map[d->irq].hwirq); |
197 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); | 197 | raw_spin_unlock_irqrestore(&pmac_pic_lock, flags); |
198 | return 1; | 198 | return 1; |
199 | } | 199 | } |
200 | 200 | ||
201 | static struct irq_chip pmac_pic = { | 201 | static struct irq_chip pmac_pic = { |
202 | .name = "PMAC-PIC", | 202 | .name = "PMAC-PIC", |
203 | .startup = pmac_startup_irq, | 203 | .irq_startup = pmac_startup_irq, |
204 | .mask = pmac_mask_irq, | 204 | .irq_mask = pmac_mask_irq, |
205 | .ack = pmac_ack_irq, | 205 | .irq_ack = pmac_ack_irq, |
206 | .mask_ack = pmac_mask_and_ack_irq, | 206 | .irq_mask_ack = pmac_mask_and_ack_irq, |
207 | .unmask = pmac_unmask_irq, | 207 | .irq_unmask = pmac_unmask_irq, |
208 | .retrigger = pmac_retrigger, | 208 | .irq_retrigger = pmac_retrigger, |
209 | }; | 209 | }; |
210 | 210 | ||
211 | static irqreturn_t gatwick_action(int cpl, void *dev_id) | 211 | static irqreturn_t gatwick_action(int cpl, void *dev_id) |
@@ -472,12 +472,14 @@ int of_irq_map_oldworld(struct device_node *device, int index, | |||
472 | 472 | ||
473 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) | 473 | static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) |
474 | { | 474 | { |
475 | struct mpic *mpic = desc->handler_data; | 475 | struct irq_chip *chip = get_irq_desc_chip(desc); |
476 | 476 | struct mpic *mpic = get_irq_desc_data(desc); | |
477 | unsigned int cascade_irq = mpic_get_one_irq(mpic); | 477 | unsigned int cascade_irq = mpic_get_one_irq(mpic); |
478 | |||
478 | if (cascade_irq != NO_IRQ) | 479 | if (cascade_irq != NO_IRQ) |
479 | generic_handle_irq(cascade_irq); | 480 | generic_handle_irq(cascade_irq); |
480 | desc->chip->eoi(irq); | 481 | |
482 | chip->irq_eoi(&desc->irq_data); | ||
481 | } | 483 | } |
482 | 484 | ||
483 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) | 485 | static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) |
@@ -707,7 +709,7 @@ static int pmacpic_resume(struct sys_device *sysdev) | |||
707 | mb(); | 709 | mb(); |
708 | for (i = 0; i < max_real_irqs; ++i) | 710 | for (i = 0; i < max_real_irqs; ++i) |
709 | if (test_bit(i, sleep_save_mask)) | 711 | if (test_bit(i, sleep_save_mask)) |
710 | pmac_unmask_irq(i); | 712 | pmac_unmask_irq(irq_get_irq_data(i)); |
711 | 713 | ||
712 | return 0; | 714 | return 0; |
713 | } | 715 | } |
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c index 92290ff4761a..3988c86682a5 100644 --- a/arch/powerpc/platforms/ps3/interrupt.c +++ b/arch/powerpc/platforms/ps3/interrupt.c | |||
@@ -99,16 +99,16 @@ static DEFINE_PER_CPU(struct ps3_private, ps3_private); | |||
99 | * Sets ps3_bmp.mask and calls lv1_did_update_interrupt_mask(). | 99 | * Sets ps3_bmp.mask and calls lv1_did_update_interrupt_mask(). |
100 | */ | 100 | */ |
101 | 101 | ||
102 | static void ps3_chip_mask(unsigned int virq) | 102 | static void ps3_chip_mask(struct irq_data *d) |
103 | { | 103 | { |
104 | struct ps3_private *pd = get_irq_chip_data(virq); | 104 | struct ps3_private *pd = irq_data_get_irq_chip_data(d); |
105 | unsigned long flags; | 105 | unsigned long flags; |
106 | 106 | ||
107 | pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, | 107 | pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, |
108 | pd->thread_id, virq); | 108 | pd->thread_id, d->irq); |
109 | 109 | ||
110 | local_irq_save(flags); | 110 | local_irq_save(flags); |
111 | clear_bit(63 - virq, &pd->bmp.mask); | 111 | clear_bit(63 - d->irq, &pd->bmp.mask); |
112 | lv1_did_update_interrupt_mask(pd->ppe_id, pd->thread_id); | 112 | lv1_did_update_interrupt_mask(pd->ppe_id, pd->thread_id); |
113 | local_irq_restore(flags); | 113 | local_irq_restore(flags); |
114 | } | 114 | } |
@@ -120,16 +120,16 @@ static void ps3_chip_mask(unsigned int virq) | |||
120 | * Clears ps3_bmp.mask and calls lv1_did_update_interrupt_mask(). | 120 | * Clears ps3_bmp.mask and calls lv1_did_update_interrupt_mask(). |
121 | */ | 121 | */ |
122 | 122 | ||
123 | static void ps3_chip_unmask(unsigned int virq) | 123 | static void ps3_chip_unmask(struct irq_data *d) |
124 | { | 124 | { |
125 | struct ps3_private *pd = get_irq_chip_data(virq); | 125 | struct ps3_private *pd = irq_data_get_irq_chip_data(d); |
126 | unsigned long flags; | 126 | unsigned long flags; |
127 | 127 | ||
128 | pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, | 128 | pr_debug("%s:%d: thread_id %llu, virq %d\n", __func__, __LINE__, |
129 | pd->thread_id, virq); | 129 | pd->thread_id, d->irq); |
130 | 130 | ||
131 | local_irq_save(flags); | 131 | local_irq_save(flags); |
132 | set_bit(63 - virq, &pd->bmp.mask); | 132 | set_bit(63 - d->irq, &pd->bmp.mask); |
133 | lv1_did_update_interrupt_mask(pd->ppe_id, pd->thread_id); | 133 | lv1_did_update_interrupt_mask(pd->ppe_id, pd->thread_id); |
134 | local_irq_restore(flags); | 134 | local_irq_restore(flags); |
135 | } | 135 | } |
@@ -141,10 +141,10 @@ static void ps3_chip_unmask(unsigned int virq) | |||
141 | * Calls lv1_end_of_interrupt_ext(). | 141 | * Calls lv1_end_of_interrupt_ext(). |
142 | */ | 142 | */ |
143 | 143 | ||
144 | static void ps3_chip_eoi(unsigned int virq) | 144 | static void ps3_chip_eoi(struct irq_data *d) |
145 | { | 145 | { |
146 | const struct ps3_private *pd = get_irq_chip_data(virq); | 146 | const struct ps3_private *pd = irq_data_get_irq_chip_data(d); |
147 | lv1_end_of_interrupt_ext(pd->ppe_id, pd->thread_id, virq); | 147 | lv1_end_of_interrupt_ext(pd->ppe_id, pd->thread_id, d->irq); |
148 | } | 148 | } |
149 | 149 | ||
150 | /** | 150 | /** |
@@ -153,9 +153,9 @@ static void ps3_chip_eoi(unsigned int virq) | |||
153 | 153 | ||
154 | static struct irq_chip ps3_irq_chip = { | 154 | static struct irq_chip ps3_irq_chip = { |
155 | .name = "ps3", | 155 | .name = "ps3", |
156 | .mask = ps3_chip_mask, | 156 | .irq_mask = ps3_chip_mask, |
157 | .unmask = ps3_chip_unmask, | 157 | .irq_unmask = ps3_chip_unmask, |
158 | .eoi = ps3_chip_eoi, | 158 | .irq_eoi = ps3_chip_eoi, |
159 | }; | 159 | }; |
160 | 160 | ||
161 | /** | 161 | /** |
@@ -202,7 +202,7 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet, | |||
202 | goto fail_set; | 202 | goto fail_set; |
203 | } | 203 | } |
204 | 204 | ||
205 | ps3_chip_mask(*virq); | 205 | ps3_chip_mask(irq_get_irq_data(*virq)); |
206 | 206 | ||
207 | return result; | 207 | return result; |
208 | 208 | ||
@@ -296,7 +296,7 @@ int ps3_irq_plug_destroy(unsigned int virq) | |||
296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, | 296 | pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__, |
297 | __LINE__, pd->ppe_id, pd->thread_id, virq); | 297 | __LINE__, pd->ppe_id, pd->thread_id, virq); |
298 | 298 | ||
299 | ps3_chip_mask(virq); | 299 | ps3_chip_mask(irq_get_irq_data(virq)); |
300 | 300 | ||
301 | result = lv1_disconnect_irq_plug_ext(pd->ppe_id, pd->thread_id, virq); | 301 | result = lv1_disconnect_irq_plug_ext(pd->ppe_id, pd->thread_id, virq); |
302 | 302 | ||
@@ -357,7 +357,7 @@ int ps3_event_receive_port_destroy(unsigned int virq) | |||
357 | 357 | ||
358 | pr_debug(" -> %s:%d virq %u\n", __func__, __LINE__, virq); | 358 | pr_debug(" -> %s:%d virq %u\n", __func__, __LINE__, virq); |
359 | 359 | ||
360 | ps3_chip_mask(virq); | 360 | ps3_chip_mask(irq_get_irq_data(virq)); |
361 | 361 | ||
362 | result = lv1_destruct_event_receive_port(virq_to_hw(virq)); | 362 | result = lv1_destruct_event_receive_port(virq_to_hw(virq)); |
363 | 363 | ||
@@ -492,7 +492,7 @@ int ps3_io_irq_destroy(unsigned int virq) | |||
492 | int result; | 492 | int result; |
493 | unsigned long outlet = virq_to_hw(virq); | 493 | unsigned long outlet = virq_to_hw(virq); |
494 | 494 | ||
495 | ps3_chip_mask(virq); | 495 | ps3_chip_mask(irq_get_irq_data(virq)); |
496 | 496 | ||
497 | /* | 497 | /* |
498 | * lv1_destruct_io_irq_outlet() will destroy the IRQ plug, | 498 | * lv1_destruct_io_irq_outlet() will destroy the IRQ plug, |
@@ -553,7 +553,7 @@ int ps3_vuart_irq_destroy(unsigned int virq) | |||
553 | { | 553 | { |
554 | int result; | 554 | int result; |
555 | 555 | ||
556 | ps3_chip_mask(virq); | 556 | ps3_chip_mask(irq_get_irq_data(virq)); |
557 | result = lv1_deconfigure_virtual_uart_irq(); | 557 | result = lv1_deconfigure_virtual_uart_irq(); |
558 | 558 | ||
559 | if (result) { | 559 | if (result) { |
@@ -605,7 +605,7 @@ int ps3_spe_irq_destroy(unsigned int virq) | |||
605 | { | 605 | { |
606 | int result; | 606 | int result; |
607 | 607 | ||
608 | ps3_chip_mask(virq); | 608 | ps3_chip_mask(irq_get_irq_data(virq)); |
609 | 609 | ||
610 | result = ps3_irq_plug_destroy(virq); | 610 | result = ps3_irq_plug_destroy(virq); |
611 | BUG_ON(result); | 611 | BUG_ON(result); |
diff --git a/arch/powerpc/platforms/pseries/cmm.c b/arch/powerpc/platforms/pseries/cmm.c index f4803868642c..3cafc306b971 100644 --- a/arch/powerpc/platforms/pseries/cmm.c +++ b/arch/powerpc/platforms/pseries/cmm.c | |||
@@ -508,12 +508,7 @@ static int cmm_memory_isolate_cb(struct notifier_block *self, | |||
508 | if (action == MEM_ISOLATE_COUNT) | 508 | if (action == MEM_ISOLATE_COUNT) |
509 | ret = cmm_count_pages(arg); | 509 | ret = cmm_count_pages(arg); |
510 | 510 | ||
511 | if (ret) | 511 | return notifier_from_errno(ret); |
512 | ret = notifier_from_errno(ret); | ||
513 | else | ||
514 | ret = NOTIFY_OK; | ||
515 | |||
516 | return ret; | ||
517 | } | 512 | } |
518 | 513 | ||
519 | static struct notifier_block cmm_mem_isolate_nb = { | 514 | static struct notifier_block cmm_mem_isolate_nb = { |
@@ -635,12 +630,7 @@ static int cmm_memory_cb(struct notifier_block *self, | |||
635 | break; | 630 | break; |
636 | } | 631 | } |
637 | 632 | ||
638 | if (ret) | 633 | return notifier_from_errno(ret); |
639 | ret = notifier_from_errno(ret); | ||
640 | else | ||
641 | ret = NOTIFY_OK; | ||
642 | |||
643 | return ret; | ||
644 | } | 634 | } |
645 | 635 | ||
646 | static struct notifier_block cmm_mem_nb = { | 636 | static struct notifier_block cmm_mem_nb = { |
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c index 17a11c82e6f8..3cc4d102b1f1 100644 --- a/arch/powerpc/platforms/pseries/eeh.c +++ b/arch/powerpc/platforms/pseries/eeh.c | |||
@@ -876,7 +876,7 @@ void eeh_restore_bars(struct pci_dn *pdn) | |||
876 | * | 876 | * |
877 | * Save the values of the device bars. Unlike the restore | 877 | * Save the values of the device bars. Unlike the restore |
878 | * routine, this routine is *not* recursive. This is because | 878 | * routine, this routine is *not* recursive. This is because |
879 | * PCI devices are added individuallly; but, for the restore, | 879 | * PCI devices are added individually; but, for the restore, |
880 | * an entire slot is reset at a time. | 880 | * an entire slot is reset at a time. |
881 | */ | 881 | */ |
882 | static void eeh_save_bars(struct pci_dn *pdn) | 882 | static void eeh_save_bars(struct pci_dn *pdn) |
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index edea60b7ee90..154c464cdca5 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <linux/pci.h> | 33 | #include <linux/pci.h> |
34 | #include <linux/dma-mapping.h> | 34 | #include <linux/dma-mapping.h> |
35 | #include <linux/crash_dump.h> | 35 | #include <linux/crash_dump.h> |
36 | #include <linux/memory.h> | ||
36 | #include <asm/io.h> | 37 | #include <asm/io.h> |
37 | #include <asm/prom.h> | 38 | #include <asm/prom.h> |
38 | #include <asm/rtas.h> | 39 | #include <asm/rtas.h> |
@@ -45,6 +46,7 @@ | |||
45 | #include <asm/tce.h> | 46 | #include <asm/tce.h> |
46 | #include <asm/ppc-pci.h> | 47 | #include <asm/ppc-pci.h> |
47 | #include <asm/udbg.h> | 48 | #include <asm/udbg.h> |
49 | #include <asm/mmzone.h> | ||
48 | 50 | ||
49 | #include "plpar_wrappers.h" | 51 | #include "plpar_wrappers.h" |
50 | 52 | ||
@@ -270,6 +272,152 @@ static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) | |||
270 | return tce_ret; | 272 | return tce_ret; |
271 | } | 273 | } |
272 | 274 | ||
275 | /* this is compatable with cells for the device tree property */ | ||
276 | struct dynamic_dma_window_prop { | ||
277 | __be32 liobn; /* tce table number */ | ||
278 | __be64 dma_base; /* address hi,lo */ | ||
279 | __be32 tce_shift; /* ilog2(tce_page_size) */ | ||
280 | __be32 window_shift; /* ilog2(tce_window_size) */ | ||
281 | }; | ||
282 | |||
283 | struct direct_window { | ||
284 | struct device_node *device; | ||
285 | const struct dynamic_dma_window_prop *prop; | ||
286 | struct list_head list; | ||
287 | }; | ||
288 | |||
289 | /* Dynamic DMA Window support */ | ||
290 | struct ddw_query_response { | ||
291 | u32 windows_available; | ||
292 | u32 largest_available_block; | ||
293 | u32 page_size; | ||
294 | u32 migration_capable; | ||
295 | }; | ||
296 | |||
297 | struct ddw_create_response { | ||
298 | u32 liobn; | ||
299 | u32 addr_hi; | ||
300 | u32 addr_lo; | ||
301 | }; | ||
302 | |||
303 | static LIST_HEAD(direct_window_list); | ||
304 | /* prevents races between memory on/offline and window creation */ | ||
305 | static DEFINE_SPINLOCK(direct_window_list_lock); | ||
306 | /* protects initializing window twice for same device */ | ||
307 | static DEFINE_MUTEX(direct_window_init_mutex); | ||
308 | #define DIRECT64_PROPNAME "linux,direct64-ddr-window-info" | ||
309 | |||
310 | static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn, | ||
311 | unsigned long num_pfn, const void *arg) | ||
312 | { | ||
313 | const struct dynamic_dma_window_prop *maprange = arg; | ||
314 | int rc; | ||
315 | u64 tce_size, num_tce, dma_offset, next; | ||
316 | u32 tce_shift; | ||
317 | long limit; | ||
318 | |||
319 | tce_shift = be32_to_cpu(maprange->tce_shift); | ||
320 | tce_size = 1ULL << tce_shift; | ||
321 | next = start_pfn << PAGE_SHIFT; | ||
322 | num_tce = num_pfn << PAGE_SHIFT; | ||
323 | |||
324 | /* round back to the beginning of the tce page size */ | ||
325 | num_tce += next & (tce_size - 1); | ||
326 | next &= ~(tce_size - 1); | ||
327 | |||
328 | /* covert to number of tces */ | ||
329 | num_tce |= tce_size - 1; | ||
330 | num_tce >>= tce_shift; | ||
331 | |||
332 | do { | ||
333 | /* | ||
334 | * Set up the page with TCE data, looping through and setting | ||
335 | * the values. | ||
336 | */ | ||
337 | limit = min_t(long, num_tce, 512); | ||
338 | dma_offset = next + be64_to_cpu(maprange->dma_base); | ||
339 | |||
340 | rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn), | ||
341 | dma_offset, | ||
342 | 0, limit); | ||
343 | num_tce -= limit; | ||
344 | } while (num_tce > 0 && !rc); | ||
345 | |||
346 | return rc; | ||
347 | } | ||
348 | |||
349 | static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn, | ||
350 | unsigned long num_pfn, const void *arg) | ||
351 | { | ||
352 | const struct dynamic_dma_window_prop *maprange = arg; | ||
353 | u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn; | ||
354 | u32 tce_shift; | ||
355 | u64 rc = 0; | ||
356 | long l, limit; | ||
357 | |||
358 | local_irq_disable(); /* to protect tcep and the page behind it */ | ||
359 | tcep = __get_cpu_var(tce_page); | ||
360 | |||
361 | if (!tcep) { | ||
362 | tcep = (u64 *)__get_free_page(GFP_ATOMIC); | ||
363 | if (!tcep) { | ||
364 | local_irq_enable(); | ||
365 | return -ENOMEM; | ||
366 | } | ||
367 | __get_cpu_var(tce_page) = tcep; | ||
368 | } | ||
369 | |||
370 | proto_tce = TCE_PCI_READ | TCE_PCI_WRITE; | ||
371 | |||
372 | liobn = (u64)be32_to_cpu(maprange->liobn); | ||
373 | tce_shift = be32_to_cpu(maprange->tce_shift); | ||
374 | tce_size = 1ULL << tce_shift; | ||
375 | next = start_pfn << PAGE_SHIFT; | ||
376 | num_tce = num_pfn << PAGE_SHIFT; | ||
377 | |||
378 | /* round back to the beginning of the tce page size */ | ||
379 | num_tce += next & (tce_size - 1); | ||
380 | next &= ~(tce_size - 1); | ||
381 | |||
382 | /* covert to number of tces */ | ||
383 | num_tce |= tce_size - 1; | ||
384 | num_tce >>= tce_shift; | ||
385 | |||
386 | /* We can map max one pageful of TCEs at a time */ | ||
387 | do { | ||
388 | /* | ||
389 | * Set up the page with TCE data, looping through and setting | ||
390 | * the values. | ||
391 | */ | ||
392 | limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE); | ||
393 | dma_offset = next + be64_to_cpu(maprange->dma_base); | ||
394 | |||
395 | for (l = 0; l < limit; l++) { | ||
396 | tcep[l] = proto_tce | next; | ||
397 | next += tce_size; | ||
398 | } | ||
399 | |||
400 | rc = plpar_tce_put_indirect(liobn, | ||
401 | dma_offset, | ||
402 | (u64)virt_to_abs(tcep), | ||
403 | limit); | ||
404 | |||
405 | num_tce -= limit; | ||
406 | } while (num_tce > 0 && !rc); | ||
407 | |||
408 | /* error cleanup: caller will clear whole range */ | ||
409 | |||
410 | local_irq_enable(); | ||
411 | return rc; | ||
412 | } | ||
413 | |||
414 | static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn, | ||
415 | unsigned long num_pfn, void *arg) | ||
416 | { | ||
417 | return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg); | ||
418 | } | ||
419 | |||
420 | |||
273 | #ifdef CONFIG_PCI | 421 | #ifdef CONFIG_PCI |
274 | static void iommu_table_setparms(struct pci_controller *phb, | 422 | static void iommu_table_setparms(struct pci_controller *phb, |
275 | struct device_node *dn, | 423 | struct device_node *dn, |
@@ -495,6 +643,329 @@ static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) | |||
495 | pci_name(dev)); | 643 | pci_name(dev)); |
496 | } | 644 | } |
497 | 645 | ||
646 | static int __read_mostly disable_ddw; | ||
647 | |||
648 | static int __init disable_ddw_setup(char *str) | ||
649 | { | ||
650 | disable_ddw = 1; | ||
651 | printk(KERN_INFO "ppc iommu: disabling ddw.\n"); | ||
652 | |||
653 | return 0; | ||
654 | } | ||
655 | |||
656 | early_param("disable_ddw", disable_ddw_setup); | ||
657 | |||
658 | static void remove_ddw(struct device_node *np) | ||
659 | { | ||
660 | struct dynamic_dma_window_prop *dwp; | ||
661 | struct property *win64; | ||
662 | const u32 *ddr_avail; | ||
663 | u64 liobn; | ||
664 | int len, ret; | ||
665 | |||
666 | ddr_avail = of_get_property(np, "ibm,ddw-applicable", &len); | ||
667 | win64 = of_find_property(np, DIRECT64_PROPNAME, NULL); | ||
668 | if (!win64 || !ddr_avail || len < 3 * sizeof(u32)) | ||
669 | return; | ||
670 | |||
671 | dwp = win64->value; | ||
672 | liobn = (u64)be32_to_cpu(dwp->liobn); | ||
673 | |||
674 | /* clear the whole window, note the arg is in kernel pages */ | ||
675 | ret = tce_clearrange_multi_pSeriesLP(0, | ||
676 | 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp); | ||
677 | if (ret) | ||
678 | pr_warning("%s failed to clear tces in window.\n", | ||
679 | np->full_name); | ||
680 | else | ||
681 | pr_debug("%s successfully cleared tces in window.\n", | ||
682 | np->full_name); | ||
683 | |||
684 | ret = rtas_call(ddr_avail[2], 1, 1, NULL, liobn); | ||
685 | if (ret) | ||
686 | pr_warning("%s: failed to remove direct window: rtas returned " | ||
687 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", | ||
688 | np->full_name, ret, ddr_avail[2], liobn); | ||
689 | else | ||
690 | pr_debug("%s: successfully removed direct window: rtas returned " | ||
691 | "%d to ibm,remove-pe-dma-window(%x) %llx\n", | ||
692 | np->full_name, ret, ddr_avail[2], liobn); | ||
693 | } | ||
694 | |||
695 | |||
696 | static int dupe_ddw_if_already_created(struct pci_dev *dev, struct device_node *pdn) | ||
697 | { | ||
698 | struct device_node *dn; | ||
699 | struct pci_dn *pcidn; | ||
700 | struct direct_window *window; | ||
701 | const struct dynamic_dma_window_prop *direct64; | ||
702 | u64 dma_addr = 0; | ||
703 | |||
704 | dn = pci_device_to_OF_node(dev); | ||
705 | pcidn = PCI_DN(dn); | ||
706 | spin_lock(&direct_window_list_lock); | ||
707 | /* check if we already created a window and dupe that config if so */ | ||
708 | list_for_each_entry(window, &direct_window_list, list) { | ||
709 | if (window->device == pdn) { | ||
710 | direct64 = window->prop; | ||
711 | dma_addr = direct64->dma_base; | ||
712 | break; | ||
713 | } | ||
714 | } | ||
715 | spin_unlock(&direct_window_list_lock); | ||
716 | |||
717 | return dma_addr; | ||
718 | } | ||
719 | |||
720 | static u64 dupe_ddw_if_kexec(struct pci_dev *dev, struct device_node *pdn) | ||
721 | { | ||
722 | struct device_node *dn; | ||
723 | struct pci_dn *pcidn; | ||
724 | int len; | ||
725 | struct direct_window *window; | ||
726 | const struct dynamic_dma_window_prop *direct64; | ||
727 | u64 dma_addr = 0; | ||
728 | |||
729 | dn = pci_device_to_OF_node(dev); | ||
730 | pcidn = PCI_DN(dn); | ||
731 | direct64 = of_get_property(pdn, DIRECT64_PROPNAME, &len); | ||
732 | if (direct64) { | ||
733 | window = kzalloc(sizeof(*window), GFP_KERNEL); | ||
734 | if (!window) { | ||
735 | remove_ddw(pdn); | ||
736 | } else { | ||
737 | window->device = pdn; | ||
738 | window->prop = direct64; | ||
739 | spin_lock(&direct_window_list_lock); | ||
740 | list_add(&window->list, &direct_window_list); | ||
741 | spin_unlock(&direct_window_list_lock); | ||
742 | dma_addr = direct64->dma_base; | ||
743 | } | ||
744 | } | ||
745 | |||
746 | return dma_addr; | ||
747 | } | ||
748 | |||
749 | static int query_ddw(struct pci_dev *dev, const u32 *ddr_avail, | ||
750 | struct ddw_query_response *query) | ||
751 | { | ||
752 | struct device_node *dn; | ||
753 | struct pci_dn *pcidn; | ||
754 | u32 cfg_addr; | ||
755 | u64 buid; | ||
756 | int ret; | ||
757 | |||
758 | /* | ||
759 | * Get the config address and phb buid of the PE window. | ||
760 | * Rely on eeh to retrieve this for us. | ||
761 | * Retrieve them from the pci device, not the node with the | ||
762 | * dma-window property | ||
763 | */ | ||
764 | dn = pci_device_to_OF_node(dev); | ||
765 | pcidn = PCI_DN(dn); | ||
766 | cfg_addr = pcidn->eeh_config_addr; | ||
767 | if (pcidn->eeh_pe_config_addr) | ||
768 | cfg_addr = pcidn->eeh_pe_config_addr; | ||
769 | buid = pcidn->phb->buid; | ||
770 | ret = rtas_call(ddr_avail[0], 3, 5, (u32 *)query, | ||
771 | cfg_addr, BUID_HI(buid), BUID_LO(buid)); | ||
772 | dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x" | ||
773 | " returned %d\n", ddr_avail[0], cfg_addr, BUID_HI(buid), | ||
774 | BUID_LO(buid), ret); | ||
775 | return ret; | ||
776 | } | ||
777 | |||
778 | static int create_ddw(struct pci_dev *dev, const u32 *ddr_avail, | ||
779 | struct ddw_create_response *create, int page_shift, | ||
780 | int window_shift) | ||
781 | { | ||
782 | struct device_node *dn; | ||
783 | struct pci_dn *pcidn; | ||
784 | u32 cfg_addr; | ||
785 | u64 buid; | ||
786 | int ret; | ||
787 | |||
788 | /* | ||
789 | * Get the config address and phb buid of the PE window. | ||
790 | * Rely on eeh to retrieve this for us. | ||
791 | * Retrieve them from the pci device, not the node with the | ||
792 | * dma-window property | ||
793 | */ | ||
794 | dn = pci_device_to_OF_node(dev); | ||
795 | pcidn = PCI_DN(dn); | ||
796 | cfg_addr = pcidn->eeh_config_addr; | ||
797 | if (pcidn->eeh_pe_config_addr) | ||
798 | cfg_addr = pcidn->eeh_pe_config_addr; | ||
799 | buid = pcidn->phb->buid; | ||
800 | |||
801 | do { | ||
802 | /* extra outputs are LIOBN and dma-addr (hi, lo) */ | ||
803 | ret = rtas_call(ddr_avail[1], 5, 4, (u32 *)create, cfg_addr, | ||
804 | BUID_HI(buid), BUID_LO(buid), page_shift, window_shift); | ||
805 | } while (rtas_busy_delay(ret)); | ||
806 | dev_info(&dev->dev, | ||
807 | "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d " | ||
808 | "(liobn = 0x%x starting addr = %x %x)\n", ddr_avail[1], | ||
809 | cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift, | ||
810 | window_shift, ret, create->liobn, create->addr_hi, create->addr_lo); | ||
811 | |||
812 | return ret; | ||
813 | } | ||
814 | |||
815 | /* | ||
816 | * If the PE supports dynamic dma windows, and there is space for a table | ||
817 | * that can map all pages in a linear offset, then setup such a table, | ||
818 | * and record the dma-offset in the struct device. | ||
819 | * | ||
820 | * dev: the pci device we are checking | ||
821 | * pdn: the parent pe node with the ibm,dma_window property | ||
822 | * Future: also check if we can remap the base window for our base page size | ||
823 | * | ||
824 | * returns the dma offset for use by dma_set_mask | ||
825 | */ | ||
826 | static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn) | ||
827 | { | ||
828 | int len, ret; | ||
829 | struct ddw_query_response query; | ||
830 | struct ddw_create_response create; | ||
831 | int page_shift; | ||
832 | u64 dma_addr, max_addr; | ||
833 | struct device_node *dn; | ||
834 | const u32 *uninitialized_var(ddr_avail); | ||
835 | struct direct_window *window; | ||
836 | struct property *uninitialized_var(win64); | ||
837 | struct dynamic_dma_window_prop *ddwprop; | ||
838 | |||
839 | mutex_lock(&direct_window_init_mutex); | ||
840 | |||
841 | dma_addr = dupe_ddw_if_already_created(dev, pdn); | ||
842 | if (dma_addr != 0) | ||
843 | goto out_unlock; | ||
844 | |||
845 | dma_addr = dupe_ddw_if_kexec(dev, pdn); | ||
846 | if (dma_addr != 0) | ||
847 | goto out_unlock; | ||
848 | |||
849 | /* | ||
850 | * the ibm,ddw-applicable property holds the tokens for: | ||
851 | * ibm,query-pe-dma-window | ||
852 | * ibm,create-pe-dma-window | ||
853 | * ibm,remove-pe-dma-window | ||
854 | * for the given node in that order. | ||
855 | * the property is actually in the parent, not the PE | ||
856 | */ | ||
857 | ddr_avail = of_get_property(pdn, "ibm,ddw-applicable", &len); | ||
858 | if (!ddr_avail || len < 3 * sizeof(u32)) | ||
859 | goto out_unlock; | ||
860 | |||
861 | /* | ||
862 | * Query if there is a second window of size to map the | ||
863 | * whole partition. Query returns number of windows, largest | ||
864 | * block assigned to PE (partition endpoint), and two bitmasks | ||
865 | * of page sizes: supported and supported for migrate-dma. | ||
866 | */ | ||
867 | dn = pci_device_to_OF_node(dev); | ||
868 | ret = query_ddw(dev, ddr_avail, &query); | ||
869 | if (ret != 0) | ||
870 | goto out_unlock; | ||
871 | |||
872 | if (query.windows_available == 0) { | ||
873 | /* | ||
874 | * no additional windows are available for this device. | ||
875 | * We might be able to reallocate the existing window, | ||
876 | * trading in for a larger page size. | ||
877 | */ | ||
878 | dev_dbg(&dev->dev, "no free dynamic windows"); | ||
879 | goto out_unlock; | ||
880 | } | ||
881 | if (query.page_size & 4) { | ||
882 | page_shift = 24; /* 16MB */ | ||
883 | } else if (query.page_size & 2) { | ||
884 | page_shift = 16; /* 64kB */ | ||
885 | } else if (query.page_size & 1) { | ||
886 | page_shift = 12; /* 4kB */ | ||
887 | } else { | ||
888 | dev_dbg(&dev->dev, "no supported direct page size in mask %x", | ||
889 | query.page_size); | ||
890 | goto out_unlock; | ||
891 | } | ||
892 | /* verify the window * number of ptes will map the partition */ | ||
893 | /* check largest block * page size > max memory hotplug addr */ | ||
894 | max_addr = memory_hotplug_max(); | ||
895 | if (query.largest_available_block < (max_addr >> page_shift)) { | ||
896 | dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u " | ||
897 | "%llu-sized pages\n", max_addr, query.largest_available_block, | ||
898 | 1ULL << page_shift); | ||
899 | goto out_unlock; | ||
900 | } | ||
901 | len = order_base_2(max_addr); | ||
902 | win64 = kzalloc(sizeof(struct property), GFP_KERNEL); | ||
903 | if (!win64) { | ||
904 | dev_info(&dev->dev, | ||
905 | "couldn't allocate property for 64bit dma window\n"); | ||
906 | goto out_unlock; | ||
907 | } | ||
908 | win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL); | ||
909 | win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL); | ||
910 | if (!win64->name || !win64->value) { | ||
911 | dev_info(&dev->dev, | ||
912 | "couldn't allocate property name and value\n"); | ||
913 | goto out_free_prop; | ||
914 | } | ||
915 | |||
916 | ret = create_ddw(dev, ddr_avail, &create, page_shift, len); | ||
917 | if (ret != 0) | ||
918 | goto out_free_prop; | ||
919 | |||
920 | ddwprop->liobn = cpu_to_be32(create.liobn); | ||
921 | ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2)); | ||
922 | ddwprop->tce_shift = cpu_to_be32(page_shift); | ||
923 | ddwprop->window_shift = cpu_to_be32(len); | ||
924 | |||
925 | dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n", | ||
926 | create.liobn, dn->full_name); | ||
927 | |||
928 | window = kzalloc(sizeof(*window), GFP_KERNEL); | ||
929 | if (!window) | ||
930 | goto out_clear_window; | ||
931 | |||
932 | ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT, | ||
933 | win64->value, tce_setrange_multi_pSeriesLP_walk); | ||
934 | if (ret) { | ||
935 | dev_info(&dev->dev, "failed to map direct window for %s: %d\n", | ||
936 | dn->full_name, ret); | ||
937 | goto out_clear_window; | ||
938 | } | ||
939 | |||
940 | ret = prom_add_property(pdn, win64); | ||
941 | if (ret) { | ||
942 | dev_err(&dev->dev, "unable to add dma window property for %s: %d", | ||
943 | pdn->full_name, ret); | ||
944 | goto out_clear_window; | ||
945 | } | ||
946 | |||
947 | window->device = pdn; | ||
948 | window->prop = ddwprop; | ||
949 | spin_lock(&direct_window_list_lock); | ||
950 | list_add(&window->list, &direct_window_list); | ||
951 | spin_unlock(&direct_window_list_lock); | ||
952 | |||
953 | dma_addr = of_read_number(&create.addr_hi, 2); | ||
954 | goto out_unlock; | ||
955 | |||
956 | out_clear_window: | ||
957 | remove_ddw(pdn); | ||
958 | |||
959 | out_free_prop: | ||
960 | kfree(win64->name); | ||
961 | kfree(win64->value); | ||
962 | kfree(win64); | ||
963 | |||
964 | out_unlock: | ||
965 | mutex_unlock(&direct_window_init_mutex); | ||
966 | return dma_addr; | ||
967 | } | ||
968 | |||
498 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) | 969 | static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) |
499 | { | 970 | { |
500 | struct device_node *pdn, *dn; | 971 | struct device_node *pdn, *dn; |
@@ -541,23 +1012,137 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) | |||
541 | 1012 | ||
542 | set_iommu_table_base(&dev->dev, pci->iommu_table); | 1013 | set_iommu_table_base(&dev->dev, pci->iommu_table); |
543 | } | 1014 | } |
1015 | |||
1016 | static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask) | ||
1017 | { | ||
1018 | bool ddw_enabled = false; | ||
1019 | struct device_node *pdn, *dn; | ||
1020 | struct pci_dev *pdev; | ||
1021 | const void *dma_window = NULL; | ||
1022 | u64 dma_offset; | ||
1023 | |||
1024 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | ||
1025 | return -EIO; | ||
1026 | |||
1027 | /* only attempt to use a new window if 64-bit DMA is requested */ | ||
1028 | if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) { | ||
1029 | pdev = to_pci_dev(dev); | ||
1030 | |||
1031 | dn = pci_device_to_OF_node(pdev); | ||
1032 | dev_dbg(dev, "node is %s\n", dn->full_name); | ||
1033 | |||
1034 | /* | ||
1035 | * the device tree might contain the dma-window properties | ||
1036 | * per-device and not neccesarily for the bus. So we need to | ||
1037 | * search upwards in the tree until we either hit a dma-window | ||
1038 | * property, OR find a parent with a table already allocated. | ||
1039 | */ | ||
1040 | for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table; | ||
1041 | pdn = pdn->parent) { | ||
1042 | dma_window = of_get_property(pdn, "ibm,dma-window", NULL); | ||
1043 | if (dma_window) | ||
1044 | break; | ||
1045 | } | ||
1046 | if (pdn && PCI_DN(pdn)) { | ||
1047 | dma_offset = enable_ddw(pdev, pdn); | ||
1048 | if (dma_offset != 0) { | ||
1049 | dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset); | ||
1050 | set_dma_offset(dev, dma_offset); | ||
1051 | set_dma_ops(dev, &dma_direct_ops); | ||
1052 | ddw_enabled = true; | ||
1053 | } | ||
1054 | } | ||
1055 | } | ||
1056 | |||
1057 | /* fall-through to iommu ops */ | ||
1058 | if (!ddw_enabled) { | ||
1059 | dev_info(dev, "Using 32-bit DMA via iommu\n"); | ||
1060 | set_dma_ops(dev, &dma_iommu_ops); | ||
1061 | } | ||
1062 | |||
1063 | *dev->dma_mask = dma_mask; | ||
1064 | return 0; | ||
1065 | } | ||
1066 | |||
544 | #else /* CONFIG_PCI */ | 1067 | #else /* CONFIG_PCI */ |
545 | #define pci_dma_bus_setup_pSeries NULL | 1068 | #define pci_dma_bus_setup_pSeries NULL |
546 | #define pci_dma_dev_setup_pSeries NULL | 1069 | #define pci_dma_dev_setup_pSeries NULL |
547 | #define pci_dma_bus_setup_pSeriesLP NULL | 1070 | #define pci_dma_bus_setup_pSeriesLP NULL |
548 | #define pci_dma_dev_setup_pSeriesLP NULL | 1071 | #define pci_dma_dev_setup_pSeriesLP NULL |
1072 | #define dma_set_mask_pSeriesLP NULL | ||
549 | #endif /* !CONFIG_PCI */ | 1073 | #endif /* !CONFIG_PCI */ |
550 | 1074 | ||
1075 | static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action, | ||
1076 | void *data) | ||
1077 | { | ||
1078 | struct direct_window *window; | ||
1079 | struct memory_notify *arg = data; | ||
1080 | int ret = 0; | ||
1081 | |||
1082 | switch (action) { | ||
1083 | case MEM_GOING_ONLINE: | ||
1084 | spin_lock(&direct_window_list_lock); | ||
1085 | list_for_each_entry(window, &direct_window_list, list) { | ||
1086 | ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn, | ||
1087 | arg->nr_pages, window->prop); | ||
1088 | /* XXX log error */ | ||
1089 | } | ||
1090 | spin_unlock(&direct_window_list_lock); | ||
1091 | break; | ||
1092 | case MEM_CANCEL_ONLINE: | ||
1093 | case MEM_OFFLINE: | ||
1094 | spin_lock(&direct_window_list_lock); | ||
1095 | list_for_each_entry(window, &direct_window_list, list) { | ||
1096 | ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn, | ||
1097 | arg->nr_pages, window->prop); | ||
1098 | /* XXX log error */ | ||
1099 | } | ||
1100 | spin_unlock(&direct_window_list_lock); | ||
1101 | break; | ||
1102 | default: | ||
1103 | break; | ||
1104 | } | ||
1105 | if (ret && action != MEM_CANCEL_ONLINE) | ||
1106 | return NOTIFY_BAD; | ||
1107 | |||
1108 | return NOTIFY_OK; | ||
1109 | } | ||
1110 | |||
1111 | static struct notifier_block iommu_mem_nb = { | ||
1112 | .notifier_call = iommu_mem_notifier, | ||
1113 | }; | ||
1114 | |||
551 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) | 1115 | static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node) |
552 | { | 1116 | { |
553 | int err = NOTIFY_OK; | 1117 | int err = NOTIFY_OK; |
554 | struct device_node *np = node; | 1118 | struct device_node *np = node; |
555 | struct pci_dn *pci = PCI_DN(np); | 1119 | struct pci_dn *pci = PCI_DN(np); |
1120 | struct direct_window *window; | ||
556 | 1121 | ||
557 | switch (action) { | 1122 | switch (action) { |
558 | case PSERIES_RECONFIG_REMOVE: | 1123 | case PSERIES_RECONFIG_REMOVE: |
559 | if (pci && pci->iommu_table) | 1124 | if (pci && pci->iommu_table) |
560 | iommu_free_table(pci->iommu_table, np->full_name); | 1125 | iommu_free_table(pci->iommu_table, np->full_name); |
1126 | |||
1127 | spin_lock(&direct_window_list_lock); | ||
1128 | list_for_each_entry(window, &direct_window_list, list) { | ||
1129 | if (window->device == np) { | ||
1130 | list_del(&window->list); | ||
1131 | kfree(window); | ||
1132 | break; | ||
1133 | } | ||
1134 | } | ||
1135 | spin_unlock(&direct_window_list_lock); | ||
1136 | |||
1137 | /* | ||
1138 | * Because the notifier runs after isolation of the | ||
1139 | * slot, we are guaranteed any DMA window has already | ||
1140 | * been revoked and the TCEs have been marked invalid, | ||
1141 | * so we don't need a call to remove_ddw(np). However, | ||
1142 | * if an additional notifier action is added before the | ||
1143 | * isolate call, we should update this code for | ||
1144 | * completeness with such a call. | ||
1145 | */ | ||
561 | break; | 1146 | break; |
562 | default: | 1147 | default: |
563 | err = NOTIFY_DONE; | 1148 | err = NOTIFY_DONE; |
@@ -587,6 +1172,7 @@ void iommu_init_early_pSeries(void) | |||
587 | ppc_md.tce_get = tce_get_pSeriesLP; | 1172 | ppc_md.tce_get = tce_get_pSeriesLP; |
588 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; | 1173 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP; |
589 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; | 1174 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP; |
1175 | ppc_md.dma_set_mask = dma_set_mask_pSeriesLP; | ||
590 | } else { | 1176 | } else { |
591 | ppc_md.tce_build = tce_build_pSeries; | 1177 | ppc_md.tce_build = tce_build_pSeries; |
592 | ppc_md.tce_free = tce_free_pSeries; | 1178 | ppc_md.tce_free = tce_free_pSeries; |
@@ -597,6 +1183,7 @@ void iommu_init_early_pSeries(void) | |||
597 | 1183 | ||
598 | 1184 | ||
599 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); | 1185 | pSeries_reconfig_notifier_register(&iommu_reconfig_nb); |
1186 | register_memory_notifier(&iommu_mem_nb); | ||
600 | 1187 | ||
601 | set_pci_dma_ops(&dma_iommu_ops); | 1188 | set_pci_dma_ops(&dma_iommu_ops); |
602 | } | 1189 | } |
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c index 1164c3430f2c..18ac801f8e90 100644 --- a/arch/powerpc/platforms/pseries/msi.c +++ b/arch/powerpc/platforms/pseries/msi.c | |||
@@ -93,8 +93,18 @@ static void rtas_disable_msi(struct pci_dev *pdev) | |||
93 | if (!pdn) | 93 | if (!pdn) |
94 | return; | 94 | return; |
95 | 95 | ||
96 | if (rtas_change_msi(pdn, RTAS_CHANGE_FN, 0) != 0) | 96 | /* |
97 | pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); | 97 | * disabling MSI with the explicit interface also disables MSI-X |
98 | */ | ||
99 | if (rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, 0) != 0) { | ||
100 | /* | ||
101 | * may have failed because explicit interface is not | ||
102 | * present | ||
103 | */ | ||
104 | if (rtas_change_msi(pdn, RTAS_CHANGE_FN, 0) != 0) { | ||
105 | pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); | ||
106 | } | ||
107 | } | ||
98 | } | 108 | } |
99 | 109 | ||
100 | static int rtas_query_irq_number(struct pci_dn *pdn, int offset) | 110 | static int rtas_query_irq_number(struct pci_dn *pdn, int offset) |
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c index 7e828ba29bc3..419707b07248 100644 --- a/arch/powerpc/platforms/pseries/nvram.c +++ b/arch/powerpc/platforms/pseries/nvram.c | |||
@@ -16,6 +16,8 @@ | |||
16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
19 | #include <linux/slab.h> | ||
20 | #include <linux/kmsg_dump.h> | ||
19 | #include <asm/uaccess.h> | 21 | #include <asm/uaccess.h> |
20 | #include <asm/nvram.h> | 22 | #include <asm/nvram.h> |
21 | #include <asm/rtas.h> | 23 | #include <asm/rtas.h> |
@@ -30,17 +32,54 @@ static int nvram_fetch, nvram_store; | |||
30 | static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */ | 32 | static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */ |
31 | static DEFINE_SPINLOCK(nvram_lock); | 33 | static DEFINE_SPINLOCK(nvram_lock); |
32 | 34 | ||
33 | static long nvram_error_log_index = -1; | ||
34 | static long nvram_error_log_size = 0; | ||
35 | |||
36 | struct err_log_info { | 35 | struct err_log_info { |
37 | int error_type; | 36 | int error_type; |
38 | unsigned int seq_num; | 37 | unsigned int seq_num; |
39 | }; | 38 | }; |
40 | #define NVRAM_MAX_REQ 2079 | ||
41 | #define NVRAM_MIN_REQ 1055 | ||
42 | 39 | ||
43 | #define NVRAM_LOG_PART_NAME "ibm,rtas-log" | 40 | struct nvram_os_partition { |
41 | const char *name; | ||
42 | int req_size; /* desired size, in bytes */ | ||
43 | int min_size; /* minimum acceptable size (0 means req_size) */ | ||
44 | long size; /* size of data portion (excluding err_log_info) */ | ||
45 | long index; /* offset of data portion of partition */ | ||
46 | }; | ||
47 | |||
48 | static struct nvram_os_partition rtas_log_partition = { | ||
49 | .name = "ibm,rtas-log", | ||
50 | .req_size = 2079, | ||
51 | .min_size = 1055, | ||
52 | .index = -1 | ||
53 | }; | ||
54 | |||
55 | static struct nvram_os_partition oops_log_partition = { | ||
56 | .name = "lnx,oops-log", | ||
57 | .req_size = 4000, | ||
58 | .min_size = 2000, | ||
59 | .index = -1 | ||
60 | }; | ||
61 | |||
62 | static const char *pseries_nvram_os_partitions[] = { | ||
63 | "ibm,rtas-log", | ||
64 | "lnx,oops-log", | ||
65 | NULL | ||
66 | }; | ||
67 | |||
68 | static void oops_to_nvram(struct kmsg_dumper *dumper, | ||
69 | enum kmsg_dump_reason reason, | ||
70 | const char *old_msgs, unsigned long old_len, | ||
71 | const char *new_msgs, unsigned long new_len); | ||
72 | |||
73 | static struct kmsg_dumper nvram_kmsg_dumper = { | ||
74 | .dump = oops_to_nvram | ||
75 | }; | ||
76 | |||
77 | /* See clobbering_unread_rtas_event() */ | ||
78 | #define NVRAM_RTAS_READ_TIMEOUT 5 /* seconds */ | ||
79 | static unsigned long last_unread_rtas_event; /* timestamp */ | ||
80 | |||
81 | /* We preallocate oops_buf during init to avoid kmalloc during oops/panic. */ | ||
82 | static char *oops_buf; | ||
44 | 83 | ||
45 | static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index) | 84 | static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index) |
46 | { | 85 | { |
@@ -134,7 +173,7 @@ static ssize_t pSeries_nvram_get_size(void) | |||
134 | } | 173 | } |
135 | 174 | ||
136 | 175 | ||
137 | /* nvram_write_error_log | 176 | /* nvram_write_os_partition, nvram_write_error_log |
138 | * | 177 | * |
139 | * We need to buffer the error logs into nvram to ensure that we have | 178 | * We need to buffer the error logs into nvram to ensure that we have |
140 | * the failure information to decode. If we have a severe error there | 179 | * the failure information to decode. If we have a severe error there |
@@ -156,48 +195,58 @@ static ssize_t pSeries_nvram_get_size(void) | |||
156 | * The 'data' section would look like (in bytes): | 195 | * The 'data' section would look like (in bytes): |
157 | * +--------------+------------+-----------------------------------+ | 196 | * +--------------+------------+-----------------------------------+ |
158 | * | event_logged | sequence # | error log | | 197 | * | event_logged | sequence # | error log | |
159 | * |0 3|4 7|8 nvram_error_log_size-1| | 198 | * |0 3|4 7|8 error_log_size-1| |
160 | * +--------------+------------+-----------------------------------+ | 199 | * +--------------+------------+-----------------------------------+ |
161 | * | 200 | * |
162 | * event_logged: 0 if event has not been logged to syslog, 1 if it has | 201 | * event_logged: 0 if event has not been logged to syslog, 1 if it has |
163 | * sequence #: The unique sequence # for each event. (until it wraps) | 202 | * sequence #: The unique sequence # for each event. (until it wraps) |
164 | * error log: The error log from event_scan | 203 | * error log: The error log from event_scan |
165 | */ | 204 | */ |
166 | int nvram_write_error_log(char * buff, int length, | 205 | int nvram_write_os_partition(struct nvram_os_partition *part, char * buff, |
167 | unsigned int err_type, unsigned int error_log_cnt) | 206 | int length, unsigned int err_type, unsigned int error_log_cnt) |
168 | { | 207 | { |
169 | int rc; | 208 | int rc; |
170 | loff_t tmp_index; | 209 | loff_t tmp_index; |
171 | struct err_log_info info; | 210 | struct err_log_info info; |
172 | 211 | ||
173 | if (nvram_error_log_index == -1) { | 212 | if (part->index == -1) { |
174 | return -ESPIPE; | 213 | return -ESPIPE; |
175 | } | 214 | } |
176 | 215 | ||
177 | if (length > nvram_error_log_size) { | 216 | if (length > part->size) { |
178 | length = nvram_error_log_size; | 217 | length = part->size; |
179 | } | 218 | } |
180 | 219 | ||
181 | info.error_type = err_type; | 220 | info.error_type = err_type; |
182 | info.seq_num = error_log_cnt; | 221 | info.seq_num = error_log_cnt; |
183 | 222 | ||
184 | tmp_index = nvram_error_log_index; | 223 | tmp_index = part->index; |
185 | 224 | ||
186 | rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index); | 225 | rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index); |
187 | if (rc <= 0) { | 226 | if (rc <= 0) { |
188 | printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); | 227 | pr_err("%s: Failed nvram_write (%d)\n", __FUNCTION__, rc); |
189 | return rc; | 228 | return rc; |
190 | } | 229 | } |
191 | 230 | ||
192 | rc = ppc_md.nvram_write(buff, length, &tmp_index); | 231 | rc = ppc_md.nvram_write(buff, length, &tmp_index); |
193 | if (rc <= 0) { | 232 | if (rc <= 0) { |
194 | printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc); | 233 | pr_err("%s: Failed nvram_write (%d)\n", __FUNCTION__, rc); |
195 | return rc; | 234 | return rc; |
196 | } | 235 | } |
197 | 236 | ||
198 | return 0; | 237 | return 0; |
199 | } | 238 | } |
200 | 239 | ||
240 | int nvram_write_error_log(char * buff, int length, | ||
241 | unsigned int err_type, unsigned int error_log_cnt) | ||
242 | { | ||
243 | int rc = nvram_write_os_partition(&rtas_log_partition, buff, length, | ||
244 | err_type, error_log_cnt); | ||
245 | if (!rc) | ||
246 | last_unread_rtas_event = get_seconds(); | ||
247 | return rc; | ||
248 | } | ||
249 | |||
201 | /* nvram_read_error_log | 250 | /* nvram_read_error_log |
202 | * | 251 | * |
203 | * Reads nvram for error log for at most 'length' | 252 | * Reads nvram for error log for at most 'length' |
@@ -209,13 +258,13 @@ int nvram_read_error_log(char * buff, int length, | |||
209 | loff_t tmp_index; | 258 | loff_t tmp_index; |
210 | struct err_log_info info; | 259 | struct err_log_info info; |
211 | 260 | ||
212 | if (nvram_error_log_index == -1) | 261 | if (rtas_log_partition.index == -1) |
213 | return -1; | 262 | return -1; |
214 | 263 | ||
215 | if (length > nvram_error_log_size) | 264 | if (length > rtas_log_partition.size) |
216 | length = nvram_error_log_size; | 265 | length = rtas_log_partition.size; |
217 | 266 | ||
218 | tmp_index = nvram_error_log_index; | 267 | tmp_index = rtas_log_partition.index; |
219 | 268 | ||
220 | rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index); | 269 | rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index); |
221 | if (rc <= 0) { | 270 | if (rc <= 0) { |
@@ -244,37 +293,40 @@ int nvram_clear_error_log(void) | |||
244 | int clear_word = ERR_FLAG_ALREADY_LOGGED; | 293 | int clear_word = ERR_FLAG_ALREADY_LOGGED; |
245 | int rc; | 294 | int rc; |
246 | 295 | ||
247 | if (nvram_error_log_index == -1) | 296 | if (rtas_log_partition.index == -1) |
248 | return -1; | 297 | return -1; |
249 | 298 | ||
250 | tmp_index = nvram_error_log_index; | 299 | tmp_index = rtas_log_partition.index; |
251 | 300 | ||
252 | rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index); | 301 | rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index); |
253 | if (rc <= 0) { | 302 | if (rc <= 0) { |
254 | printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc); | 303 | printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc); |
255 | return rc; | 304 | return rc; |
256 | } | 305 | } |
306 | last_unread_rtas_event = 0; | ||
257 | 307 | ||
258 | return 0; | 308 | return 0; |
259 | } | 309 | } |
260 | 310 | ||
261 | /* pseries_nvram_init_log_partition | 311 | /* pseries_nvram_init_os_partition |
262 | * | 312 | * |
263 | * This will setup the partition we need for buffering the | 313 | * This sets up a partition with an "OS" signature. |
264 | * error logs and cleanup partitions if needed. | ||
265 | * | 314 | * |
266 | * The general strategy is the following: | 315 | * The general strategy is the following: |
267 | * 1.) If there is log partition large enough then use it. | 316 | * 1.) If a partition with the indicated name already exists... |
268 | * 2.) If there is none large enough, search | 317 | * - If it's large enough, use it. |
269 | * for a free partition that is large enough. | 318 | * - Otherwise, recycle it and keep going. |
270 | * 3.) If there is not a free partition large enough remove | 319 | * 2.) Search for a free partition that is large enough. |
271 | * _all_ OS partitions and consolidate the space. | 320 | * 3.) If there's not a free partition large enough, recycle any obsolete |
272 | * 4.) Will first try getting a chunk that will satisfy the maximum | 321 | * OS partitions and try again. |
273 | * error log size (NVRAM_MAX_REQ). | 322 | * 4.) Will first try getting a chunk that will satisfy the requested size. |
274 | * 5.) If the max chunk cannot be allocated then try finding a chunk | 323 | * 5.) If a chunk of the requested size cannot be allocated, then try finding |
275 | * that will satisfy the minum needed (NVRAM_MIN_REQ). | 324 | * a chunk that will satisfy the minum needed. |
325 | * | ||
326 | * Returns 0 on success, else -1. | ||
276 | */ | 327 | */ |
277 | static int __init pseries_nvram_init_log_partition(void) | 328 | static int __init pseries_nvram_init_os_partition(struct nvram_os_partition |
329 | *part) | ||
278 | { | 330 | { |
279 | loff_t p; | 331 | loff_t p; |
280 | int size; | 332 | int size; |
@@ -282,47 +334,76 @@ static int __init pseries_nvram_init_log_partition(void) | |||
282 | /* Scan nvram for partitions */ | 334 | /* Scan nvram for partitions */ |
283 | nvram_scan_partitions(); | 335 | nvram_scan_partitions(); |
284 | 336 | ||
285 | /* Lookg for ours */ | 337 | /* Look for ours */ |
286 | p = nvram_find_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, &size); | 338 | p = nvram_find_partition(part->name, NVRAM_SIG_OS, &size); |
287 | 339 | ||
288 | /* Found one but too small, remove it */ | 340 | /* Found one but too small, remove it */ |
289 | if (p && size < NVRAM_MIN_REQ) { | 341 | if (p && size < part->min_size) { |
290 | pr_info("nvram: Found too small "NVRAM_LOG_PART_NAME" partition" | 342 | pr_info("nvram: Found too small %s partition," |
291 | ",removing it..."); | 343 | " removing it...\n", part->name); |
292 | nvram_remove_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS); | 344 | nvram_remove_partition(part->name, NVRAM_SIG_OS, NULL); |
293 | p = 0; | 345 | p = 0; |
294 | } | 346 | } |
295 | 347 | ||
296 | /* Create one if we didn't find */ | 348 | /* Create one if we didn't find */ |
297 | if (!p) { | 349 | if (!p) { |
298 | p = nvram_create_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, | 350 | p = nvram_create_partition(part->name, NVRAM_SIG_OS, |
299 | NVRAM_MAX_REQ, NVRAM_MIN_REQ); | 351 | part->req_size, part->min_size); |
300 | /* No room for it, try to get rid of any OS partition | ||
301 | * and try again | ||
302 | */ | ||
303 | if (p == -ENOSPC) { | 352 | if (p == -ENOSPC) { |
304 | pr_info("nvram: No room to create "NVRAM_LOG_PART_NAME | 353 | pr_info("nvram: No room to create %s partition, " |
305 | " partition, deleting all OS partitions..."); | 354 | "deleting any obsolete OS partitions...\n", |
306 | nvram_remove_partition(NULL, NVRAM_SIG_OS); | 355 | part->name); |
307 | p = nvram_create_partition(NVRAM_LOG_PART_NAME, | 356 | nvram_remove_partition(NULL, NVRAM_SIG_OS, |
308 | NVRAM_SIG_OS, NVRAM_MAX_REQ, | 357 | pseries_nvram_os_partitions); |
309 | NVRAM_MIN_REQ); | 358 | p = nvram_create_partition(part->name, NVRAM_SIG_OS, |
359 | part->req_size, part->min_size); | ||
310 | } | 360 | } |
311 | } | 361 | } |
312 | 362 | ||
313 | if (p <= 0) { | 363 | if (p <= 0) { |
314 | pr_err("nvram: Failed to find or create "NVRAM_LOG_PART_NAME | 364 | pr_err("nvram: Failed to find or create %s" |
315 | " partition, err %d\n", (int)p); | 365 | " partition, err %d\n", part->name, (int)p); |
316 | return 0; | 366 | return -1; |
317 | } | 367 | } |
318 | 368 | ||
319 | nvram_error_log_index = p; | 369 | part->index = p; |
320 | nvram_error_log_size = nvram_get_partition_size(p) - | 370 | part->size = nvram_get_partition_size(p) - sizeof(struct err_log_info); |
321 | sizeof(struct err_log_info); | ||
322 | 371 | ||
323 | return 0; | 372 | return 0; |
324 | } | 373 | } |
325 | machine_arch_initcall(pseries, pseries_nvram_init_log_partition); | 374 | |
375 | static void __init nvram_init_oops_partition(int rtas_partition_exists) | ||
376 | { | ||
377 | int rc; | ||
378 | |||
379 | rc = pseries_nvram_init_os_partition(&oops_log_partition); | ||
380 | if (rc != 0) { | ||
381 | if (!rtas_partition_exists) | ||
382 | return; | ||
383 | pr_notice("nvram: Using %s partition to log both" | ||
384 | " RTAS errors and oops/panic reports\n", | ||
385 | rtas_log_partition.name); | ||
386 | memcpy(&oops_log_partition, &rtas_log_partition, | ||
387 | sizeof(rtas_log_partition)); | ||
388 | } | ||
389 | oops_buf = kmalloc(oops_log_partition.size, GFP_KERNEL); | ||
390 | rc = kmsg_dump_register(&nvram_kmsg_dumper); | ||
391 | if (rc != 0) { | ||
392 | pr_err("nvram: kmsg_dump_register() failed; returned %d\n", rc); | ||
393 | kfree(oops_buf); | ||
394 | return; | ||
395 | } | ||
396 | } | ||
397 | |||
398 | static int __init pseries_nvram_init_log_partitions(void) | ||
399 | { | ||
400 | int rc; | ||
401 | |||
402 | rc = pseries_nvram_init_os_partition(&rtas_log_partition); | ||
403 | nvram_init_oops_partition(rc == 0); | ||
404 | return 0; | ||
405 | } | ||
406 | machine_arch_initcall(pseries, pseries_nvram_init_log_partitions); | ||
326 | 407 | ||
327 | int __init pSeries_nvram_init(void) | 408 | int __init pSeries_nvram_init(void) |
328 | { | 409 | { |
@@ -353,3 +434,59 @@ int __init pSeries_nvram_init(void) | |||
353 | 434 | ||
354 | return 0; | 435 | return 0; |
355 | } | 436 | } |
437 | |||
438 | /* | ||
439 | * Try to capture the last capture_len bytes of the printk buffer. Return | ||
440 | * the amount actually captured. | ||
441 | */ | ||
442 | static size_t capture_last_msgs(const char *old_msgs, size_t old_len, | ||
443 | const char *new_msgs, size_t new_len, | ||
444 | char *captured, size_t capture_len) | ||
445 | { | ||
446 | if (new_len >= capture_len) { | ||
447 | memcpy(captured, new_msgs + (new_len - capture_len), | ||
448 | capture_len); | ||
449 | return capture_len; | ||
450 | } else { | ||
451 | /* Grab the end of old_msgs. */ | ||
452 | size_t old_tail_len = min(old_len, capture_len - new_len); | ||
453 | memcpy(captured, old_msgs + (old_len - old_tail_len), | ||
454 | old_tail_len); | ||
455 | memcpy(captured + old_tail_len, new_msgs, new_len); | ||
456 | return old_tail_len + new_len; | ||
457 | } | ||
458 | } | ||
459 | |||
460 | /* | ||
461 | * Are we using the ibm,rtas-log for oops/panic reports? And if so, | ||
462 | * would logging this oops/panic overwrite an RTAS event that rtas_errd | ||
463 | * hasn't had a chance to read and process? Return 1 if so, else 0. | ||
464 | * | ||
465 | * We assume that if rtas_errd hasn't read the RTAS event in | ||
466 | * NVRAM_RTAS_READ_TIMEOUT seconds, it's probably not going to. | ||
467 | */ | ||
468 | static int clobbering_unread_rtas_event(void) | ||
469 | { | ||
470 | return (oops_log_partition.index == rtas_log_partition.index | ||
471 | && last_unread_rtas_event | ||
472 | && get_seconds() - last_unread_rtas_event <= | ||
473 | NVRAM_RTAS_READ_TIMEOUT); | ||
474 | } | ||
475 | |||
476 | /* our kmsg_dump callback */ | ||
477 | static void oops_to_nvram(struct kmsg_dumper *dumper, | ||
478 | enum kmsg_dump_reason reason, | ||
479 | const char *old_msgs, unsigned long old_len, | ||
480 | const char *new_msgs, unsigned long new_len) | ||
481 | { | ||
482 | static unsigned int oops_count = 0; | ||
483 | size_t text_len; | ||
484 | |||
485 | if (clobbering_unread_rtas_event()) | ||
486 | return; | ||
487 | |||
488 | text_len = capture_last_msgs(old_msgs, old_len, new_msgs, new_len, | ||
489 | oops_buf, oops_log_partition.size); | ||
490 | (void) nvram_write_os_partition(&oops_log_partition, oops_buf, | ||
491 | (int) text_len, ERR_TYPE_KERNEL_PANIC, ++oops_count); | ||
492 | } | ||
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index d345bfd56bbe..2a0089a2c829 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c | |||
@@ -114,10 +114,13 @@ static void __init fwnmi_init(void) | |||
114 | 114 | ||
115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) | 115 | static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc) |
116 | { | 116 | { |
117 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
117 | unsigned int cascade_irq = i8259_irq(); | 118 | unsigned int cascade_irq = i8259_irq(); |
119 | |||
118 | if (cascade_irq != NO_IRQ) | 120 | if (cascade_irq != NO_IRQ) |
119 | generic_handle_irq(cascade_irq); | 121 | generic_handle_irq(cascade_irq); |
120 | desc->chip->eoi(irq); | 122 | |
123 | chip->irq_eoi(&desc->irq_data); | ||
121 | } | 124 | } |
122 | 125 | ||
123 | static void __init pseries_setup_i8259_cascade(void) | 126 | static void __init pseries_setup_i8259_cascade(void) |
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 7b96e5a270ce..01fea46c0335 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c | |||
@@ -202,20 +202,20 @@ static int get_irq_server(unsigned int virq, const struct cpumask *cpumask, | |||
202 | #define get_irq_server(virq, cpumask, strict_check) (default_server) | 202 | #define get_irq_server(virq, cpumask, strict_check) (default_server) |
203 | #endif | 203 | #endif |
204 | 204 | ||
205 | static void xics_unmask_irq(unsigned int virq) | 205 | static void xics_unmask_irq(struct irq_data *d) |
206 | { | 206 | { |
207 | unsigned int irq; | 207 | unsigned int irq; |
208 | int call_status; | 208 | int call_status; |
209 | int server; | 209 | int server; |
210 | 210 | ||
211 | pr_devel("xics: unmask virq %d\n", virq); | 211 | pr_devel("xics: unmask virq %d\n", d->irq); |
212 | 212 | ||
213 | irq = (unsigned int)irq_map[virq].hwirq; | 213 | irq = (unsigned int)irq_map[d->irq].hwirq; |
214 | pr_devel(" -> map to hwirq 0x%x\n", irq); | 214 | pr_devel(" -> map to hwirq 0x%x\n", irq); |
215 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 215 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
216 | return; | 216 | return; |
217 | 217 | ||
218 | server = get_irq_server(virq, irq_to_desc(virq)->affinity, 0); | 218 | server = get_irq_server(d->irq, d->affinity, 0); |
219 | 219 | ||
220 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, | 220 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server, |
221 | DEFAULT_PRIORITY); | 221 | DEFAULT_PRIORITY); |
@@ -235,61 +235,61 @@ static void xics_unmask_irq(unsigned int virq) | |||
235 | } | 235 | } |
236 | } | 236 | } |
237 | 237 | ||
238 | static unsigned int xics_startup(unsigned int virq) | 238 | static unsigned int xics_startup(struct irq_data *d) |
239 | { | 239 | { |
240 | /* | 240 | /* |
241 | * The generic MSI code returns with the interrupt disabled on the | 241 | * The generic MSI code returns with the interrupt disabled on the |
242 | * card, using the MSI mask bits. Firmware doesn't appear to unmask | 242 | * card, using the MSI mask bits. Firmware doesn't appear to unmask |
243 | * at that level, so we do it here by hand. | 243 | * at that level, so we do it here by hand. |
244 | */ | 244 | */ |
245 | if (irq_to_desc(virq)->msi_desc) | 245 | if (d->msi_desc) |
246 | unmask_msi_irq(irq_get_irq_data(virq)); | 246 | unmask_msi_irq(d); |
247 | 247 | ||
248 | /* unmask it */ | 248 | /* unmask it */ |
249 | xics_unmask_irq(virq); | 249 | xics_unmask_irq(d); |
250 | return 0; | 250 | return 0; |
251 | } | 251 | } |
252 | 252 | ||
253 | static void xics_mask_real_irq(unsigned int irq) | 253 | static void xics_mask_real_irq(struct irq_data *d) |
254 | { | 254 | { |
255 | int call_status; | 255 | int call_status; |
256 | 256 | ||
257 | if (irq == XICS_IPI) | 257 | if (d->irq == XICS_IPI) |
258 | return; | 258 | return; |
259 | 259 | ||
260 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq); | 260 | call_status = rtas_call(ibm_int_off, 1, 1, NULL, d->irq); |
261 | if (call_status != 0) { | 261 | if (call_status != 0) { |
262 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", | 262 | printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n", |
263 | __func__, irq, call_status); | 263 | __func__, d->irq, call_status); |
264 | return; | 264 | return; |
265 | } | 265 | } |
266 | 266 | ||
267 | /* Have to set XIVE to 0xff to be able to remove a slot */ | 267 | /* Have to set XIVE to 0xff to be able to remove a slot */ |
268 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, | 268 | call_status = rtas_call(ibm_set_xive, 3, 1, NULL, d->irq, |
269 | default_server, 0xff); | 269 | default_server, 0xff); |
270 | if (call_status != 0) { | 270 | if (call_status != 0) { |
271 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", | 271 | printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n", |
272 | __func__, irq, call_status); | 272 | __func__, d->irq, call_status); |
273 | return; | 273 | return; |
274 | } | 274 | } |
275 | } | 275 | } |
276 | 276 | ||
277 | static void xics_mask_irq(unsigned int virq) | 277 | static void xics_mask_irq(struct irq_data *d) |
278 | { | 278 | { |
279 | unsigned int irq; | 279 | unsigned int irq; |
280 | 280 | ||
281 | pr_devel("xics: mask virq %d\n", virq); | 281 | pr_devel("xics: mask virq %d\n", d->irq); |
282 | 282 | ||
283 | irq = (unsigned int)irq_map[virq].hwirq; | 283 | irq = (unsigned int)irq_map[d->irq].hwirq; |
284 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 284 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
285 | return; | 285 | return; |
286 | xics_mask_real_irq(irq); | 286 | xics_mask_real_irq(d); |
287 | } | 287 | } |
288 | 288 | ||
289 | static void xics_mask_unknown_vec(unsigned int vec) | 289 | static void xics_mask_unknown_vec(unsigned int vec) |
290 | { | 290 | { |
291 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); | 291 | printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec); |
292 | xics_mask_real_irq(vec); | 292 | xics_mask_real_irq(irq_get_irq_data(vec)); |
293 | } | 293 | } |
294 | 294 | ||
295 | static inline unsigned int xics_xirr_vector(unsigned int xirr) | 295 | static inline unsigned int xics_xirr_vector(unsigned int xirr) |
@@ -371,30 +371,31 @@ static unsigned char pop_cppr(void) | |||
371 | return os_cppr->stack[--os_cppr->index]; | 371 | return os_cppr->stack[--os_cppr->index]; |
372 | } | 372 | } |
373 | 373 | ||
374 | static void xics_eoi_direct(unsigned int virq) | 374 | static void xics_eoi_direct(struct irq_data *d) |
375 | { | 375 | { |
376 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; | 376 | unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; |
377 | 377 | ||
378 | iosync(); | 378 | iosync(); |
379 | direct_xirr_info_set((pop_cppr() << 24) | irq); | 379 | direct_xirr_info_set((pop_cppr() << 24) | irq); |
380 | } | 380 | } |
381 | 381 | ||
382 | static void xics_eoi_lpar(unsigned int virq) | 382 | static void xics_eoi_lpar(struct irq_data *d) |
383 | { | 383 | { |
384 | unsigned int irq = (unsigned int)irq_map[virq].hwirq; | 384 | unsigned int irq = (unsigned int)irq_map[d->irq].hwirq; |
385 | 385 | ||
386 | iosync(); | 386 | iosync(); |
387 | lpar_xirr_info_set((pop_cppr() << 24) | irq); | 387 | lpar_xirr_info_set((pop_cppr() << 24) | irq); |
388 | } | 388 | } |
389 | 389 | ||
390 | static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | 390 | static int |
391 | xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force) | ||
391 | { | 392 | { |
392 | unsigned int irq; | 393 | unsigned int irq; |
393 | int status; | 394 | int status; |
394 | int xics_status[2]; | 395 | int xics_status[2]; |
395 | int irq_server; | 396 | int irq_server; |
396 | 397 | ||
397 | irq = (unsigned int)irq_map[virq].hwirq; | 398 | irq = (unsigned int)irq_map[d->irq].hwirq; |
398 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 399 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
399 | return -1; | 400 | return -1; |
400 | 401 | ||
@@ -406,13 +407,13 @@ static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | |||
406 | return -1; | 407 | return -1; |
407 | } | 408 | } |
408 | 409 | ||
409 | irq_server = get_irq_server(virq, cpumask, 1); | 410 | irq_server = get_irq_server(d->irq, cpumask, 1); |
410 | if (irq_server == -1) { | 411 | if (irq_server == -1) { |
411 | char cpulist[128]; | 412 | char cpulist[128]; |
412 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); | 413 | cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask); |
413 | printk(KERN_WARNING | 414 | printk(KERN_WARNING |
414 | "%s: No online cpus in the mask %s for irq %d\n", | 415 | "%s: No online cpus in the mask %s for irq %d\n", |
415 | __func__, cpulist, virq); | 416 | __func__, cpulist, d->irq); |
416 | return -1; | 417 | return -1; |
417 | } | 418 | } |
418 | 419 | ||
@@ -430,20 +431,20 @@ static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask) | |||
430 | 431 | ||
431 | static struct irq_chip xics_pic_direct = { | 432 | static struct irq_chip xics_pic_direct = { |
432 | .name = "XICS", | 433 | .name = "XICS", |
433 | .startup = xics_startup, | 434 | .irq_startup = xics_startup, |
434 | .mask = xics_mask_irq, | 435 | .irq_mask = xics_mask_irq, |
435 | .unmask = xics_unmask_irq, | 436 | .irq_unmask = xics_unmask_irq, |
436 | .eoi = xics_eoi_direct, | 437 | .irq_eoi = xics_eoi_direct, |
437 | .set_affinity = xics_set_affinity | 438 | .irq_set_affinity = xics_set_affinity |
438 | }; | 439 | }; |
439 | 440 | ||
440 | static struct irq_chip xics_pic_lpar = { | 441 | static struct irq_chip xics_pic_lpar = { |
441 | .name = "XICS", | 442 | .name = "XICS", |
442 | .startup = xics_startup, | 443 | .irq_startup = xics_startup, |
443 | .mask = xics_mask_irq, | 444 | .irq_mask = xics_mask_irq, |
444 | .unmask = xics_unmask_irq, | 445 | .irq_unmask = xics_unmask_irq, |
445 | .eoi = xics_eoi_lpar, | 446 | .irq_eoi = xics_eoi_lpar, |
446 | .set_affinity = xics_set_affinity | 447 | .irq_set_affinity = xics_set_affinity |
447 | }; | 448 | }; |
448 | 449 | ||
449 | 450 | ||
@@ -890,6 +891,7 @@ void xics_migrate_irqs_away(void) | |||
890 | 891 | ||
891 | for_each_irq(virq) { | 892 | for_each_irq(virq) { |
892 | struct irq_desc *desc; | 893 | struct irq_desc *desc; |
894 | struct irq_chip *chip; | ||
893 | int xics_status[2]; | 895 | int xics_status[2]; |
894 | int status; | 896 | int status; |
895 | unsigned long flags; | 897 | unsigned long flags; |
@@ -903,12 +905,15 @@ void xics_migrate_irqs_away(void) | |||
903 | /* We need to get IPIs still. */ | 905 | /* We need to get IPIs still. */ |
904 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) | 906 | if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS) |
905 | continue; | 907 | continue; |
908 | |||
906 | desc = irq_to_desc(virq); | 909 | desc = irq_to_desc(virq); |
907 | 910 | ||
908 | /* We only need to migrate enabled IRQS */ | 911 | /* We only need to migrate enabled IRQS */ |
909 | if (desc == NULL || desc->chip == NULL | 912 | if (desc == NULL || desc->action == NULL) |
910 | || desc->action == NULL | 913 | continue; |
911 | || desc->chip->set_affinity == NULL) | 914 | |
915 | chip = get_irq_desc_chip(desc); | ||
916 | if (chip == NULL || chip->irq_set_affinity == NULL) | ||
912 | continue; | 917 | continue; |
913 | 918 | ||
914 | raw_spin_lock_irqsave(&desc->lock, flags); | 919 | raw_spin_lock_irqsave(&desc->lock, flags); |
@@ -934,8 +939,8 @@ void xics_migrate_irqs_away(void) | |||
934 | virq, cpu); | 939 | virq, cpu); |
935 | 940 | ||
936 | /* Reset affinity to all cpus */ | 941 | /* Reset affinity to all cpus */ |
937 | cpumask_setall(irq_to_desc(virq)->affinity); | 942 | cpumask_setall(desc->irq_data.affinity); |
938 | desc->chip->set_affinity(virq, cpu_all_mask); | 943 | chip->irq_set_affinity(&desc->irq_data, cpu_all_mask, true); |
939 | unlock: | 944 | unlock: |
940 | raw_spin_unlock_irqrestore(&desc->lock, flags); | 945 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
941 | } | 946 | } |
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c index 00852124ff4a..0476bcc7c3e1 100644 --- a/arch/powerpc/sysdev/cpm1.c +++ b/arch/powerpc/sysdev/cpm1.c | |||
@@ -56,32 +56,32 @@ static cpic8xx_t __iomem *cpic_reg; | |||
56 | 56 | ||
57 | static struct irq_host *cpm_pic_host; | 57 | static struct irq_host *cpm_pic_host; |
58 | 58 | ||
59 | static void cpm_mask_irq(unsigned int irq) | 59 | static void cpm_mask_irq(struct irq_data *d) |
60 | { | 60 | { |
61 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; | 61 | unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; |
62 | 62 | ||
63 | clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | 63 | clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); |
64 | } | 64 | } |
65 | 65 | ||
66 | static void cpm_unmask_irq(unsigned int irq) | 66 | static void cpm_unmask_irq(struct irq_data *d) |
67 | { | 67 | { |
68 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; | 68 | unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; |
69 | 69 | ||
70 | setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); | 70 | setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); |
71 | } | 71 | } |
72 | 72 | ||
73 | static void cpm_end_irq(unsigned int irq) | 73 | static void cpm_end_irq(struct irq_data *d) |
74 | { | 74 | { |
75 | unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; | 75 | unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq; |
76 | 76 | ||
77 | out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); | 77 | out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); |
78 | } | 78 | } |
79 | 79 | ||
80 | static struct irq_chip cpm_pic = { | 80 | static struct irq_chip cpm_pic = { |
81 | .name = "CPM PIC", | 81 | .name = "CPM PIC", |
82 | .mask = cpm_mask_irq, | 82 | .irq_mask = cpm_mask_irq, |
83 | .unmask = cpm_unmask_irq, | 83 | .irq_unmask = cpm_unmask_irq, |
84 | .eoi = cpm_end_irq, | 84 | .irq_eoi = cpm_end_irq, |
85 | }; | 85 | }; |
86 | 86 | ||
87 | int cpm_get_irq(void) | 87 | int cpm_get_irq(void) |
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c index fcea4ff825dd..473032556715 100644 --- a/arch/powerpc/sysdev/cpm2_pic.c +++ b/arch/powerpc/sysdev/cpm2_pic.c | |||
@@ -78,10 +78,10 @@ static const u_char irq_to_siubit[] = { | |||
78 | 24, 25, 26, 27, 28, 29, 30, 31, | 78 | 24, 25, 26, 27, 28, 29, 30, 31, |
79 | }; | 79 | }; |
80 | 80 | ||
81 | static void cpm2_mask_irq(unsigned int virq) | 81 | static void cpm2_mask_irq(struct irq_data *d) |
82 | { | 82 | { |
83 | int bit, word; | 83 | int bit, word; |
84 | unsigned int irq_nr = virq_to_hw(virq); | 84 | unsigned int irq_nr = virq_to_hw(d->irq); |
85 | 85 | ||
86 | bit = irq_to_siubit[irq_nr]; | 86 | bit = irq_to_siubit[irq_nr]; |
87 | word = irq_to_siureg[irq_nr]; | 87 | word = irq_to_siureg[irq_nr]; |
@@ -90,10 +90,10 @@ static void cpm2_mask_irq(unsigned int virq) | |||
90 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); | 90 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); |
91 | } | 91 | } |
92 | 92 | ||
93 | static void cpm2_unmask_irq(unsigned int virq) | 93 | static void cpm2_unmask_irq(struct irq_data *d) |
94 | { | 94 | { |
95 | int bit, word; | 95 | int bit, word; |
96 | unsigned int irq_nr = virq_to_hw(virq); | 96 | unsigned int irq_nr = virq_to_hw(d->irq); |
97 | 97 | ||
98 | bit = irq_to_siubit[irq_nr]; | 98 | bit = irq_to_siubit[irq_nr]; |
99 | word = irq_to_siureg[irq_nr]; | 99 | word = irq_to_siureg[irq_nr]; |
@@ -102,10 +102,10 @@ static void cpm2_unmask_irq(unsigned int virq) | |||
102 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); | 102 | out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); |
103 | } | 103 | } |
104 | 104 | ||
105 | static void cpm2_ack(unsigned int virq) | 105 | static void cpm2_ack(struct irq_data *d) |
106 | { | 106 | { |
107 | int bit, word; | 107 | int bit, word; |
108 | unsigned int irq_nr = virq_to_hw(virq); | 108 | unsigned int irq_nr = virq_to_hw(d->irq); |
109 | 109 | ||
110 | bit = irq_to_siubit[irq_nr]; | 110 | bit = irq_to_siubit[irq_nr]; |
111 | word = irq_to_siureg[irq_nr]; | 111 | word = irq_to_siureg[irq_nr]; |
@@ -113,11 +113,11 @@ static void cpm2_ack(unsigned int virq) | |||
113 | out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit); | 113 | out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit); |
114 | } | 114 | } |
115 | 115 | ||
116 | static void cpm2_end_irq(unsigned int virq) | 116 | static void cpm2_end_irq(struct irq_data *d) |
117 | { | 117 | { |
118 | struct irq_desc *desc; | 118 | struct irq_desc *desc; |
119 | int bit, word; | 119 | int bit, word; |
120 | unsigned int irq_nr = virq_to_hw(virq); | 120 | unsigned int irq_nr = virq_to_hw(d->irq); |
121 | 121 | ||
122 | desc = irq_to_desc(irq_nr); | 122 | desc = irq_to_desc(irq_nr); |
123 | if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) | 123 | if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) |
@@ -137,10 +137,10 @@ static void cpm2_end_irq(unsigned int virq) | |||
137 | } | 137 | } |
138 | } | 138 | } |
139 | 139 | ||
140 | static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type) | 140 | static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type) |
141 | { | 141 | { |
142 | unsigned int src = virq_to_hw(virq); | 142 | unsigned int src = virq_to_hw(d->irq); |
143 | struct irq_desc *desc = irq_to_desc(virq); | 143 | struct irq_desc *desc = irq_to_desc(d->irq); |
144 | unsigned int vold, vnew, edibit; | 144 | unsigned int vold, vnew, edibit; |
145 | 145 | ||
146 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or | 146 | /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or |
@@ -199,11 +199,11 @@ err_sense: | |||
199 | 199 | ||
200 | static struct irq_chip cpm2_pic = { | 200 | static struct irq_chip cpm2_pic = { |
201 | .name = "CPM2 SIU", | 201 | .name = "CPM2 SIU", |
202 | .mask = cpm2_mask_irq, | 202 | .irq_mask = cpm2_mask_irq, |
203 | .unmask = cpm2_unmask_irq, | 203 | .irq_unmask = cpm2_unmask_irq, |
204 | .ack = cpm2_ack, | 204 | .irq_ack = cpm2_ack, |
205 | .eoi = cpm2_end_irq, | 205 | .irq_eoi = cpm2_end_irq, |
206 | .set_type = cpm2_set_irq_type, | 206 | .irq_set_type = cpm2_set_irq_type, |
207 | }; | 207 | }; |
208 | 208 | ||
209 | unsigned int cpm2_get_irq(void) | 209 | unsigned int cpm2_get_irq(void) |
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c index 2b9f0c925326..5f88797dce73 100644 --- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c +++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | |||
@@ -93,14 +93,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev) | |||
93 | l2cache_size = *prop; | 93 | l2cache_size = *prop; |
94 | 94 | ||
95 | sram_params.sram_size = get_cache_sram_size(); | 95 | sram_params.sram_size = get_cache_sram_size(); |
96 | if (sram_params.sram_size <= 0) { | 96 | if ((int)sram_params.sram_size <= 0) { |
97 | dev_err(&dev->dev, | 97 | dev_err(&dev->dev, |
98 | "Entire L2 as cache, Aborting Cache-SRAM stuff\n"); | 98 | "Entire L2 as cache, Aborting Cache-SRAM stuff\n"); |
99 | return -EINVAL; | 99 | return -EINVAL; |
100 | } | 100 | } |
101 | 101 | ||
102 | sram_params.sram_offset = get_cache_sram_offset(); | 102 | sram_params.sram_offset = get_cache_sram_offset(); |
103 | if (sram_params.sram_offset <= 0) { | 103 | if ((int64_t)sram_params.sram_offset <= 0) { |
104 | dev_err(&dev->dev, | 104 | dev_err(&dev->dev, |
105 | "Entire L2 as cache, provide a valid sram offset\n"); | 105 | "Entire L2 as cache, provide a valid sram offset\n"); |
106 | return -EINVAL; | 106 | return -EINVAL; |
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c index ee6a8a52ac71..58e09b2833f2 100644 --- a/arch/powerpc/sysdev/fsl_msi.c +++ b/arch/powerpc/sysdev/fsl_msi.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. |
3 | * | 3 | * |
4 | * Author: Tony Li <tony.li@freescale.com> | 4 | * Author: Tony Li <tony.li@freescale.com> |
5 | * Jason Jin <Jason.jin@freescale.com> | 5 | * Jason Jin <Jason.jin@freescale.com> |
@@ -47,14 +47,14 @@ static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) | |||
47 | * We do not need this actually. The MSIR register has been read once | 47 | * We do not need this actually. The MSIR register has been read once |
48 | * in the cascade interrupt. So, this MSI interrupt has been acked | 48 | * in the cascade interrupt. So, this MSI interrupt has been acked |
49 | */ | 49 | */ |
50 | static void fsl_msi_end_irq(unsigned int virq) | 50 | static void fsl_msi_end_irq(struct irq_data *d) |
51 | { | 51 | { |
52 | } | 52 | } |
53 | 53 | ||
54 | static struct irq_chip fsl_msi_chip = { | 54 | static struct irq_chip fsl_msi_chip = { |
55 | .irq_mask = mask_msi_irq, | 55 | .irq_mask = mask_msi_irq, |
56 | .irq_unmask = unmask_msi_irq, | 56 | .irq_unmask = unmask_msi_irq, |
57 | .ack = fsl_msi_end_irq, | 57 | .irq_ack = fsl_msi_end_irq, |
58 | .name = "FSL-MSI", | 58 | .name = "FSL-MSI", |
59 | }; | 59 | }; |
60 | 60 | ||
@@ -183,6 +183,7 @@ out_free: | |||
183 | 183 | ||
184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | 184 | static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) |
185 | { | 185 | { |
186 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
186 | unsigned int cascade_irq; | 187 | unsigned int cascade_irq; |
187 | struct fsl_msi *msi_data; | 188 | struct fsl_msi *msi_data; |
188 | int msir_index = -1; | 189 | int msir_index = -1; |
@@ -196,11 +197,11 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
196 | 197 | ||
197 | raw_spin_lock(&desc->lock); | 198 | raw_spin_lock(&desc->lock); |
198 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { | 199 | if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { |
199 | if (desc->chip->mask_ack) | 200 | if (chip->irq_mask_ack) |
200 | desc->chip->mask_ack(irq); | 201 | chip->irq_mask_ack(&desc->irq_data); |
201 | else { | 202 | else { |
202 | desc->chip->mask(irq); | 203 | chip->irq_mask(&desc->irq_data); |
203 | desc->chip->ack(irq); | 204 | chip->irq_ack(&desc->irq_data); |
204 | } | 205 | } |
205 | } | 206 | } |
206 | 207 | ||
@@ -238,11 +239,11 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) | |||
238 | 239 | ||
239 | switch (msi_data->feature & FSL_PIC_IP_MASK) { | 240 | switch (msi_data->feature & FSL_PIC_IP_MASK) { |
240 | case FSL_PIC_IP_MPIC: | 241 | case FSL_PIC_IP_MPIC: |
241 | desc->chip->eoi(irq); | 242 | chip->irq_eoi(&desc->irq_data); |
242 | break; | 243 | break; |
243 | case FSL_PIC_IP_IPIC: | 244 | case FSL_PIC_IP_IPIC: |
244 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | 245 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) |
245 | desc->chip->unmask(irq); | 246 | chip->irq_unmask(&desc->irq_data); |
246 | break; | 247 | break; |
247 | } | 248 | } |
248 | unlock: | 249 | unlock: |
@@ -273,18 +274,46 @@ static int fsl_of_msi_remove(struct platform_device *ofdev) | |||
273 | return 0; | 274 | return 0; |
274 | } | 275 | } |
275 | 276 | ||
277 | static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi, | ||
278 | struct platform_device *dev, | ||
279 | int offset, int irq_index) | ||
280 | { | ||
281 | struct fsl_msi_cascade_data *cascade_data = NULL; | ||
282 | int virt_msir; | ||
283 | |||
284 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); | ||
285 | if (virt_msir == NO_IRQ) { | ||
286 | dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n", | ||
287 | __func__, irq_index); | ||
288 | return 0; | ||
289 | } | ||
290 | |||
291 | cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL); | ||
292 | if (!cascade_data) { | ||
293 | dev_err(&dev->dev, "No memory for MSI cascade data\n"); | ||
294 | return -ENOMEM; | ||
295 | } | ||
296 | |||
297 | msi->msi_virqs[irq_index] = virt_msir; | ||
298 | cascade_data->index = offset + irq_index; | ||
299 | cascade_data->msi_data = msi; | ||
300 | set_irq_data(virt_msir, cascade_data); | ||
301 | set_irq_chained_handler(virt_msir, fsl_msi_cascade); | ||
302 | |||
303 | return 0; | ||
304 | } | ||
305 | |||
276 | static int __devinit fsl_of_msi_probe(struct platform_device *dev) | 306 | static int __devinit fsl_of_msi_probe(struct platform_device *dev) |
277 | { | 307 | { |
278 | struct fsl_msi *msi; | 308 | struct fsl_msi *msi; |
279 | struct resource res; | 309 | struct resource res; |
280 | int err, i, count; | 310 | int err, i, j, irq_index, count; |
281 | int rc; | 311 | int rc; |
282 | int virt_msir; | ||
283 | const u32 *p; | 312 | const u32 *p; |
284 | struct fsl_msi_feature *features; | 313 | struct fsl_msi_feature *features; |
285 | struct fsl_msi_cascade_data *cascade_data = NULL; | ||
286 | int len; | 314 | int len; |
287 | u32 offset; | 315 | u32 offset; |
316 | static const u32 all_avail[] = { 0, NR_MSI_IRQS }; | ||
288 | 317 | ||
289 | if (!dev->dev.of_match) | 318 | if (!dev->dev.of_match) |
290 | return -EINVAL; | 319 | return -EINVAL; |
@@ -335,42 +364,34 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev) | |||
335 | goto error_out; | 364 | goto error_out; |
336 | } | 365 | } |
337 | 366 | ||
338 | p = of_get_property(dev->dev.of_node, "interrupts", &count); | 367 | p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); |
339 | if (!p) { | 368 | if (p && len % (2 * sizeof(u32)) != 0) { |
340 | dev_err(&dev->dev, "no interrupts property found on %s\n", | 369 | dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n", |
341 | dev->dev.of_node->full_name); | 370 | __func__); |
342 | err = -ENODEV; | ||
343 | goto error_out; | ||
344 | } | ||
345 | if (count % 8 != 0) { | ||
346 | dev_err(&dev->dev, "Malformed interrupts property on %s\n", | ||
347 | dev->dev.of_node->full_name); | ||
348 | err = -EINVAL; | 371 | err = -EINVAL; |
349 | goto error_out; | 372 | goto error_out; |
350 | } | 373 | } |
351 | offset = 0; | 374 | |
352 | p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); | 375 | if (!p) |
353 | if (p) | 376 | p = all_avail; |
354 | offset = *p / IRQS_PER_MSI_REG; | 377 | |
355 | 378 | for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) { | |
356 | count /= sizeof(u32); | 379 | if (p[i * 2] % IRQS_PER_MSI_REG || |
357 | for (i = 0; i < min(count / 2, NR_MSI_REG); i++) { | 380 | p[i * 2 + 1] % IRQS_PER_MSI_REG) { |
358 | virt_msir = irq_of_parse_and_map(dev->dev.of_node, i); | 381 | printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n", |
359 | if (virt_msir != NO_IRQ) { | 382 | __func__, dev->dev.of_node->full_name, |
360 | cascade_data = kzalloc( | 383 | p[i * 2 + 1], p[i * 2]); |
361 | sizeof(struct fsl_msi_cascade_data), | 384 | err = -EINVAL; |
362 | GFP_KERNEL); | 385 | goto error_out; |
363 | if (!cascade_data) { | 386 | } |
364 | dev_err(&dev->dev, | 387 | |
365 | "No memory for MSI cascade data\n"); | 388 | offset = p[i * 2] / IRQS_PER_MSI_REG; |
366 | err = -ENOMEM; | 389 | count = p[i * 2 + 1] / IRQS_PER_MSI_REG; |
390 | |||
391 | for (j = 0; j < count; j++, irq_index++) { | ||
392 | err = fsl_msi_setup_hwirq(msi, dev, offset, irq_index); | ||
393 | if (err) | ||
367 | goto error_out; | 394 | goto error_out; |
368 | } | ||
369 | msi->msi_virqs[i] = virt_msir; | ||
370 | cascade_data->index = i + offset; | ||
371 | cascade_data->msi_data = msi; | ||
372 | set_irq_data(virt_msir, (void *)cascade_data); | ||
373 | set_irq_chained_handler(virt_msir, fsl_msi_cascade); | ||
374 | } | 395 | } |
375 | } | 396 | } |
376 | 397 | ||
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 818f7c6c8fa1..f8f7f28c6343 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. | 2 | * MPC83xx/85xx/86xx PCI/PCIE support routing. |
3 | * | 3 | * |
4 | * Copyright 2007-2010 Freescale Semiconductor, Inc. | 4 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
5 | * Copyright 2008-2009 MontaVista Software, Inc. | 5 | * Copyright 2008-2009 MontaVista Software, Inc. |
6 | * | 6 | * |
7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> | 7 | * Initial author: Xianghua Xiao <x.xiao@freescale.com> |
@@ -99,7 +99,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
99 | struct resource *rsrc) | 99 | struct resource *rsrc) |
100 | { | 100 | { |
101 | struct ccsr_pci __iomem *pci; | 101 | struct ccsr_pci __iomem *pci; |
102 | int i, j, n, mem_log, win_idx = 2; | 102 | int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; |
103 | u64 mem, sz, paddr_hi = 0; | 103 | u64 mem, sz, paddr_hi = 0; |
104 | u64 paddr_lo = ULLONG_MAX; | 104 | u64 paddr_lo = ULLONG_MAX; |
105 | u32 pcicsrbar = 0, pcicsrbar_sz; | 105 | u32 pcicsrbar = 0, pcicsrbar_sz; |
@@ -109,6 +109,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
109 | 109 | ||
110 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", | 110 | pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", |
111 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); | 111 | (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); |
112 | |||
113 | if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) { | ||
114 | win_idx = 2; | ||
115 | start_idx = 0; | ||
116 | end_idx = 3; | ||
117 | } | ||
118 | |||
112 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); | 119 | pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); |
113 | if (!pci) { | 120 | if (!pci) { |
114 | dev_err(hose->parent, "Unable to map ATMU registers\n"); | 121 | dev_err(hose->parent, "Unable to map ATMU registers\n"); |
@@ -118,7 +125,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
118 | /* Disable all windows (except powar0 since it's ignored) */ | 125 | /* Disable all windows (except powar0 since it's ignored) */ |
119 | for(i = 1; i < 5; i++) | 126 | for(i = 1; i < 5; i++) |
120 | out_be32(&pci->pow[i].powar, 0); | 127 | out_be32(&pci->pow[i].powar, 0); |
121 | for(i = 0; i < 3; i++) | 128 | for (i = start_idx; i < end_idx; i++) |
122 | out_be32(&pci->piw[i].piwar, 0); | 129 | out_be32(&pci->piw[i].piwar, 0); |
123 | 130 | ||
124 | /* Setup outbound MEM window */ | 131 | /* Setup outbound MEM window */ |
@@ -204,7 +211,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose, | |||
204 | mem_log++; | 211 | mem_log++; |
205 | } | 212 | } |
206 | 213 | ||
207 | piwar |= (mem_log - 1); | 214 | piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); |
208 | 215 | ||
209 | /* Setup inbound memory window */ | 216 | /* Setup inbound memory window */ |
210 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); | 217 | out_be32(&pci->piw[win_idx].pitar, 0x00000000); |
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 8ad72a11f77b..a39ed5cc2c5a 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * MPC85xx/86xx PCI Express structure define | 2 | * MPC85xx/86xx PCI Express structure define |
3 | * | 3 | * |
4 | * Copyright 2007 Freescale Semiconductor, Inc | 4 | * Copyright 2007,2011 Freescale Semiconductor, Inc |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms of the GNU General Public License as published by the | 7 | * under the terms of the GNU General Public License as published by the |
@@ -21,6 +21,7 @@ | |||
21 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ | 21 | #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ |
22 | #define PIWAR_READ_SNOOP 0x00050000 | 22 | #define PIWAR_READ_SNOOP 0x00050000 |
23 | #define PIWAR_WRITE_SNOOP 0x00005000 | 23 | #define PIWAR_WRITE_SNOOP 0x00005000 |
24 | #define PIWAR_SZ_MASK 0x0000003f | ||
24 | 25 | ||
25 | /* PCI/PCI Express outbound window reg */ | 26 | /* PCI/PCI Express outbound window reg */ |
26 | struct pci_outbound_window_regs { | 27 | struct pci_outbound_window_regs { |
@@ -49,7 +50,9 @@ struct ccsr_pci { | |||
49 | __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | 50 | __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ |
50 | __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ | 51 | __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ |
51 | __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ | 52 | __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ |
52 | u8 res2[12]; | 53 | __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */ |
54 | __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */ | ||
55 | u8 res2[4]; | ||
53 | __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ | 56 | __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ |
54 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ | 57 | __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ |
55 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ | 58 | __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ |
@@ -62,14 +65,14 @@ struct ccsr_pci { | |||
62 | * in all of the other outbound windows. | 65 | * in all of the other outbound windows. |
63 | */ | 66 | */ |
64 | struct pci_outbound_window_regs pow[5]; | 67 | struct pci_outbound_window_regs pow[5]; |
65 | 68 | u8 res14[96]; | |
66 | u8 res14[256]; | 69 | struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */ |
67 | 70 | u8 res6[96]; | |
68 | /* PCI/PCI Express inbound window 3-1 | 71 | /* PCI/PCI Express inbound window 3-0 |
69 | * inbound window 1 supports only a 32-bit base address and does not | 72 | * inbound window 1 supports only a 32-bit base address and does not |
70 | * define an inbound window base extended address register. | 73 | * define an inbound window base extended address register. |
71 | */ | 74 | */ |
72 | struct pci_inbound_window_regs piw[3]; | 75 | struct pci_inbound_window_regs piw[4]; |
73 | 76 | ||
74 | __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ | 77 | __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ |
75 | u8 res21[4]; | 78 | u8 res21[4]; |
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c index 6323e70e6bf4..aeda4c8d0a0a 100644 --- a/arch/powerpc/sysdev/i8259.c +++ b/arch/powerpc/sysdev/i8259.c | |||
@@ -78,19 +78,19 @@ unsigned int i8259_irq(void) | |||
78 | return irq; | 78 | return irq; |
79 | } | 79 | } |
80 | 80 | ||
81 | static void i8259_mask_and_ack_irq(unsigned int irq_nr) | 81 | static void i8259_mask_and_ack_irq(struct irq_data *d) |
82 | { | 82 | { |
83 | unsigned long flags; | 83 | unsigned long flags; |
84 | 84 | ||
85 | raw_spin_lock_irqsave(&i8259_lock, flags); | 85 | raw_spin_lock_irqsave(&i8259_lock, flags); |
86 | if (irq_nr > 7) { | 86 | if (d->irq > 7) { |
87 | cached_A1 |= 1 << (irq_nr-8); | 87 | cached_A1 |= 1 << (d->irq-8); |
88 | inb(0xA1); /* DUMMY */ | 88 | inb(0xA1); /* DUMMY */ |
89 | outb(cached_A1, 0xA1); | 89 | outb(cached_A1, 0xA1); |
90 | outb(0x20, 0xA0); /* Non-specific EOI */ | 90 | outb(0x20, 0xA0); /* Non-specific EOI */ |
91 | outb(0x20, 0x20); /* Non-specific EOI to cascade */ | 91 | outb(0x20, 0x20); /* Non-specific EOI to cascade */ |
92 | } else { | 92 | } else { |
93 | cached_21 |= 1 << irq_nr; | 93 | cached_21 |= 1 << d->irq; |
94 | inb(0x21); /* DUMMY */ | 94 | inb(0x21); /* DUMMY */ |
95 | outb(cached_21, 0x21); | 95 | outb(cached_21, 0x21); |
96 | outb(0x20, 0x20); /* Non-specific EOI */ | 96 | outb(0x20, 0x20); /* Non-specific EOI */ |
@@ -104,42 +104,42 @@ static void i8259_set_irq_mask(int irq_nr) | |||
104 | outb(cached_21,0x21); | 104 | outb(cached_21,0x21); |
105 | } | 105 | } |
106 | 106 | ||
107 | static void i8259_mask_irq(unsigned int irq_nr) | 107 | static void i8259_mask_irq(struct irq_data *d) |
108 | { | 108 | { |
109 | unsigned long flags; | 109 | unsigned long flags; |
110 | 110 | ||
111 | pr_debug("i8259_mask_irq(%d)\n", irq_nr); | 111 | pr_debug("i8259_mask_irq(%d)\n", d->irq); |
112 | 112 | ||
113 | raw_spin_lock_irqsave(&i8259_lock, flags); | 113 | raw_spin_lock_irqsave(&i8259_lock, flags); |
114 | if (irq_nr < 8) | 114 | if (d->irq < 8) |
115 | cached_21 |= 1 << irq_nr; | 115 | cached_21 |= 1 << d->irq; |
116 | else | 116 | else |
117 | cached_A1 |= 1 << (irq_nr-8); | 117 | cached_A1 |= 1 << (d->irq-8); |
118 | i8259_set_irq_mask(irq_nr); | 118 | i8259_set_irq_mask(d->irq); |
119 | raw_spin_unlock_irqrestore(&i8259_lock, flags); | 119 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
120 | } | 120 | } |
121 | 121 | ||
122 | static void i8259_unmask_irq(unsigned int irq_nr) | 122 | static void i8259_unmask_irq(struct irq_data *d) |
123 | { | 123 | { |
124 | unsigned long flags; | 124 | unsigned long flags; |
125 | 125 | ||
126 | pr_debug("i8259_unmask_irq(%d)\n", irq_nr); | 126 | pr_debug("i8259_unmask_irq(%d)\n", d->irq); |
127 | 127 | ||
128 | raw_spin_lock_irqsave(&i8259_lock, flags); | 128 | raw_spin_lock_irqsave(&i8259_lock, flags); |
129 | if (irq_nr < 8) | 129 | if (d->irq < 8) |
130 | cached_21 &= ~(1 << irq_nr); | 130 | cached_21 &= ~(1 << d->irq); |
131 | else | 131 | else |
132 | cached_A1 &= ~(1 << (irq_nr-8)); | 132 | cached_A1 &= ~(1 << (d->irq-8)); |
133 | i8259_set_irq_mask(irq_nr); | 133 | i8259_set_irq_mask(d->irq); |
134 | raw_spin_unlock_irqrestore(&i8259_lock, flags); | 134 | raw_spin_unlock_irqrestore(&i8259_lock, flags); |
135 | } | 135 | } |
136 | 136 | ||
137 | static struct irq_chip i8259_pic = { | 137 | static struct irq_chip i8259_pic = { |
138 | .name = "i8259", | 138 | .name = "i8259", |
139 | .mask = i8259_mask_irq, | 139 | .irq_mask = i8259_mask_irq, |
140 | .disable = i8259_mask_irq, | 140 | .irq_disable = i8259_mask_irq, |
141 | .unmask = i8259_unmask_irq, | 141 | .irq_unmask = i8259_unmask_irq, |
142 | .mask_ack = i8259_mask_and_ack_irq, | 142 | .irq_mask_ack = i8259_mask_and_ack_irq, |
143 | }; | 143 | }; |
144 | 144 | ||
145 | static struct resource pic1_iores = { | 145 | static struct resource pic1_iores = { |
@@ -188,7 +188,7 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq, | |||
188 | static void i8259_host_unmap(struct irq_host *h, unsigned int virq) | 188 | static void i8259_host_unmap(struct irq_host *h, unsigned int virq) |
189 | { | 189 | { |
190 | /* Make sure irq is masked in hardware */ | 190 | /* Make sure irq is masked in hardware */ |
191 | i8259_mask_irq(virq); | 191 | i8259_mask_irq(irq_get_irq_data(virq)); |
192 | 192 | ||
193 | /* remove chip and handler */ | 193 | /* remove chip and handler */ |
194 | set_irq_chip_and_handler(virq, NULL, NULL); | 194 | set_irq_chip_and_handler(virq, NULL, NULL); |
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c index d7b9b9c69287..497047dc986e 100644 --- a/arch/powerpc/sysdev/ipic.c +++ b/arch/powerpc/sysdev/ipic.c | |||
@@ -523,10 +523,10 @@ static inline struct ipic * ipic_from_irq(unsigned int virq) | |||
523 | 523 | ||
524 | #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) | 524 | #define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
525 | 525 | ||
526 | static void ipic_unmask_irq(unsigned int virq) | 526 | static void ipic_unmask_irq(struct irq_data *d) |
527 | { | 527 | { |
528 | struct ipic *ipic = ipic_from_irq(virq); | 528 | struct ipic *ipic = ipic_from_irq(d->irq); |
529 | unsigned int src = ipic_irq_to_hw(virq); | 529 | unsigned int src = ipic_irq_to_hw(d->irq); |
530 | unsigned long flags; | 530 | unsigned long flags; |
531 | u32 temp; | 531 | u32 temp; |
532 | 532 | ||
@@ -539,10 +539,10 @@ static void ipic_unmask_irq(unsigned int virq) | |||
539 | raw_spin_unlock_irqrestore(&ipic_lock, flags); | 539 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
540 | } | 540 | } |
541 | 541 | ||
542 | static void ipic_mask_irq(unsigned int virq) | 542 | static void ipic_mask_irq(struct irq_data *d) |
543 | { | 543 | { |
544 | struct ipic *ipic = ipic_from_irq(virq); | 544 | struct ipic *ipic = ipic_from_irq(d->irq); |
545 | unsigned int src = ipic_irq_to_hw(virq); | 545 | unsigned int src = ipic_irq_to_hw(d->irq); |
546 | unsigned long flags; | 546 | unsigned long flags; |
547 | u32 temp; | 547 | u32 temp; |
548 | 548 | ||
@@ -559,10 +559,10 @@ static void ipic_mask_irq(unsigned int virq) | |||
559 | raw_spin_unlock_irqrestore(&ipic_lock, flags); | 559 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
560 | } | 560 | } |
561 | 561 | ||
562 | static void ipic_ack_irq(unsigned int virq) | 562 | static void ipic_ack_irq(struct irq_data *d) |
563 | { | 563 | { |
564 | struct ipic *ipic = ipic_from_irq(virq); | 564 | struct ipic *ipic = ipic_from_irq(d->irq); |
565 | unsigned int src = ipic_irq_to_hw(virq); | 565 | unsigned int src = ipic_irq_to_hw(d->irq); |
566 | unsigned long flags; | 566 | unsigned long flags; |
567 | u32 temp; | 567 | u32 temp; |
568 | 568 | ||
@@ -578,10 +578,10 @@ static void ipic_ack_irq(unsigned int virq) | |||
578 | raw_spin_unlock_irqrestore(&ipic_lock, flags); | 578 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
579 | } | 579 | } |
580 | 580 | ||
581 | static void ipic_mask_irq_and_ack(unsigned int virq) | 581 | static void ipic_mask_irq_and_ack(struct irq_data *d) |
582 | { | 582 | { |
583 | struct ipic *ipic = ipic_from_irq(virq); | 583 | struct ipic *ipic = ipic_from_irq(d->irq); |
584 | unsigned int src = ipic_irq_to_hw(virq); | 584 | unsigned int src = ipic_irq_to_hw(d->irq); |
585 | unsigned long flags; | 585 | unsigned long flags; |
586 | u32 temp; | 586 | u32 temp; |
587 | 587 | ||
@@ -601,11 +601,11 @@ static void ipic_mask_irq_and_ack(unsigned int virq) | |||
601 | raw_spin_unlock_irqrestore(&ipic_lock, flags); | 601 | raw_spin_unlock_irqrestore(&ipic_lock, flags); |
602 | } | 602 | } |
603 | 603 | ||
604 | static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) | 604 | static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
605 | { | 605 | { |
606 | struct ipic *ipic = ipic_from_irq(virq); | 606 | struct ipic *ipic = ipic_from_irq(d->irq); |
607 | unsigned int src = ipic_irq_to_hw(virq); | 607 | unsigned int src = ipic_irq_to_hw(d->irq); |
608 | struct irq_desc *desc = irq_to_desc(virq); | 608 | struct irq_desc *desc = irq_to_desc(d->irq); |
609 | unsigned int vold, vnew, edibit; | 609 | unsigned int vold, vnew, edibit; |
610 | 610 | ||
611 | if (flow_type == IRQ_TYPE_NONE) | 611 | if (flow_type == IRQ_TYPE_NONE) |
@@ -630,10 +630,10 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) | |||
630 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { | 630 | if (flow_type & IRQ_TYPE_LEVEL_LOW) { |
631 | desc->status |= IRQ_LEVEL; | 631 | desc->status |= IRQ_LEVEL; |
632 | desc->handle_irq = handle_level_irq; | 632 | desc->handle_irq = handle_level_irq; |
633 | desc->chip = &ipic_level_irq_chip; | 633 | desc->irq_data.chip = &ipic_level_irq_chip; |
634 | } else { | 634 | } else { |
635 | desc->handle_irq = handle_edge_irq; | 635 | desc->handle_irq = handle_edge_irq; |
636 | desc->chip = &ipic_edge_irq_chip; | 636 | desc->irq_data.chip = &ipic_edge_irq_chip; |
637 | } | 637 | } |
638 | 638 | ||
639 | /* only EXT IRQ senses are programmable on ipic | 639 | /* only EXT IRQ senses are programmable on ipic |
@@ -661,19 +661,19 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) | |||
661 | /* level interrupts and edge interrupts have different ack operations */ | 661 | /* level interrupts and edge interrupts have different ack operations */ |
662 | static struct irq_chip ipic_level_irq_chip = { | 662 | static struct irq_chip ipic_level_irq_chip = { |
663 | .name = "IPIC", | 663 | .name = "IPIC", |
664 | .unmask = ipic_unmask_irq, | 664 | .irq_unmask = ipic_unmask_irq, |
665 | .mask = ipic_mask_irq, | 665 | .irq_mask = ipic_mask_irq, |
666 | .mask_ack = ipic_mask_irq, | 666 | .irq_mask_ack = ipic_mask_irq, |
667 | .set_type = ipic_set_irq_type, | 667 | .irq_set_type = ipic_set_irq_type, |
668 | }; | 668 | }; |
669 | 669 | ||
670 | static struct irq_chip ipic_edge_irq_chip = { | 670 | static struct irq_chip ipic_edge_irq_chip = { |
671 | .name = "IPIC", | 671 | .name = "IPIC", |
672 | .unmask = ipic_unmask_irq, | 672 | .irq_unmask = ipic_unmask_irq, |
673 | .mask = ipic_mask_irq, | 673 | .irq_mask = ipic_mask_irq, |
674 | .mask_ack = ipic_mask_irq_and_ack, | 674 | .irq_mask_ack = ipic_mask_irq_and_ack, |
675 | .ack = ipic_ack_irq, | 675 | .irq_ack = ipic_ack_irq, |
676 | .set_type = ipic_set_irq_type, | 676 | .irq_set_type = ipic_set_irq_type, |
677 | }; | 677 | }; |
678 | 678 | ||
679 | static int ipic_host_match(struct irq_host *h, struct device_node *node) | 679 | static int ipic_host_match(struct irq_host *h, struct device_node *node) |
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c index 8c27d261aba8..1a75a7fb4a99 100644 --- a/arch/powerpc/sysdev/mpc8xx_pic.c +++ b/arch/powerpc/sysdev/mpc8xx_pic.c | |||
@@ -25,10 +25,10 @@ static sysconf8xx_t __iomem *siu_reg; | |||
25 | 25 | ||
26 | int cpm_get_irq(struct pt_regs *regs); | 26 | int cpm_get_irq(struct pt_regs *regs); |
27 | 27 | ||
28 | static void mpc8xx_unmask_irq(unsigned int virq) | 28 | static void mpc8xx_unmask_irq(struct irq_data *d) |
29 | { | 29 | { |
30 | int bit, word; | 30 | int bit, word; |
31 | unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; | 31 | unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; |
32 | 32 | ||
33 | bit = irq_nr & 0x1f; | 33 | bit = irq_nr & 0x1f; |
34 | word = irq_nr >> 5; | 34 | word = irq_nr >> 5; |
@@ -37,10 +37,10 @@ static void mpc8xx_unmask_irq(unsigned int virq) | |||
37 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); | 37 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); |
38 | } | 38 | } |
39 | 39 | ||
40 | static void mpc8xx_mask_irq(unsigned int virq) | 40 | static void mpc8xx_mask_irq(struct irq_data *d) |
41 | { | 41 | { |
42 | int bit, word; | 42 | int bit, word; |
43 | unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; | 43 | unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; |
44 | 44 | ||
45 | bit = irq_nr & 0x1f; | 45 | bit = irq_nr & 0x1f; |
46 | word = irq_nr >> 5; | 46 | word = irq_nr >> 5; |
@@ -49,19 +49,19 @@ static void mpc8xx_mask_irq(unsigned int virq) | |||
49 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); | 49 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); |
50 | } | 50 | } |
51 | 51 | ||
52 | static void mpc8xx_ack(unsigned int virq) | 52 | static void mpc8xx_ack(struct irq_data *d) |
53 | { | 53 | { |
54 | int bit; | 54 | int bit; |
55 | unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; | 55 | unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; |
56 | 56 | ||
57 | bit = irq_nr & 0x1f; | 57 | bit = irq_nr & 0x1f; |
58 | out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); | 58 | out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); |
59 | } | 59 | } |
60 | 60 | ||
61 | static void mpc8xx_end_irq(unsigned int virq) | 61 | static void mpc8xx_end_irq(struct irq_data *d) |
62 | { | 62 | { |
63 | int bit, word; | 63 | int bit, word; |
64 | unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; | 64 | unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq; |
65 | 65 | ||
66 | bit = irq_nr & 0x1f; | 66 | bit = irq_nr & 0x1f; |
67 | word = irq_nr >> 5; | 67 | word = irq_nr >> 5; |
@@ -70,9 +70,9 @@ static void mpc8xx_end_irq(unsigned int virq) | |||
70 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); | 70 | out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); |
71 | } | 71 | } |
72 | 72 | ||
73 | static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) | 73 | static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type) |
74 | { | 74 | { |
75 | struct irq_desc *desc = irq_to_desc(virq); | 75 | struct irq_desc *desc = irq_to_desc(d->irq); |
76 | 76 | ||
77 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 77 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); |
78 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | 78 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; |
@@ -80,7 +80,7 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) | |||
80 | desc->status |= IRQ_LEVEL; | 80 | desc->status |= IRQ_LEVEL; |
81 | 81 | ||
82 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { | 82 | if (flow_type & IRQ_TYPE_EDGE_FALLING) { |
83 | irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq; | 83 | irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq; |
84 | unsigned int siel = in_be32(&siu_reg->sc_siel); | 84 | unsigned int siel = in_be32(&siu_reg->sc_siel); |
85 | 85 | ||
86 | /* only external IRQ senses are programmable */ | 86 | /* only external IRQ senses are programmable */ |
@@ -95,11 +95,11 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) | |||
95 | 95 | ||
96 | static struct irq_chip mpc8xx_pic = { | 96 | static struct irq_chip mpc8xx_pic = { |
97 | .name = "MPC8XX SIU", | 97 | .name = "MPC8XX SIU", |
98 | .unmask = mpc8xx_unmask_irq, | 98 | .irq_unmask = mpc8xx_unmask_irq, |
99 | .mask = mpc8xx_mask_irq, | 99 | .irq_mask = mpc8xx_mask_irq, |
100 | .ack = mpc8xx_ack, | 100 | .irq_ack = mpc8xx_ack, |
101 | .eoi = mpc8xx_end_irq, | 101 | .irq_eoi = mpc8xx_end_irq, |
102 | .set_type = mpc8xx_set_irq_type, | 102 | .irq_set_type = mpc8xx_set_irq_type, |
103 | }; | 103 | }; |
104 | 104 | ||
105 | unsigned int mpc8xx_get_irq(void) | 105 | unsigned int mpc8xx_get_irq(void) |
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c index c48cd8178079..232e701245d7 100644 --- a/arch/powerpc/sysdev/mpc8xxx_gpio.c +++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c | |||
@@ -155,43 +155,43 @@ static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) | |||
155 | 32 - ffs(mask))); | 155 | 32 - ffs(mask))); |
156 | } | 156 | } |
157 | 157 | ||
158 | static void mpc8xxx_irq_unmask(unsigned int virq) | 158 | static void mpc8xxx_irq_unmask(struct irq_data *d) |
159 | { | 159 | { |
160 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); | 160 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
161 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 161 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
162 | unsigned long flags; | 162 | unsigned long flags; |
163 | 163 | ||
164 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | 164 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
165 | 165 | ||
166 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); | 166 | setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); |
167 | 167 | ||
168 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | 168 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
169 | } | 169 | } |
170 | 170 | ||
171 | static void mpc8xxx_irq_mask(unsigned int virq) | 171 | static void mpc8xxx_irq_mask(struct irq_data *d) |
172 | { | 172 | { |
173 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); | 173 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
174 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 174 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
175 | unsigned long flags; | 175 | unsigned long flags; |
176 | 176 | ||
177 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | 177 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
178 | 178 | ||
179 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); | 179 | clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); |
180 | 180 | ||
181 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | 181 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
182 | } | 182 | } |
183 | 183 | ||
184 | static void mpc8xxx_irq_ack(unsigned int virq) | 184 | static void mpc8xxx_irq_ack(struct irq_data *d) |
185 | { | 185 | { |
186 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); | 186 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
187 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 187 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
188 | 188 | ||
189 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq))); | 189 | out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(d->irq))); |
190 | } | 190 | } |
191 | 191 | ||
192 | static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) | 192 | static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
193 | { | 193 | { |
194 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); | 194 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
195 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 195 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
196 | unsigned long flags; | 196 | unsigned long flags; |
197 | 197 | ||
@@ -199,14 +199,14 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) | |||
199 | case IRQ_TYPE_EDGE_FALLING: | 199 | case IRQ_TYPE_EDGE_FALLING: |
200 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | 200 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
201 | setbits32(mm->regs + GPIO_ICR, | 201 | setbits32(mm->regs + GPIO_ICR, |
202 | mpc8xxx_gpio2mask(virq_to_hw(virq))); | 202 | mpc8xxx_gpio2mask(virq_to_hw(d->irq))); |
203 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | 203 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
204 | break; | 204 | break; |
205 | 205 | ||
206 | case IRQ_TYPE_EDGE_BOTH: | 206 | case IRQ_TYPE_EDGE_BOTH: |
207 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); | 207 | spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
208 | clrbits32(mm->regs + GPIO_ICR, | 208 | clrbits32(mm->regs + GPIO_ICR, |
209 | mpc8xxx_gpio2mask(virq_to_hw(virq))); | 209 | mpc8xxx_gpio2mask(virq_to_hw(d->irq))); |
210 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); | 210 | spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
211 | break; | 211 | break; |
212 | 212 | ||
@@ -217,11 +217,11 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) | |||
217 | return 0; | 217 | return 0; |
218 | } | 218 | } |
219 | 219 | ||
220 | static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type) | 220 | static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
221 | { | 221 | { |
222 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); | 222 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
223 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; | 223 | struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; |
224 | unsigned long gpio = virq_to_hw(virq); | 224 | unsigned long gpio = virq_to_hw(d->irq); |
225 | void __iomem *reg; | 225 | void __iomem *reg; |
226 | unsigned int shift; | 226 | unsigned int shift; |
227 | unsigned long flags; | 227 | unsigned long flags; |
@@ -264,10 +264,10 @@ static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type) | |||
264 | 264 | ||
265 | static struct irq_chip mpc8xxx_irq_chip = { | 265 | static struct irq_chip mpc8xxx_irq_chip = { |
266 | .name = "mpc8xxx-gpio", | 266 | .name = "mpc8xxx-gpio", |
267 | .unmask = mpc8xxx_irq_unmask, | 267 | .irq_unmask = mpc8xxx_irq_unmask, |
268 | .mask = mpc8xxx_irq_mask, | 268 | .irq_mask = mpc8xxx_irq_mask, |
269 | .ack = mpc8xxx_irq_ack, | 269 | .irq_ack = mpc8xxx_irq_ack, |
270 | .set_type = mpc8xxx_irq_set_type, | 270 | .irq_set_type = mpc8xxx_irq_set_type, |
271 | }; | 271 | }; |
272 | 272 | ||
273 | static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, | 273 | static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, |
@@ -276,7 +276,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, | |||
276 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; | 276 | struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; |
277 | 277 | ||
278 | if (mpc8xxx_gc->of_dev_id_data) | 278 | if (mpc8xxx_gc->of_dev_id_data) |
279 | mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data; | 279 | mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; |
280 | 280 | ||
281 | set_irq_chip_data(virq, h->host_data); | 281 | set_irq_chip_data(virq, h->host_data); |
282 | set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); | 282 | set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); |
@@ -310,6 +310,7 @@ static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { | |||
310 | { .compatible = "fsl,mpc8572-gpio", }, | 310 | { .compatible = "fsl,mpc8572-gpio", }, |
311 | { .compatible = "fsl,mpc8610-gpio", }, | 311 | { .compatible = "fsl,mpc8610-gpio", }, |
312 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, | 312 | { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, |
313 | { .compatible = "fsl,qoriq-gpio", }, | ||
313 | {} | 314 | {} |
314 | }; | 315 | }; |
315 | 316 | ||
@@ -389,9 +390,6 @@ static int __init mpc8xxx_add_gpiochips(void) | |||
389 | for_each_matching_node(np, mpc8xxx_gpio_ids) | 390 | for_each_matching_node(np, mpc8xxx_gpio_ids) |
390 | mpc8xxx_add_controller(np); | 391 | mpc8xxx_add_controller(np); |
391 | 392 | ||
392 | for_each_compatible_node(np, NULL, "fsl,qoriq-gpio") | ||
393 | mpc8xxx_add_controller(np); | ||
394 | |||
395 | return 0; | 393 | return 0; |
396 | } | 394 | } |
397 | arch_initcall(mpc8xxx_add_gpiochips); | 395 | arch_initcall(mpc8xxx_add_gpiochips); |
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index b0c8469e5ddd..eb7021815e2d 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -611,7 +611,7 @@ static struct mpic *mpic_find(unsigned int irq) | |||
611 | if (irq < NUM_ISA_INTERRUPTS) | 611 | if (irq < NUM_ISA_INTERRUPTS) |
612 | return NULL; | 612 | return NULL; |
613 | 613 | ||
614 | return irq_to_desc(irq)->chip_data; | 614 | return get_irq_chip_data(irq); |
615 | } | 615 | } |
616 | 616 | ||
617 | /* Determine if the linux irq is an IPI */ | 617 | /* Determine if the linux irq is an IPI */ |
@@ -636,16 +636,22 @@ static inline u32 mpic_physmask(u32 cpumask) | |||
636 | 636 | ||
637 | #ifdef CONFIG_SMP | 637 | #ifdef CONFIG_SMP |
638 | /* Get the mpic structure from the IPI number */ | 638 | /* Get the mpic structure from the IPI number */ |
639 | static inline struct mpic * mpic_from_ipi(unsigned int ipi) | 639 | static inline struct mpic * mpic_from_ipi(struct irq_data *d) |
640 | { | 640 | { |
641 | return irq_to_desc(ipi)->chip_data; | 641 | return irq_data_get_irq_chip_data(d); |
642 | } | 642 | } |
643 | #endif | 643 | #endif |
644 | 644 | ||
645 | /* Get the mpic structure from the irq number */ | 645 | /* Get the mpic structure from the irq number */ |
646 | static inline struct mpic * mpic_from_irq(unsigned int irq) | 646 | static inline struct mpic * mpic_from_irq(unsigned int irq) |
647 | { | 647 | { |
648 | return irq_to_desc(irq)->chip_data; | 648 | return get_irq_chip_data(irq); |
649 | } | ||
650 | |||
651 | /* Get the mpic structure from the irq data */ | ||
652 | static inline struct mpic * mpic_from_irq_data(struct irq_data *d) | ||
653 | { | ||
654 | return irq_data_get_irq_chip_data(d); | ||
649 | } | 655 | } |
650 | 656 | ||
651 | /* Send an EOI */ | 657 | /* Send an EOI */ |
@@ -660,13 +666,13 @@ static inline void mpic_eoi(struct mpic *mpic) | |||
660 | */ | 666 | */ |
661 | 667 | ||
662 | 668 | ||
663 | void mpic_unmask_irq(unsigned int irq) | 669 | void mpic_unmask_irq(struct irq_data *d) |
664 | { | 670 | { |
665 | unsigned int loops = 100000; | 671 | unsigned int loops = 100000; |
666 | struct mpic *mpic = mpic_from_irq(irq); | 672 | struct mpic *mpic = mpic_from_irq_data(d); |
667 | unsigned int src = mpic_irq_to_hw(irq); | 673 | unsigned int src = mpic_irq_to_hw(d->irq); |
668 | 674 | ||
669 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); | 675 | DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); |
670 | 676 | ||
671 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), | 677 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
672 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & | 678 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & |
@@ -681,13 +687,13 @@ void mpic_unmask_irq(unsigned int irq) | |||
681 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); | 687 | } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); |
682 | } | 688 | } |
683 | 689 | ||
684 | void mpic_mask_irq(unsigned int irq) | 690 | void mpic_mask_irq(struct irq_data *d) |
685 | { | 691 | { |
686 | unsigned int loops = 100000; | 692 | unsigned int loops = 100000; |
687 | struct mpic *mpic = mpic_from_irq(irq); | 693 | struct mpic *mpic = mpic_from_irq_data(d); |
688 | unsigned int src = mpic_irq_to_hw(irq); | 694 | unsigned int src = mpic_irq_to_hw(d->irq); |
689 | 695 | ||
690 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); | 696 | DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); |
691 | 697 | ||
692 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), | 698 | mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), |
693 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | | 699 | mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | |
@@ -703,12 +709,12 @@ void mpic_mask_irq(unsigned int irq) | |||
703 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); | 709 | } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); |
704 | } | 710 | } |
705 | 711 | ||
706 | void mpic_end_irq(unsigned int irq) | 712 | void mpic_end_irq(struct irq_data *d) |
707 | { | 713 | { |
708 | struct mpic *mpic = mpic_from_irq(irq); | 714 | struct mpic *mpic = mpic_from_irq_data(d); |
709 | 715 | ||
710 | #ifdef DEBUG_IRQ | 716 | #ifdef DEBUG_IRQ |
711 | DBG("%s: end_irq: %d\n", mpic->name, irq); | 717 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
712 | #endif | 718 | #endif |
713 | /* We always EOI on end_irq() even for edge interrupts since that | 719 | /* We always EOI on end_irq() even for edge interrupts since that |
714 | * should only lower the priority, the MPIC should have properly | 720 | * should only lower the priority, the MPIC should have properly |
@@ -720,51 +726,51 @@ void mpic_end_irq(unsigned int irq) | |||
720 | 726 | ||
721 | #ifdef CONFIG_MPIC_U3_HT_IRQS | 727 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
722 | 728 | ||
723 | static void mpic_unmask_ht_irq(unsigned int irq) | 729 | static void mpic_unmask_ht_irq(struct irq_data *d) |
724 | { | 730 | { |
725 | struct mpic *mpic = mpic_from_irq(irq); | 731 | struct mpic *mpic = mpic_from_irq_data(d); |
726 | unsigned int src = mpic_irq_to_hw(irq); | 732 | unsigned int src = mpic_irq_to_hw(d->irq); |
727 | 733 | ||
728 | mpic_unmask_irq(irq); | 734 | mpic_unmask_irq(d); |
729 | 735 | ||
730 | if (irq_to_desc(irq)->status & IRQ_LEVEL) | 736 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
731 | mpic_ht_end_irq(mpic, src); | 737 | mpic_ht_end_irq(mpic, src); |
732 | } | 738 | } |
733 | 739 | ||
734 | static unsigned int mpic_startup_ht_irq(unsigned int irq) | 740 | static unsigned int mpic_startup_ht_irq(struct irq_data *d) |
735 | { | 741 | { |
736 | struct mpic *mpic = mpic_from_irq(irq); | 742 | struct mpic *mpic = mpic_from_irq_data(d); |
737 | unsigned int src = mpic_irq_to_hw(irq); | 743 | unsigned int src = mpic_irq_to_hw(d->irq); |
738 | 744 | ||
739 | mpic_unmask_irq(irq); | 745 | mpic_unmask_irq(d); |
740 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); | 746 | mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); |
741 | 747 | ||
742 | return 0; | 748 | return 0; |
743 | } | 749 | } |
744 | 750 | ||
745 | static void mpic_shutdown_ht_irq(unsigned int irq) | 751 | static void mpic_shutdown_ht_irq(struct irq_data *d) |
746 | { | 752 | { |
747 | struct mpic *mpic = mpic_from_irq(irq); | 753 | struct mpic *mpic = mpic_from_irq_data(d); |
748 | unsigned int src = mpic_irq_to_hw(irq); | 754 | unsigned int src = mpic_irq_to_hw(d->irq); |
749 | 755 | ||
750 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); | 756 | mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status); |
751 | mpic_mask_irq(irq); | 757 | mpic_mask_irq(d); |
752 | } | 758 | } |
753 | 759 | ||
754 | static void mpic_end_ht_irq(unsigned int irq) | 760 | static void mpic_end_ht_irq(struct irq_data *d) |
755 | { | 761 | { |
756 | struct mpic *mpic = mpic_from_irq(irq); | 762 | struct mpic *mpic = mpic_from_irq_data(d); |
757 | unsigned int src = mpic_irq_to_hw(irq); | 763 | unsigned int src = mpic_irq_to_hw(d->irq); |
758 | 764 | ||
759 | #ifdef DEBUG_IRQ | 765 | #ifdef DEBUG_IRQ |
760 | DBG("%s: end_irq: %d\n", mpic->name, irq); | 766 | DBG("%s: end_irq: %d\n", mpic->name, d->irq); |
761 | #endif | 767 | #endif |
762 | /* We always EOI on end_irq() even for edge interrupts since that | 768 | /* We always EOI on end_irq() even for edge interrupts since that |
763 | * should only lower the priority, the MPIC should have properly | 769 | * should only lower the priority, the MPIC should have properly |
764 | * latched another edge interrupt coming in anyway | 770 | * latched another edge interrupt coming in anyway |
765 | */ | 771 | */ |
766 | 772 | ||
767 | if (irq_to_desc(irq)->status & IRQ_LEVEL) | 773 | if (irq_to_desc(d->irq)->status & IRQ_LEVEL) |
768 | mpic_ht_end_irq(mpic, src); | 774 | mpic_ht_end_irq(mpic, src); |
769 | mpic_eoi(mpic); | 775 | mpic_eoi(mpic); |
770 | } | 776 | } |
@@ -772,23 +778,23 @@ static void mpic_end_ht_irq(unsigned int irq) | |||
772 | 778 | ||
773 | #ifdef CONFIG_SMP | 779 | #ifdef CONFIG_SMP |
774 | 780 | ||
775 | static void mpic_unmask_ipi(unsigned int irq) | 781 | static void mpic_unmask_ipi(struct irq_data *d) |
776 | { | 782 | { |
777 | struct mpic *mpic = mpic_from_ipi(irq); | 783 | struct mpic *mpic = mpic_from_ipi(d); |
778 | unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; | 784 | unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0]; |
779 | 785 | ||
780 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); | 786 | DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); |
781 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); | 787 | mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); |
782 | } | 788 | } |
783 | 789 | ||
784 | static void mpic_mask_ipi(unsigned int irq) | 790 | static void mpic_mask_ipi(struct irq_data *d) |
785 | { | 791 | { |
786 | /* NEVER disable an IPI... that's just plain wrong! */ | 792 | /* NEVER disable an IPI... that's just plain wrong! */ |
787 | } | 793 | } |
788 | 794 | ||
789 | static void mpic_end_ipi(unsigned int irq) | 795 | static void mpic_end_ipi(struct irq_data *d) |
790 | { | 796 | { |
791 | struct mpic *mpic = mpic_from_ipi(irq); | 797 | struct mpic *mpic = mpic_from_ipi(d); |
792 | 798 | ||
793 | /* | 799 | /* |
794 | * IPIs are marked IRQ_PER_CPU. This has the side effect of | 800 | * IPIs are marked IRQ_PER_CPU. This has the side effect of |
@@ -802,10 +808,11 @@ static void mpic_end_ipi(unsigned int irq) | |||
802 | 808 | ||
803 | #endif /* CONFIG_SMP */ | 809 | #endif /* CONFIG_SMP */ |
804 | 810 | ||
805 | int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | 811 | int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
812 | bool force) | ||
806 | { | 813 | { |
807 | struct mpic *mpic = mpic_from_irq(irq); | 814 | struct mpic *mpic = mpic_from_irq_data(d); |
808 | unsigned int src = mpic_irq_to_hw(irq); | 815 | unsigned int src = mpic_irq_to_hw(d->irq); |
809 | 816 | ||
810 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { | 817 | if (mpic->flags & MPIC_SINGLE_DEST_CPU) { |
811 | int cpuid = irq_choose_cpu(cpumask); | 818 | int cpuid = irq_choose_cpu(cpumask); |
@@ -848,15 +855,15 @@ static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) | |||
848 | } | 855 | } |
849 | } | 856 | } |
850 | 857 | ||
851 | int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) | 858 | int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
852 | { | 859 | { |
853 | struct mpic *mpic = mpic_from_irq(virq); | 860 | struct mpic *mpic = mpic_from_irq_data(d); |
854 | unsigned int src = mpic_irq_to_hw(virq); | 861 | unsigned int src = mpic_irq_to_hw(d->irq); |
855 | struct irq_desc *desc = irq_to_desc(virq); | 862 | struct irq_desc *desc = irq_to_desc(d->irq); |
856 | unsigned int vecpri, vold, vnew; | 863 | unsigned int vecpri, vold, vnew; |
857 | 864 | ||
858 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", | 865 | DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", |
859 | mpic, virq, src, flow_type); | 866 | mpic, d->irq, src, flow_type); |
860 | 867 | ||
861 | if (src >= mpic->irq_count) | 868 | if (src >= mpic->irq_count) |
862 | return -EINVAL; | 869 | return -EINVAL; |
@@ -907,28 +914,28 @@ void mpic_set_vector(unsigned int virq, unsigned int vector) | |||
907 | } | 914 | } |
908 | 915 | ||
909 | static struct irq_chip mpic_irq_chip = { | 916 | static struct irq_chip mpic_irq_chip = { |
910 | .mask = mpic_mask_irq, | 917 | .irq_mask = mpic_mask_irq, |
911 | .unmask = mpic_unmask_irq, | 918 | .irq_unmask = mpic_unmask_irq, |
912 | .eoi = mpic_end_irq, | 919 | .irq_eoi = mpic_end_irq, |
913 | .set_type = mpic_set_irq_type, | 920 | .irq_set_type = mpic_set_irq_type, |
914 | }; | 921 | }; |
915 | 922 | ||
916 | #ifdef CONFIG_SMP | 923 | #ifdef CONFIG_SMP |
917 | static struct irq_chip mpic_ipi_chip = { | 924 | static struct irq_chip mpic_ipi_chip = { |
918 | .mask = mpic_mask_ipi, | 925 | .irq_mask = mpic_mask_ipi, |
919 | .unmask = mpic_unmask_ipi, | 926 | .irq_unmask = mpic_unmask_ipi, |
920 | .eoi = mpic_end_ipi, | 927 | .irq_eoi = mpic_end_ipi, |
921 | }; | 928 | }; |
922 | #endif /* CONFIG_SMP */ | 929 | #endif /* CONFIG_SMP */ |
923 | 930 | ||
924 | #ifdef CONFIG_MPIC_U3_HT_IRQS | 931 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
925 | static struct irq_chip mpic_irq_ht_chip = { | 932 | static struct irq_chip mpic_irq_ht_chip = { |
926 | .startup = mpic_startup_ht_irq, | 933 | .irq_startup = mpic_startup_ht_irq, |
927 | .shutdown = mpic_shutdown_ht_irq, | 934 | .irq_shutdown = mpic_shutdown_ht_irq, |
928 | .mask = mpic_mask_irq, | 935 | .irq_mask = mpic_mask_irq, |
929 | .unmask = mpic_unmask_ht_irq, | 936 | .irq_unmask = mpic_unmask_ht_irq, |
930 | .eoi = mpic_end_ht_irq, | 937 | .irq_eoi = mpic_end_ht_irq, |
931 | .set_type = mpic_set_irq_type, | 938 | .irq_set_type = mpic_set_irq_type, |
932 | }; | 939 | }; |
933 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ | 940 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
934 | 941 | ||
@@ -1060,12 +1067,12 @@ struct mpic * __init mpic_alloc(struct device_node *node, | |||
1060 | mpic->hc_irq = mpic_irq_chip; | 1067 | mpic->hc_irq = mpic_irq_chip; |
1061 | mpic->hc_irq.name = name; | 1068 | mpic->hc_irq.name = name; |
1062 | if (flags & MPIC_PRIMARY) | 1069 | if (flags & MPIC_PRIMARY) |
1063 | mpic->hc_irq.set_affinity = mpic_set_affinity; | 1070 | mpic->hc_irq.irq_set_affinity = mpic_set_affinity; |
1064 | #ifdef CONFIG_MPIC_U3_HT_IRQS | 1071 | #ifdef CONFIG_MPIC_U3_HT_IRQS |
1065 | mpic->hc_ht_irq = mpic_irq_ht_chip; | 1072 | mpic->hc_ht_irq = mpic_irq_ht_chip; |
1066 | mpic->hc_ht_irq.name = name; | 1073 | mpic->hc_ht_irq.name = name; |
1067 | if (flags & MPIC_PRIMARY) | 1074 | if (flags & MPIC_PRIMARY) |
1068 | mpic->hc_ht_irq.set_affinity = mpic_set_affinity; | 1075 | mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; |
1069 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ | 1076 | #endif /* CONFIG_MPIC_U3_HT_IRQS */ |
1070 | 1077 | ||
1071 | #ifdef CONFIG_SMP | 1078 | #ifdef CONFIG_SMP |
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h index e4a6df77b8d7..13f3e8913a93 100644 --- a/arch/powerpc/sysdev/mpic.h +++ b/arch/powerpc/sysdev/mpic.h | |||
@@ -34,9 +34,10 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic) | |||
34 | } | 34 | } |
35 | #endif | 35 | #endif |
36 | 36 | ||
37 | extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); | 37 | extern int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type); |
38 | extern void mpic_set_vector(unsigned int virq, unsigned int vector); | 38 | extern void mpic_set_vector(unsigned int virq, unsigned int vector); |
39 | extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask); | 39 | extern int mpic_set_affinity(struct irq_data *d, |
40 | const struct cpumask *cpumask, bool force); | ||
40 | extern void mpic_reset_core(int cpu); | 41 | extern void mpic_reset_core(int cpu); |
41 | 42 | ||
42 | #endif /* _POWERPC_SYSDEV_MPIC_H */ | 43 | #endif /* _POWERPC_SYSDEV_MPIC_H */ |
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c index 320ad5a9a25d..0b7794acfce1 100644 --- a/arch/powerpc/sysdev/mpic_pasemi_msi.c +++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c | |||
@@ -43,24 +43,24 @@ static void mpic_pasemi_msi_mask_irq(struct irq_data *data) | |||
43 | { | 43 | { |
44 | pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); | 44 | pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); |
45 | mask_msi_irq(data); | 45 | mask_msi_irq(data); |
46 | mpic_mask_irq(data->irq); | 46 | mpic_mask_irq(data); |
47 | } | 47 | } |
48 | 48 | ||
49 | static void mpic_pasemi_msi_unmask_irq(struct irq_data *data) | 49 | static void mpic_pasemi_msi_unmask_irq(struct irq_data *data) |
50 | { | 50 | { |
51 | pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); | 51 | pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); |
52 | mpic_unmask_irq(data->irq); | 52 | mpic_unmask_irq(data); |
53 | unmask_msi_irq(data); | 53 | unmask_msi_irq(data); |
54 | } | 54 | } |
55 | 55 | ||
56 | static struct irq_chip mpic_pasemi_msi_chip = { | 56 | static struct irq_chip mpic_pasemi_msi_chip = { |
57 | .irq_shutdown = mpic_pasemi_msi_mask_irq, | 57 | .irq_shutdown = mpic_pasemi_msi_mask_irq, |
58 | .irq_mask = mpic_pasemi_msi_mask_irq, | 58 | .irq_mask = mpic_pasemi_msi_mask_irq, |
59 | .irq_unmask = mpic_pasemi_msi_unmask_irq, | 59 | .irq_unmask = mpic_pasemi_msi_unmask_irq, |
60 | .eoi = mpic_end_irq, | 60 | .irq_eoi = mpic_end_irq, |
61 | .set_type = mpic_set_irq_type, | 61 | .irq_set_type = mpic_set_irq_type, |
62 | .set_affinity = mpic_set_affinity, | 62 | .irq_set_affinity = mpic_set_affinity, |
63 | .name = "PASEMI-MSI", | 63 | .name = "PASEMI-MSI", |
64 | }; | 64 | }; |
65 | 65 | ||
66 | static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type) | 66 | static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type) |
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c index a2b028b4a202..71900ac78270 100644 --- a/arch/powerpc/sysdev/mpic_u3msi.c +++ b/arch/powerpc/sysdev/mpic_u3msi.c | |||
@@ -26,23 +26,23 @@ static struct mpic *msi_mpic; | |||
26 | static void mpic_u3msi_mask_irq(struct irq_data *data) | 26 | static void mpic_u3msi_mask_irq(struct irq_data *data) |
27 | { | 27 | { |
28 | mask_msi_irq(data); | 28 | mask_msi_irq(data); |
29 | mpic_mask_irq(data->irq); | 29 | mpic_mask_irq(data); |
30 | } | 30 | } |
31 | 31 | ||
32 | static void mpic_u3msi_unmask_irq(struct irq_data *data) | 32 | static void mpic_u3msi_unmask_irq(struct irq_data *data) |
33 | { | 33 | { |
34 | mpic_unmask_irq(data->irq); | 34 | mpic_unmask_irq(data); |
35 | unmask_msi_irq(data); | 35 | unmask_msi_irq(data); |
36 | } | 36 | } |
37 | 37 | ||
38 | static struct irq_chip mpic_u3msi_chip = { | 38 | static struct irq_chip mpic_u3msi_chip = { |
39 | .irq_shutdown = mpic_u3msi_mask_irq, | 39 | .irq_shutdown = mpic_u3msi_mask_irq, |
40 | .irq_mask = mpic_u3msi_mask_irq, | 40 | .irq_mask = mpic_u3msi_mask_irq, |
41 | .irq_unmask = mpic_u3msi_unmask_irq, | 41 | .irq_unmask = mpic_u3msi_unmask_irq, |
42 | .eoi = mpic_end_irq, | 42 | .irq_eoi = mpic_end_irq, |
43 | .set_type = mpic_set_irq_type, | 43 | .irq_set_type = mpic_set_irq_type, |
44 | .set_affinity = mpic_set_affinity, | 44 | .irq_set_affinity = mpic_set_affinity, |
45 | .name = "MPIC-U3MSI", | 45 | .name = "MPIC-U3MSI", |
46 | }; | 46 | }; |
47 | 47 | ||
48 | static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) | 48 | static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) |
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c index feaee402e2d6..0f6af41ebb44 100644 --- a/arch/powerpc/sysdev/mv64x60_dev.c +++ b/arch/powerpc/sysdev/mv64x60_dev.c | |||
@@ -346,7 +346,7 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id) | |||
346 | if (prop) | 346 | if (prop) |
347 | pdata.freq_m = *prop; | 347 | pdata.freq_m = *prop; |
348 | 348 | ||
349 | pdata.freq_m = 3; /* default */ | 349 | pdata.freq_n = 3; /* default */ |
350 | prop = of_get_property(np, "freq_n", NULL); | 350 | prop = of_get_property(np, "freq_n", NULL); |
351 | if (prop) | 351 | if (prop) |
352 | pdata.freq_n = *prop; | 352 | pdata.freq_n = *prop; |
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index 485b92477d7c..bc61ebb8987c 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c | |||
@@ -76,9 +76,9 @@ static struct irq_host *mv64x60_irq_host; | |||
76 | * mv64x60_chip_low functions | 76 | * mv64x60_chip_low functions |
77 | */ | 77 | */ |
78 | 78 | ||
79 | static void mv64x60_mask_low(unsigned int virq) | 79 | static void mv64x60_mask_low(struct irq_data *d) |
80 | { | 80 | { |
81 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 81 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
82 | unsigned long flags; | 82 | unsigned long flags; |
83 | 83 | ||
84 | spin_lock_irqsave(&mv64x60_lock, flags); | 84 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -89,9 +89,9 @@ static void mv64x60_mask_low(unsigned int virq) | |||
89 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); | 89 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); |
90 | } | 90 | } |
91 | 91 | ||
92 | static void mv64x60_unmask_low(unsigned int virq) | 92 | static void mv64x60_unmask_low(struct irq_data *d) |
93 | { | 93 | { |
94 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 94 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
95 | unsigned long flags; | 95 | unsigned long flags; |
96 | 96 | ||
97 | spin_lock_irqsave(&mv64x60_lock, flags); | 97 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -104,18 +104,18 @@ static void mv64x60_unmask_low(unsigned int virq) | |||
104 | 104 | ||
105 | static struct irq_chip mv64x60_chip_low = { | 105 | static struct irq_chip mv64x60_chip_low = { |
106 | .name = "mv64x60_low", | 106 | .name = "mv64x60_low", |
107 | .mask = mv64x60_mask_low, | 107 | .irq_mask = mv64x60_mask_low, |
108 | .mask_ack = mv64x60_mask_low, | 108 | .irq_mask_ack = mv64x60_mask_low, |
109 | .unmask = mv64x60_unmask_low, | 109 | .irq_unmask = mv64x60_unmask_low, |
110 | }; | 110 | }; |
111 | 111 | ||
112 | /* | 112 | /* |
113 | * mv64x60_chip_high functions | 113 | * mv64x60_chip_high functions |
114 | */ | 114 | */ |
115 | 115 | ||
116 | static void mv64x60_mask_high(unsigned int virq) | 116 | static void mv64x60_mask_high(struct irq_data *d) |
117 | { | 117 | { |
118 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 118 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
119 | unsigned long flags; | 119 | unsigned long flags; |
120 | 120 | ||
121 | spin_lock_irqsave(&mv64x60_lock, flags); | 121 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -126,9 +126,9 @@ static void mv64x60_mask_high(unsigned int virq) | |||
126 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); | 126 | (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); |
127 | } | 127 | } |
128 | 128 | ||
129 | static void mv64x60_unmask_high(unsigned int virq) | 129 | static void mv64x60_unmask_high(struct irq_data *d) |
130 | { | 130 | { |
131 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 131 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
132 | unsigned long flags; | 132 | unsigned long flags; |
133 | 133 | ||
134 | spin_lock_irqsave(&mv64x60_lock, flags); | 134 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -141,18 +141,18 @@ static void mv64x60_unmask_high(unsigned int virq) | |||
141 | 141 | ||
142 | static struct irq_chip mv64x60_chip_high = { | 142 | static struct irq_chip mv64x60_chip_high = { |
143 | .name = "mv64x60_high", | 143 | .name = "mv64x60_high", |
144 | .mask = mv64x60_mask_high, | 144 | .irq_mask = mv64x60_mask_high, |
145 | .mask_ack = mv64x60_mask_high, | 145 | .irq_mask_ack = mv64x60_mask_high, |
146 | .unmask = mv64x60_unmask_high, | 146 | .irq_unmask = mv64x60_unmask_high, |
147 | }; | 147 | }; |
148 | 148 | ||
149 | /* | 149 | /* |
150 | * mv64x60_chip_gpp functions | 150 | * mv64x60_chip_gpp functions |
151 | */ | 151 | */ |
152 | 152 | ||
153 | static void mv64x60_mask_gpp(unsigned int virq) | 153 | static void mv64x60_mask_gpp(struct irq_data *d) |
154 | { | 154 | { |
155 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 155 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
156 | unsigned long flags; | 156 | unsigned long flags; |
157 | 157 | ||
158 | spin_lock_irqsave(&mv64x60_lock, flags); | 158 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -163,9 +163,9 @@ static void mv64x60_mask_gpp(unsigned int virq) | |||
163 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); | 163 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); |
164 | } | 164 | } |
165 | 165 | ||
166 | static void mv64x60_mask_ack_gpp(unsigned int virq) | 166 | static void mv64x60_mask_ack_gpp(struct irq_data *d) |
167 | { | 167 | { |
168 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 168 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
169 | unsigned long flags; | 169 | unsigned long flags; |
170 | 170 | ||
171 | spin_lock_irqsave(&mv64x60_lock, flags); | 171 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -178,9 +178,9 @@ static void mv64x60_mask_ack_gpp(unsigned int virq) | |||
178 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); | 178 | (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); |
179 | } | 179 | } |
180 | 180 | ||
181 | static void mv64x60_unmask_gpp(unsigned int virq) | 181 | static void mv64x60_unmask_gpp(struct irq_data *d) |
182 | { | 182 | { |
183 | int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; | 183 | int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK; |
184 | unsigned long flags; | 184 | unsigned long flags; |
185 | 185 | ||
186 | spin_lock_irqsave(&mv64x60_lock, flags); | 186 | spin_lock_irqsave(&mv64x60_lock, flags); |
@@ -193,9 +193,9 @@ static void mv64x60_unmask_gpp(unsigned int virq) | |||
193 | 193 | ||
194 | static struct irq_chip mv64x60_chip_gpp = { | 194 | static struct irq_chip mv64x60_chip_gpp = { |
195 | .name = "mv64x60_gpp", | 195 | .name = "mv64x60_gpp", |
196 | .mask = mv64x60_mask_gpp, | 196 | .irq_mask = mv64x60_mask_gpp, |
197 | .mask_ack = mv64x60_mask_ack_gpp, | 197 | .irq_mask_ack = mv64x60_mask_ack_gpp, |
198 | .unmask = mv64x60_unmask_gpp, | 198 | .irq_unmask = mv64x60_unmask_gpp, |
199 | }; | 199 | }; |
200 | 200 | ||
201 | /* | 201 | /* |
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c index 541ba9863647..8c9ded8ea07c 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c | |||
@@ -189,15 +189,20 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg | |||
189 | 189 | ||
190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) | 190 | static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) |
191 | { | 191 | { |
192 | return irq_to_desc(virq)->chip_data; | 192 | return get_irq_chip_data(virq); |
193 | } | ||
194 | |||
195 | static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d) | ||
196 | { | ||
197 | return irq_data_get_irq_chip_data(d); | ||
193 | } | 198 | } |
194 | 199 | ||
195 | #define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) | 200 | #define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) |
196 | 201 | ||
197 | static void qe_ic_unmask_irq(unsigned int virq) | 202 | static void qe_ic_unmask_irq(struct irq_data *d) |
198 | { | 203 | { |
199 | struct qe_ic *qe_ic = qe_ic_from_irq(virq); | 204 | struct qe_ic *qe_ic = qe_ic_from_irq_data(d); |
200 | unsigned int src = virq_to_hw(virq); | 205 | unsigned int src = virq_to_hw(d->irq); |
201 | unsigned long flags; | 206 | unsigned long flags; |
202 | u32 temp; | 207 | u32 temp; |
203 | 208 | ||
@@ -210,10 +215,10 @@ static void qe_ic_unmask_irq(unsigned int virq) | |||
210 | raw_spin_unlock_irqrestore(&qe_ic_lock, flags); | 215 | raw_spin_unlock_irqrestore(&qe_ic_lock, flags); |
211 | } | 216 | } |
212 | 217 | ||
213 | static void qe_ic_mask_irq(unsigned int virq) | 218 | static void qe_ic_mask_irq(struct irq_data *d) |
214 | { | 219 | { |
215 | struct qe_ic *qe_ic = qe_ic_from_irq(virq); | 220 | struct qe_ic *qe_ic = qe_ic_from_irq_data(d); |
216 | unsigned int src = virq_to_hw(virq); | 221 | unsigned int src = virq_to_hw(d->irq); |
217 | unsigned long flags; | 222 | unsigned long flags; |
218 | u32 temp; | 223 | u32 temp; |
219 | 224 | ||
@@ -238,9 +243,9 @@ static void qe_ic_mask_irq(unsigned int virq) | |||
238 | 243 | ||
239 | static struct irq_chip qe_ic_irq_chip = { | 244 | static struct irq_chip qe_ic_irq_chip = { |
240 | .name = "QEIC", | 245 | .name = "QEIC", |
241 | .unmask = qe_ic_unmask_irq, | 246 | .irq_unmask = qe_ic_unmask_irq, |
242 | .mask = qe_ic_mask_irq, | 247 | .irq_mask = qe_ic_mask_irq, |
243 | .mask_ack = qe_ic_mask_irq, | 248 | .irq_mask_ack = qe_ic_mask_irq, |
244 | }; | 249 | }; |
245 | 250 | ||
246 | static int qe_ic_host_match(struct irq_host *h, struct device_node *node) | 251 | static int qe_ic_host_match(struct irq_host *h, struct device_node *node) |
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 0ab9281e49ae..02c91db90037 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c | |||
@@ -343,24 +343,9 @@ static inline unsigned int get_pci_source(void) | |||
343 | * Linux descriptor level callbacks | 343 | * Linux descriptor level callbacks |
344 | */ | 344 | */ |
345 | 345 | ||
346 | static void tsi108_pci_irq_enable(u_int irq) | 346 | static void tsi108_pci_irq_unmask(struct irq_data *d) |
347 | { | 347 | { |
348 | tsi108_pci_int_unmask(irq); | 348 | tsi108_pci_int_unmask(d->irq); |
349 | } | ||
350 | |||
351 | static void tsi108_pci_irq_disable(u_int irq) | ||
352 | { | ||
353 | tsi108_pci_int_mask(irq); | ||
354 | } | ||
355 | |||
356 | static void tsi108_pci_irq_ack(u_int irq) | ||
357 | { | ||
358 | tsi108_pci_int_mask(irq); | ||
359 | } | ||
360 | |||
361 | static void tsi108_pci_irq_end(u_int irq) | ||
362 | { | ||
363 | tsi108_pci_int_unmask(irq); | ||
364 | 349 | ||
365 | /* Enable interrupts from PCI block */ | 350 | /* Enable interrupts from PCI block */ |
366 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, | 351 | tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, |
@@ -370,16 +355,25 @@ static void tsi108_pci_irq_end(u_int irq) | |||
370 | mb(); | 355 | mb(); |
371 | } | 356 | } |
372 | 357 | ||
358 | static void tsi108_pci_irq_mask(struct irq_data *d) | ||
359 | { | ||
360 | tsi108_pci_int_mask(d->irq); | ||
361 | } | ||
362 | |||
363 | static void tsi108_pci_irq_ack(struct irq_data *d) | ||
364 | { | ||
365 | tsi108_pci_int_mask(d->irq); | ||
366 | } | ||
367 | |||
373 | /* | 368 | /* |
374 | * Interrupt controller descriptor for cascaded PCI interrupt controller. | 369 | * Interrupt controller descriptor for cascaded PCI interrupt controller. |
375 | */ | 370 | */ |
376 | 371 | ||
377 | static struct irq_chip tsi108_pci_irq = { | 372 | static struct irq_chip tsi108_pci_irq = { |
378 | .name = "tsi108_PCI_int", | 373 | .name = "tsi108_PCI_int", |
379 | .mask = tsi108_pci_irq_disable, | 374 | .irq_mask = tsi108_pci_irq_mask, |
380 | .ack = tsi108_pci_irq_ack, | 375 | .irq_ack = tsi108_pci_irq_ack, |
381 | .end = tsi108_pci_irq_end, | 376 | .irq_unmask = tsi108_pci_irq_unmask, |
382 | .unmask = tsi108_pci_irq_enable, | ||
383 | }; | 377 | }; |
384 | 378 | ||
385 | static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, | 379 | static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, |
@@ -437,8 +431,11 @@ void __init tsi108_pci_int_init(struct device_node *node) | |||
437 | 431 | ||
438 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) | 432 | void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) |
439 | { | 433 | { |
434 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
440 | unsigned int cascade_irq = get_pci_source(); | 435 | unsigned int cascade_irq = get_pci_source(); |
436 | |||
441 | if (cascade_irq != NO_IRQ) | 437 | if (cascade_irq != NO_IRQ) |
442 | generic_handle_irq(cascade_irq); | 438 | generic_handle_irq(cascade_irq); |
443 | desc->chip->eoi(irq); | 439 | |
440 | chip->irq_eoi(&desc->irq_data); | ||
444 | } | 441 | } |
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c index 0038fb78f094..835f7958b237 100644 --- a/arch/powerpc/sysdev/uic.c +++ b/arch/powerpc/sysdev/uic.c | |||
@@ -55,11 +55,11 @@ struct uic { | |||
55 | struct irq_host *irqhost; | 55 | struct irq_host *irqhost; |
56 | }; | 56 | }; |
57 | 57 | ||
58 | static void uic_unmask_irq(unsigned int virq) | 58 | static void uic_unmask_irq(struct irq_data *d) |
59 | { | 59 | { |
60 | struct irq_desc *desc = irq_to_desc(virq); | 60 | struct irq_desc *desc = irq_to_desc(d->irq); |
61 | struct uic *uic = get_irq_chip_data(virq); | 61 | struct uic *uic = irq_data_get_irq_chip_data(d); |
62 | unsigned int src = uic_irq_to_hw(virq); | 62 | unsigned int src = uic_irq_to_hw(d->irq); |
63 | unsigned long flags; | 63 | unsigned long flags; |
64 | u32 er, sr; | 64 | u32 er, sr; |
65 | 65 | ||
@@ -74,10 +74,10 @@ static void uic_unmask_irq(unsigned int virq) | |||
74 | spin_unlock_irqrestore(&uic->lock, flags); | 74 | spin_unlock_irqrestore(&uic->lock, flags); |
75 | } | 75 | } |
76 | 76 | ||
77 | static void uic_mask_irq(unsigned int virq) | 77 | static void uic_mask_irq(struct irq_data *d) |
78 | { | 78 | { |
79 | struct uic *uic = get_irq_chip_data(virq); | 79 | struct uic *uic = irq_data_get_irq_chip_data(d); |
80 | unsigned int src = uic_irq_to_hw(virq); | 80 | unsigned int src = uic_irq_to_hw(d->irq); |
81 | unsigned long flags; | 81 | unsigned long flags; |
82 | u32 er; | 82 | u32 er; |
83 | 83 | ||
@@ -88,10 +88,10 @@ static void uic_mask_irq(unsigned int virq) | |||
88 | spin_unlock_irqrestore(&uic->lock, flags); | 88 | spin_unlock_irqrestore(&uic->lock, flags); |
89 | } | 89 | } |
90 | 90 | ||
91 | static void uic_ack_irq(unsigned int virq) | 91 | static void uic_ack_irq(struct irq_data *d) |
92 | { | 92 | { |
93 | struct uic *uic = get_irq_chip_data(virq); | 93 | struct uic *uic = irq_data_get_irq_chip_data(d); |
94 | unsigned int src = uic_irq_to_hw(virq); | 94 | unsigned int src = uic_irq_to_hw(d->irq); |
95 | unsigned long flags; | 95 | unsigned long flags; |
96 | 96 | ||
97 | spin_lock_irqsave(&uic->lock, flags); | 97 | spin_lock_irqsave(&uic->lock, flags); |
@@ -99,11 +99,11 @@ static void uic_ack_irq(unsigned int virq) | |||
99 | spin_unlock_irqrestore(&uic->lock, flags); | 99 | spin_unlock_irqrestore(&uic->lock, flags); |
100 | } | 100 | } |
101 | 101 | ||
102 | static void uic_mask_ack_irq(unsigned int virq) | 102 | static void uic_mask_ack_irq(struct irq_data *d) |
103 | { | 103 | { |
104 | struct irq_desc *desc = irq_to_desc(virq); | 104 | struct irq_desc *desc = irq_to_desc(d->irq); |
105 | struct uic *uic = get_irq_chip_data(virq); | 105 | struct uic *uic = irq_data_get_irq_chip_data(d); |
106 | unsigned int src = uic_irq_to_hw(virq); | 106 | unsigned int src = uic_irq_to_hw(d->irq); |
107 | unsigned long flags; | 107 | unsigned long flags; |
108 | u32 er, sr; | 108 | u32 er, sr; |
109 | 109 | ||
@@ -125,18 +125,18 @@ static void uic_mask_ack_irq(unsigned int virq) | |||
125 | spin_unlock_irqrestore(&uic->lock, flags); | 125 | spin_unlock_irqrestore(&uic->lock, flags); |
126 | } | 126 | } |
127 | 127 | ||
128 | static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) | 128 | static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
129 | { | 129 | { |
130 | struct uic *uic = get_irq_chip_data(virq); | 130 | struct uic *uic = irq_data_get_irq_chip_data(d); |
131 | unsigned int src = uic_irq_to_hw(virq); | 131 | unsigned int src = uic_irq_to_hw(d->irq); |
132 | struct irq_desc *desc = irq_to_desc(virq); | 132 | struct irq_desc *desc = irq_to_desc(d->irq); |
133 | unsigned long flags; | 133 | unsigned long flags; |
134 | int trigger, polarity; | 134 | int trigger, polarity; |
135 | u32 tr, pr, mask; | 135 | u32 tr, pr, mask; |
136 | 136 | ||
137 | switch (flow_type & IRQ_TYPE_SENSE_MASK) { | 137 | switch (flow_type & IRQ_TYPE_SENSE_MASK) { |
138 | case IRQ_TYPE_NONE: | 138 | case IRQ_TYPE_NONE: |
139 | uic_mask_irq(virq); | 139 | uic_mask_irq(d); |
140 | return 0; | 140 | return 0; |
141 | 141 | ||
142 | case IRQ_TYPE_EDGE_RISING: | 142 | case IRQ_TYPE_EDGE_RISING: |
@@ -178,11 +178,11 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) | |||
178 | 178 | ||
179 | static struct irq_chip uic_irq_chip = { | 179 | static struct irq_chip uic_irq_chip = { |
180 | .name = "UIC", | 180 | .name = "UIC", |
181 | .unmask = uic_unmask_irq, | 181 | .irq_unmask = uic_unmask_irq, |
182 | .mask = uic_mask_irq, | 182 | .irq_mask = uic_mask_irq, |
183 | .mask_ack = uic_mask_ack_irq, | 183 | .irq_mask_ack = uic_mask_ack_irq, |
184 | .ack = uic_ack_irq, | 184 | .irq_ack = uic_ack_irq, |
185 | .set_type = uic_set_irq_type, | 185 | .irq_set_type = uic_set_irq_type, |
186 | }; | 186 | }; |
187 | 187 | ||
188 | static int uic_host_map(struct irq_host *h, unsigned int virq, | 188 | static int uic_host_map(struct irq_host *h, unsigned int virq, |
@@ -220,6 +220,7 @@ static struct irq_host_ops uic_host_ops = { | |||
220 | 220 | ||
221 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | 221 | void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) |
222 | { | 222 | { |
223 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
223 | struct uic *uic = get_irq_data(virq); | 224 | struct uic *uic = get_irq_data(virq); |
224 | u32 msr; | 225 | u32 msr; |
225 | int src; | 226 | int src; |
@@ -227,9 +228,9 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
227 | 228 | ||
228 | raw_spin_lock(&desc->lock); | 229 | raw_spin_lock(&desc->lock); |
229 | if (desc->status & IRQ_LEVEL) | 230 | if (desc->status & IRQ_LEVEL) |
230 | desc->chip->mask(virq); | 231 | chip->irq_mask(&desc->irq_data); |
231 | else | 232 | else |
232 | desc->chip->mask_ack(virq); | 233 | chip->irq_mask_ack(&desc->irq_data); |
233 | raw_spin_unlock(&desc->lock); | 234 | raw_spin_unlock(&desc->lock); |
234 | 235 | ||
235 | msr = mfdcr(uic->dcrbase + UIC_MSR); | 236 | msr = mfdcr(uic->dcrbase + UIC_MSR); |
@@ -244,9 +245,9 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) | |||
244 | uic_irq_ret: | 245 | uic_irq_ret: |
245 | raw_spin_lock(&desc->lock); | 246 | raw_spin_lock(&desc->lock); |
246 | if (desc->status & IRQ_LEVEL) | 247 | if (desc->status & IRQ_LEVEL) |
247 | desc->chip->ack(virq); | 248 | chip->irq_ack(&desc->irq_data); |
248 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) | 249 | if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask) |
249 | desc->chip->unmask(virq); | 250 | chip->irq_unmask(&desc->irq_data); |
250 | raw_spin_unlock(&desc->lock); | 251 | raw_spin_unlock(&desc->lock); |
251 | } | 252 | } |
252 | 253 | ||
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c index 1e0ccfaf403e..7436f3ed4df6 100644 --- a/arch/powerpc/sysdev/xilinx_intc.c +++ b/arch/powerpc/sysdev/xilinx_intc.c | |||
@@ -69,17 +69,17 @@ static unsigned char xilinx_intc_map_senses[] = { | |||
69 | * | 69 | * |
70 | * IRQ Chip common (across level and edge) operations | 70 | * IRQ Chip common (across level and edge) operations |
71 | */ | 71 | */ |
72 | static void xilinx_intc_mask(unsigned int virq) | 72 | static void xilinx_intc_mask(struct irq_data *d) |
73 | { | 73 | { |
74 | int irq = virq_to_hw(virq); | 74 | int irq = virq_to_hw(d->irq); |
75 | void * regs = get_irq_chip_data(virq); | 75 | void * regs = irq_data_get_irq_chip_data(d); |
76 | pr_debug("mask: %d\n", irq); | 76 | pr_debug("mask: %d\n", irq); |
77 | out_be32(regs + XINTC_CIE, 1 << irq); | 77 | out_be32(regs + XINTC_CIE, 1 << irq); |
78 | } | 78 | } |
79 | 79 | ||
80 | static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type) | 80 | static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type) |
81 | { | 81 | { |
82 | struct irq_desc *desc = irq_to_desc(virq); | 82 | struct irq_desc *desc = irq_to_desc(d->irq); |
83 | 83 | ||
84 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); | 84 | desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); |
85 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; | 85 | desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; |
@@ -91,10 +91,10 @@ static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type) | |||
91 | /* | 91 | /* |
92 | * IRQ Chip level operations | 92 | * IRQ Chip level operations |
93 | */ | 93 | */ |
94 | static void xilinx_intc_level_unmask(unsigned int virq) | 94 | static void xilinx_intc_level_unmask(struct irq_data *d) |
95 | { | 95 | { |
96 | int irq = virq_to_hw(virq); | 96 | int irq = virq_to_hw(d->irq); |
97 | void * regs = get_irq_chip_data(virq); | 97 | void * regs = irq_data_get_irq_chip_data(d); |
98 | pr_debug("unmask: %d\n", irq); | 98 | pr_debug("unmask: %d\n", irq); |
99 | out_be32(regs + XINTC_SIE, 1 << irq); | 99 | out_be32(regs + XINTC_SIE, 1 << irq); |
100 | 100 | ||
@@ -107,37 +107,37 @@ static void xilinx_intc_level_unmask(unsigned int virq) | |||
107 | 107 | ||
108 | static struct irq_chip xilinx_intc_level_irqchip = { | 108 | static struct irq_chip xilinx_intc_level_irqchip = { |
109 | .name = "Xilinx Level INTC", | 109 | .name = "Xilinx Level INTC", |
110 | .mask = xilinx_intc_mask, | 110 | .irq_mask = xilinx_intc_mask, |
111 | .mask_ack = xilinx_intc_mask, | 111 | .irq_mask_ack = xilinx_intc_mask, |
112 | .unmask = xilinx_intc_level_unmask, | 112 | .irq_unmask = xilinx_intc_level_unmask, |
113 | .set_type = xilinx_intc_set_type, | 113 | .irq_set_type = xilinx_intc_set_type, |
114 | }; | 114 | }; |
115 | 115 | ||
116 | /* | 116 | /* |
117 | * IRQ Chip edge operations | 117 | * IRQ Chip edge operations |
118 | */ | 118 | */ |
119 | static void xilinx_intc_edge_unmask(unsigned int virq) | 119 | static void xilinx_intc_edge_unmask(struct irq_data *d) |
120 | { | 120 | { |
121 | int irq = virq_to_hw(virq); | 121 | int irq = virq_to_hw(d->irq); |
122 | void *regs = get_irq_chip_data(virq); | 122 | void *regs = irq_data_get_irq_chip_data(d); |
123 | pr_debug("unmask: %d\n", irq); | 123 | pr_debug("unmask: %d\n", irq); |
124 | out_be32(regs + XINTC_SIE, 1 << irq); | 124 | out_be32(regs + XINTC_SIE, 1 << irq); |
125 | } | 125 | } |
126 | 126 | ||
127 | static void xilinx_intc_edge_ack(unsigned int virq) | 127 | static void xilinx_intc_edge_ack(struct irq_data *d) |
128 | { | 128 | { |
129 | int irq = virq_to_hw(virq); | 129 | int irq = virq_to_hw(d->irq); |
130 | void * regs = get_irq_chip_data(virq); | 130 | void * regs = irq_data_get_irq_chip_data(d); |
131 | pr_debug("ack: %d\n", irq); | 131 | pr_debug("ack: %d\n", irq); |
132 | out_be32(regs + XINTC_IAR, 1 << irq); | 132 | out_be32(regs + XINTC_IAR, 1 << irq); |
133 | } | 133 | } |
134 | 134 | ||
135 | static struct irq_chip xilinx_intc_edge_irqchip = { | 135 | static struct irq_chip xilinx_intc_edge_irqchip = { |
136 | .name = "Xilinx Edge INTC", | 136 | .name = "Xilinx Edge INTC", |
137 | .mask = xilinx_intc_mask, | 137 | .irq_mask = xilinx_intc_mask, |
138 | .unmask = xilinx_intc_edge_unmask, | 138 | .irq_unmask = xilinx_intc_edge_unmask, |
139 | .ack = xilinx_intc_edge_ack, | 139 | .irq_ack = xilinx_intc_edge_ack, |
140 | .set_type = xilinx_intc_set_type, | 140 | .irq_set_type = xilinx_intc_set_type, |
141 | }; | 141 | }; |
142 | 142 | ||
143 | /* | 143 | /* |
@@ -229,12 +229,14 @@ int xilinx_intc_get_irq(void) | |||
229 | */ | 229 | */ |
230 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) | 230 | static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) |
231 | { | 231 | { |
232 | struct irq_chip *chip = get_irq_desc_chip(desc); | ||
232 | unsigned int cascade_irq = i8259_irq(); | 233 | unsigned int cascade_irq = i8259_irq(); |
234 | |||
233 | if (cascade_irq) | 235 | if (cascade_irq) |
234 | generic_handle_irq(cascade_irq); | 236 | generic_handle_irq(cascade_irq); |
235 | 237 | ||
236 | /* Let xilinx_intc end the interrupt */ | 238 | /* Let xilinx_intc end the interrupt */ |
237 | desc->chip->unmask(irq); | 239 | chip->irq_unmask(&desc->irq_data); |
238 | } | 240 | } |
239 | 241 | ||
240 | static void __init xilinx_i8259_setup_cascade(void) | 242 | static void __init xilinx_i8259_setup_cascade(void) |