aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/sysdev/fsl_pci.h
diff options
context:
space:
mode:
authorWang Dongsheng <dongsheng.wang@freescale.com>2014-03-19 23:19:37 -0400
committerScott Wood <scottwood@freescale.com>2014-03-19 23:37:44 -0400
commit48b16180d0d91324e5d2423c6d53d97bbe3dcc14 (patch)
tree522da33ee1abe3f0a3ed55a337756903cb7ea74e /arch/powerpc/sysdev/fsl_pci.h
parent093943735718a28d45dcfcc74a737ed39e402893 (diff)
fsl/pci: The new pci suspend/resume implementation
If we do nothing in suspend/resume, some platform PCIe ip-block can't guarantee the link back to L0 state from sleep, then, when we read the EP device will hang. Only we send pme turnoff message in pci controller suspend, and send pme exit message in resume, the link state will be normal. When we send pme turnoff message in pci controller suspend, the links will into l2/l3 ready, then, host cannot communicate with ep device, but pci-driver will call back EP device to save them state. So we need to change platform_driver->suspend/resume to syscore->suspend/resume. So the new suspend/resume implementation, send pme turnoff message in suspend, and send pme exit message in resume. And add a PME handler, to response PME & message interrupt. Change platform_driver->suspend/resume to syscore->suspend/resume. pci-driver will call back EP device, to save EP state in pci_pm_suspend_noirq, so we need to keep the link, until pci_pm_suspend_noirq finish. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8d455df58471..c1cec771d5ea 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -32,6 +32,13 @@ struct platform_device;
32#define PIWAR_WRITE_SNOOP 0x00005000 32#define PIWAR_WRITE_SNOOP 0x00005000
33#define PIWAR_SZ_MASK 0x0000003f 33#define PIWAR_SZ_MASK 0x0000003f
34 34
35#define PEX_PMCR_PTOMR 0x1
36#define PEX_PMCR_EXL2S 0x2
37
38#define PME_DISR_EN_PTOD 0x00008000
39#define PME_DISR_EN_ENL23D 0x00002000
40#define PME_DISR_EN_EXL23D 0x00001000
41
35/* PCI/PCI Express outbound window reg */ 42/* PCI/PCI Express outbound window reg */
36struct pci_outbound_window_regs { 43struct pci_outbound_window_regs {
37 __be32 potar; /* 0x.0 - Outbound translation address register */ 44 __be32 potar; /* 0x.0 - Outbound translation address register */
@@ -111,6 +118,7 @@ struct ccsr_pci {
111 118
112extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); 119extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
113extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); 120extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
121extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
114extern int mpc83xx_add_bridge(struct device_node *dev); 122extern int mpc83xx_add_bridge(struct device_node *dev);
115u64 fsl_pci_immrbar_base(struct pci_controller *hose); 123u64 fsl_pci_immrbar_base(struct pci_controller *hose);
116 124