powerpc: Context switch the new EBB SPRs

This context switches the new Event Based Branching (EBB) SPRs.  The three new
SPRs are:
  - Event Based Branch Handler Register (EBBHR)
  - Event Based Branch Return Register (EBBRR)
  - Branch Event Status and Control Register (BESCR)

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 files changed, 19 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index b6c17ec9b169..172233eab799 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -124,6 +124,9 @@ int main(void)
 
 #ifdef CONFIG_PPC_BOOK3S_64
         DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
+        DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
+        DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
+        DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
 #endif
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 7a6801faaa83..3fe5259e2fea 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -458,6 +458,14 @@ BEGIN_FTR_SECTION
          */
         mfspr   r0,SPRN_TAR
         std     r0,THREAD_TAR(r3)
+
+        /* Event based branch registers */
+        mfspr   r0, SPRN_BESCR
+        std     r0, THREAD_BESCR(r3)
+        mfspr   r0, SPRN_EBBHR
+        std     r0, THREAD_EBBHR(r3)
+        mfspr   r0, SPRN_EBBRR
+        std     r0, THREAD_EBBRR(r3)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
@@ -545,6 +553,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
+        /* Event based branch registers */
+        ld      r0, THREAD_BESCR(r4)
+        mtspr   SPRN_BESCR, r0
+        ld      r0, THREAD_EBBHR(r4)
+        mtspr   SPRN_EBBHR, r0
+        ld      r0, THREAD_EBBRR(r4)
+        mtspr   SPRN_EBBRR, r0
+
         ld      r0,THREAD_TAR(r4)
         mtspr   SPRN_TAR,r0
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)