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-rw-r--r--arch/powerpc/include/asm/processor.h3
-rw-r--r--arch/powerpc/include/asm/reg.h3
-rw-r--r--arch/powerpc/kernel/asm-offsets.c3
-rw-r--r--arch/powerpc/kernel/entry_64.S16
4 files changed, 25 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 0a4cc5d649e1..d7e67ca8b4a6 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -281,6 +281,9 @@ struct thread_struct {
281#endif 281#endif
282#ifdef CONFIG_PPC_BOOK3S_64 282#ifdef CONFIG_PPC_BOOK3S_64
283 unsigned long tar; 283 unsigned long tar;
284 unsigned long ebbrr;
285 unsigned long ebbhr;
286 unsigned long bescr;
284#endif 287#endif
285}; 288};
286 289
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 93be5fb20394..3d17427e4fd7 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -663,6 +663,9 @@
663#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */ 663#define SPRN_MMCRH 316 /* Hypervisor monitor mode control register */
664#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */ 664#define SPRN_MMCRS 894 /* Supervisor monitor mode control register */
665#define SPRN_MMCRC 851 /* Core monitor mode control register */ 665#define SPRN_MMCRC 851 /* Core monitor mode control register */
666#define SPRN_EBBHR 804 /* Event based branch handler register */
667#define SPRN_EBBRR 805 /* Event based branch return register */
668#define SPRN_BESCR 806 /* Branch event status and control register */
666 669
667#define SPRN_PMC1 787 670#define SPRN_PMC1 787
668#define SPRN_PMC2 788 671#define SPRN_PMC2 788
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index b6c17ec9b169..172233eab799 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -124,6 +124,9 @@ int main(void)
124 124
125#ifdef CONFIG_PPC_BOOK3S_64 125#ifdef CONFIG_PPC_BOOK3S_64
126 DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar)); 126 DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
127 DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
128 DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
129 DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
127#endif 130#endif
128#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 131#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
129 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch)); 132 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 7a6801faaa83..3fe5259e2fea 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -458,6 +458,14 @@ BEGIN_FTR_SECTION
458 */ 458 */
459 mfspr r0,SPRN_TAR 459 mfspr r0,SPRN_TAR
460 std r0,THREAD_TAR(r3) 460 std r0,THREAD_TAR(r3)
461
462 /* Event based branch registers */
463 mfspr r0, SPRN_BESCR
464 std r0, THREAD_BESCR(r3)
465 mfspr r0, SPRN_EBBHR
466 std r0, THREAD_EBBHR(r3)
467 mfspr r0, SPRN_EBBRR
468 std r0, THREAD_EBBRR(r3)
461END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 469END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
462#endif 470#endif
463 471
@@ -545,6 +553,14 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
545 553
546#ifdef CONFIG_PPC_BOOK3S_64 554#ifdef CONFIG_PPC_BOOK3S_64
547BEGIN_FTR_SECTION 555BEGIN_FTR_SECTION
556 /* Event based branch registers */
557 ld r0, THREAD_BESCR(r4)
558 mtspr SPRN_BESCR, r0
559 ld r0, THREAD_EBBHR(r4)
560 mtspr SPRN_EBBHR, r0
561 ld r0, THREAD_EBBRR(r4)
562 mtspr SPRN_EBBRR, r0
563
548 ld r0,THREAD_TAR(r4) 564 ld r0,THREAD_TAR(r4)
549 mtspr SPRN_TAR,r0 565 mtspr SPRN_TAR,r0
550END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 566END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)