diff options
author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2011-04-14 18:32:01 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2011-04-26 23:02:02 -0400 |
commit | 76b4eda866c4936af8d696f040abea56bf688e16 (patch) | |
tree | 8b4b6279353fa3d726e5fa95822f0e05b27456c7 /arch/powerpc/kernel | |
parent | 411e689d929d5fc2e9066e30de55e8bcdbd573ad (diff) |
powerpc: Add A2 cpu support
Add the cputable entry, regs and setup & restore entries for
the PowerPC A2 core.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r-- | arch/powerpc/kernel/Makefile | 1 | ||||
-rw-r--r-- | arch/powerpc/kernel/cpu_setup_a2.S | 114 | ||||
-rw-r--r-- | arch/powerpc/kernel/cputable.c | 25 |
3 files changed, 138 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 0fd6273bb8a9..058bc8bac488 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile | |||
@@ -41,6 +41,7 @@ obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o | |||
41 | obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o | 41 | obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o |
42 | obj64-$(CONFIG_RELOCATABLE) += reloc_64.o | 42 | obj64-$(CONFIG_RELOCATABLE) += reloc_64.o |
43 | obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o | 43 | obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o |
44 | obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o | ||
44 | obj-$(CONFIG_PPC64) += vdso64/ | 45 | obj-$(CONFIG_PPC64) += vdso64/ |
45 | obj-$(CONFIG_ALTIVEC) += vecemu.o | 46 | obj-$(CONFIG_ALTIVEC) += vecemu.o |
46 | obj-$(CONFIG_PPC_970_NAP) += idle_power4.o | 47 | obj-$(CONFIG_PPC_970_NAP) += idle_power4.o |
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S new file mode 100644 index 000000000000..7f818feaa7a5 --- /dev/null +++ b/arch/powerpc/kernel/cpu_setup_a2.S | |||
@@ -0,0 +1,114 @@ | |||
1 | /* | ||
2 | * A2 specific assembly support code | ||
3 | * | ||
4 | * Copyright 2009 Ben Herrenschmidt, IBM Corp. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #include <asm/asm-offsets.h> | ||
13 | #include <asm/ppc_asm.h> | ||
14 | #include <asm/ppc-opcode.h> | ||
15 | #include <asm/processor.h> | ||
16 | #include <asm/reg_a2.h> | ||
17 | #include <asm/reg.h> | ||
18 | #include <asm/thread_info.h> | ||
19 | |||
20 | /* | ||
21 | * Disable thdid and class fields in ERATs to bump PID to full 14 bits capacity. | ||
22 | * This also prevents external LPID accesses but that isn't a problem when not a | ||
23 | * guest. Under PV, this setting will be ignored and MMUCR will return the right | ||
24 | * number of PID bits we can use. | ||
25 | */ | ||
26 | #define MMUCR1_EXTEND_PID \ | ||
27 | (MMUCR1_ICTID | MMUCR1_ITTID | MMUCR1_DCTID | \ | ||
28 | MMUCR1_DTTID | MMUCR1_DCCD) | ||
29 | |||
30 | /* | ||
31 | * Use extended PIDs if enabled. | ||
32 | * Don't clear the ERATs on context sync events and enable I & D LRU. | ||
33 | * Enable ERAT back invalidate when tlbwe overwrites an entry. | ||
34 | */ | ||
35 | #define INITIAL_MMUCR1 \ | ||
36 | (MMUCR1_EXTEND_PID | MMUCR1_CSINV_NEVER | MMUCR1_IRRE | \ | ||
37 | MMUCR1_DRRE | MMUCR1_TLBWE_BINV) | ||
38 | |||
39 | _GLOBAL(__setup_cpu_a2) | ||
40 | /* Some of these are actually thread local and some are | ||
41 | * core local but doing it always won't hurt | ||
42 | */ | ||
43 | |||
44 | #ifdef CONFIG_PPC_WSP_COPRO | ||
45 | /* Make sure ACOP starts out as zero */ | ||
46 | li r3,0 | ||
47 | mtspr SPRN_ACOP,r3 | ||
48 | |||
49 | /* Enable icswx instruction */ | ||
50 | mfspr r3,SPRN_A2_CCR2 | ||
51 | ori r3,r3,A2_CCR2_ENABLE_ICSWX | ||
52 | mtspr SPRN_A2_CCR2,r3 | ||
53 | |||
54 | /* Unmask all CTs in HACOP */ | ||
55 | li r3,-1 | ||
56 | mtspr SPRN_HACOP,r3 | ||
57 | #endif /* CONFIG_PPC_WSP_COPRO */ | ||
58 | |||
59 | /* Enable doorbell */ | ||
60 | mfspr r3,SPRN_A2_CCR2 | ||
61 | oris r3,r3,A2_CCR2_ENABLE_PC@h | ||
62 | mtspr SPRN_A2_CCR2,r3 | ||
63 | isync | ||
64 | |||
65 | /* Setup CCR0 to disable power saving for now as it's busted | ||
66 | * in the current implementations. Setup CCR1 to wake on | ||
67 | * interrupts normally (we write the default value but who | ||
68 | * knows what FW may have clobbered...) | ||
69 | */ | ||
70 | li r3,0 | ||
71 | mtspr SPRN_A2_CCR0, r3 | ||
72 | LOAD_REG_IMMEDIATE(r3,0x0f0f0f0f) | ||
73 | mtspr SPRN_A2_CCR1, r3 | ||
74 | |||
75 | /* Initialise MMUCR1 */ | ||
76 | lis r3,INITIAL_MMUCR1@h | ||
77 | ori r3,r3,INITIAL_MMUCR1@l | ||
78 | mtspr SPRN_MMUCR1,r3 | ||
79 | |||
80 | /* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */ | ||
81 | LOAD_REG_IMMEDIATE(r3, 0x000a7531) | ||
82 | mtspr SPRN_MMUCR2,r3 | ||
83 | |||
84 | /* Set MMUCR3 to write all thids bit to the TLB */ | ||
85 | LOAD_REG_IMMEDIATE(r3, 0x0000000f) | ||
86 | mtspr SPRN_MMUCR3,r3 | ||
87 | |||
88 | /* Don't do ERAT stuff if running guest mode */ | ||
89 | mfmsr r3 | ||
90 | andis. r0,r3,MSR_GS@h | ||
91 | bne 1f | ||
92 | |||
93 | /* Now set the I-ERAT watermark to 15 */ | ||
94 | lis r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h | ||
95 | mtspr SPRN_MMUCR0, r4 | ||
96 | li r4,A2_IERAT_SIZE-1 | ||
97 | PPC_ERATWE(r4,r4,3) | ||
98 | |||
99 | /* Now set the D-ERAT watermark to 31 */ | ||
100 | lis r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h | ||
101 | mtspr SPRN_MMUCR0, r4 | ||
102 | li r4,A2_DERAT_SIZE-1 | ||
103 | PPC_ERATWE(r4,r4,3) | ||
104 | |||
105 | /* And invalidate the beast just in case. That won't get rid of | ||
106 | * a bolted entry though it will be in LRU and so will go away eventually | ||
107 | * but let's not bother for now | ||
108 | */ | ||
109 | PPC_ERATILX(0,0,0) | ||
110 | 1: | ||
111 | blr | ||
112 | |||
113 | _GLOBAL(__restore_cpu_a2) | ||
114 | b __setup_cpu_a2 | ||
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index b65b4908d3c7..3d7b65ad4962 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
@@ -62,10 +62,12 @@ extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec); | |||
62 | extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); | 62 | extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); |
63 | extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); | 63 | extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); |
64 | extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); | 64 | extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); |
65 | extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec); | ||
65 | extern void __restore_cpu_pa6t(void); | 66 | extern void __restore_cpu_pa6t(void); |
66 | extern void __restore_cpu_ppc970(void); | 67 | extern void __restore_cpu_ppc970(void); |
67 | extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); | 68 | extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); |
68 | extern void __restore_cpu_power7(void); | 69 | extern void __restore_cpu_power7(void); |
70 | extern void __restore_cpu_a2(void); | ||
69 | #endif /* CONFIG_PPC64 */ | 71 | #endif /* CONFIG_PPC64 */ |
70 | #if defined(CONFIG_E500) | 72 | #if defined(CONFIG_E500) |
71 | extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); | 73 | extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); |
@@ -2011,7 +2013,26 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
2011 | #endif /* CONFIG_PPC32 */ | 2013 | #endif /* CONFIG_PPC32 */ |
2012 | #endif /* CONFIG_E500 */ | 2014 | #endif /* CONFIG_E500 */ |
2013 | 2015 | ||
2014 | #ifdef CONFIG_PPC_BOOK3E_64 | 2016 | #ifdef CONFIG_PPC_A2 |
2017 | { /* Standard A2 (>= DD2) + FPU core */ | ||
2018 | .pvr_mask = 0xffff0000, | ||
2019 | .pvr_value = 0x00480000, | ||
2020 | .cpu_name = "A2 (>= DD2)", | ||
2021 | .cpu_features = CPU_FTRS_A2, | ||
2022 | .cpu_user_features = COMMON_USER_PPC64, | ||
2023 | .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | | ||
2024 | MMU_FTR_USE_TLBIVAX_BCAST | | ||
2025 | MMU_FTR_LOCK_BCAST_INVAL | | ||
2026 | MMU_FTR_USE_TLBRSRV | | ||
2027 | MMU_FTR_USE_PAIRED_MAS, | ||
2028 | .icache_bsize = 64, | ||
2029 | .dcache_bsize = 64, | ||
2030 | .num_pmcs = 0, | ||
2031 | .cpu_setup = __setup_cpu_a2, | ||
2032 | .cpu_restore = __restore_cpu_a2, | ||
2033 | .machine_check = machine_check_generic, | ||
2034 | .platform = "ppca2", | ||
2035 | }, | ||
2015 | { /* This is a default entry to get going, to be replaced by | 2036 | { /* This is a default entry to get going, to be replaced by |
2016 | * a real one at some stage | 2037 | * a real one at some stage |
2017 | */ | 2038 | */ |
@@ -2032,7 +2053,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
2032 | .machine_check = machine_check_generic, | 2053 | .machine_check = machine_check_generic, |
2033 | .platform = "power6", | 2054 | .platform = "power6", |
2034 | }, | 2055 | }, |
2035 | #endif | 2056 | #endif /* CONFIG_PPC_A2 */ |
2036 | }; | 2057 | }; |
2037 | 2058 | ||
2038 | static struct cpu_spec the_cpu_spec; | 2059 | static struct cpu_spec the_cpu_spec; |