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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-14 18:32:01 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-26 23:02:02 -0400
commit76b4eda866c4936af8d696f040abea56bf688e16 (patch)
tree8b4b6279353fa3d726e5fa95822f0e05b27456c7
parent411e689d929d5fc2e9066e30de55e8bcdbd573ad (diff)
powerpc: Add A2 cpu support
Add the cputable entry, regs and setup & restore entries for the PowerPC A2 core. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/include/asm/cputable.h8
-rw-r--r--arch/powerpc/include/asm/reg_a2.h156
-rw-r--r--arch/powerpc/kernel/Makefile1
-rw-r--r--arch/powerpc/kernel/cpu_setup_a2.S114
-rw-r--r--arch/powerpc/kernel/cputable.c25
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype4
6 files changed, 304 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 2fe37d781933..2d71523ebb03 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -437,9 +437,13 @@ extern const char *powerpc_base_platform;
437 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) 437 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
438#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 438#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
439 439
440#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
441 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
442 CPU_FTR_16M_PAGE)
443
440#ifdef __powerpc64__ 444#ifdef __powerpc64__
441#ifdef CONFIG_PPC_BOOK3E 445#ifdef CONFIG_PPC_BOOK3E
442#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500) 446#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500 | CPU_FTRS_A2)
443#else 447#else
444#define CPU_FTRS_POSSIBLE \ 448#define CPU_FTRS_POSSIBLE \
445 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 449 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
@@ -488,7 +492,7 @@ enum {
488 492
489#ifdef __powerpc64__ 493#ifdef __powerpc64__
490#ifdef CONFIG_PPC_BOOK3E 494#ifdef CONFIG_PPC_BOOK3E
491#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500) 495#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500 & CPU_FTRS_A2)
492#else 496#else
493#define CPU_FTRS_ALWAYS \ 497#define CPU_FTRS_ALWAYS \
494 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 498 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
diff --git a/arch/powerpc/include/asm/reg_a2.h b/arch/powerpc/include/asm/reg_a2.h
new file mode 100644
index 000000000000..3ba9c6f096fc
--- /dev/null
+++ b/arch/powerpc/include/asm/reg_a2.h
@@ -0,0 +1,156 @@
1/*
2 * Register definitions specific to the A2 core
3 *
4 * Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __ASM_POWERPC_REG_A2_H__
13#define __ASM_POWERPC_REG_A2_H__
14
15#define SPRN_TENSR 0x1b5
16#define SPRN_TENS 0x1b6 /* Thread ENable Set */
17#define SPRN_TENC 0x1b7 /* Thread ENable Clear */
18
19#define SPRN_A2_CCR0 0x3f0 /* Core Configuration Register 0 */
20#define SPRN_A2_CCR1 0x3f1 /* Core Configuration Register 1 */
21#define SPRN_A2_CCR2 0x3f2 /* Core Configuration Register 2 */
22#define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
23#define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
24#define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
25#define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
26
27#define SPRN_IAR 0x372
28
29#define SPRN_IUCR0 0x3f3
30#define IUCR0_ICBI_ACK 0x1000
31
32#define SPRN_XUCR0 0x3f6 /* Execution Unit Config Register 0 */
33
34#define A2_IERAT_SIZE 16
35#define A2_DERAT_SIZE 32
36
37/* A2 MMUCR0 bits */
38#define MMUCR0_ECL 0x80000000 /* Extended Class for TLB fills */
39#define MMUCR0_TID_NZ 0x40000000 /* TID is non-zero */
40#define MMUCR0_TS 0x10000000 /* Translation space for TLB fills */
41#define MMUCR0_TGS 0x20000000 /* Guest space for TLB fills */
42#define MMUCR0_TLBSEL 0x0c000000 /* TLB or ERAT target for TLB fills */
43#define MMUCR0_TLBSEL_U 0x00000000 /* TLBSEL = UTLB */
44#define MMUCR0_TLBSEL_I 0x08000000 /* TLBSEL = I-ERAT */
45#define MMUCR0_TLBSEL_D 0x0c000000 /* TLBSEL = D-ERAT */
46#define MMUCR0_LOCKSRSH 0x02000000 /* Use TLB lock on tlbsx. */
47#define MMUCR0_TID_MASK 0x000000ff /* TID field */
48
49/* A2 MMUCR1 bits */
50#define MMUCR1_IRRE 0x80000000 /* I-ERAT round robin enable */
51#define MMUCR1_DRRE 0x40000000 /* D-ERAT round robin enable */
52#define MMUCR1_REE 0x20000000 /* Reference Exception Enable*/
53#define MMUCR1_CEE 0x10000000 /* Change exception enable */
54#define MMUCR1_CSINV_ALL 0x00000000 /* Inval ERAT on all CS evts */
55#define MMUCR1_CSINV_NISYNC 0x04000000 /* Inval ERAT on all ex isync*/
56#define MMUCR1_CSINV_NEVER 0x0c000000 /* Don't inval ERAT on CS */
57#define MMUCR1_ICTID 0x00080000 /* IERAT class field as TID */
58#define MMUCR1_ITTID 0x00040000 /* IERAT thdid field as TID */
59#define MMUCR1_DCTID 0x00020000 /* DERAT class field as TID */
60#define MMUCR1_DTTID 0x00010000 /* DERAT thdid field as TID */
61#define MMUCR1_DCCD 0x00008000 /* DERAT class ignore */
62#define MMUCR1_TLBWE_BINV 0x00004000 /* back invalidate on tlbwe */
63
64/* A2 MMUCR2 bits */
65#define MMUCR2_PSSEL_SHIFT 4
66
67/* A2 MMUCR3 bits */
68#define MMUCR3_THID 0x0000000f /* Thread ID */
69
70/* *** ERAT TLB bits definitions */
71#define TLB0_EPN_MASK ASM_CONST(0xfffffffffffff000)
72#define TLB0_CLASS_MASK ASM_CONST(0x0000000000000c00)
73#define TLB0_CLASS_00 ASM_CONST(0x0000000000000000)
74#define TLB0_CLASS_01 ASM_CONST(0x0000000000000400)
75#define TLB0_CLASS_10 ASM_CONST(0x0000000000000800)
76#define TLB0_CLASS_11 ASM_CONST(0x0000000000000c00)
77#define TLB0_V ASM_CONST(0x0000000000000200)
78#define TLB0_X ASM_CONST(0x0000000000000100)
79#define TLB0_SIZE_MASK ASM_CONST(0x00000000000000f0)
80#define TLB0_SIZE_4K ASM_CONST(0x0000000000000010)
81#define TLB0_SIZE_64K ASM_CONST(0x0000000000000030)
82#define TLB0_SIZE_1M ASM_CONST(0x0000000000000050)
83#define TLB0_SIZE_16M ASM_CONST(0x0000000000000070)
84#define TLB0_SIZE_1G ASM_CONST(0x00000000000000a0)
85#define TLB0_THDID_MASK ASM_CONST(0x000000000000000f)
86#define TLB0_THDID_0 ASM_CONST(0x0000000000000001)
87#define TLB0_THDID_1 ASM_CONST(0x0000000000000002)
88#define TLB0_THDID_2 ASM_CONST(0x0000000000000004)
89#define TLB0_THDID_3 ASM_CONST(0x0000000000000008)
90#define TLB0_THDID_ALL ASM_CONST(0x000000000000000f)
91
92#define TLB1_RESVATTR ASM_CONST(0x00f0000000000000)
93#define TLB1_U0 ASM_CONST(0x0008000000000000)
94#define TLB1_U1 ASM_CONST(0x0004000000000000)
95#define TLB1_U2 ASM_CONST(0x0002000000000000)
96#define TLB1_U3 ASM_CONST(0x0001000000000000)
97#define TLB1_R ASM_CONST(0x0000800000000000)
98#define TLB1_C ASM_CONST(0x0000400000000000)
99#define TLB1_RPN_MASK ASM_CONST(0x000003fffffff000)
100#define TLB1_W ASM_CONST(0x0000000000000800)
101#define TLB1_I ASM_CONST(0x0000000000000400)
102#define TLB1_M ASM_CONST(0x0000000000000200)
103#define TLB1_G ASM_CONST(0x0000000000000100)
104#define TLB1_E ASM_CONST(0x0000000000000080)
105#define TLB1_VF ASM_CONST(0x0000000000000040)
106#define TLB1_UX ASM_CONST(0x0000000000000020)
107#define TLB1_SX ASM_CONST(0x0000000000000010)
108#define TLB1_UW ASM_CONST(0x0000000000000008)
109#define TLB1_SW ASM_CONST(0x0000000000000004)
110#define TLB1_UR ASM_CONST(0x0000000000000002)
111#define TLB1_SR ASM_CONST(0x0000000000000001)
112
113/* A2 erativax attributes definitions */
114#define ERATIVAX_RS_IS_ALL 0x000
115#define ERATIVAX_RS_IS_TID 0x040
116#define ERATIVAX_RS_IS_CLASS 0x080
117#define ERATIVAX_RS_IS_FULLMATCH 0x0c0
118#define ERATIVAX_CLASS_00 0x000
119#define ERATIVAX_CLASS_01 0x010
120#define ERATIVAX_CLASS_10 0x020
121#define ERATIVAX_CLASS_11 0x030
122#define ERATIVAX_PSIZE_4K (TLB_PSIZE_4K >> 1)
123#define ERATIVAX_PSIZE_64K (TLB_PSIZE_64K >> 1)
124#define ERATIVAX_PSIZE_1M (TLB_PSIZE_1M >> 1)
125#define ERATIVAX_PSIZE_16M (TLB_PSIZE_16M >> 1)
126#define ERATIVAX_PSIZE_1G (TLB_PSIZE_1G >> 1)
127
128/* A2 eratilx attributes definitions */
129#define ERATILX_T_ALL 0
130#define ERATILX_T_TID 1
131#define ERATILX_T_TGS 2
132#define ERATILX_T_FULLMATCH 3
133#define ERATILX_T_CLASS0 4
134#define ERATILX_T_CLASS1 5
135#define ERATILX_T_CLASS2 6
136#define ERATILX_T_CLASS3 7
137
138/* XUCR0 bits */
139#define XUCR0_TRACE_UM_T0 0x40000000 /* Thread 0 */
140#define XUCR0_TRACE_UM_T1 0x20000000 /* Thread 1 */
141#define XUCR0_TRACE_UM_T2 0x10000000 /* Thread 2 */
142#define XUCR0_TRACE_UM_T3 0x08000000 /* Thread 3 */
143
144/* A2 CCR0 register */
145#define A2_CCR0_PME_DISABLED 0x00000000
146#define A2_CCR0_PME_SLEEP 0x40000000
147#define A2_CCR0_PME_RVW 0x80000000
148#define A2_CCR0_PME_DISABLED2 0xc0000000
149
150/* A2 CCR2 register */
151#define A2_CCR2_ERAT_ONLY_MODE 0x00000001
152#define A2_CCR2_ENABLE_ICSWX 0x00000002
153#define A2_CCR2_ENABLE_PC 0x20000000
154#define A2_CCR2_ENABLE_TRACE 0x40000000
155
156#endif /* __ASM_POWERPC_REG_A2_H__ */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 0fd6273bb8a9..058bc8bac488 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
41obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o 41obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o
42obj64-$(CONFIG_RELOCATABLE) += reloc_64.o 42obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
43obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o 43obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
44obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o
44obj-$(CONFIG_PPC64) += vdso64/ 45obj-$(CONFIG_PPC64) += vdso64/
45obj-$(CONFIG_ALTIVEC) += vecemu.o 46obj-$(CONFIG_ALTIVEC) += vecemu.o
46obj-$(CONFIG_PPC_970_NAP) += idle_power4.o 47obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S
new file mode 100644
index 000000000000..7f818feaa7a5
--- /dev/null
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -0,0 +1,114 @@
1/*
2 * A2 specific assembly support code
3 *
4 * Copyright 2009 Ben Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <asm/asm-offsets.h>
13#include <asm/ppc_asm.h>
14#include <asm/ppc-opcode.h>
15#include <asm/processor.h>
16#include <asm/reg_a2.h>
17#include <asm/reg.h>
18#include <asm/thread_info.h>
19
20/*
21 * Disable thdid and class fields in ERATs to bump PID to full 14 bits capacity.
22 * This also prevents external LPID accesses but that isn't a problem when not a
23 * guest. Under PV, this setting will be ignored and MMUCR will return the right
24 * number of PID bits we can use.
25 */
26#define MMUCR1_EXTEND_PID \
27 (MMUCR1_ICTID | MMUCR1_ITTID | MMUCR1_DCTID | \
28 MMUCR1_DTTID | MMUCR1_DCCD)
29
30/*
31 * Use extended PIDs if enabled.
32 * Don't clear the ERATs on context sync events and enable I & D LRU.
33 * Enable ERAT back invalidate when tlbwe overwrites an entry.
34 */
35#define INITIAL_MMUCR1 \
36 (MMUCR1_EXTEND_PID | MMUCR1_CSINV_NEVER | MMUCR1_IRRE | \
37 MMUCR1_DRRE | MMUCR1_TLBWE_BINV)
38
39_GLOBAL(__setup_cpu_a2)
40 /* Some of these are actually thread local and some are
41 * core local but doing it always won't hurt
42 */
43
44#ifdef CONFIG_PPC_WSP_COPRO
45 /* Make sure ACOP starts out as zero */
46 li r3,0
47 mtspr SPRN_ACOP,r3
48
49 /* Enable icswx instruction */
50 mfspr r3,SPRN_A2_CCR2
51 ori r3,r3,A2_CCR2_ENABLE_ICSWX
52 mtspr SPRN_A2_CCR2,r3
53
54 /* Unmask all CTs in HACOP */
55 li r3,-1
56 mtspr SPRN_HACOP,r3
57#endif /* CONFIG_PPC_WSP_COPRO */
58
59 /* Enable doorbell */
60 mfspr r3,SPRN_A2_CCR2
61 oris r3,r3,A2_CCR2_ENABLE_PC@h
62 mtspr SPRN_A2_CCR2,r3
63 isync
64
65 /* Setup CCR0 to disable power saving for now as it's busted
66 * in the current implementations. Setup CCR1 to wake on
67 * interrupts normally (we write the default value but who
68 * knows what FW may have clobbered...)
69 */
70 li r3,0
71 mtspr SPRN_A2_CCR0, r3
72 LOAD_REG_IMMEDIATE(r3,0x0f0f0f0f)
73 mtspr SPRN_A2_CCR1, r3
74
75 /* Initialise MMUCR1 */
76 lis r3,INITIAL_MMUCR1@h
77 ori r3,r3,INITIAL_MMUCR1@l
78 mtspr SPRN_MMUCR1,r3
79
80 /* Set MMUCR2 to enable 4K, 64K, 1M, 16M and 1G pages */
81 LOAD_REG_IMMEDIATE(r3, 0x000a7531)
82 mtspr SPRN_MMUCR2,r3
83
84 /* Set MMUCR3 to write all thids bit to the TLB */
85 LOAD_REG_IMMEDIATE(r3, 0x0000000f)
86 mtspr SPRN_MMUCR3,r3
87
88 /* Don't do ERAT stuff if running guest mode */
89 mfmsr r3
90 andis. r0,r3,MSR_GS@h
91 bne 1f
92
93 /* Now set the I-ERAT watermark to 15 */
94 lis r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h
95 mtspr SPRN_MMUCR0, r4
96 li r4,A2_IERAT_SIZE-1
97 PPC_ERATWE(r4,r4,3)
98
99 /* Now set the D-ERAT watermark to 31 */
100 lis r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h
101 mtspr SPRN_MMUCR0, r4
102 li r4,A2_DERAT_SIZE-1
103 PPC_ERATWE(r4,r4,3)
104
105 /* And invalidate the beast just in case. That won't get rid of
106 * a bolted entry though it will be in LRU and so will go away eventually
107 * but let's not bother for now
108 */
109 PPC_ERATILX(0,0,0)
1101:
111 blr
112
113_GLOBAL(__restore_cpu_a2)
114 b __setup_cpu_a2
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b65b4908d3c7..3d7b65ad4962 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -62,10 +62,12 @@ extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
62extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec); 62extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
63extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec); 63extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
64extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec); 64extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
65extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
65extern void __restore_cpu_pa6t(void); 66extern void __restore_cpu_pa6t(void);
66extern void __restore_cpu_ppc970(void); 67extern void __restore_cpu_ppc970(void);
67extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); 68extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
68extern void __restore_cpu_power7(void); 69extern void __restore_cpu_power7(void);
70extern void __restore_cpu_a2(void);
69#endif /* CONFIG_PPC64 */ 71#endif /* CONFIG_PPC64 */
70#if defined(CONFIG_E500) 72#if defined(CONFIG_E500)
71extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); 73extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -2011,7 +2013,26 @@ static struct cpu_spec __initdata cpu_specs[] = {
2011#endif /* CONFIG_PPC32 */ 2013#endif /* CONFIG_PPC32 */
2012#endif /* CONFIG_E500 */ 2014#endif /* CONFIG_E500 */
2013 2015
2014#ifdef CONFIG_PPC_BOOK3E_64 2016#ifdef CONFIG_PPC_A2
2017 { /* Standard A2 (>= DD2) + FPU core */
2018 .pvr_mask = 0xffff0000,
2019 .pvr_value = 0x00480000,
2020 .cpu_name = "A2 (>= DD2)",
2021 .cpu_features = CPU_FTRS_A2,
2022 .cpu_user_features = COMMON_USER_PPC64,
2023 .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
2024 MMU_FTR_USE_TLBIVAX_BCAST |
2025 MMU_FTR_LOCK_BCAST_INVAL |
2026 MMU_FTR_USE_TLBRSRV |
2027 MMU_FTR_USE_PAIRED_MAS,
2028 .icache_bsize = 64,
2029 .dcache_bsize = 64,
2030 .num_pmcs = 0,
2031 .cpu_setup = __setup_cpu_a2,
2032 .cpu_restore = __restore_cpu_a2,
2033 .machine_check = machine_check_generic,
2034 .platform = "ppca2",
2035 },
2015 { /* This is a default entry to get going, to be replaced by 2036 { /* This is a default entry to get going, to be replaced by
2016 * a real one at some stage 2037 * a real one at some stage
2017 */ 2038 */
@@ -2032,7 +2053,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
2032 .machine_check = machine_check_generic, 2053 .machine_check = machine_check_generic,
2033 .platform = "power6", 2054 .platform = "power6",
2034 }, 2055 },
2035#endif 2056#endif /* CONFIG_PPC_A2 */
2036}; 2057};
2037 2058
2038static struct cpu_spec the_cpu_spec; 2059static struct cpu_spec the_cpu_spec;
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 111138c55f9c..7c1e1c64437b 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -107,6 +107,10 @@ config POWER4
107 depends on PPC64 && PPC_BOOK3S 107 depends on PPC64 && PPC_BOOK3S
108 def_bool y 108 def_bool y
109 109
110config PPC_A2
111 bool
112 depends on PPC_BOOK3E_64
113
110config TUNE_CELL 114config TUNE_CELL
111 bool "Optimize for Cell Broadband Engine" 115 bool "Optimize for Cell Broadband Engine"
112 depends on PPC64 && PPC_BOOK3S 116 depends on PPC64 && PPC_BOOK3S
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 06:09:45 -0400