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author | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
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committer | Andrea Bastoni <bastoni@cs.unc.edu> | 2010-05-30 19:16:45 -0400 |
commit | ada47b5fe13d89735805b566185f4885f5a3f750 (patch) | |
tree | 644b88f8a71896307d71438e9b3af49126ffb22b /arch/powerpc/include/asm/reg.h | |
parent | 43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff) | |
parent | 3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff) |
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 6315edc205d8..5572e86223f4 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -426,6 +426,10 @@ | |||
426 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ | 426 | #define SRR1_WAKEMT 0x00280000 /* mtctrl */ |
427 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ | 427 | #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ |
428 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ | 428 | #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ |
429 | #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ | ||
430 | #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ | ||
431 | #define SRR1_PROGTRAP 0x00020000 /* Trap */ | ||
432 | #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ | ||
429 | #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ | 433 | #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ |
430 | #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ | 434 | #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ |
431 | 435 | ||
@@ -489,6 +493,8 @@ | |||
489 | #define SPRN_MMCR1 798 | 493 | #define SPRN_MMCR1 798 |
490 | #define SPRN_MMCRA 0x312 | 494 | #define SPRN_MMCRA 0x312 |
491 | #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ | 495 | #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ |
496 | #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL | ||
497 | #define MMCRA_SDAR_ERAT_MISS 0x20000000UL | ||
492 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ | 498 | #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ |
493 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ | 499 | #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ |
494 | #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ | 500 | #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ |