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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/powerpc/include/asm/ptrace.h
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/powerpc/include/asm/ptrace.h')
-rw-r--r--arch/powerpc/include/asm/ptrace.h84
1 files changed, 78 insertions, 6 deletions
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 8c341490cfc5..9e2d84c06b74 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,6 +24,12 @@
24 * 2 of the License, or (at your option) any later version. 24 * 2 of the License, or (at your option) any later version.
25 */ 25 */
26 26
27#ifdef __KERNEL__
28#include <linux/types.h>
29#else
30#include <stdint.h>
31#endif
32
27#ifndef __ASSEMBLY__ 33#ifndef __ASSEMBLY__
28 34
29struct pt_regs { 35struct pt_regs {
@@ -131,14 +137,9 @@ do { \
131} while (0) 137} while (0)
132#endif /* __powerpc64__ */ 138#endif /* __powerpc64__ */
133 139
134/*
135 * These are defined as per linux/ptrace.h, which see.
136 */
137#define arch_has_single_step() (1) 140#define arch_has_single_step() (1)
138#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601)) 141#define arch_has_block_step() (!cpu_has_feature(CPU_FTR_601))
139extern void user_enable_single_step(struct task_struct *); 142#define ARCH_HAS_USER_SINGLE_STEP_INFO
140extern void user_enable_block_step(struct task_struct *);
141extern void user_disable_single_step(struct task_struct *);
142 143
143#endif /* __ASSEMBLY__ */ 144#endif /* __ASSEMBLY__ */
144 145
@@ -292,4 +293,75 @@ extern void user_disable_single_step(struct task_struct *);
292 293
293#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */ 294#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
294 295
296#define PPC_PTRACE_GETHWDBGINFO 0x89
297#define PPC_PTRACE_SETHWDEBUG 0x88
298#define PPC_PTRACE_DELHWDEBUG 0x87
299
300#ifndef __ASSEMBLY__
301
302struct ppc_debug_info {
303 uint32_t version; /* Only version 1 exists to date */
304 uint32_t num_instruction_bps;
305 uint32_t num_data_bps;
306 uint32_t num_condition_regs;
307 uint32_t data_bp_alignment;
308 uint32_t sizeof_condition; /* size of the DVC register */
309 uint64_t features;
310};
311
312#endif /* __ASSEMBLY__ */
313
314/*
315 * features will have bits indication whether there is support for:
316 */
317#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
318#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
319#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
320#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
321
322#ifndef __ASSEMBLY__
323
324struct ppc_hw_breakpoint {
325 uint32_t version; /* currently, version must be 1 */
326 uint32_t trigger_type; /* only some combinations allowed */
327 uint32_t addr_mode; /* address match mode */
328 uint32_t condition_mode; /* break/watchpoint condition flags */
329 uint64_t addr; /* break/watchpoint address */
330 uint64_t addr2; /* range end or mask */
331 uint64_t condition_value; /* contents of the DVC register */
332};
333
334#endif /* __ASSEMBLY__ */
335
336/*
337 * Trigger Type
338 */
339#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
340#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
341#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
342#define PPC_BREAKPOINT_TRIGGER_RW \
343 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
344
345/*
346 * Address Mode
347 */
348#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
349#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
350#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
351#define PPC_BREAKPOINT_MODE_MASK 0x00000003
352
353/*
354 * Condition Mode
355 */
356#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
357#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
358#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
359#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
360#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
361#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
362#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
363#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
364#define PPC_BREAKPOINT_CONDITION_BE(n) \
365 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
366
295#endif /* _ASM_POWERPC_PTRACE_H */ 367#endif /* _ASM_POWERPC_PTRACE_H */