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authorPaul Mundt <lethal@linux-sh.org>2012-01-08 19:56:37 -0500
committerPaul Mundt <lethal@linux-sh.org>2012-01-08 19:56:37 -0500
commit04cf399640b7acfa9abe2eb7900cd934db8af697 (patch)
treef9a055f2f0170550f5f0b0507b06ffce8d98945d /arch/powerpc/boot
parent17f0056e6a2f3d1818801705f5e12b71217bf4ef (diff)
parenta0e86bd4252519321b0d102dc4ed90557aa7bee9 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into rmobile-latest
Conflicts: arch/arm/mach-shmobile/Makefile Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/Makefile12
-rw-r--r--arch/powerpc/boot/dcr.h6
-rw-r--r--arch/powerpc/boot/div64.S52
-rw-r--r--arch/powerpc/boot/dts/asp834x-redboot.dts4
-rw-r--r--arch/powerpc/boot/dts/currituck.dts237
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi248
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi63
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi191
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi63
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi143
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi62
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi270
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi65
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi304
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi64
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi196
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi70
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-post.dtsi198
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi64
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi174
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi225
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi235
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi224
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi76
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-post.dtsi194
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi69
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi325
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi111
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi352
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi112
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-post.dtsi296
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi125
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi350
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi143
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi355
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi96
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi60
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi60
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi59
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi42
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi45
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi65
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi66
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi51
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi40
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi53
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi106
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi68
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi39
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi100
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi109
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi109
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/gef_ppc9a.dts4
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts4
-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts4
-rw-r--r--arch/powerpc/boot/dts/klondike.dts227
-rw-r--r--arch/powerpc/boot/dts/kmeter1.dts2
-rw-r--r--arch/powerpc/boot/dts/kuroboxHD.dts4
-rw-r--r--arch/powerpc/boot/dts/kuroboxHG.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8308_p1m.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8308rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc832x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc832x_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitx.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8349emitxgp.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc834x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc836x_rdk.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8377_wlan.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts456
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi141
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts410
-rw-r--r--arch/powerpc/boot/dts/mpc8540ads.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8541cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dts473
-rw-r--r--arch/powerpc/boot/dts/mpc8544ds.dtsi161
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts505
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8568mds.dts482
-rw-r--r--arch/powerpc/boot/dts/mpc8569mds.dts414
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dts757
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi397
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_36b.dts746
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts487
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts245
-rw-r--r--arch/powerpc/boot/dts/mpc8610_hpcd.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn.dts73
-rw-r--r--arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts4
-rw-r--r--arch/powerpc/boot/dts/obs600.dts314
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dts228
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi234
-rw-r--r--arch/powerpc/boot/dts/p1010rdb_36b.dts89
-rw-r--r--arch/powerpc/boot/dts/p1010si.dtsi374
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts262
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dtsi247
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_36b.dts66
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core0.dts154
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core1.dts11
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi377
-rw-r--r--arch/powerpc/boot/dts/p1021mds.dts425
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts459
-rw-r--r--arch/powerpc/boot/dts/p1023rds.dts383
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts353
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dtsi316
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts71
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts141
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts107
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi382
-rw-r--r--arch/powerpc/boot/dts/p2041rdb.dts22
-rw-r--r--arch/powerpc/boot/dts/p2041si.dtsi692
-rw-r--r--arch/powerpc/boot/dts/p3041ds.dts23
-rw-r--r--arch/powerpc/boot/dts/p3041si.dtsi729
-rw-r--r--arch/powerpc/boot/dts/p3060qds.dts12
-rw-r--r--arch/powerpc/boot/dts/p3060si.dtsi719
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts24
-rw-r--r--arch/powerpc/boot/dts/p4080si.dtsi755
-rw-r--r--arch/powerpc/boot/dts/p5020ds.dts24
-rw-r--r--arch/powerpc/boot/dts/p5020si.dtsi716
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8548.dts4
-rw-r--r--arch/powerpc/boot/dts/sbc8641d.dts4
-rw-r--r--arch/powerpc/boot/dts/socrates.dts4
-rw-r--r--arch/powerpc/boot/dts/storcenter.dts4
-rw-r--r--arch/powerpc/boot/dts/stxssa8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts23
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts23
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts4
-rw-r--r--arch/powerpc/boot/dts/tqm8xx.dts25
-rw-r--r--arch/powerpc/boot/dts/xcalibur1501.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5200.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5200_xmon.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5301.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5330.dts4
-rw-r--r--arch/powerpc/boot/dts/xpedite5370.dts4
-rw-r--r--arch/powerpc/boot/treeboot-currituck.c119
-rwxr-xr-xarch/powerpc/boot/wrapper45
182 files changed, 11850 insertions, 11863 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 72ee8c1fba48..15986e70799c 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -45,6 +45,7 @@ $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=405
45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405 45$(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 46$(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
47$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405 47$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
48$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
48$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405 49$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
49 50
50 51
@@ -79,7 +80,8 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
79 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 80 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
80 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 81 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
81 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ 82 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
82 gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c 83 gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
84 treeboot-currituck.c
83src-boot := $(src-wlib) $(src-plat) empty.c 85src-boot := $(src-wlib) $(src-plat) empty.c
84 86
85src-boot := $(addprefix $(obj)/, $(src-boot)) 87src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -199,6 +201,7 @@ image-$(CONFIG_EP405) += dtbImage.ep405
199image-$(CONFIG_HOTFOOT) += cuImage.hotfoot 201image-$(CONFIG_HOTFOOT) += cuImage.hotfoot
200image-$(CONFIG_WALNUT) += treeImage.walnut 202image-$(CONFIG_WALNUT) += treeImage.walnut
201image-$(CONFIG_ACADIA) += cuImage.acadia 203image-$(CONFIG_ACADIA) += cuImage.acadia
204image-$(CONFIG_OBS600) += uImage.obs600
202 205
203# Board ports in arch/powerpc/platform/44x/Kconfig 206# Board ports in arch/powerpc/platform/44x/Kconfig
204image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony 207image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
@@ -212,6 +215,7 @@ image-$(CONFIG_WARP) += cuImage.warp
212image-$(CONFIG_YOSEMITE) += cuImage.yosemite 215image-$(CONFIG_YOSEMITE) += cuImage.yosemite
213image-$(CONFIG_ISS4xx) += treeImage.iss4xx \ 216image-$(CONFIG_ISS4xx) += treeImage.iss4xx \
214 treeImage.iss4xx-mpic 217 treeImage.iss4xx-mpic
218image-$(CONFIG_CURRITUCK) += treeImage.currituck
215 219
216# Board ports in arch/powerpc/platform/8xx/Kconfig 220# Board ports in arch/powerpc/platform/8xx/Kconfig
217image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads 221image-$(CONFIG_MPC86XADS) += cuImage.mpc866ads
@@ -316,6 +320,12 @@ $(obj)/zImage.iseries: vmlinux
316$(obj)/uImage: vmlinux $(wrapperbits) 320$(obj)/uImage: vmlinux $(wrapperbits)
317 $(call if_changed,wrap,uboot) 321 $(call if_changed,wrap,uboot)
318 322
323$(obj)/uImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
324 $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
325
326$(obj)/uImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
327 $(call if_changed,wrap,uboot-$*,,$(obj)/$*.dtb)
328
319$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits) 329$(obj)/cuImage.initrd.%: vmlinux $(obj)/%.dtb $(wrapperbits)
320 $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz) 330 $(call if_changed,wrap,cuboot-$*,,$(obj)/$*.dtb,$(obj)/ramdisk.image.gz)
321 331
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h
index 645a7c964e5f..cc73f7a95e26 100644
--- a/arch/powerpc/boot/dcr.h
+++ b/arch/powerpc/boot/dcr.h
@@ -9,6 +9,12 @@
9 }) 9 })
10#define mtdcr(rn, val) \ 10#define mtdcr(rn, val) \
11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val)) 11 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
12#define mfdcrx(rn) \
13 ({ \
14 unsigned long rval; \
15 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
16 rval; \
17 })
12 18
13/* 440GP/440GX SDRAM controller DCRs */ 19/* 440GP/440GX SDRAM controller DCRs */
14#define DCRN_SDRAM0_CFGADDR 0x010 20#define DCRN_SDRAM0_CFGADDR 0x010
diff --git a/arch/powerpc/boot/div64.S b/arch/powerpc/boot/div64.S
index d271ab542673..bbcb8a4cc121 100644
--- a/arch/powerpc/boot/div64.S
+++ b/arch/powerpc/boot/div64.S
@@ -57,3 +57,55 @@ __div64_32:
57 stw r8,4(r3) 57 stw r8,4(r3)
58 mr r3,r6 # return the remainder in r3 58 mr r3,r6 # return the remainder in r3
59 blr 59 blr
60
61/*
62 * Extended precision shifts.
63 *
64 * Updated to be valid for shift counts from 0 to 63 inclusive.
65 * -- Gabriel
66 *
67 * R3/R4 has 64 bit value
68 * R5 has shift count
69 * result in R3/R4
70 *
71 * ashrdi3: arithmetic right shift (sign propagation)
72 * lshrdi3: logical right shift
73 * ashldi3: left shift
74 */
75 .globl __ashrdi3
76__ashrdi3:
77 subfic r6,r5,32
78 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
79 addi r7,r5,32 # could be xori, or addi with -32
80 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
81 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
82 sraw r7,r3,r7 # t2 = MSW >> (count-32)
83 or r4,r4,r6 # LSW |= t1
84 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
85 sraw r3,r3,r5 # MSW = MSW >> count
86 or r4,r4,r7 # LSW |= t2
87 blr
88
89 .globl __ashldi3
90__ashldi3:
91 subfic r6,r5,32
92 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
93 addi r7,r5,32 # could be xori, or addi with -32
94 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
95 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
96 or r3,r3,r6 # MSW |= t1
97 slw r4,r4,r5 # LSW = LSW << count
98 or r3,r3,r7 # MSW |= t2
99 blr
100
101 .globl __lshrdi3
102__lshrdi3:
103 subfic r6,r5,32
104 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
105 addi r7,r5,32 # could be xori, or addi with -32
106 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
107 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
108 or r4,r4,r6 # LSW |= t1
109 srw r3,r3,r5 # MSW = MSW >> count
110 or r4,r4,r7 # LSW |= t2
111 blr
diff --git a/arch/powerpc/boot/dts/asp834x-redboot.dts b/arch/powerpc/boot/dts/asp834x-redboot.dts
index 261d10c4534b..227290db866d 100644
--- a/arch/powerpc/boot/dts/asp834x-redboot.dts
+++ b/arch/powerpc/boot/dts/asp834x-redboot.dts
@@ -256,7 +256,7 @@
256 serial0: serial@4500 { 256 serial0: serial@4500 {
257 cell-index = <0>; 257 cell-index = <0>;
258 device_type = "serial"; 258 device_type = "serial";
259 compatible = "ns16550"; 259 compatible = "fsl,ns16550", "ns16550";
260 reg = <0x4500 0x100>; 260 reg = <0x4500 0x100>;
261 clock-frequency = <400000000>; 261 clock-frequency = <400000000>;
262 interrupts = <9 0x8>; 262 interrupts = <9 0x8>;
@@ -266,7 +266,7 @@
266 serial1: serial@4600 { 266 serial1: serial@4600 {
267 cell-index = <1>; 267 cell-index = <1>;
268 device_type = "serial"; 268 device_type = "serial";
269 compatible = "ns16550"; 269 compatible = "fsl,ns16550", "ns16550";
270 reg = <0x4600 0x100>; 270 reg = <0x4600 0x100>;
271 clock-frequency = <400000000>; 271 clock-frequency = <400000000>;
272 interrupts = <10 0x8>; 272 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
new file mode 100644
index 000000000000..b801dd06e573
--- /dev/null
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -0,0 +1,237 @@
1/*
2 * Device Tree Source for IBM Embedded PPC 476 Platform
3 *
4 * Copyright © 2011 Tony Breeds IBM Corporation
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
10
11/dts-v1/;
12
13/memreserve/ 0x01f00000 0x00100000; // spin table
14
15/ {
16 #address-cells = <2>;
17 #size-cells = <2>;
18 model = "ibm,currituck";
19 compatible = "ibm,currituck";
20 dcr-parent = <&{/cpus/cpu@0}>;
21
22 aliases {
23 serial0 = &UART0;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 model = "PowerPC,476";
33 reg = <0>;
34 clock-frequency = <1600000000>; // 1.6 GHz
35 timebase-frequency = <100000000>; // 100Mhz
36 i-cache-line-size = <32>;
37 d-cache-line-size = <32>;
38 i-cache-size = <32768>;
39 d-cache-size = <32768>;
40 dcr-controller;
41 dcr-access-method = "native";
42 status = "ok";
43 };
44 cpu@1 {
45 device_type = "cpu";
46 model = "PowerPC,476";
47 reg = <1>;
48 clock-frequency = <1600000000>; // 1.6 GHz
49 timebase-frequency = <100000000>; // 100Mhz
50 i-cache-line-size = <32>;
51 d-cache-line-size = <32>;
52 i-cache-size = <32768>;
53 d-cache-size = <32768>;
54 dcr-controller;
55 dcr-access-method = "native";
56 status = "disabled";
57 enable-method = "spin-table";
58 cpu-release-addr = <0x0 0x01f00000>;
59 };
60 };
61
62 memory {
63 device_type = "memory";
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
65 };
66
67 MPIC: interrupt-controller {
68 compatible = "chrp,open-pic";
69 interrupt-controller;
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
74
75 };
76
77 plb {
78 compatible = "ibm,plb6";
79 #address-cells = <2>;
80 #size-cells = <2>;
81 ranges;
82 clock-frequency = <200000000>; // 200Mhz
83
84 POB0: opb {
85 compatible = "ibm,opb-4xx", "ibm,opb";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 /* Wish there was a nicer way of specifying a full
89 * 32-bit range
90 */
91 ranges = <0x00000000 0x00000200 0x00000000 0x80000000
92 0x80000000 0x00000200 0x80000000 0x80000000>;
93 clock-frequency = <100000000>;
94
95 UART0: serial@10000000 {
96 device_type = "serial";
97 compatible = "ns16750", "ns16550";
98 reg = <0x10000000 0x00000008>;
99 virtual-reg = <0xe1000000>;
100 clock-frequency = <1851851>; // PCIe refclk/MCGC0_CTL[UART]
101 current-speed = <115200>;
102 interrupt-parent = <&MPIC>;
103 interrupts = <34 2>;
104 };
105
106 IIC0: i2c@00000000 {
107 compatible = "ibm,iic-currituck", "ibm,iic";
108 reg = <0x0 0x00000014>;
109 interrupt-parent = <&MPIC>;
110 interrupts = <79 2>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 rtc@68 {
114 compatible = "stm,m41t80", "m41st85";
115 reg = <0x68>;
116 };
117 };
118 };
119
120 PCIE0: pciex@10100000000 { // 4xGBIF1
121 device_type = "pci";
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
126 primary;
127 port = <0x0>; /* port number */
128 reg = <0x00000101 0x00000000 0x0 0x10000000 /* Config space access */
129 0x00000100 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
130 dcr-reg = <0x80 0x20>;
131
132// pci_space < pci_addr > < cpu_addr > < size >
133 ranges = <0x02000000 0x00000000 0x80000000 0x00000110 0x80000000 0x0 0x80000000
134 0x01000000 0x0 0x0 0x00000140 0x0 0x0 0x00010000>;
135
136 /* Inbound starting at 0 to memsize filled in by zImage */
137 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
138
139 /* This drives busses 0 to 0xf */
140 bus-range = <0x0 0xf>;
141
142 /* Legacy interrupts (note the weird polarity, the bridge seems
143 * to invert PCIe legacy interrupts).
144 * We are de-swizzling here because the numbers are actually for
145 * port of the root complex virtual P2P bridge. But I want
146 * to avoid putting a node for it in the tree, so the numbers
147 * below are basically de-swizzled numbers.
148 * The real slot is on idsel 0, so the swizzling is 1:1
149 */
150 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
151 interrupt-map = <
152 0x0 0x0 0x0 0x1 &MPIC 46 0x2 /* int A */
153 0x0 0x0 0x0 0x2 &MPIC 47 0x2 /* int B */
154 0x0 0x0 0x0 0x3 &MPIC 48 0x2 /* int C */
155 0x0 0x0 0x0 0x4 &MPIC 49 0x2 /* int D */>;
156 };
157
158 PCIE1: pciex@30100000000 { // 4xGBIF0
159 device_type = "pci";
160 #interrupt-cells = <1>;
161 #size-cells = <2>;
162 #address-cells = <3>;
163 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
164 primary;
165 port = <0x1>; /* port number */
166 reg = <0x00000301 0x00000000 0x0 0x10000000 /* Config space access */
167 0x00000300 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
168 dcr-reg = <0x60 0x20>;
169
170 ranges = <0x02000000 0x00000000 0x80000000 0x00000310 0x80000000 0x0 0x80000000
171 0x01000000 0x0 0x0 0x00000340 0x0 0x0 0x00010000>;
172
173 /* Inbound starting at 0 to memsize filled in by zImage */
174 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
175
176 /* This drives busses 0 to 0xf */
177 bus-range = <0x0 0xf>;
178
179 /* Legacy interrupts (note the weird polarity, the bridge seems
180 * to invert PCIe legacy interrupts).
181 * We are de-swizzling here because the numbers are actually for
182 * port of the root complex virtual P2P bridge. But I want
183 * to avoid putting a node for it in the tree, so the numbers
184 * below are basically de-swizzled numbers.
185 * The real slot is on idsel 0, so the swizzling is 1:1
186 */
187 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
188 interrupt-map = <
189 0x0 0x0 0x0 0x1 &MPIC 38 0x2 /* int A */
190 0x0 0x0 0x0 0x2 &MPIC 39 0x2 /* int B */
191 0x0 0x0 0x0 0x3 &MPIC 40 0x2 /* int C */
192 0x0 0x0 0x0 0x4 &MPIC 41 0x2 /* int D */>;
193 };
194
195 PCIE2: pciex@38100000000 { // 2xGBIF0
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 compatible = "ibm,plb-pciex-476fpe", "ibm,plb-pciex";
201 primary;
202 port = <0x2>; /* port number */
203 reg = <0x00000381 0x00000000 0x0 0x10000000 /* Config space access */
204 0x00000380 0x00000000 0x0 0x00001000>; /* UTL Registers space access */
205 dcr-reg = <0xA0 0x20>;
206
207 ranges = <0x02000000 0x00000000 0x80000000 0x00000390 0x80000000 0x0 0x80000000
208 0x01000000 0x0 0x0 0x000003C0 0x0 0x0 0x00010000>;
209
210 /* Inbound starting at 0 to memsize filled in by zImage */
211 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x0>;
212
213 /* This drives busses 0 to 0xf */
214 bus-range = <0x0 0xf>;
215
216 /* Legacy interrupts (note the weird polarity, the bridge seems
217 * to invert PCIe legacy interrupts).
218 * We are de-swizzling here because the numbers are actually for
219 * port of the root complex virtual P2P bridge. But I want
220 * to avoid putting a node for it in the tree, so the numbers
221 * below are basically de-swizzled numbers.
222 * The real slot is on idsel 0, so the swizzling is 1:1
223 */
224 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
225 interrupt-map = <
226 0x0 0x0 0x0 0x1 &MPIC 54 0x2 /* int A */
227 0x0 0x0 0x0 0x2 &MPIC 55 0x2 /* int B */
228 0x0 0x0 0x0 0x3 &MPIC 56 0x2 /* int C */
229 0x0 0x0 0x0 0x4 &MPIC 57 0x2 /* int D */>;
230 };
231
232 };
233
234 chosen {
235 linux,stdout-path = &UART0;
236 };
237};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
new file mode 100644
index 000000000000..89af62637707
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -0,0 +1,248 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8548-pcie";
56 device_type = "pci";
57 #size-cells = <2>;
58 #address-cells = <3>;
59 bus-range = <0 255>;
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
62
63 pcie@0 {
64 reg = <0 0 0 0 0>;
65 #interrupt-cells = <1>;
66 #size-cells = <2>;
67 #address-cells = <3>;
68 device_type = "pci";
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
71
72 interrupt-map = <
73 /* IDSEL 0x0 */
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
78 >;
79 };
80};
81
82/* controller at 0xa000 */
83&pci2 {
84 compatible = "fsl,mpc8548-pcie";
85 device_type = "pci";
86 #size-cells = <2>;
87 #address-cells = <3>;
88 bus-range = <0 255>;
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
91
92 pcie@0 {
93 reg = <0 0 0 0 0>;
94 #interrupt-cells = <1>;
95 #size-cells = <2>;
96 #address-cells = <3>;
97 device_type = "pci";
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
100 interrupt-map = <
101 /* IDSEL 0x0 */
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
106 >;
107 };
108};
109
110/* controller at 0xb000 */
111&pci3 {
112 compatible = "fsl,mpc8548-pcie";
113 device_type = "pci";
114 #size-cells = <2>;
115 #address-cells = <3>;
116 bus-range = <0 255>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
119
120 pcie@0 {
121 reg = <0 0 0 0 0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 device_type = "pci";
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
128 interrupt-map = <
129 /* IDSEL 0x0 */
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
134 >;
135 };
136};
137&soc {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 device_type = "soc";
141 compatible = "fsl,mpc8536-immr", "simple-bus";
142 bus-frequency = <0>; // Filled out by uboot.
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <12>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2 0 0>;
154 };
155
156 memory-controller@2000 {
157 compatible = "fsl,mpc8536-memory-controller";
158 reg = <0x2000 0x1000>;
159 interrupts = <18 2 0 0>;
160 };
161
162/include/ "pq3-i2c-0.dtsi"
163/include/ "pq3-i2c-1.dtsi"
164/include/ "pq3-duart-0.dtsi"
165
166/include/ "pq3-espi-0.dtsi"
167 spi@7000 {
168 fsl,espi-num-chipselects = <4>;
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 /* mark compat w/8572 to get some erratum treatment */
174 gpio-controller@f000 {
175 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
176 };
177
178 sata@18000 {
179 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
180 reg = <0x18000 0x1000>;
181 cell-index = <1>;
182 interrupts = <74 0x2 0 0>;
183 };
184
185 sata@19000 {
186 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
187 reg = <0x19000 0x1000>;
188 cell-index = <2>;
189 interrupts = <41 0x2 0 0>;
190 };
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,mpc8536-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x80000>; // L2, 512K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-etsec1-0.dtsi"
202/include/ "pq3-etsec1-timer-0.dtsi"
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupts = <28 0x2 0 0>;
210 };
211
212 usb@23000 {
213 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 interrupts = <46 0x2 0 0>;
218 };
219
220 ptp_clock@24e00 {
221 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
222 };
223
224/include/ "pq3-etsec1-2.dtsi"
225
226 ethernet@26000 {
227 cell-index = <1>;
228 };
229
230 usb@2b000 {
231 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
232 reg = <0x2b000 0x1000>;
233 #address-cells = <1>;
234 #size-cells = <0>;
235 interrupts = <60 0x2 0 0>;
236 };
237
238/include/ "pq3-esdhc-0.dtsi"
239/include/ "pq3-sec3.0-0.dtsi"
240/include/ "pq3-mpic.dtsi"
241/include/ "pq3-mpic-timer-B.dtsi"
242
243 global-utilities@e0000 {
244 compatible = "fsl,mpc8536-guts";
245 reg = <0xe0000 0x1000>;
246 fsl,has-rstcr;
247 };
248};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
new file mode 100644
index 000000000000..7de45a784df6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi
@@ -0,0 +1,63 @@
1/*
2 * MPC8536 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8536";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 pci3 = &pci3;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8536@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
new file mode 100644
index 000000000000..b68eb119faef
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi
@@ -0,0 +1,191 @@
1/*
2 * MPC8544 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8548-pcie";
56 device_type = "pci";
57 #size-cells = <2>;
58 #address-cells = <3>;
59 bus-range = <0 255>;
60 clock-frequency = <33333333>;
61 interrupts = <25 2 0 0>;
62
63 pcie@0 {
64 reg = <0 0 0 0 0>;
65 #interrupt-cells = <1>;
66 #size-cells = <2>;
67 #address-cells = <3>;
68 device_type = "pci";
69 interrupts = <25 2 0 0>;
70 interrupt-map-mask = <0xf800 0 0 7>;
71
72 interrupt-map = <
73 /* IDSEL 0x0 */
74 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
75 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
76 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
77 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
78 >;
79 };
80};
81
82/* controller at 0xa000 */
83&pci2 {
84 compatible = "fsl,mpc8548-pcie";
85 device_type = "pci";
86 #size-cells = <2>;
87 #address-cells = <3>;
88 bus-range = <0 255>;
89 clock-frequency = <33333333>;
90 interrupts = <26 2 0 0>;
91
92 pcie@0 {
93 reg = <0 0 0 0 0>;
94 #interrupt-cells = <1>;
95 #size-cells = <2>;
96 #address-cells = <3>;
97 device_type = "pci";
98 interrupts = <26 2 0 0>;
99 interrupt-map-mask = <0xf800 0 0 7>;
100 interrupt-map = <
101 /* IDSEL 0x0 */
102 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
103 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
104 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
105 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
106 >;
107 };
108};
109
110/* controller at 0xb000 */
111&pci3 {
112 compatible = "fsl,mpc8548-pcie";
113 device_type = "pci";
114 #size-cells = <2>;
115 #address-cells = <3>;
116 bus-range = <0 255>;
117 clock-frequency = <33333333>;
118 interrupts = <27 2 0 0>;
119
120 pcie@0 {
121 reg = <0 0 0 0 0>;
122 #interrupt-cells = <1>;
123 #size-cells = <2>;
124 #address-cells = <3>;
125 device_type = "pci";
126 interrupts = <27 2 0 0>;
127 interrupt-map-mask = <0xf800 0 0 7>;
128 interrupt-map = <
129 /* IDSEL 0x0 */
130 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
131 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
132 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
133 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
134 >;
135 };
136};
137
138&soc {
139 #address-cells = <1>;
140 #size-cells = <1>;
141 device_type = "soc";
142 compatible = "fsl,mpc8544-immr", "simple-bus";
143 bus-frequency = <0>; // Filled out by uboot.
144
145 ecm-law@0 {
146 compatible = "fsl,ecm-law";
147 reg = <0x0 0x1000>;
148 fsl,num-laws = <10>;
149 };
150
151 ecm@1000 {
152 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
153 reg = <0x1000 0x1000>;
154 interrupts = <17 2 0 0>;
155 };
156
157 memory-controller@2000 {
158 compatible = "fsl,mpc8544-memory-controller";
159 reg = <0x2000 0x1000>;
160 interrupts = <18 2 0 0>;
161 };
162
163/include/ "pq3-i2c-0.dtsi"
164/include/ "pq3-i2c-1.dtsi"
165/include/ "pq3-duart-0.dtsi"
166
167 L2: l2-cache-controller@20000 {
168 compatible = "fsl,mpc8544-l2-cache-controller";
169 reg = <0x20000 0x1000>;
170 cache-line-size = <32>; // 32 bytes
171 cache-size = <0x40000>; // L2, 256K
172 interrupts = <16 2 0 0>;
173 };
174
175/include/ "pq3-dma-0.dtsi"
176/include/ "pq3-etsec1-0.dtsi"
177/include/ "pq3-etsec1-2.dtsi"
178
179 ethernet@26000 {
180 cell-index = <1>;
181 };
182
183/include/ "pq3-sec2.1-0.dtsi"
184/include/ "pq3-mpic.dtsi"
185
186 global-utilities@e0000 {
187 compatible = "fsl,mpc8544-guts";
188 reg = <0xe0000 0x1000>;
189 fsl,has-rstcr;
190 };
191};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
new file mode 100644
index 000000000000..8777f9239d9e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8544si-pre.dtsi
@@ -0,0 +1,63 @@
1/*
2 * MPC8544 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8544";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 pci3 = &pci3;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8544@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62 };
63};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
new file mode 100644
index 000000000000..9d8023a69d7d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -0,0 +1,143 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
45 device_type = "pci";
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
51};
52
53/* controller at 0x9000 */
54&pci1 {
55 compatible = "fsl,mpc8540-pci";
56 device_type = "pci";
57 interrupts = <25 0x2 0 0>;
58 bus-range = <0 0xff>;
59 #interrupt-cells = <1>;
60 #size-cells = <2>;
61 #address-cells = <3>;
62};
63
64/* controller at 0xa000 */
65&pci2 {
66 compatible = "fsl,mpc8548-pcie";
67 device_type = "pci";
68 #size-cells = <2>;
69 #address-cells = <3>;
70 bus-range = <0 255>;
71 clock-frequency = <33333333>;
72 interrupts = <26 2 0 0>;
73
74 pcie@0 {
75 reg = <0 0 0 0 0>;
76 #interrupt-cells = <1>;
77 #size-cells = <2>;
78 #address-cells = <3>;
79 device_type = "pci";
80 interrupts = <26 2 0 0>;
81 interrupt-map-mask = <0xf800 0 0 7>;
82 interrupt-map = <
83 /* IDSEL 0x0 */
84 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
85 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
86 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
87 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
88 >;
89 };
90};
91
92&soc {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 device_type = "soc";
96 compatible = "fsl,mpc8548-immr", "simple-bus";
97 bus-frequency = <0>; // Filled out by uboot.
98
99 ecm-law@0 {
100 compatible = "fsl,ecm-law";
101 reg = <0x0 0x1000>;
102 fsl,num-laws = <10>;
103 };
104
105 ecm@1000 {
106 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
107 reg = <0x1000 0x1000>;
108 interrupts = <17 2 0 0>;
109 };
110
111 memory-controller@2000 {
112 compatible = "fsl,mpc8548-memory-controller";
113 reg = <0x2000 0x1000>;
114 interrupts = <18 2 0 0>;
115 };
116
117/include/ "pq3-i2c-0.dtsi"
118/include/ "pq3-i2c-1.dtsi"
119/include/ "pq3-duart-0.dtsi"
120
121 L2: l2-cache-controller@20000 {
122 compatible = "fsl,mpc8548-l2-cache-controller";
123 reg = <0x20000 0x1000>;
124 cache-line-size = <32>; // 32 bytes
125 cache-size = <0x80000>; // L2, 512K
126 interrupts = <16 2 0 0>;
127 };
128
129/include/ "pq3-dma-0.dtsi"
130/include/ "pq3-etsec1-0.dtsi"
131/include/ "pq3-etsec1-1.dtsi"
132/include/ "pq3-etsec1-2.dtsi"
133/include/ "pq3-etsec1-3.dtsi"
134
135/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi"
137
138 global-utilities@e0000 {
139 compatible = "fsl,mpc8548-guts";
140 reg = <0xe0000 0x1000>;
141 fsl,has-rstcr;
142 };
143};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
new file mode 100644
index 000000000000..289f1218d755
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -0,0 +1,62 @@
1/*
2 * MPC8548 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8548";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet2;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8548@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61 };
62};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
new file mode 100644
index 000000000000..64e7075a9cd4
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-post.dtsi
@@ -0,0 +1,270 @@
1/*
2 * MPC8568 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0x8000 */
44&pci0 {
45 compatible = "fsl,mpc8540-pci";
46 device_type = "pci";
47 interrupts = <24 0x2 0 0>;
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
52 sleep = <&pmc 0x80000000>;
53};
54
55/* controller at 0xa000 */
56&pci1 {
57 compatible = "fsl,mpc8548-pcie";
58 device_type = "pci";
59 #size-cells = <2>;
60 #address-cells = <3>;
61 bus-range = <0 255>;
62 clock-frequency = <33333333>;
63 interrupts = <26 2 0 0>;
64 sleep = <&pmc 0x20000000>;
65
66 pcie@0 {
67 reg = <0 0 0 0 0>;
68 #interrupt-cells = <1>;
69 #size-cells = <2>;
70 #address-cells = <3>;
71 device_type = "pci";
72 interrupts = <26 2 0 0>;
73 interrupt-map-mask = <0xf800 0 0 7>;
74 interrupt-map = <
75 /* IDSEL 0x0 */
76 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
77 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
78 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
79 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
80 >;
81 };
82};
83
84&rio {
85 compatible = "fsl,srio";
86 interrupts = <48 2 0 0>;
87 #address-cells = <2>;
88 #size-cells = <2>;
89 fsl,srio-rmu-handle = <&rmu>;
90 sleep = <&pmc 0x00080000>;
91 ranges;
92
93 port1 {
94 #address-cells = <2>;
95 #size-cells = <2>;
96 cell-index = <1>;
97 };
98};
99
100&soc {
101 #address-cells = <1>;
102 #size-cells = <1>;
103 device_type = "soc";
104 compatible = "fsl,mpc8568-immr", "simple-bus";
105 bus-frequency = <0>; // Filled out by uboot.
106
107 ecm-law@0 {
108 compatible = "fsl,ecm-law";
109 reg = <0x0 0x1000>;
110 fsl,num-laws = <10>;
111 };
112
113 ecm@1000 {
114 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
115 reg = <0x1000 0x1000>;
116 interrupts = <17 2 0 0>;
117 };
118
119 memory-controller@2000 {
120 compatible = "fsl,mpc8568-memory-controller";
121 reg = <0x2000 0x1000>;
122 interrupts = <18 2 0 0>;
123 };
124
125 i2c-sleep-nexus {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "simple-bus";
129 sleep = <&pmc 0x00000004>;
130 ranges;
131
132/include/ "pq3-i2c-0.dtsi"
133/include/ "pq3-i2c-1.dtsi"
134
135 };
136
137 duart-sleep-nexus {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "simple-bus";
141 sleep = <&pmc 0x00000002>;
142 ranges;
143
144/include/ "pq3-duart-0.dtsi"
145
146 };
147
148 L2: l2-cache-controller@20000 {
149 compatible = "fsl,mpc8568-l2-cache-controller";
150 reg = <0x20000 0x1000>;
151 cache-line-size = <32>; // 32 bytes
152 cache-size = <0x80000>; // L2, 512K
153 interrupts = <16 2 0 0>;
154 };
155
156/include/ "pq3-dma-0.dtsi"
157 dma@21300 {
158 sleep = <&pmc 0x00000400>;
159 };
160
161/include/ "pq3-etsec1-0.dtsi"
162 ethernet@24000 {
163 sleep = <&pmc 0x00000080>;
164 };
165
166/include/ "pq3-etsec1-1.dtsi"
167 ethernet@25000 {
168 sleep = <&pmc 0x00000040>;
169 };
170
171 par_io@e0100 {
172 reg = <0xe0100 0x100>;
173 device_type = "par_io";
174 };
175
176/include/ "pq3-sec2.1-0.dtsi"
177 crypto@30000 {
178 sleep = <&pmc 0x01000000>;
179 };
180
181/include/ "pq3-mpic.dtsi"
182/include/ "pq3-rmu-0.dtsi"
183 rmu@d3000 {
184 sleep = <&pmc 0x00040000>;
185 };
186
187 global-utilities@e0000 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
191 reg = <0xe0000 0x1000>;
192 ranges = <0 0xe0000 0x1000>;
193 fsl,has-rstcr;
194
195 pmc: power@70 {
196 compatible = "fsl,mpc8568-pmc",
197 "fsl,mpc8548-pmc";
198 reg = <0x70 0x20>;
199 };
200 };
201};
202
203&qe {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 device_type = "qe";
207 compatible = "fsl,qe";
208 sleep = <&pmc 0x00000800>;
209 brg-frequency = <0>;
210 bus-frequency = <396000000>;
211 fsl,qe-num-riscs = <2>;
212 fsl,qe-num-snums = <28>;
213
214 qeic: interrupt-controller@80 {
215 interrupt-controller;
216 compatible = "fsl,qe-ic";
217 #address-cells = <0>;
218 #interrupt-cells = <1>;
219 reg = <0x80 0x80>;
220 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
221 interrupt-parent = <&mpic>;
222 };
223
224 spi@4c0 {
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "fsl,spi";
228 reg = <0x4c0 0x40>;
229 cell-index = <0>;
230 interrupts = <2>;
231 interrupt-parent = <&qeic>;
232 };
233
234 spi@500 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl,spi";
239 reg = <0x500 0x40>;
240 interrupts = <1>;
241 interrupt-parent = <&qeic>;
242 };
243
244 ucc@2000 {
245 cell-index = <1>;
246 reg = <0x2000 0x200>;
247 interrupts = <32>;
248 interrupt-parent = <&qeic>;
249 };
250
251 ucc@3000 {
252 cell-index = <2>;
253 reg = <0x3000 0x200>;
254 interrupts = <33>;
255 interrupt-parent = <&qeic>;
256 };
257
258 muram@10000 {
259 #address-cells = <1>;
260 #size-cells = <1>;
261 compatible = "fsl,qe-muram", "fsl,cpm-muram";
262 ranges = <0x0 0x10000 0x10000>;
263
264 data-only@0 {
265 compatible = "fsl,qe-muram-data",
266 "fsl,cpm-muram-data";
267 reg = <0x0 0x10000>;
268 };
269 };
270};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
new file mode 100644
index 000000000000..eacd62c5fe6c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8568si-pre.dtsi
@@ -0,0 +1,65 @@
1/*
2 * MPC8568 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8568";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci0 = &pci0;
50 pci1 = &pci1;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,8568@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 sleep = <&pmc 0x00008000 // core
62 &pmc 0x00004000>; // timebase
63 };
64 };
65};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
new file mode 100644
index 000000000000..3e6346a4a183
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-post.dtsi
@@ -0,0 +1,304 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
41};
42
43/* controller at 0xa000 */
44&pci1 {
45 compatible = "fsl,mpc8548-pcie";
46 device_type = "pci";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
53
54 pcie@0 {
55 reg = <0 0 0 0 0>;
56 #interrupt-cells = <1>;
57 #size-cells = <2>;
58 #address-cells = <3>;
59 device_type = "pci";
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
62 interrupt-map = <
63 /* IDSEL 0x0 */
64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
68 >;
69 };
70};
71
72&rio {
73 compatible = "fsl,srio";
74 interrupts = <48 2 0 0>;
75 #address-cells = <2>;
76 #size-cells = <2>;
77 fsl,srio-rmu-handle = <&rmu>;
78 sleep = <&pmc 0x00080000>;
79 ranges;
80
81 port1 {
82 #address-cells = <2>;
83 #size-cells = <2>;
84 cell-index = <1>;
85 };
86
87 port2 {
88 #address-cells = <2>;
89 #size-cells = <2>;
90 cell-index = <2>;
91 };
92};
93
94&soc {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 device_type = "soc";
98 compatible = "fsl,mpc8569-immr", "simple-bus";
99 bus-frequency = <0>; // Filled out by uboot.
100
101 ecm-law@0 {
102 compatible = "fsl,ecm-law";
103 reg = <0x0 0x1000>;
104 fsl,num-laws = <10>;
105 };
106
107 ecm@1000 {
108 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
109 reg = <0x1000 0x1000>;
110 interrupts = <17 2 0 0>;
111 };
112
113 memory-controller@2000 {
114 compatible = "fsl,mpc8569-memory-controller";
115 reg = <0x2000 0x1000>;
116 interrupts = <18 2 0 0>;
117 };
118
119 i2c-sleep-nexus {
120 #address-cells = <1>;
121 #size-cells = <1>;
122 compatible = "simple-bus";
123 sleep = <&pmc 0x00000004>;
124 ranges;
125
126/include/ "pq3-i2c-0.dtsi"
127/include/ "pq3-i2c-1.dtsi"
128
129 };
130
131 duart-sleep-nexus {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "simple-bus";
135 sleep = <&pmc 0x00000002>;
136 ranges;
137
138/include/ "pq3-duart-0.dtsi"
139
140 };
141
142 L2: l2-cache-controller@20000 {
143 compatible = "fsl,mpc8569-l2-cache-controller";
144 reg = <0x20000 0x1000>;
145 cache-line-size = <32>; // 32 bytes
146 cache-size = <0x80000>; // L2, 512K
147 interrupts = <16 2 0 0>;
148 };
149
150/include/ "pq3-dma-0.dtsi"
151/include/ "pq3-esdhc-0.dtsi"
152 sdhc@2e000 {
153 sleep = <&pmc 0x00200000>;
154 };
155
156 par_io@e0100 {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 reg = <0xe0100 0x100>;
160 ranges = <0x0 0xe0100 0x100>;
161 device_type = "par_io";
162 };
163
164/include/ "pq3-sec3.1-0.dtsi"
165 crypto@30000 {
166 sleep = <&pmc 0x01000000>;
167 };
168
169/include/ "pq3-mpic.dtsi"
170/include/ "pq3-rmu-0.dtsi"
171 rmu@d3000 {
172 sleep = <&pmc 0x00040000>;
173 };
174
175 global-utilities@e0000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
179 reg = <0xe0000 0x1000>;
180 ranges = <0 0xe0000 0x1000>;
181 fsl,has-rstcr;
182
183 pmc: power@70 {
184 compatible = "fsl,mpc8569-pmc",
185 "fsl,mpc8548-pmc";
186 reg = <0x70 0x20>;
187 };
188 };
189};
190
191&qe {
192 #address-cells = <1>;
193 #size-cells = <1>;
194 device_type = "qe";
195 compatible = "fsl,qe";
196 sleep = <&pmc 0x00000800>;
197 brg-frequency = <0>;
198 bus-frequency = <0>;
199 fsl,qe-num-riscs = <4>;
200 fsl,qe-num-snums = <46>;
201
202 qeic: interrupt-controller@80 {
203 interrupt-controller;
204 compatible = "fsl,qe-ic";
205 #address-cells = <0>;
206 #interrupt-cells = <1>;
207 reg = <0x80 0x80>;
208 interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30
209 interrupt-parent = <&mpic>;
210 };
211
212 timer@440 {
213 compatible = "fsl,mpc8569-qe-gtm",
214 "fsl,qe-gtm", "fsl,gtm";
215 reg = <0x440 0x40>;
216 interrupts = <12 13 14 15>;
217 interrupt-parent = <&qeic>;
218 /* Filled in by U-Boot */
219 clock-frequency = <0>;
220 };
221
222 spi@4c0 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
226 reg = <0x4c0 0x40>;
227 cell-index = <0>;
228 interrupts = <2>;
229 interrupt-parent = <&qeic>;
230 };
231
232 spi@500 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 cell-index = <1>;
236 compatible = "fsl,spi";
237 reg = <0x500 0x40>;
238 interrupts = <1>;
239 interrupt-parent = <&qeic>;
240 };
241
242 usb@6c0 {
243 compatible = "fsl,mpc8569-qe-usb",
244 "fsl,mpc8323-qe-usb";
245 reg = <0x6c0 0x40 0x8b00 0x100>;
246 interrupts = <11>;
247 interrupt-parent = <&qeic>;
248 };
249
250 ucc@2000 {
251 cell-index = <1>;
252 reg = <0x2000 0x200>;
253 interrupts = <32>;
254 interrupt-parent = <&qeic>;
255 };
256
257 ucc@2200 {
258 cell-index = <3>;
259 reg = <0x2200 0x200>;
260 interrupts = <34>;
261 interrupt-parent = <&qeic>;
262 };
263
264 ucc@3000 {
265 cell-index = <2>;
266 reg = <0x3000 0x200>;
267 interrupts = <33>;
268 interrupt-parent = <&qeic>;
269 };
270
271 ucc@3200 {
272 cell-index = <4>;
273 reg = <0x3200 0x200>;
274 interrupts = <35>;
275 interrupt-parent = <&qeic>;
276 };
277
278 ucc@3400 {
279 cell-index = <6>;
280 reg = <0x3400 0x200>;
281 interrupts = <41>;
282 interrupt-parent = <&qeic>;
283 };
284
285 ucc@3600 {
286 cell-index = <8>;
287 reg = <0x3600 0x200>;
288 interrupts = <43>;
289 interrupt-parent = <&qeic>;
290 };
291
292 muram@10000 {
293 #address-cells = <1>;
294 #size-cells = <1>;
295 compatible = "fsl,qe-muram", "fsl,cpm-muram";
296 ranges = <0x0 0x10000 0x20000>;
297
298 data-only@0 {
299 compatible = "fsl,qe-muram-data",
300 "fsl,cpm-muram-data";
301 reg = <0x0 0x20000>;
302 };
303 };
304};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
new file mode 100644
index 000000000000..b07064d11930
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8569si-pre.dtsi
@@ -0,0 +1,64 @@
1/*
2 * MPC8569 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8569";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,8569@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 sleep = <&pmc 0x00008000 // core
61 &pmc 0x00004000>; // timebase
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
new file mode 100644
index 000000000000..d44e25a48734
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
@@ -0,0 +1,196 @@
1/*
2 * MPC8572 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x8000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <24 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <24 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60
61 interrupt-map = <
62 /* IDSEL 0x0 */
63 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
64 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
65 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
66 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
67 >;
68 };
69};
70
71/* controller at 0x9000 */
72&pci1 {
73 compatible = "fsl,mpc8548-pcie";
74 device_type = "pci";
75 #size-cells = <2>;
76 #address-cells = <3>;
77 bus-range = <0 255>;
78 clock-frequency = <33333333>;
79 interrupts = <25 2 0 0>;
80
81 pcie@0 {
82 reg = <0 0 0 0 0>;
83 #interrupt-cells = <1>;
84 #size-cells = <2>;
85 #address-cells = <3>;
86 device_type = "pci";
87 interrupts = <25 2 0 0>;
88 interrupt-map-mask = <0xf800 0 0 7>;
89
90 interrupt-map = <
91 /* IDSEL 0x0 */
92 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
93 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
94 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
95 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
96 >;
97 };
98};
99
100/* controller at 0xa000 */
101&pci2 {
102 compatible = "fsl,mpc8548-pcie";
103 device_type = "pci";
104 #size-cells = <2>;
105 #address-cells = <3>;
106 bus-range = <0 255>;
107 clock-frequency = <33333333>;
108 interrupts = <26 2 0 0>;
109
110 pcie@0 {
111 reg = <0 0 0 0 0>;
112 #interrupt-cells = <1>;
113 #size-cells = <2>;
114 #address-cells = <3>;
115 device_type = "pci";
116 interrupts = <26 2 0 0>;
117 interrupt-map-mask = <0xf800 0 0 7>;
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,mpc8572-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <17 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,mpc8572-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <18 2 0 0>;
151 };
152
153 memory-controller@6000 {
154 compatible = "fsl,mpc8572-memory-controller";
155 reg = <0x6000 0x1000>;
156 interrupts = <18 2 0 0>;
157 };
158
159/include/ "pq3-i2c-0.dtsi"
160/include/ "pq3-i2c-1.dtsi"
161/include/ "pq3-duart-0.dtsi"
162/include/ "pq3-dma-1.dtsi"
163/include/ "pq3-gpio-0.dtsi"
164 gpio-controller@f000 {
165 compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio";
166 };
167
168 L2: l2-cache-controller@20000 {
169 compatible = "fsl,mpc8572-l2-cache-controller";
170 reg = <0x20000 0x1000>;
171 cache-line-size = <32>; // 32 bytes
172 cache-size = <0x100000>; // L2,1M
173 interrupts = <16 2 0 0>;
174 };
175
176/include/ "pq3-dma-0.dtsi"
177/include/ "pq3-etsec1-0.dtsi"
178/include/ "pq3-etsec1-timer-0.dtsi"
179
180 ptp_clock@24e00 {
181 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
182 };
183
184/include/ "pq3-etsec1-1.dtsi"
185/include/ "pq3-etsec1-2.dtsi"
186/include/ "pq3-etsec1-3.dtsi"
187/include/ "pq3-sec3.0-0.dtsi"
188/include/ "pq3-mpic.dtsi"
189/include/ "pq3-mpic-timer-B.dtsi"
190
191 global-utilities@e0000 {
192 compatible = "fsl,mpc8572-guts";
193 reg = <0xe0000 0x1000>;
194 fsl,has-rstcr;
195 };
196};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
new file mode 100644
index 000000000000..ca188326c2ca
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-pre.dtsi
@@ -0,0 +1,70 @@
1/*
2 * MPC8572 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,MPC8572";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
49 pci0 = &pci0;
50 pci1 = &pci1;
51 pci2 = &pci2;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 PowerPC,8572@0 {
59 device_type = "cpu";
60 reg = <0x0>;
61 next-level-cache = <&L2>;
62 };
63
64 PowerPC,8572@1 {
65 device_type = "cpu";
66 reg = <0x1>;
67 next-level-cache = <&L2>;
68 };
69 };
70};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
new file mode 100644
index 000000000000..bd9e163c764b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -0,0 +1,198 @@
1/*
2 * P1010/P1014 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <16 2 0 0 19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1010-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1010-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1010-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127/include/ "pq3-espi-0.dtsi"
128 spi0: spi@7000 {
129 fsl,espi-num-chipselects = <1>;
130 };
131
132/include/ "pq3-gpio-0.dtsi"
133/include/ "pq3-sata2-0.dtsi"
134/include/ "pq3-sata2-1.dtsi"
135
136 can0: can@1c000 {
137 compatible = "fsl,p1010-flexcan";
138 reg = <0x1c000 0x1000>;
139 interrupts = <48 0x2 0 0>;
140 };
141
142 can1: can@1d000 {
143 compatible = "fsl,p1010-flexcan";
144 reg = <0x1d000 0x1000>;
145 interrupts = <61 0x2 0 0>;
146 };
147
148 L2: l2-cache-controller@20000 {
149 compatible = "fsl,p1010-l2-cache-controller",
150 "fsl,p1014-l2-cache-controller";
151 reg = <0x20000 0x1000>;
152 cache-line-size = <32>; // 32 bytes
153 cache-size = <0x40000>; // L2,256K
154 interrupts = <16 2 0 0>;
155 };
156
157/include/ "pq3-dma-0.dtsi"
158/include/ "pq3-usb2-dr-0.dtsi"
159/include/ "pq3-esdhc-0.dtsi"
160 sdhc@2e000 {
161 fsl,sdhci-auto-cmd12;
162 };
163
164/include/ "pq3-sec4.4-0.dtsi"
165/include/ "pq3-mpic.dtsi"
166/include/ "pq3-mpic-timer-B.dtsi"
167
168/include/ "pq3-etsec2-0.dtsi"
169 enet0: ethernet@b0000 {
170 queue-group@b0000 {
171 fsl,rx-bit-map = <0xff>;
172 fsl,tx-bit-map = <0xff>;
173 };
174 };
175
176/include/ "pq3-etsec2-1.dtsi"
177 enet1: ethernet@b1000 {
178 queue-group@b1000 {
179 fsl,rx-bit-map = <0xff>;
180 fsl,tx-bit-map = <0xff>;
181 };
182 };
183
184/include/ "pq3-etsec2-2.dtsi"
185 enet2: ethernet@b2000 {
186 queue-group@b2000 {
187 fsl,rx-bit-map = <0xff>;
188 fsl,tx-bit-map = <0xff>;
189 };
190
191 };
192
193 global-utilities@e0000 {
194 compatible = "fsl,p1010-guts";
195 reg = <0xe0000 0x1000>;
196 fsl,has-rstcr;
197 };
198};
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
new file mode 100644
index 000000000000..7354a8f90ea5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1010si-pre.dtsi
@@ -0,0 +1,64 @@
1/*
2 * P1010/P1014 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1010";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 can0 = &can0;
51 can1 = &can1;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 PowerPC,P1010@0 {
59 device_type = "cpu";
60 reg = <0x0>;
61 next-level-cache = <&L2>;
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
new file mode 100644
index 000000000000..fc924c5ffebe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -0,0 +1,174 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1020-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1020-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1020-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1020-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145/include/ "pq3-usb2-dr-1.dtsi"
146
147/include/ "pq3-esdhc-0.dtsi"
148/include/ "pq3-sec3.3-0.dtsi"
149
150/include/ "pq3-mpic.dtsi"
151/include/ "pq3-mpic-timer-B.dtsi"
152
153/include/ "pq3-etsec2-0.dtsi"
154 enet0: enet0_grp2: ethernet@b0000 {
155 };
156
157/include/ "pq3-etsec2-1.dtsi"
158 enet1: enet1_grp2: ethernet@b1000 {
159 };
160
161/include/ "pq3-etsec2-2.dtsi"
162 enet2: enet2_grp2: ethernet@b2000 {
163 };
164
165 global-utilities@e0000 {
166 compatible = "fsl,p1020-guts";
167 reg = <0xe0000 0x1000>;
168 fsl,has-rstcr;
169 };
170};
171
172/include/ "pq3-etsec2-grp2-0.dtsi"
173/include/ "pq3-etsec2-grp2-1.dtsi"
174/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
new file mode 100644
index 000000000000..6f0376e554eb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1020si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1020/P1011 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1020@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1020@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
new file mode 100644
index 000000000000..38ba54d1e32e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -0,0 +1,225 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1021-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1021-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1021-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1021-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146/include/ "pq3-esdhc-0.dtsi"
147/include/ "pq3-sec3.3-0.dtsi"
148
149/include/ "pq3-mpic.dtsi"
150/include/ "pq3-mpic-timer-B.dtsi"
151
152/include/ "pq3-etsec2-0.dtsi"
153 enet0: enet0_grp2: ethernet@b0000 {
154 };
155
156/include/ "pq3-etsec2-1.dtsi"
157 enet1: enet1_grp2: ethernet@b1000 {
158 };
159
160/include/ "pq3-etsec2-2.dtsi"
161 enet2: enet2_grp2: ethernet@b2000 {
162 };
163
164 global-utilities@e0000 {
165 compatible = "fsl,p1021-guts";
166 reg = <0xe0000 0x1000>;
167 fsl,has-rstcr;
168 };
169};
170
171&qe {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 device_type = "qe";
175 compatible = "fsl,qe";
176 fsl,qe-num-riscs = <1>;
177 fsl,qe-num-snums = <28>;
178
179 qeic: interrupt-controller@80 {
180 interrupt-controller;
181 compatible = "fsl,qe-ic";
182 #address-cells = <0>;
183 #interrupt-cells = <1>;
184 reg = <0x80 0x80>;
185 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
186 };
187
188 ucc@2000 {
189 cell-index = <1>;
190 reg = <0x2000 0x200>;
191 interrupts = <32>;
192 interrupt-parent = <&qeic>;
193 };
194
195 mdio@2120 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0x2120 0x18>;
199 compatible = "fsl,ucc-mdio";
200 };
201
202 ucc@2400 {
203 cell-index = <5>;
204 reg = <0x2400 0x200>;
205 interrupts = <40>;
206 interrupt-parent = <&qeic>;
207 };
208
209 muram@10000 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,qe-muram", "fsl,cpm-muram";
213 ranges = <0x0 0x10000 0x6000>;
214
215 data-only@0 {
216 compatible = "fsl,qe-muram-data",
217 "fsl,cpm-muram-data";
218 reg = <0x0 0x6000>;
219 };
220 };
221};
222
223/include/ "pq3-etsec2-grp2-0.dtsi"
224/include/ "pq3-etsec2-grp2-1.dtsi"
225/include/ "pq3-etsec2-grp2-2.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
new file mode 100644
index 000000000000..4abd54bc3308
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1021si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1021/P1012 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1021";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1021@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1021@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
new file mode 100644
index 000000000000..16239b199d0a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -0,0 +1,235 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0x9000 */
43&pci0 {
44 compatible = "fsl,p1022-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <16 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0xa000 */
71&pci1 {
72 compatible = "fsl,p1022-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <16 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <16 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0xb000 */
100&pci2 {
101 compatible = "fsl,p1022-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <16 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <16 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p1022-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p1022-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <16 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p1022-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <16 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162 dma@c300 {
163 dma00: dma-channel@0 {
164 compatible = "fsl,ssi-dma-channel";
165 };
166 dma01: dma-channel@80 {
167 compatible = "fsl,ssi-dma-channel";
168 };
169 };
170
171/include/ "pq3-gpio-0.dtsi"
172
173 display@10000 {
174 compatible = "fsl,diu", "fsl,p1022-diu";
175 reg = <0x10000 1000>;
176 interrupts = <64 2 0 0>;
177 };
178
179 ssi@15000 {
180 compatible = "fsl,mpc8610-ssi";
181 cell-index = <0>;
182 reg = <0x15000 0x100>;
183 interrupts = <75 2 0 0>;
184 fsl,playback-dma = <&dma00>;
185 fsl,capture-dma = <&dma01>;
186 fsl,fifo-depth = <15>;
187 };
188
189/include/ "pq3-sata2-0.dtsi"
190/include/ "pq3-sata2-1.dtsi"
191
192 L2: l2-cache-controller@20000 {
193 compatible = "fsl,p1022-l2-cache-controller";
194 reg = <0x20000 0x1000>;
195 cache-line-size = <32>; // 32 bytes
196 cache-size = <0x40000>; // L2,256K
197 interrupts = <16 2 0 0>;
198 };
199
200/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-usb2-dr-0.dtsi"
202/include/ "pq3-usb2-dr-1.dtsi"
203
204/include/ "pq3-esdhc-0.dtsi"
205 sdhc@2e000 {
206 fsl,sdhci-auto-cmd12;
207 };
208
209/include/ "pq3-sec3.3-0.dtsi"
210/include/ "pq3-mpic.dtsi"
211/include/ "pq3-mpic-timer-B.dtsi"
212
213/include/ "pq3-etsec2-0.dtsi"
214 enet0: enet0_grp2: ethernet@b0000 {
215 };
216
217/include/ "pq3-etsec2-1.dtsi"
218 enet1: enet1_grp2: ethernet@b1000 {
219 };
220
221 global-utilities@e0000 {
222 compatible = "fsl,p1022-guts";
223 reg = <0xe0000 0x1000>;
224 fsl,has-rstcr;
225 };
226
227 power@e0070{
228 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
229 reg = <0xe0070 0x20>;
230 };
231
232};
233
234/include/ "pq3-etsec2-grp2-0.dtsi"
235/include/ "pq3-etsec2-grp2-1.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
new file mode 100644
index 000000000000..e930f4f7ca89
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1022si-pre.dtsi
@@ -0,0 +1,68 @@
1/*
2 * P1022/P1013 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1022";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 pci0 = &pci0;
48 pci1 = &pci1;
49 pci2 = &pci2;
50 };
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 PowerPC,P1022@0 {
57 device_type = "cpu";
58 reg = <0x0>;
59 next-level-cache = <&L2>;
60 };
61
62 PowerPC,P1022@1 {
63 device_type = "cpu";
64 reg = <0x1>;
65 next-level-cache = <&L2>;
66 };
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
new file mode 100644
index 000000000000..b06bb4cc1fe8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -0,0 +1,224 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 0 0>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 0 0>;
58 };
59};
60
61/* controller at 0x9000 */
62&pci1 {
63 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
64 device_type = "pci";
65 #size-cells = <2>;
66 #address-cells = <3>;
67 bus-range = <0 0xff>;
68 clock-frequency = <33333333>;
69 interrupts = <16 2 0 0>;
70 pcie@0 {
71 reg = <0 0 0 0 0>;
72 #interrupt-cells = <1>;
73 #size-cells = <2>;
74 #address-cells = <3>;
75 device_type = "pci";
76 interrupts = <16 2 0 0>;
77 };
78};
79
80/* controller at 0xb000 */
81&pci2 {
82 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
83 device_type = "pci";
84 #size-cells = <2>;
85 #address-cells = <3>;
86 bus-range = <0x0 0xff>;
87 clock-frequency = <33333333>;
88 interrupts = <16 2 0 0>;
89 pcie@0 {
90 reg = <0 0 0 0 0>;
91 #interrupt-cells = <1>;
92 #size-cells = <2>;
93 #address-cells = <3>;
94 device_type = "pci";
95 interrupts = <16 2 0 0>;
96 };
97};
98
99&soc {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 device_type = "soc";
103 compatible = "fsl,p1023-immr", "simple-bus";
104 bus-frequency = <0>; // Filled out by uboot.
105
106 ecm-law@0 {
107 compatible = "fsl,ecm-law";
108 reg = <0x0 0x1000>;
109 fsl,num-laws = <12>;
110 };
111
112 ecm@1000 {
113 compatible = "fsl,p1023-ecm", "fsl,ecm";
114 reg = <0x1000 0x1000>;
115 interrupts = <16 2 0 0>;
116 };
117
118 memory-controller@2000 {
119 compatible = "fsl,p1023-memory-controller";
120 reg = <0x2000 0x1000>;
121 interrupts = <16 2 0 0>;
122 };
123
124/include/ "pq3-i2c-0.dtsi"
125/include/ "pq3-i2c-1.dtsi"
126/include/ "pq3-duart-0.dtsi"
127
128/include/ "pq3-espi-0.dtsi"
129 spi@7000 {
130 fsl,espi-num-chipselects = <4>;
131 };
132
133/include/ "pq3-gpio-0.dtsi"
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,p1023-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x40000>; // L2,256K
140 interrupts = <16 2 0 0>;
141 };
142
143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi"
145
146 crypto: crypto@300000 {
147 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <0x30000 0x10000>;
151 ranges = <0 0x30000 0x10000>;
152 interrupts = <58 2 0 0>;
153
154 sec_jr0: jr@1000 {
155 compatible = "fsl,sec-v4.2-job-ring",
156 "fsl,sec-v4.0-job-ring";
157 reg = <0x1000 0x1000>;
158 interrupts = <45 2 0 0>;
159 };
160
161 sec_jr1: jr@2000 {
162 compatible = "fsl,sec-v4.2-job-ring",
163 "fsl,sec-v4.0-job-ring";
164 reg = <0x2000 0x1000>;
165 interrupts = <45 2 0 0>;
166 };
167
168 sec_jr2: jr@3000 {
169 compatible = "fsl,sec-v4.2-job-ring",
170 "fsl,sec-v4.0-job-ring";
171 reg = <0x3000 0x1000>;
172 interrupts = <57 2 0 0>;
173 };
174
175 sec_jr3: jr@4000 {
176 compatible = "fsl,sec-v4.2-job-ring",
177 "fsl,sec-v4.0-job-ring";
178 reg = <0x4000 0x1000>;
179 interrupts = <57 2 0 0>;
180 };
181
182 rtic@6000 {
183 compatible = "fsl,sec-v4.2-rtic",
184 "fsl,sec-v4.0-rtic";
185 #address-cells = <1>;
186 #size-cells = <1>;
187 reg = <0x6000 0x100>;
188 ranges = <0x0 0x6100 0xe00>;
189
190 rtic_a: rtic-a@0 {
191 compatible = "fsl,sec-v4.2-rtic-memory",
192 "fsl,sec-v4.0-rtic-memory";
193 reg = <0x00 0x20 0x100 0x80>;
194 };
195
196 rtic_b: rtic-b@20 {
197 compatible = "fsl,sec-v4.2-rtic-memory",
198 "fsl,sec-v4.0-rtic-memory";
199 reg = <0x20 0x20 0x200 0x80>;
200 };
201
202 rtic_c: rtic-c@40 {
203 compatible = "fsl,sec-v4.2-rtic-memory",
204 "fsl,sec-v4.0-rtic-memory";
205 reg = <0x40 0x20 0x300 0x80>;
206 };
207
208 rtic_d: rtic-d@60 {
209 compatible = "fsl,sec-v4.2-rtic-memory",
210 "fsl,sec-v4.0-rtic-memory";
211 reg = <0x60 0x20 0x500 0x80>;
212 };
213 };
214 };
215
216/include/ "pq3-mpic.dtsi"
217/include/ "pq3-mpic-timer-B.dtsi"
218
219 global-utilities@e0000 {
220 compatible = "fsl,p1023-guts";
221 reg = <0xe0000 0x1000>;
222 fsl,has-rstcr;
223 };
224};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
new file mode 100644
index 000000000000..ac45f6d93385
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p1023si-pre.dtsi
@@ -0,0 +1,76 @@
1/*
2 * P1023/P1017 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P1023";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 pci0 = &pci0;
46 pci1 = &pci1;
47 pci2 = &pci2;
48
49 crypto = &crypto;
50 sec_jr0 = &sec_jr0;
51 sec_jr1 = &sec_jr1;
52 sec_jr2 = &sec_jr2;
53 sec_jr3 = &sec_jr3;
54 rtic_a = &rtic_a;
55 rtic_b = &rtic_b;
56 rtic_c = &rtic_c;
57 rtic_d = &rtic_d;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 PowerPC,P1023@0 {
65 device_type = "cpu";
66 reg = <0x0>;
67 next-level-cache = <&L2>;
68 };
69
70 PowerPC,P1023@1 {
71 device_type = "cpu";
72 reg = <0x1>;
73 next-level-cache = <&L2>;
74 };
75 };
76};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
new file mode 100644
index 000000000000..c041050561a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -0,0 +1,194 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 interrupts = <19 2 0 0>;
40};
41
42/* controller at 0xa000 */
43&pci0 {
44 compatible = "fsl,mpc8548-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
50 interrupts = <26 2 0 0>;
51
52 pcie@0 {
53 reg = <0 0 0 0 0>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
57 device_type = "pci";
58 interrupts = <26 2 0 0>;
59 interrupt-map-mask = <0xf800 0 0 7>;
60 interrupt-map = <
61 /* IDSEL 0x0 */
62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
63 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
64 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
65 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
66 >;
67 };
68};
69
70/* controller at 0x9000 */
71&pci1 {
72 compatible = "fsl,mpc8548-pcie";
73 device_type = "pci";
74 #size-cells = <2>;
75 #address-cells = <3>;
76 bus-range = <0 255>;
77 clock-frequency = <33333333>;
78 interrupts = <25 2 0 0>;
79
80 pcie@0 {
81 reg = <0 0 0 0 0>;
82 #interrupt-cells = <1>;
83 #size-cells = <2>;
84 #address-cells = <3>;
85 device_type = "pci";
86 interrupts = <25 2 0 0>;
87 interrupt-map-mask = <0xf800 0 0 7>;
88
89 interrupt-map = <
90 /* IDSEL 0x0 */
91 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
92 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
93 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
94 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
95 >;
96 };
97};
98
99/* controller at 0x8000 */
100&pci2 {
101 compatible = "fsl,mpc8548-pcie";
102 device_type = "pci";
103 #size-cells = <2>;
104 #address-cells = <3>;
105 bus-range = <0 255>;
106 clock-frequency = <33333333>;
107 interrupts = <24 2 0 0>;
108
109 pcie@0 {
110 reg = <0 0 0 0 0>;
111 #interrupt-cells = <1>;
112 #size-cells = <2>;
113 #address-cells = <3>;
114 device_type = "pci";
115 interrupts = <24 2 0 0>;
116 interrupt-map-mask = <0xf800 0 0 7>;
117
118 interrupt-map = <
119 /* IDSEL 0x0 */
120 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
121 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
122 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
123 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
124 >;
125 };
126};
127
128&soc {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 device_type = "soc";
132 compatible = "fsl,p2020-immr", "simple-bus";
133 bus-frequency = <0>; // Filled out by uboot.
134
135 ecm-law@0 {
136 compatible = "fsl,ecm-law";
137 reg = <0x0 0x1000>;
138 fsl,num-laws = <12>;
139 };
140
141 ecm@1000 {
142 compatible = "fsl,p2020-ecm", "fsl,ecm";
143 reg = <0x1000 0x1000>;
144 interrupts = <17 2 0 0>;
145 };
146
147 memory-controller@2000 {
148 compatible = "fsl,p2020-memory-controller";
149 reg = <0x2000 0x1000>;
150 interrupts = <18 2 0 0>;
151 };
152
153/include/ "pq3-i2c-0.dtsi"
154/include/ "pq3-i2c-1.dtsi"
155/include/ "pq3-duart-0.dtsi"
156/include/ "pq3-espi-0.dtsi"
157 spi0: spi@7000 {
158 fsl,espi-num-chipselects = <4>;
159 };
160
161/include/ "pq3-dma-1.dtsi"
162/include/ "pq3-gpio-0.dtsi"
163
164 L2: l2-cache-controller@20000 {
165 compatible = "fsl,p2020-l2-cache-controller";
166 reg = <0x20000 0x1000>;
167 cache-line-size = <32>; // 32 bytes
168 cache-size = <0x80000>; // L2,512K
169 interrupts = <16 2 0 0>;
170 };
171
172/include/ "pq3-dma-0.dtsi"
173/include/ "pq3-usb2-dr-0.dtsi"
174/include/ "pq3-etsec1-0.dtsi"
175/include/ "pq3-etsec1-timer-0.dtsi"
176
177 ptp_clock@24e00 {
178 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
179 };
180
181
182/include/ "pq3-etsec1-1.dtsi"
183/include/ "pq3-etsec1-2.dtsi"
184/include/ "pq3-esdhc-0.dtsi"
185/include/ "pq3-sec3.1-0.dtsi"
186/include/ "pq3-mpic.dtsi"
187/include/ "pq3-mpic-timer-B.dtsi"
188
189 global-utilities@e0000 {
190 compatible = "fsl,p2020-guts";
191 reg = <0xe0000 0x1000>;
192 fsl,has-rstcr;
193 };
194};
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
new file mode 100644
index 000000000000..3213288641d1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2020si-pre.dtsi
@@ -0,0 +1,69 @@
1/*
2 * P2020/P2010 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P2020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 serial0 = &serial0;
44 serial1 = &serial1;
45 ethernet0 = &enet0;
46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51 };
52
53 cpus {
54 #address-cells = <1>;
55 #size-cells = <0>;
56
57 PowerPC,P2020@0 {
58 device_type = "cpu";
59 reg = <0x0>;
60 next-level-cache = <&L2>;
61 };
62
63 PowerPC,P2020@1 {
64 device_type = "cpu";
65 reg = <0x1>;
66 next-level-cache = <&L2>;
67 };
68 };
69};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
new file mode 100644
index 000000000000..234a399ddeb2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -0,0 +1,325 @@
1/*
2 * P2041/P2040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&rio {
124 compatible = "fsl,srio";
125 interrupts = <16 2 1 11>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 ranges;
129
130 port1 {
131 #address-cells = <2>;
132 #size-cells = <2>;
133 cell-index = <1>;
134 };
135
136 port2 {
137 #address-cells = <2>;
138 #size-cells = <2>;
139 cell-index = <2>;
140 };
141};
142
143&dcsr {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,dcsr", "simple-bus";
147
148 dcsr-epu@0 {
149 compatible = "fsl,dcsr-epu";
150 interrupts = <52 2 0 0
151 84 2 0 0
152 85 2 0 0>;
153 reg = <0x0 0x1000>;
154 };
155 dcsr-npc {
156 compatible = "fsl,dcsr-npc";
157 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 };
159 dcsr-nxc@2000 {
160 compatible = "fsl,dcsr-nxc";
161 reg = <0x2000 0x1000>;
162 };
163 dcsr-corenet {
164 compatible = "fsl,dcsr-corenet";
165 reg = <0x8000 0x1000 0xB0000 0x1000>;
166 };
167 dcsr-dpaa@9000 {
168 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
169 reg = <0x9000 0x1000>;
170 };
171 dcsr-ocn@11000 {
172 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
173 reg = <0x11000 0x1000>;
174 };
175 dcsr-ddr@12000 {
176 compatible = "fsl,dcsr-ddr";
177 dev-handle = <&ddr1>;
178 reg = <0x12000 0x1000>;
179 };
180 dcsr-nal@18000 {
181 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
182 reg = <0x18000 0x1000>;
183 };
184 dcsr-rcpm@22000 {
185 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
186 reg = <0x22000 0x1000>;
187 };
188 dcsr-cpu-sb-proxy@40000 {
189 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
190 cpu-handle = <&cpu0>;
191 reg = <0x40000 0x1000>;
192 };
193 dcsr-cpu-sb-proxy@41000 {
194 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
195 cpu-handle = <&cpu1>;
196 reg = <0x41000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@42000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu2>;
201 reg = <0x42000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@43000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu3>;
206 reg = <0x43000 0x1000>;
207 };
208};
209
210&soc {
211 #address-cells = <1>;
212 #size-cells = <1>;
213 device_type = "soc";
214 compatible = "simple-bus";
215
216 soc-sram-error {
217 compatible = "fsl,soc-sram-error";
218 interrupts = <16 2 1 29>;
219 };
220
221 corenet-law@0 {
222 compatible = "fsl,corenet-law";
223 reg = <0x0 0x1000>;
224 fsl,num-laws = <32>;
225 };
226
227 ddr1: memory-controller@8000 {
228 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
229 reg = <0x8000 0x1000>;
230 interrupts = <16 2 1 23>;
231 };
232
233 cpc: l3-cache-controller@10000 {
234 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
235 reg = <0x10000 0x1000>;
236 interrupts = <16 2 1 27>;
237 };
238
239 corenet-cf@18000 {
240 compatible = "fsl,corenet-cf";
241 reg = <0x18000 0x1000>;
242 interrupts = <16 2 1 31>;
243 fsl,ccf-num-csdids = <32>;
244 fsl,ccf-num-snoopids = <32>;
245 };
246
247 iommu@20000 {
248 compatible = "fsl,pamu-v1.0", "fsl,pamu";
249 reg = <0x20000 0x4000>;
250 interrupts = <
251 24 2 0 0
252 16 2 1 30>;
253 };
254
255/include/ "qoriq-mpic.dtsi"
256
257 guts: global-utilities@e0000 {
258 compatible = "fsl,qoriq-device-config-1.0";
259 reg = <0xe0000 0xe00>;
260 fsl,has-rstcr;
261 #sleep-cells = <1>;
262 fsl,liodn-bits = <12>;
263 };
264
265 pins: global-utilities@e0e00 {
266 compatible = "fsl,qoriq-pin-control-1.0";
267 reg = <0xe0e00 0x200>;
268 #sleep-cells = <2>;
269 };
270
271 clockgen: global-utilities@e1000 {
272 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
273 reg = <0xe1000 0x1000>;
274 clock-frequency = <0>;
275 };
276
277 rcpm: global-utilities@e2000 {
278 compatible = "fsl,qoriq-rcpm-1.0";
279 reg = <0xe2000 0x1000>;
280 #sleep-cells = <1>;
281 };
282
283 sfp: sfp@e8000 {
284 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
285 reg = <0xe8000 0x1000>;
286 };
287
288 serdes: serdes@ea000 {
289 compatible = "fsl,p2041-serdes";
290 reg = <0xea000 0x1000>;
291 };
292
293/include/ "qoriq-dma-0.dtsi"
294/include/ "qoriq-dma-1.dtsi"
295/include/ "qoriq-espi-0.dtsi"
296 spi@110000 {
297 fsl,espi-num-chipselects = <4>;
298 };
299
300/include/ "qoriq-esdhc-0.dtsi"
301 sdhc@114000 {
302 sdhci,auto-cmd12;
303 };
304
305/include/ "qoriq-i2c-0.dtsi"
306/include/ "qoriq-i2c-1.dtsi"
307/include/ "qoriq-duart-0.dtsi"
308/include/ "qoriq-duart-1.dtsi"
309/include/ "qoriq-gpio-0.dtsi"
310/include/ "qoriq-usb2-mph-0.dtsi"
311 usb0: usb@210000 {
312 phy_type = "utmi";
313 port0;
314 };
315
316/include/ "qoriq-usb2-dr-0.dtsi"
317 usb1: usb@211000 {
318 dr_mode = "host";
319 phy_type = "utmi";
320 };
321
322/include/ "qoriq-sata2-0.dtsi"
323/include/ "qoriq-sata2-1.dtsi"
324/include/ "qoriq-sec4.2-0.dtsi"
325};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
new file mode 100644
index 000000000000..2d0a40d6b10f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -0,0 +1,111 @@
1/*
2 * P2041 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P2041";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 };
111};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
new file mode 100644
index 000000000000..d41d08de7f7e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -0,0 +1,352 @@
1/*
2 * P3041 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x203000 */
124&pci3 {
125 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <16 2 1 12>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&rio {
151 compatible = "fsl,srio";
152 interrupts = <16 2 1 11>;
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 port1 {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 cell-index = <1>;
161 };
162
163 port2 {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 cell-index = <2>;
167 };
168};
169
170&dcsr {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "fsl,dcsr", "simple-bus";
174
175 dcsr-epu@0 {
176 compatible = "fsl,dcsr-epu";
177 interrupts = <52 2 0 0
178 84 2 0 0
179 85 2 0 0>;
180 reg = <0x0 0x1000>;
181 };
182 dcsr-npc {
183 compatible = "fsl,dcsr-npc";
184 reg = <0x1000 0x1000 0x1000000 0x8000>;
185 };
186 dcsr-nxc@2000 {
187 compatible = "fsl,dcsr-nxc";
188 reg = <0x2000 0x1000>;
189 };
190 dcsr-corenet {
191 compatible = "fsl,dcsr-corenet";
192 reg = <0x8000 0x1000 0xB0000 0x1000>;
193 };
194 dcsr-dpaa@9000 {
195 compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
196 reg = <0x9000 0x1000>;
197 };
198 dcsr-ocn@11000 {
199 compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
200 reg = <0x11000 0x1000>;
201 };
202 dcsr-ddr@12000 {
203 compatible = "fsl,dcsr-ddr";
204 dev-handle = <&ddr1>;
205 reg = <0x12000 0x1000>;
206 };
207 dcsr-nal@18000 {
208 compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
209 reg = <0x18000 0x1000>;
210 };
211 dcsr-rcpm@22000 {
212 compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
213 reg = <0x22000 0x1000>;
214 };
215 dcsr-cpu-sb-proxy@40000 {
216 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
217 cpu-handle = <&cpu0>;
218 reg = <0x40000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@41000 {
221 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu1>;
223 reg = <0x41000 0x1000>;
224 };
225 dcsr-cpu-sb-proxy@42000 {
226 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu2>;
228 reg = <0x42000 0x1000>;
229 };
230 dcsr-cpu-sb-proxy@43000 {
231 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
232 cpu-handle = <&cpu3>;
233 reg = <0x43000 0x1000>;
234 };
235};
236
237&soc {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 device_type = "soc";
241 compatible = "simple-bus";
242
243 soc-sram-error {
244 compatible = "fsl,soc-sram-error";
245 interrupts = <16 2 1 29>;
246 };
247
248 corenet-law@0 {
249 compatible = "fsl,corenet-law";
250 reg = <0x0 0x1000>;
251 fsl,num-laws = <32>;
252 };
253
254 ddr1: memory-controller@8000 {
255 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
256 reg = <0x8000 0x1000>;
257 interrupts = <16 2 1 23>;
258 };
259
260 cpc: l3-cache-controller@10000 {
261 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
262 reg = <0x10000 0x1000>;
263 interrupts = <16 2 1 27>;
264 };
265
266 corenet-cf@18000 {
267 compatible = "fsl,corenet-cf";
268 reg = <0x18000 0x1000>;
269 interrupts = <16 2 1 31>;
270 fsl,ccf-num-csdids = <32>;
271 fsl,ccf-num-snoopids = <32>;
272 };
273
274 iommu@20000 {
275 compatible = "fsl,pamu-v1.0", "fsl,pamu";
276 reg = <0x20000 0x4000>;
277 interrupts = <
278 24 2 0 0
279 16 2 1 30>;
280 };
281
282/include/ "qoriq-mpic.dtsi"
283
284 guts: global-utilities@e0000 {
285 compatible = "fsl,qoriq-device-config-1.0";
286 reg = <0xe0000 0xe00>;
287 fsl,has-rstcr;
288 #sleep-cells = <1>;
289 fsl,liodn-bits = <12>;
290 };
291
292 pins: global-utilities@e0e00 {
293 compatible = "fsl,qoriq-pin-control-1.0";
294 reg = <0xe0e00 0x200>;
295 #sleep-cells = <2>;
296 };
297
298 clockgen: global-utilities@e1000 {
299 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
300 reg = <0xe1000 0x1000>;
301 clock-frequency = <0>;
302 };
303
304 rcpm: global-utilities@e2000 {
305 compatible = "fsl,qoriq-rcpm-1.0";
306 reg = <0xe2000 0x1000>;
307 #sleep-cells = <1>;
308 };
309
310 sfp: sfp@e8000 {
311 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
312 reg = <0xe8000 0x1000>;
313 };
314
315 serdes: serdes@ea000 {
316 compatible = "fsl,p3041-serdes";
317 reg = <0xea000 0x1000>;
318 };
319
320/include/ "qoriq-dma-0.dtsi"
321/include/ "qoriq-dma-1.dtsi"
322/include/ "qoriq-espi-0.dtsi"
323 spi@110000 {
324 fsl,espi-num-chipselects = <4>;
325 };
326
327/include/ "qoriq-esdhc-0.dtsi"
328 sdhc@114000 {
329 sdhci,auto-cmd12;
330 };
331
332/include/ "qoriq-i2c-0.dtsi"
333/include/ "qoriq-i2c-1.dtsi"
334/include/ "qoriq-duart-0.dtsi"
335/include/ "qoriq-duart-1.dtsi"
336/include/ "qoriq-gpio-0.dtsi"
337/include/ "qoriq-usb2-mph-0.dtsi"
338 usb0: usb@210000 {
339 phy_type = "utmi";
340 port0;
341 };
342
343/include/ "qoriq-usb2-dr-0.dtsi"
344 usb1: usb@211000 {
345 dr_mode = "host";
346 phy_type = "utmi";
347 };
348
349/include/ "qoriq-sata2-0.dtsi"
350/include/ "qoriq-sata2-1.dtsi"
351/include/ "qoriq-sec4.2-0.dtsi"
352};
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
new file mode 100644
index 000000000000..136def3536b6
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -0,0 +1,112 @@
1/*
2 * P3041 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P3041";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e500mc@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e500mc@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 cpu2: PowerPC,e500mc@2 {
96 device_type = "cpu";
97 reg = <2>;
98 next-level-cache = <&L2_2>;
99 L2_2: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 cpu3: PowerPC,e500mc@3 {
104 device_type = "cpu";
105 reg = <3>;
106 next-level-cache = <&L2_3>;
107 L2_3: l2-cache {
108 next-level-cache = <&cpc>;
109 };
110 };
111 };
112};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
new file mode 100644
index 000000000000..a63edd195ae5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -0,0 +1,296 @@
1/*
2 * P3060 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96&rio {
97 compatible = "fsl,srio";
98 interrupts = <16 2 1 11>;
99 #address-cells = <2>;
100 #size-cells = <2>;
101 fsl,srio-rmu-handle = <&rmu>;
102 ranges;
103
104 port1 {
105 #address-cells = <2>;
106 #size-cells = <2>;
107 cell-index = <1>;
108 };
109
110 port2 {
111 #address-cells = <2>;
112 #size-cells = <2>;
113 cell-index = <2>;
114 };
115};
116
117&dcsr {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,dcsr", "simple-bus";
121
122 dcsr-epu@0 {
123 compatible = "fsl,dcsr-epu";
124 interrupts = <52 2 0 0
125 84 2 0 0
126 85 2 0 0>;
127 reg = <0x0 0x1000>;
128 };
129 dcsr-npc {
130 compatible = "fsl,dcsr-npc";
131 reg = <0x1000 0x1000 0x1000000 0x8000>;
132 };
133 dcsr-nxc@2000 {
134 compatible = "fsl,dcsr-nxc";
135 reg = <0x2000 0x1000>;
136 };
137 dcsr-corenet {
138 compatible = "fsl,dcsr-corenet";
139 reg = <0x8000 0x1000 0xB0000 0x1000>;
140 };
141 dcsr-dpaa@9000 {
142 compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
143 reg = <0x9000 0x1000>;
144 };
145 dcsr-ocn@11000 {
146 compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
147 reg = <0x11000 0x1000>;
148 };
149 dcsr-ddr@12000 {
150 compatible = "fsl,dcsr-ddr";
151 dev-handle = <&ddr1>;
152 reg = <0x12000 0x1000>;
153 };
154 dcsr-nal@18000 {
155 compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
156 reg = <0x18000 0x1000>;
157 };
158 dcsr-rcpm@22000 {
159 compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
160 reg = <0x22000 0x1000>;
161 };
162 dcsr-cpu-sb-proxy@40000 {
163 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
164 cpu-handle = <&cpu0>;
165 reg = <0x40000 0x1000>;
166 };
167 dcsr-cpu-sb-proxy@41000 {
168 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
169 cpu-handle = <&cpu1>;
170 reg = <0x41000 0x1000>;
171 };
172 dcsr-cpu-sb-proxy@44000 {
173 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
174 cpu-handle = <&cpu4>;
175 reg = <0x44000 0x1000>;
176 };
177 dcsr-cpu-sb-proxy@45000 {
178 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
179 cpu-handle = <&cpu5>;
180 reg = <0x45000 0x1000>;
181 };
182 dcsr-cpu-sb-proxy@46000 {
183 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
184 cpu-handle = <&cpu6>;
185 reg = <0x46000 0x1000>;
186 };
187 dcsr-cpu-sb-proxy@47000 {
188 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
189 cpu-handle = <&cpu7>;
190 reg = <0x47000 0x1000>;
191 };
192
193};
194
195&soc {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 device_type = "soc";
199 compatible = "simple-bus";
200
201 soc-sram-error {
202 compatible = "fsl,soc-sram-error";
203 interrupts = <16 2 1 29>;
204 };
205
206 corenet-law@0 {
207 compatible = "fsl,corenet-law";
208 reg = <0x0 0x1000>;
209 fsl,num-laws = <32>;
210 };
211
212 ddr1: memory-controller@8000 {
213 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
214 reg = <0x8000 0x1000>;
215 interrupts = <16 2 1 23>;
216 };
217
218 cpc: l3-cache-controller@10000 {
219 compatible = "fsl,p3060-l3-cache-controller", "cache";
220 reg = <0x10000 0x1000
221 0x11000 0x1000>;
222 interrupts = <16 2 1 27
223 16 2 1 26>;
224 };
225
226 corenet-cf@18000 {
227 compatible = "fsl,corenet-cf";
228 reg = <0x18000 0x1000>;
229 interrupts = <16 2 1 31>;
230 fsl,ccf-num-csdids = <32>;
231 fsl,ccf-num-snoopids = <32>;
232 };
233
234 iommu@20000 {
235 compatible = "fsl,pamu-v1.0", "fsl,pamu";
236 reg = <0x20000 0x5000>;
237 interrupts = <
238 24 2 0 0
239 16 2 1 30>;
240 };
241
242/include/ "qoriq-rmu-0.dtsi"
243/include/ "qoriq-mpic.dtsi"
244
245 guts: global-utilities@e0000 {
246 compatible = "fsl,qoriq-device-config-1.0";
247 reg = <0xe0000 0xe00>;
248 fsl,has-rstcr;
249 #sleep-cells = <1>;
250 fsl,liodn-bits = <12>;
251 };
252
253 pins: global-utilities@e0e00 {
254 compatible = "fsl,qoriq-pin-control-1.0";
255 reg = <0xe0e00 0x200>;
256 #sleep-cells = <2>;
257 };
258
259 clockgen: global-utilities@e1000 {
260 compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
261 reg = <0xe1000 0x1000>;
262 clock-frequency = <0>;
263 };
264
265 rcpm: global-utilities@e2000 {
266 compatible = "fsl,qoriq-rcpm-1.0";
267 reg = <0xe2000 0x1000>;
268 #sleep-cells = <1>;
269 };
270
271 sfp: sfp@e8000 {
272 compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
273 reg = <0xe8000 0x1000>;
274 };
275
276 serdes: serdes@ea000 {
277 compatible = "fsl,p3060-serdes";
278 reg = <0xea000 0x1000>;
279 };
280
281/include/ "qoriq-dma-0.dtsi"
282/include/ "qoriq-dma-1.dtsi"
283/include/ "qoriq-espi-0.dtsi"
284 spi@110000 {
285 fsl,espi-num-chipselects = <4>;
286 };
287
288/include/ "qoriq-i2c-0.dtsi"
289/include/ "qoriq-i2c-1.dtsi"
290/include/ "qoriq-duart-0.dtsi"
291/include/ "qoriq-duart-1.dtsi"
292/include/ "qoriq-gpio-0.dtsi"
293/include/ "qoriq-usb2-mph-0.dtsi"
294/include/ "qoriq-usb2-dr-0.dtsi"
295/include/ "qoriq-sec4.1-0.dtsi"
296};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
new file mode 100644
index 000000000000..00c8e70e7b90
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
@@ -0,0 +1,125 @@
1/*
2 * P3060 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P3060";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 usb0 = &usb0;
53 usb1 = &usb1;
54 dma0 = &dma0;
55 dma1 = &dma1;
56 msi0 = &msi0;
57 msi1 = &msi1;
58 msi2 = &msi2;
59
60 crypto = &crypto;
61 sec_jr0 = &sec_jr0;
62 sec_jr1 = &sec_jr1;
63 sec_jr2 = &sec_jr2;
64 sec_jr3 = &sec_jr3;
65 rtic_a = &rtic_a;
66 rtic_b = &rtic_b;
67 rtic_c = &rtic_c;
68 rtic_d = &rtic_d;
69 sec_mon = &sec_mon;
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 cpu0: PowerPC,e500mc@0 {
77 device_type = "cpu";
78 reg = <0>;
79 next-level-cache = <&L2_0>;
80 L2_0: l2-cache {
81 next-level-cache = <&cpc>;
82 };
83 };
84 cpu1: PowerPC,e500mc@1 {
85 device_type = "cpu";
86 reg = <1>;
87 next-level-cache = <&L2_1>;
88 L2_1: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu4: PowerPC,e500mc@4 {
93 device_type = "cpu";
94 reg = <4>;
95 next-level-cache = <&L2_4>;
96 L2_4: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 cpu5: PowerPC,e500mc@5 {
101 device_type = "cpu";
102 reg = <5>;
103 next-level-cache = <&L2_5>;
104 L2_5: l2-cache {
105 next-level-cache = <&cpc>;
106 };
107 };
108 cpu6: PowerPC,e500mc@6 {
109 device_type = "cpu";
110 reg = <6>;
111 next-level-cache = <&L2_6>;
112 L2_6: l2-cache {
113 next-level-cache = <&cpc>;
114 };
115 };
116 cpu7: PowerPC,e500mc@7 {
117 device_type = "cpu";
118 reg = <7>;
119 next-level-cache = <&L2_7>;
120 L2_7: l2-cache {
121 next-level-cache = <&cpc>;
122 };
123 };
124 };
125};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
new file mode 100644
index 000000000000..8d35d2c1f694
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -0,0 +1,350 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p4080-pcie";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p4080-pcie";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p4080-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123&rio {
124 compatible = "fsl,srio";
125 interrupts = <16 2 1 11>;
126 #address-cells = <2>;
127 #size-cells = <2>;
128 fsl,srio-rmu-handle = <&rmu>;
129 ranges;
130
131 port1 {
132 #address-cells = <2>;
133 #size-cells = <2>;
134 cell-index = <1>;
135 };
136
137 port2 {
138 #address-cells = <2>;
139 #size-cells = <2>;
140 cell-index = <2>;
141 };
142};
143
144&dcsr {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "fsl,dcsr", "simple-bus";
148
149 dcsr-epu@0 {
150 compatible = "fsl,dcsr-epu";
151 interrupts = <52 2 0 0
152 84 2 0 0
153 85 2 0 0>;
154 reg = <0x0 0x1000>;
155 };
156 dcsr-npc {
157 compatible = "fsl,dcsr-npc";
158 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 };
160 dcsr-nxc@2000 {
161 compatible = "fsl,dcsr-nxc";
162 reg = <0x2000 0x1000>;
163 };
164 dcsr-corenet {
165 compatible = "fsl,dcsr-corenet";
166 reg = <0x8000 0x1000 0xB0000 0x1000>;
167 };
168 dcsr-dpaa@9000 {
169 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
170 reg = <0x9000 0x1000>;
171 };
172 dcsr-ocn@11000 {
173 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
174 reg = <0x11000 0x1000>;
175 };
176 dcsr-ddr@12000 {
177 compatible = "fsl,dcsr-ddr";
178 dev-handle = <&ddr1>;
179 reg = <0x12000 0x1000>;
180 };
181 dcsr-ddr@13000 {
182 compatible = "fsl,dcsr-ddr";
183 dev-handle = <&ddr2>;
184 reg = <0x13000 0x1000>;
185 };
186 dcsr-nal@18000 {
187 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
188 reg = <0x18000 0x1000>;
189 };
190 dcsr-rcpm@22000 {
191 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
192 reg = <0x22000 0x1000>;
193 };
194 dcsr-cpu-sb-proxy@40000 {
195 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
196 cpu-handle = <&cpu0>;
197 reg = <0x40000 0x1000>;
198 };
199 dcsr-cpu-sb-proxy@41000 {
200 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
201 cpu-handle = <&cpu1>;
202 reg = <0x41000 0x1000>;
203 };
204 dcsr-cpu-sb-proxy@42000 {
205 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
206 cpu-handle = <&cpu2>;
207 reg = <0x42000 0x1000>;
208 };
209 dcsr-cpu-sb-proxy@43000 {
210 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
211 cpu-handle = <&cpu3>;
212 reg = <0x43000 0x1000>;
213 };
214 dcsr-cpu-sb-proxy@44000 {
215 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
216 cpu-handle = <&cpu4>;
217 reg = <0x44000 0x1000>;
218 };
219 dcsr-cpu-sb-proxy@45000 {
220 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
221 cpu-handle = <&cpu5>;
222 reg = <0x45000 0x1000>;
223 };
224 dcsr-cpu-sb-proxy@46000 {
225 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
226 cpu-handle = <&cpu6>;
227 reg = <0x46000 0x1000>;
228 };
229 dcsr-cpu-sb-proxy@47000 {
230 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
231 cpu-handle = <&cpu7>;
232 reg = <0x47000 0x1000>;
233 };
234
235};
236
237&soc {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 device_type = "soc";
241 compatible = "simple-bus";
242
243 soc-sram-error {
244 compatible = "fsl,soc-sram-error";
245 interrupts = <16 2 1 29>;
246 };
247
248 corenet-law@0 {
249 compatible = "fsl,corenet-law";
250 reg = <0x0 0x1000>;
251 fsl,num-laws = <32>;
252 };
253
254 ddr1: memory-controller@8000 {
255 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
256 reg = <0x8000 0x1000>;
257 interrupts = <16 2 1 23>;
258 };
259
260 ddr2: memory-controller@9000 {
261 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
262 reg = <0x9000 0x1000>;
263 interrupts = <16 2 1 22>;
264 };
265
266 cpc: l3-cache-controller@10000 {
267 compatible = "fsl,p4080-l3-cache-controller", "cache";
268 reg = <0x10000 0x1000
269 0x11000 0x1000>;
270 interrupts = <16 2 1 27
271 16 2 1 26>;
272 };
273
274 corenet-cf@18000 {
275 compatible = "fsl,corenet-cf";
276 reg = <0x18000 0x1000>;
277 interrupts = <16 2 1 31>;
278 fsl,ccf-num-csdids = <32>;
279 fsl,ccf-num-snoopids = <32>;
280 };
281
282 iommu@20000 {
283 compatible = "fsl,pamu-v1.0", "fsl,pamu";
284 reg = <0x20000 0x5000>;
285 interrupts = <
286 24 2 0 0
287 16 2 1 30>;
288 };
289
290/include/ "qoriq-rmu-0.dtsi"
291/include/ "qoriq-mpic.dtsi"
292
293 guts: global-utilities@e0000 {
294 compatible = "fsl,qoriq-device-config-1.0";
295 reg = <0xe0000 0xe00>;
296 fsl,has-rstcr;
297 #sleep-cells = <1>;
298 fsl,liodn-bits = <12>;
299 };
300
301 pins: global-utilities@e0e00 {
302 compatible = "fsl,qoriq-pin-control-1.0";
303 reg = <0xe0e00 0x200>;
304 #sleep-cells = <2>;
305 };
306
307 clockgen: global-utilities@e1000 {
308 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
309 reg = <0xe1000 0x1000>;
310 clock-frequency = <0>;
311 };
312
313 rcpm: global-utilities@e2000 {
314 compatible = "fsl,qoriq-rcpm-1.0";
315 reg = <0xe2000 0x1000>;
316 #sleep-cells = <1>;
317 };
318
319 sfp: sfp@e8000 {
320 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
321 reg = <0xe8000 0x1000>;
322 };
323
324 serdes: serdes@ea000 {
325 compatible = "fsl,p4080-serdes";
326 reg = <0xea000 0x1000>;
327 };
328
329/include/ "qoriq-dma-0.dtsi"
330/include/ "qoriq-dma-1.dtsi"
331/include/ "qoriq-espi-0.dtsi"
332 spi@110000 {
333 fsl,espi-num-chipselects = <4>;
334 };
335
336/include/ "qoriq-esdhc-0.dtsi"
337 sdhc@114000 {
338 voltage-ranges = <3300 3300>;
339 sdhci,auto-cmd12;
340 };
341
342/include/ "qoriq-i2c-0.dtsi"
343/include/ "qoriq-i2c-1.dtsi"
344/include/ "qoriq-duart-0.dtsi"
345/include/ "qoriq-duart-1.dtsi"
346/include/ "qoriq-gpio-0.dtsi"
347/include/ "qoriq-usb2-mph-0.dtsi"
348/include/ "qoriq-usb2-dr-0.dtsi"
349/include/ "qoriq-sec4.0-0.dtsi"
350};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
new file mode 100644
index 000000000000..b9556ee3a639
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -0,0 +1,143 @@
1/*
2 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P4080";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 sdhc = &sdhc;
58 msi0 = &msi0;
59 msi1 = &msi1;
60 msi2 = &msi2;
61
62 crypto = &crypto;
63 sec_jr0 = &sec_jr0;
64 sec_jr1 = &sec_jr1;
65 sec_jr2 = &sec_jr2;
66 sec_jr3 = &sec_jr3;
67 rtic_a = &rtic_a;
68 rtic_b = &rtic_b;
69 rtic_c = &rtic_c;
70 rtic_d = &rtic_d;
71 sec_mon = &sec_mon;
72 };
73
74 cpus {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 cpu0: PowerPC,e500mc@0 {
79 device_type = "cpu";
80 reg = <0>;
81 next-level-cache = <&L2_0>;
82 L2_0: l2-cache {
83 next-level-cache = <&cpc>;
84 };
85 };
86 cpu1: PowerPC,e500mc@1 {
87 device_type = "cpu";
88 reg = <1>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
91 next-level-cache = <&cpc>;
92 };
93 };
94 cpu2: PowerPC,e500mc@2 {
95 device_type = "cpu";
96 reg = <2>;
97 next-level-cache = <&L2_2>;
98 L2_2: l2-cache {
99 next-level-cache = <&cpc>;
100 };
101 };
102 cpu3: PowerPC,e500mc@3 {
103 device_type = "cpu";
104 reg = <3>;
105 next-level-cache = <&L2_3>;
106 L2_3: l2-cache {
107 next-level-cache = <&cpc>;
108 };
109 };
110 cpu4: PowerPC,e500mc@4 {
111 device_type = "cpu";
112 reg = <4>;
113 next-level-cache = <&L2_4>;
114 L2_4: l2-cache {
115 next-level-cache = <&cpc>;
116 };
117 };
118 cpu5: PowerPC,e500mc@5 {
119 device_type = "cpu";
120 reg = <5>;
121 next-level-cache = <&L2_5>;
122 L2_5: l2-cache {
123 next-level-cache = <&cpc>;
124 };
125 };
126 cpu6: PowerPC,e500mc@6 {
127 device_type = "cpu";
128 reg = <6>;
129 next-level-cache = <&L2_6>;
130 L2_6: l2-cache {
131 next-level-cache = <&cpc>;
132 };
133 };
134 cpu7: PowerPC,e500mc@7 {
135 device_type = "cpu";
136 reg = <7>;
137 next-level-cache = <&L2_7>;
138 L2_7: l2-cache {
139 next-level-cache = <&cpc>;
140 };
141 };
142 };
143};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
new file mode 100644
index 000000000000..914074b91a85
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -0,0 +1,355 @@
1/*
2 * P5020/5010 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
37 interrupts = <25 2 0 0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 clock-frequency = <33333333>;
50 interrupts = <16 2 1 15>;
51 pcie@0 {
52 reg = <0 0 0 0 0>;
53 #interrupt-cells = <1>;
54 #size-cells = <2>;
55 #address-cells = <3>;
56 device_type = "pci";
57 interrupts = <16 2 1 15>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69/* controller at 0x201000 */
70&pci1 {
71 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
72 device_type = "pci";
73 #size-cells = <2>;
74 #address-cells = <3>;
75 bus-range = <0 0xff>;
76 clock-frequency = <33333333>;
77 interrupts = <16 2 1 14>;
78 pcie@0 {
79 reg = <0 0 0 0 0>;
80 #interrupt-cells = <1>;
81 #size-cells = <2>;
82 #address-cells = <3>;
83 device_type = "pci";
84 interrupts = <16 2 1 14>;
85 interrupt-map-mask = <0xf800 0 0 7>;
86 interrupt-map = <
87 /* IDSEL 0x0 */
88 0000 0 0 1 &mpic 41 1 0 0
89 0000 0 0 2 &mpic 5 1 0 0
90 0000 0 0 3 &mpic 6 1 0 0
91 0000 0 0 4 &mpic 7 1 0 0
92 >;
93 };
94};
95
96/* controller at 0x202000 */
97&pci2 {
98 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <33333333>;
104 interrupts = <16 2 1 13>;
105 pcie@0 {
106 reg = <0 0 0 0 0>;
107 #interrupt-cells = <1>;
108 #size-cells = <2>;
109 #address-cells = <3>;
110 device_type = "pci";
111 interrupts = <16 2 1 13>;
112 interrupt-map-mask = <0xf800 0 0 7>;
113 interrupt-map = <
114 /* IDSEL 0x0 */
115 0000 0 0 1 &mpic 42 1 0 0
116 0000 0 0 2 &mpic 9 1 0 0
117 0000 0 0 3 &mpic 10 1 0 0
118 0000 0 0 4 &mpic 11 1 0 0
119 >;
120 };
121};
122
123/* controller at 0x203000 */
124&pci3 {
125 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
126 device_type = "pci";
127 #size-cells = <2>;
128 #address-cells = <3>;
129 bus-range = <0x0 0xff>;
130 clock-frequency = <33333333>;
131 interrupts = <16 2 1 12>;
132 pcie@0 {
133 reg = <0 0 0 0 0>;
134 #interrupt-cells = <1>;
135 #size-cells = <2>;
136 #address-cells = <3>;
137 device_type = "pci";
138 interrupts = <16 2 1 12>;
139 interrupt-map-mask = <0xf800 0 0 7>;
140 interrupt-map = <
141 /* IDSEL 0x0 */
142 0000 0 0 1 &mpic 43 1 0 0
143 0000 0 0 2 &mpic 0 1 0 0
144 0000 0 0 3 &mpic 4 1 0 0
145 0000 0 0 4 &mpic 8 1 0 0
146 >;
147 };
148};
149
150&rio {
151 compatible = "fsl,srio";
152 interrupts = <16 2 1 11>;
153 #address-cells = <2>;
154 #size-cells = <2>;
155 ranges;
156
157 port1 {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 cell-index = <1>;
161 };
162
163 port2 {
164 #address-cells = <2>;
165 #size-cells = <2>;
166 cell-index = <2>;
167 };
168};
169
170&dcsr {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "fsl,dcsr", "simple-bus";
174
175 dcsr-epu@0 {
176 compatible = "fsl,dcsr-epu";
177 interrupts = <52 2 0 0
178 84 2 0 0
179 85 2 0 0>;
180 reg = <0x0 0x1000>;
181 };
182 dcsr-npc {
183 compatible = "fsl,dcsr-npc";
184 reg = <0x1000 0x1000 0x1000000 0x8000>;
185 };
186 dcsr-nxc@2000 {
187 compatible = "fsl,dcsr-nxc";
188 reg = <0x2000 0x1000>;
189 };
190 dcsr-corenet {
191 compatible = "fsl,dcsr-corenet";
192 reg = <0x8000 0x1000 0xB0000 0x1000>;
193 };
194 dcsr-dpaa@9000 {
195 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
196 reg = <0x9000 0x1000>;
197 };
198 dcsr-ocn@11000 {
199 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
200 reg = <0x11000 0x1000>;
201 };
202 dcsr-ddr@12000 {
203 compatible = "fsl,dcsr-ddr";
204 dev-handle = <&ddr1>;
205 reg = <0x12000 0x1000>;
206 };
207 dcsr-ddr@13000 {
208 compatible = "fsl,dcsr-ddr";
209 dev-handle = <&ddr2>;
210 reg = <0x13000 0x1000>;
211 };
212 dcsr-nal@18000 {
213 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
214 reg = <0x18000 0x1000>;
215 };
216 dcsr-rcpm@22000 {
217 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
218 reg = <0x22000 0x1000>;
219 };
220 dcsr-cpu-sb-proxy@40000 {
221 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
222 cpu-handle = <&cpu0>;
223 reg = <0x40000 0x1000>;
224 };
225 dcsr-cpu-sb-proxy@41000 {
226 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
227 cpu-handle = <&cpu1>;
228 reg = <0x41000 0x1000>;
229 };
230};
231
232&soc {
233 #address-cells = <1>;
234 #size-cells = <1>;
235 device_type = "soc";
236 compatible = "simple-bus";
237
238 soc-sram-error {
239 compatible = "fsl,soc-sram-error";
240 interrupts = <16 2 1 29>;
241 };
242
243 corenet-law@0 {
244 compatible = "fsl,corenet-law";
245 reg = <0x0 0x1000>;
246 fsl,num-laws = <32>;
247 };
248
249 ddr1: memory-controller@8000 {
250 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
251 reg = <0x8000 0x1000>;
252 interrupts = <16 2 1 23>;
253 };
254
255 ddr2: memory-controller@9000 {
256 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
257 reg = <0x9000 0x1000>;
258 interrupts = <16 2 1 22>;
259 };
260
261 cpc: l3-cache-controller@10000 {
262 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
263 reg = <0x10000 0x1000
264 0x11000 0x1000>;
265 interrupts = <16 2 1 27
266 16 2 1 26>;
267 };
268
269 corenet-cf@18000 {
270 compatible = "fsl,corenet-cf";
271 reg = <0x18000 0x1000>;
272 interrupts = <16 2 1 31>;
273 fsl,ccf-num-csdids = <32>;
274 fsl,ccf-num-snoopids = <32>;
275 };
276
277 iommu@20000 {
278 compatible = "fsl,pamu-v1.0", "fsl,pamu";
279 reg = <0x20000 0x4000>;
280 interrupts = <
281 24 2 0 0
282 16 2 1 30>;
283 };
284
285/include/ "qoriq-mpic.dtsi"
286
287 guts: global-utilities@e0000 {
288 compatible = "fsl,qoriq-device-config-1.0";
289 reg = <0xe0000 0xe00>;
290 fsl,has-rstcr;
291 #sleep-cells = <1>;
292 fsl,liodn-bits = <12>;
293 };
294
295 pins: global-utilities@e0e00 {
296 compatible = "fsl,qoriq-pin-control-1.0";
297 reg = <0xe0e00 0x200>;
298 #sleep-cells = <2>;
299 };
300
301 clockgen: global-utilities@e1000 {
302 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
303 reg = <0xe1000 0x1000>;
304 clock-frequency = <0>;
305 };
306
307 rcpm: global-utilities@e2000 {
308 compatible = "fsl,qoriq-rcpm-1.0";
309 reg = <0xe2000 0x1000>;
310 #sleep-cells = <1>;
311 };
312
313 sfp: sfp@e8000 {
314 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
315 reg = <0xe8000 0x1000>;
316 };
317
318 serdes: serdes@ea000 {
319 compatible = "fsl,p5020-serdes";
320 reg = <0xea000 0x1000>;
321 };
322
323/include/ "qoriq-dma-0.dtsi"
324/include/ "qoriq-dma-1.dtsi"
325/include/ "qoriq-espi-0.dtsi"
326 spi@110000 {
327 fsl,espi-num-chipselects = <4>;
328 };
329
330/include/ "qoriq-esdhc-0.dtsi"
331 sdhc@114000 {
332 sdhci,auto-cmd12;
333 };
334
335/include/ "qoriq-i2c-0.dtsi"
336/include/ "qoriq-i2c-1.dtsi"
337/include/ "qoriq-duart-0.dtsi"
338/include/ "qoriq-duart-1.dtsi"
339/include/ "qoriq-gpio-0.dtsi"
340/include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 {
342 phy_type = "utmi";
343 port0;
344 };
345
346/include/ "qoriq-usb2-dr-0.dtsi"
347 usb1: usb@211000 {
348 dr_mode = "host";
349 phy_type = "utmi";
350 };
351
352/include/ "qoriq-sata2-0.dtsi"
353/include/ "qoriq-sata2-1.dtsi"
354/include/ "qoriq-sec4.2-0.dtsi"
355};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
new file mode 100644
index 000000000000..ae823a47584e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -0,0 +1,96 @@
1/*
2 * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36/ {
37 compatible = "fsl,P5020";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 aliases {
43 ccsr = &soc;
44 dcsr = &dcsr;
45
46 serial0 = &serial0;
47 serial1 = &serial1;
48 serial2 = &serial2;
49 serial3 = &serial3;
50 pci0 = &pci0;
51 pci1 = &pci1;
52 pci2 = &pci2;
53 pci3 = &pci3;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e5500@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e5500@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 };
96};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
new file mode 100644
index 000000000000..b5b37ad30e75
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-0.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 DMA device tree stub [ controller @ offset 0x21000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma@21300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x21300 0x4>;
40 ranges = <0x0 0x21100 0x200>;
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <20 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <21 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <22 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <23 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
new file mode 100644
index 000000000000..28cb8a55d807
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-dma-1.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma@c300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0xc300 0x4>;
40 ranges = <0x0 0xc100 0x200>;
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <76 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <77 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <78 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <79 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
new file mode 100644
index 000000000000..5e268fdb9d1f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-duart-0.dtsi
@@ -0,0 +1,51 @@
1/*
2 * PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial0: serial@4500 {
36 cell-index = <0>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x4500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <42 2 0 0>;
42};
43
44serial1: serial@4600 {
45 cell-index = <1>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x4600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <42 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
new file mode 100644
index 000000000000..5743433e278e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-esdhc-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 eSDHC device tree stub [ controller @ offset 0x2e000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sdhc@2e000 {
36 compatible = "fsl,esdhc";
37 reg = <0x2e000 0x1000>;
38 interrupts = <72 0x2 0 0>;
39 /* Filled in by U-Boot */
40 clock-frequency = <0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
new file mode 100644
index 000000000000..75854b2e0391
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-espi-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 eSPI device tree stub [ controller @ offset 0x7000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35spi@7000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,mpc8536-espi";
39 reg = <0x7000 0x1000>;
40 interrupts = <59 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
new file mode 100644
index 000000000000..a1979ae334a7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@24000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x24000 0x1000>;
43 ranges = <0x0 0x24000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
46};
47
48mdio@24520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-mdio";
52 reg = <0x24520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
new file mode 100644
index 000000000000..4c4fdde1ec2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@25000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x25000 0x1000>;
43 ranges = <0x0 0x25000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
46};
47
48mdio@25520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x25520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
new file mode 100644
index 000000000000..4b8ab438668a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@26000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <2>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
46};
47
48mdio@26520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x26520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
new file mode 100644
index 000000000000..40c9137729ae
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -0,0 +1,53 @@
1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ethernet@27000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <3>;
39 device_type = "network";
40 model = "eTSEC";
41 compatible = "gianfar";
42 reg = <0x27000 0x1000>;
43 ranges = <0x0 0x27000 0x1000>;
44 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
46};
47
48mdio@27520 {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 compatible = "fsl,gianfar-tbi";
52 reg = <0x27520 0x20>;
53};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
new file mode 100644
index 000000000000..efe2ca04bce8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-timer-0.dtsi
@@ -0,0 +1,39 @@
1/*
2 * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35ptp_clock@24e00 {
36 compatible = "fsl,etsec-ptp";
37 reg = <0x24e00 0xb0>;
38 interrupts = <68 2 0 0 69 2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
new file mode 100644
index 000000000000..1382fec9e8c5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi
@@ -0,0 +1,60 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36mdio@24000 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-mdio";
40 reg = <0x24000 0x1000 0xb0030 0x4>;
41};
42
43ethernet@b0000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "network";
47 model = "eTSEC";
48 compatible = "fsl,etsec2";
49 fsl,num_rx_queues = <0x8>;
50 fsl,num_tx_queues = <0x8>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
53
54 queue-group@b0000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0xb0000 0x1000>;
58 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
59 };
60};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
new file mode 100644
index 000000000000..221cd2ea5b31
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi
@@ -0,0 +1,60 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35
36mdio@25000 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-tbi";
40 reg = <0x25000 0x1000 0xb1030 0x4>;
41};
42
43ethernet@b1000 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "network";
47 model = "eTSEC";
48 compatible = "fsl,etsec2";
49 fsl,num_rx_queues = <0x8>;
50 fsl,num_tx_queues = <0x8>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
53
54 queue-group@b1000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 reg = <0xb1000 0x1000>;
58 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
59 };
60};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
new file mode 100644
index 000000000000..61456c317609
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi
@@ -0,0 +1,59 @@
1/*
2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mdio@26000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,etsec2-tbi";
39 reg = <0x26000 0x1000 0xb1030 0x4>;
40};
41
42ethernet@b2000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 device_type = "network";
46 model = "eTSEC";
47 compatible = "fsl,etsec2";
48 fsl,num_rx_queues = <0x8>;
49 fsl,num_tx_queues = <0x8>;
50 fsl,magic-packet;
51 local-mac-address = [ 00 00 00 00 00 00 ];
52
53 queue-group@b2000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0xb2000 0x1000>;
57 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
58 };
59};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
new file mode 100644
index 000000000000..034ab8fac22f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-0.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet0_grp2 {
36 queue-group@b4000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb4000 0x1000>;
40 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
new file mode 100644
index 000000000000..3be9ba3b374e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-1.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet1_grp2 {
36 queue-group@b5000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb5000 0x1000>;
40 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
new file mode 100644
index 000000000000..02a33457048c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-grp2-2.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&enet2_grp2 {
36 queue-group@b6000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0xb6000 0x1000>;
40 interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
41 };
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
new file mode 100644
index 000000000000..72a3ef5945c1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-gpio-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 GPIO device tree stub [ controller @ offset 0xf000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio-controller@f000 {
36 #gpio-cells = <2>;
37 compatible = "fsl,pq3-gpio";
38 reg = <0xf000 0x100>;
39 interrupts = <47 0x2 0 0>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
new file mode 100644
index 000000000000..d1dd6fb82a78
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-0.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 I2C device tree stub [ controller @ offset 0x3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@3000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <0>;
39 compatible = "fsl-i2c";
40 reg = <0x3000 0x100>;
41 interrupts = <43 2 0 0>;
42 dfsrr;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
new file mode 100644
index 000000000000..a9bd803e2090
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-i2c-1.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 I2C device tree stub [ controller @ offset 0x3100 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@3100 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <1>;
39 compatible = "fsl-i2c";
40 reg = <0x3100 0x100>;
41 interrupts = <43 2 0 0>;
42 dfsrr;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
new file mode 100644
index 000000000000..8734cffae1a1
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-timer-B.dtsi
@@ -0,0 +1,42 @@
1/*
2 * PQ3 MPIC Timer (Group B) device tree stub [ controller @ offset 0x42100 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35timer@42100 {
36 compatible = "fsl,mpic-global-timer";
37 reg = <0x42100 0x100 0x42300 4>;
38 interrupts = <4 0 3 0
39 5 0 3 0
40 6 0 3 0
41 7 0 3 0>;
42};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
new file mode 100644
index 000000000000..5c8046065844
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -0,0 +1,66 @@
1/*
2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic";
41 device_type = "open-pic";
42};
43
44timer@41100 {
45 compatible = "fsl,mpic-global-timer";
46 reg = <0x41100 0x100 0x41300 4>;
47 interrupts = <0 0 3 0
48 1 0 3 0
49 2 0 3 0
50 3 0 3 0>;
51};
52
53msi@41600 {
54 compatible = "fsl,mpic-msi";
55 reg = <0x41600 0x80>;
56 msi-available-ranges = <0 0x100>;
57 interrupts = <
58 0xe0 0 0 0
59 0xe1 0 0 0
60 0xe2 0 0 0
61 0xe3 0 0 0
62 0xe4 0 0 0
63 0xe5 0 0 0
64 0xe6 0 0 0
65 0xe7 0 0 0>;
66};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
new file mode 100644
index 000000000000..587ca9ffad7d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-rmu-0.dtsi
@@ -0,0 +1,68 @@
1/*
2 * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35rmu: rmu@d3000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,srio-rmu";
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
41
42 message-unit@0 {
43 compatible = "fsl,srio-msg-unit";
44 reg = <0x0 0x100>;
45 interrupts = <
46 53 2 0 0 /* msg1_tx_irq */
47 54 2 0 0>;/* msg1_rx_irq */
48 };
49 message-unit@100 {
50 compatible = "fsl,srio-msg-unit";
51 reg = <0x100 0x100>;
52 interrupts = <
53 55 2 0 0 /* msg2_tx_irq */
54 56 2 0 0>;/* msg2_rx_irq */
55 };
56 doorbell-unit@400 {
57 compatible = "fsl,srio-dbell-unit";
58 reg = <0x400 0x80>;
59 interrupts = <
60 49 2 0 0 /* bell_outb_irq */
61 50 2 0 0>;/* bell_inb_irq */
62 };
63 port-write-unit@4e0 {
64 compatible = "fsl,srio-port-write-unit";
65 reg = <0x4e0 0x20>;
66 interrupts = <48 2 0 0>;
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
new file mode 100644
index 000000000000..3c28dd08d38b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-0.dtsi
@@ -0,0 +1,40 @@
1/*
2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@18000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x18000 0x1000>;
38 cell-index = <1>;
39 interrupts = <74 0x2 0 0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
new file mode 100644
index 000000000000..eefaf2855e3b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sata2-1.dtsi
@@ -0,0 +1,40 @@
1/*
2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@19000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x19000 0x1000>;
38 cell-index = <2>;
39 interrupts = <41 0x2 0 0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
new file mode 100644
index 000000000000..02a5c7ae72d0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec2.1-0.dtsi
@@ -0,0 +1,43 @@
1/*
2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec2.1", "fsl,sec2.0";
37 reg = <0x30000 0x10000>;
38 interrupts = <45 2 0 0>;
39 fsl,num-channels = <4>;
40 fsl,channel-fifo-len = <24>;
41 fsl,exec-units-mask = <0xfe>;
42 fsl,descriptor-types-mask = <0x12b0ebf>;
43};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
new file mode 100644
index 000000000000..bba1ba44ccf0
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.0-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0x9fe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
new file mode 100644
index 000000000000..8f0a5669bee5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.1-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.1", "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0xbfe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
new file mode 100644
index 000000000000..c227f2748a24
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec3.3-0.dtsi
@@ -0,0 +1,45 @@
1/*
2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
37 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
41 fsl,num-channels = <4>;
42 fsl,channel-fifo-len = <24>;
43 fsl,exec-units-mask = <0x97c>;
44 fsl,descriptor-types-mask = <0x3a30abf>;
45};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
new file mode 100644
index 000000000000..bf957a7fca2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -0,0 +1,65 @@
1/*
2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto@30000 {
36 compatible = "fsl,sec4.4", "fsl,sec4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>;
41
42 sec_jr0: jr@1000 {
43 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
44 reg = <0x1000 0x1000>;
45 interrupts = <45 2 0 0>;
46 };
47
48 sec_jr1: jr@2000 {
49 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
50 reg = <0x2000 0x1000>;
51 interrupts = <45 2 0 0>;
52 };
53
54 sec_jr2: jr@3000 {
55 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
56 reg = <0x3000 0x1000>;
57 interrupts = <45 2 0 0>;
58 };
59
60 sec_jr3: jr@4000 {
61 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring";
62 reg = <0x4000 0x1000>;
63 interrupts = <45 2 0 0>;
64 };
65};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..185ab9dc3ecd
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 USB DR device tree stub [ controller @ offset 0x22000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@22000 {
36 compatible = "fsl-usb2-dr";
37 reg = <0x22000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <28 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
new file mode 100644
index 000000000000..fe24cd612fff
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-usb2-dr-1.dtsi
@@ -0,0 +1,41 @@
1/*
2 * PQ3 USB DR device tree stub [ controller @ offset 0x23000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@23000 {
36 compatible = "fsl-usb2-dr";
37 reg = <0x23000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <46 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
new file mode 100644
index 000000000000..1aebf3ea4ca5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-0.dtsi
@@ -0,0 +1,66 @@
1/*
2 * QorIQ DMA device tree stub [ controller @ offset 0x100000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x100300 0x4>;
40 ranges = <0x0 0x100100 0x200>;
41 cell-index = <0>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <28 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <29 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <30 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <31 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
new file mode 100644
index 000000000000..ecf5e180fe79
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-dma-1.dtsi
@@ -0,0 +1,66 @@
1/*
2 * QorIQ DMA device tree stub [ controller @ offset 0x101000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,eloplus-dma";
39 reg = <0x101300 0x4>;
40 ranges = <0x0 0x101100 0x200>;
41 cell-index = <1>;
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <32 2 0 0>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
50 reg = <0x80 0x80>;
51 cell-index = <1>;
52 interrupts = <33 2 0 0>;
53 };
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
56 reg = <0x100 0x80>;
57 cell-index = <2>;
58 interrupts = <34 2 0 0>;
59 };
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
62 reg = <0x180 0x80>;
63 cell-index = <3>;
64 interrupts = <35 2 0 0>;
65 };
66};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
new file mode 100644
index 000000000000..225c07b4e8ab
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-0.dtsi
@@ -0,0 +1,51 @@
1/*
2 * QorIQ DUART device tree stub [ controller @ offset 0x11c000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial0: serial@11c500 {
36 cell-index = <0>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x11c500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <36 2 0 0>;
42};
43
44serial1: serial@11c600 {
45 cell-index = <1>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x11c600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <36 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
new file mode 100644
index 000000000000..d23233a56b91
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-duart-1.dtsi
@@ -0,0 +1,51 @@
1/*
2 * QorIQ DUART device tree stub [ controller @ offset 0x11d000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35serial2: serial@11d500 {
36 cell-index = <2>;
37 device_type = "serial";
38 compatible = "fsl,ns16550", "ns16550";
39 reg = <0x11d500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <37 2 0 0>;
42};
43
44serial3: serial@11d600 {
45 cell-index = <3>;
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550";
48 reg = <0x11d600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <37 2 0 0>;
51};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
new file mode 100644
index 000000000000..20835ae216c7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-esdhc-0.dtsi
@@ -0,0 +1,40 @@
1/*
2 * QorIQ eSDHC device tree stub [ controller @ offset 0x114000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sdhc: sdhc@114000 {
36 compatible = "fsl,esdhc";
37 reg = <0x114000 0x1000>;
38 interrupts = <48 2 0 0>;
39 clock-frequency = <0>;
40};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
new file mode 100644
index 000000000000..6db06975e095
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-espi-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35spi@110000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,mpc8536-espi";
39 reg = <0x110000 0x1000>;
40 interrupts = <53 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
new file mode 100644
index 000000000000..cf714f5f68bc
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ GPIO device tree stub [ controller @ offset 0x130000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio0: gpio@130000 {
36 compatible = "fsl,qoriq-gpio";
37 reg = <0x130000 0x1000>;
38 interrupts = <55 2 0 0>;
39 #gpio-cells = <2>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
new file mode 100644
index 000000000000..5f9bf7debe4c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
@@ -0,0 +1,53 @@
1/*
2 * QorIQ I2C device tree stub [ controller @ offset 0x118000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@118000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <0>;
39 compatible = "fsl-i2c";
40 reg = <0x118000 0x100>;
41 interrupts = <38 2 0 0>;
42 dfsrr;
43};
44
45i2c@118100 {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cell-index = <1>;
49 compatible = "fsl-i2c";
50 reg = <0x118100 0x100>;
51 interrupts = <38 2 0 0>;
52 dfsrr;
53};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
new file mode 100644
index 000000000000..7989bf5eeb53
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
@@ -0,0 +1,53 @@
1/*
2 * QorIQ I2C device tree stub [ controller @ offset 0x119000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35i2c@119000 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 cell-index = <2>;
39 compatible = "fsl-i2c";
40 reg = <0x119000 0x100>;
41 interrupts = <39 2 0 0>;
42 dfsrr;
43};
44
45i2c@119100 {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cell-index = <3>;
49 compatible = "fsl-i2c";
50 reg = <0x119100 0x100>;
51 interrupts = <39 2 0 0>;
52 dfsrr;
53};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
new file mode 100644
index 000000000000..b9bada6a87dc
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -0,0 +1,106 @@
1/*
2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35mpic: pic@40000 {
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
40 compatible = "fsl,mpic", "chrp,open-pic";
41 device_type = "open-pic";
42 clock-frequency = <0x0>;
43};
44
45timer@41100 {
46 compatible = "fsl,mpic-global-timer";
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
52};
53
54msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
56 reg = <0x41600 0x200>;
57 msi-available-ranges = <0 0x100>;
58 interrupts = <
59 0xe0 0 0 0
60 0xe1 0 0 0
61 0xe2 0 0 0
62 0xe3 0 0 0
63 0xe4 0 0 0
64 0xe5 0 0 0
65 0xe6 0 0 0
66 0xe7 0 0 0>;
67};
68
69msi1: msi@41800 {
70 compatible = "fsl,mpic-msi";
71 reg = <0x41800 0x200>;
72 msi-available-ranges = <0 0x100>;
73 interrupts = <
74 0xe8 0 0 0
75 0xe9 0 0 0
76 0xea 0 0 0
77 0xeb 0 0 0
78 0xec 0 0 0
79 0xed 0 0 0
80 0xee 0 0 0
81 0xef 0 0 0>;
82};
83
84msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi";
86 reg = <0x41a00 0x200>;
87 msi-available-ranges = <0 0x100>;
88 interrupts = <
89 0xf0 0 0 0
90 0xf1 0 0 0
91 0xf2 0 0 0
92 0xf3 0 0 0
93 0xf4 0 0 0
94 0xf5 0 0 0
95 0xf6 0 0 0
96 0xf7 0 0 0>;
97};
98
99timer@42100 {
100 compatible = "fsl,mpic-global-timer";
101 reg = <0x42100 0x100 0x42300 4>;
102 interrupts = <4 0 3 0
103 5 0 3 0
104 6 0 3 0
105 7 0 3 0>;
106};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
new file mode 100644
index 000000000000..ca7fec792e53
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-rmu-0.dtsi
@@ -0,0 +1,68 @@
1/*
2 * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35rmu: rmu@d3000 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,srio-rmu";
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
41
42 message-unit@0 {
43 compatible = "fsl,srio-msg-unit";
44 reg = <0x0 0x100>;
45 interrupts = <
46 60 2 0 0 /* msg1_tx_irq */
47 61 2 0 0>;/* msg1_rx_irq */
48 };
49 message-unit@100 {
50 compatible = "fsl,srio-msg-unit";
51 reg = <0x100 0x100>;
52 interrupts = <
53 62 2 0 0 /* msg2_tx_irq */
54 63 2 0 0>;/* msg2_rx_irq */
55 };
56 doorbell-unit@400 {
57 compatible = "fsl,srio-dbell-unit";
58 reg = <0x400 0x80>;
59 interrupts = <
60 56 2 0 0 /* bell_outb_irq */
61 57 2 0 0>;/* bell_inb_irq */
62 };
63 port-write-unit@4e0 {
64 compatible = "fsl,srio-port-write-unit";
65 reg = <0x4e0 0x20>;
66 interrupts = <16 2 1 11>;
67 };
68};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
new file mode 100644
index 000000000000..b642047fdecf
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-0.dtsi
@@ -0,0 +1,39 @@
1/*
2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@220000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x220000 0x1000>;
38 interrupts = <68 0x2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
new file mode 100644
index 000000000000..c57370259750
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sata2-1.dtsi
@@ -0,0 +1,39 @@
1/*
2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x221000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35sata@221000 {
36 compatible = "fsl,pq-sata-v2";
37 reg = <0x221000 0x1000>;
38 interrupts = <69 0x2 0 0>;
39};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
new file mode 100644
index 000000000000..0cbbac329539
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,100 @@
1/*
2 * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.0-job-ring";
45 reg = <0x1000 0x1000>;
46 interrupts = <88 2 0 0>;
47 };
48
49 sec_jr1: jr@2000 {
50 compatible = "fsl,sec-v4.0-job-ring";
51 reg = <0x2000 0x1000>;
52 interrupts = <89 2 0 0>;
53 };
54
55 sec_jr2: jr@3000 {
56 compatible = "fsl,sec-v4.0-job-ring";
57 reg = <0x3000 0x1000>;
58 interrupts = <90 2 0 0>;
59 };
60
61 sec_jr3: jr@4000 {
62 compatible = "fsl,sec-v4.0-job-ring";
63 reg = <0x4000 0x1000>;
64 interrupts = <91 2 0 0>;
65 };
66
67 rtic@6000 {
68 compatible = "fsl,sec-v4.0-rtic";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 reg = <0x6000 0x100>;
72 ranges = <0x0 0x6100 0xe00>;
73
74 rtic_a: rtic-a@0 {
75 compatible = "fsl,sec-v4.0-rtic-memory";
76 reg = <0x00 0x20 0x100 0x80>;
77 };
78
79 rtic_b: rtic-b@20 {
80 compatible = "fsl,sec-v4.0-rtic-memory";
81 reg = <0x20 0x20 0x200 0x80>;
82 };
83
84 rtic_c: rtic-c@40 {
85 compatible = "fsl,sec-v4.0-rtic-memory";
86 reg = <0x40 0x20 0x300 0x80>;
87 };
88
89 rtic_d: rtic-d@60 {
90 compatible = "fsl,sec-v4.0-rtic-memory";
91 reg = <0x60 0x20 0x500 0x80>;
92 };
93 };
94};
95
96sec_mon: sec_mon@314000 {
97 compatible = "fsl,sec-v4.0-mon";
98 reg = <0x314000 0x1000>;
99 interrupts = <93 2 0 0>;
100};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
new file mode 100644
index 000000000000..3308986bba0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
@@ -0,0 +1,109 @@
1/*
2 * QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.1-job-ring",
45 "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
48 };
49
50 sec_jr1: jr@2000 {
51 compatible = "fsl,sec-v4.1-job-ring",
52 "fsl,sec-v4.0-job-ring";
53 reg = <0x2000 0x1000>;
54 interrupts = <89 2 0 0>;
55 };
56
57 sec_jr2: jr@3000 {
58 compatible = "fsl,sec-v4.1-job-ring",
59 "fsl,sec-v4.0-job-ring";
60 reg = <0x3000 0x1000>;
61 interrupts = <90 2 0 0>;
62 };
63
64 sec_jr3: jr@4000 {
65 compatible = "fsl,sec-v4.1-job-ring",
66 "fsl,sec-v4.0-job-ring";
67 reg = <0x4000 0x1000>;
68 interrupts = <91 2 0 0>;
69 };
70
71 rtic@6000 {
72 compatible = "fsl,sec-v4.1-rtic",
73 "fsl,sec-v4.0-rtic";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x6000 0x100>;
77 ranges = <0x0 0x6100 0xe00>;
78
79 rtic_a: rtic-a@0 {
80 compatible = "fsl,sec-v4.1-rtic-memory",
81 "fsl,sec-v4.0-rtic-memory";
82 reg = <0x00 0x20 0x100 0x80>;
83 };
84
85 rtic_b: rtic-b@20 {
86 compatible = "fsl,sec-v4.1-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x20 0x20 0x200 0x80>;
89 };
90
91 rtic_c: rtic-c@40 {
92 compatible = "fsl,sec-v4.1-rtic-memory",
93 "fsl,sec-v4.0-rtic-memory";
94 reg = <0x40 0x20 0x300 0x80>;
95 };
96
97 rtic_d: rtic-d@60 {
98 compatible = "fsl,sec-v4.1-rtic-memory",
99 "fsl,sec-v4.0-rtic-memory";
100 reg = <0x60 0x20 0x500 0x80>;
101 };
102 };
103};
104
105sec_mon: sec_mon@314000 {
106 compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
107 reg = <0x314000 0x1000>;
108 interrupts = <93 2 0 0>;
109};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
new file mode 100644
index 000000000000..7990e0d3d6f2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,109 @@
1/*
2 * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x300000 0x10000>;
40 ranges = <0 0x300000 0x10000>;
41 interrupts = <92 2 0 0>;
42
43 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.2-job-ring",
45 "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>;
48 };
49
50 sec_jr1: jr@2000 {
51 compatible = "fsl,sec-v4.2-job-ring",
52 "fsl,sec-v4.0-job-ring";
53 reg = <0x2000 0x1000>;
54 interrupts = <89 2 0 0>;
55 };
56
57 sec_jr2: jr@3000 {
58 compatible = "fsl,sec-v4.2-job-ring",
59 "fsl,sec-v4.0-job-ring";
60 reg = <0x3000 0x1000>;
61 interrupts = <90 2 0 0>;
62 };
63
64 sec_jr3: jr@4000 {
65 compatible = "fsl,sec-v4.2-job-ring",
66 "fsl,sec-v4.0-job-ring";
67 reg = <0x4000 0x1000>;
68 interrupts = <91 2 0 0>;
69 };
70
71 rtic@6000 {
72 compatible = "fsl,sec-v4.2-rtic",
73 "fsl,sec-v4.0-rtic";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x6000 0x100>;
77 ranges = <0x0 0x6100 0xe00>;
78
79 rtic_a: rtic-a@0 {
80 compatible = "fsl,sec-v4.2-rtic-memory",
81 "fsl,sec-v4.0-rtic-memory";
82 reg = <0x00 0x20 0x100 0x80>;
83 };
84
85 rtic_b: rtic-b@20 {
86 compatible = "fsl,sec-v4.2-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x20 0x20 0x200 0x80>;
89 };
90
91 rtic_c: rtic-c@40 {
92 compatible = "fsl,sec-v4.2-rtic-memory",
93 "fsl,sec-v4.0-rtic-memory";
94 reg = <0x40 0x20 0x300 0x80>;
95 };
96
97 rtic_d: rtic-d@60 {
98 compatible = "fsl,sec-v4.2-rtic-memory",
99 "fsl,sec-v4.0-rtic-memory";
100 reg = <0x60 0x20 0x500 0x80>;
101 };
102 };
103};
104
105sec_mon: sec_mon@314000 {
106 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
107 reg = <0x314000 0x1000>;
108 interrupts = <93 2 0 0>;
109};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..4dd6f84c239c
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ USB DR device tree stub [ controller @ offset 0x211000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@211000 {
36 compatible = "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
37 reg = <0x211000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <45 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
new file mode 100644
index 000000000000..f053835aa1c7
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-usb2-mph-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ USB Host device tree stub [ controller @ offset 0x210000 ]
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@210000 {
36 compatible = "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
37 reg = <0x210000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index 2266bbb303d0..38dcb96c8e26 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -339,7 +339,7 @@
339 serial0: serial@4500 { 339 serial0: serial@4500 {
340 cell-index = <0>; 340 cell-index = <0>;
341 device_type = "serial"; 341 device_type = "serial";
342 compatible = "ns16550"; 342 compatible = "fsl,ns16550", "ns16550";
343 reg = <0x4500 0x100>; 343 reg = <0x4500 0x100>;
344 clock-frequency = <0>; 344 clock-frequency = <0>;
345 interrupts = <0x2a 0x2>; 345 interrupts = <0x2a 0x2>;
@@ -349,7 +349,7 @@
349 serial1: serial@4600 { 349 serial1: serial@4600 {
350 cell-index = <1>; 350 cell-index = <1>;
351 device_type = "serial"; 351 device_type = "serial";
352 compatible = "ns16550"; 352 compatible = "fsl,ns16550", "ns16550";
353 reg = <0x4600 0x100>; 353 reg = <0x4600 0x100>;
354 clock-frequency = <0>; 354 clock-frequency = <0>;
355 interrupts = <0x1c 0x2>; 355 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 429e87d9acef..5ab8932d09b7 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>; 343 interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
347 serial1: serial@4600 { 347 serial1: serial@4600 {
348 cell-index = <1>; 348 cell-index = <1>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4600 0x100>; 351 reg = <0x4600 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>; 353 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index d81201ac2cad..d5341f5741aa 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 interrupts = <0x2a 0x2>; 343 interrupts = <0x2a 0x2>;
@@ -347,7 +347,7 @@
347 serial1: serial@4600 { 347 serial1: serial@4600 {
348 cell-index = <1>; 348 cell-index = <1>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4600 0x100>; 351 reg = <0x4600 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <0x1c 0x2>; 353 interrupts = <0x1c 0x2>;
diff --git a/arch/powerpc/boot/dts/klondike.dts b/arch/powerpc/boot/dts/klondike.dts
new file mode 100644
index 000000000000..8c9429033618
--- /dev/null
+++ b/arch/powerpc/boot/dts/klondike.dts
@@ -0,0 +1,227 @@
1/*
2 * Device Tree for Klondike (APM8018X) board.
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tanmay Inamdar <tinamdar@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24/dts-v1/;
25
26/ {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 model = "apm,klondike";
30 compatible = "apm,klondike";
31 dcr-parent = <&{/cpus/cpu@0}>;
32
33 aliases {
34 ethernet0 = &EMAC0;
35 ethernet1 = &EMAC1;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu@0 {
43 device_type = "cpu";
44 model = "PowerPC,apm8018x";
45 reg = <0x00000000>;
46 clock-frequency = <300000000>; /* Filled in by U-Boot */
47 timebase-frequency = <300000000>; /* Filled in by U-Boot */
48 i-cache-line-size = <32>;
49 d-cache-line-size = <32>;
50 i-cache-size = <16384>; /* 16 kB */
51 d-cache-size = <16384>; /* 16 kB */
52 dcr-controller;
53 dcr-access-method = "native";
54 };
55 };
56
57 memory {
58 device_type = "memory";
59 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
60 };
61
62 UIC0: interrupt-controller {
63 compatible = "ibm,uic";
64 interrupt-controller;
65 cell-index = <0>;
66 dcr-reg = <0x0c0 0x010>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 };
71
72 UIC1: interrupt-controller1 {
73 compatible = "ibm,uic";
74 interrupt-controller;
75 cell-index = <1>;
76 dcr-reg = <0x0d0 0x010>;
77 #address-cells = <0>;
78 #size-cells = <0>;
79 #interrupt-cells = <2>;
80 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
81 interrupt-parent = <&UIC0>;
82 };
83
84 UIC2: interrupt-controller2 {
85 compatible = "ibm,uic";
86 interrupt-controller;
87 cell-index = <2>;
88 dcr-reg = <0x0e0 0x010>;
89 #address-cells = <0>;
90 #size-cells = <0>;
91 #interrupt-cells = <2>;
92 interrupts = <0x0a 0x4 0x0b 0x4>; /* cascade */
93 interrupt-parent = <&UIC0>;
94 };
95
96 UIC3: interrupt-controller3 {
97 compatible = "ibm,uic";
98 interrupt-controller;
99 cell-index = <3>;
100 dcr-reg = <0x0f0 0x010>;
101 #address-cells = <0>;
102 #size-cells = <0>;
103 #interrupt-cells = <2>;
104 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
105 interrupt-parent = <&UIC0>;
106 };
107
108 plb {
109 compatible = "ibm,plb4";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113 clock-frequency = <0>; /* Filled in by U-Boot */
114
115 SDRAM0: memory-controller {
116 compatible = "ibm,sdram-apm8018x";
117 dcr-reg = <0x010 0x002>;
118 };
119
120 MAL0: mcmal {
121 compatible = "ibm,mcmal2";
122 dcr-reg = <0x180 0x062>;
123 num-tx-chans = <2>;
124 num-rx-chans = <16>;
125 #address-cells = <0>;
126 #size-cells = <0>;
127 interrupt-parent = <&UIC1>;
128 interrupts = </*TXEOB*/ 0x6 0x4
129 /*RXEOB*/ 0x7 0x4
130 /*SERR*/ 0x1 0x4
131 /*TXDE*/ 0x2 0x4
132 /*RXDE*/ 0x3 0x4>;
133 };
134
135 POB0: opb {
136 compatible = "ibm,opb";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0x20000000 0x20000000 0x30000000
140 0x50000000 0x50000000 0x10000000
141 0x60000000 0x60000000 0x10000000
142 0xFE000000 0xFE000000 0x00010000>;
143 dcr-reg = <0x100 0x020>;
144 clock-frequency = <300000000>; /* Filled in by U-Boot */
145
146 RGMII0: emac-rgmii@400a2000 {
147 compatible = "ibm,rgmii";
148 reg = <0x400a2000 0x00000010>;
149 has-mdio;
150 };
151
152 TAH0: emac-tah@400a3000 {
153 compatible = "ibm,tah";
154 reg = <0x400a3000 0x100>;
155 };
156
157 TAH1: emac-tah@400a4000 {
158 compatible = "ibm,tah";
159 reg = <0x400a4000 0x100>;
160 };
161
162 EMAC0: ethernet@400a0000 {
163 compatible = "ibm,emac4", "ibm-emac4sync";
164 interrupt-parent = <&EMAC0>;
165 interrupts = <0x0>;
166 #interrupt-cells = <1>;
167 #address-cells = <0>;
168 #size-cells = <0>;
169 interrupt-map = </*Status*/ 0x0 &UIC0 0x13 0x4>;
170 reg = <0x400a0000 0x00000100>;
171 local-mac-address = [000000000000]; /* Filled in by U-Boot */
172 mal-device = <&MAL0>;
173 mal-tx-channel = <0x0>;
174 mal-rx-channel = <0x0>;
175 cell-index = <0>;
176 max-frame-size = <9000>;
177 rx-fifo-size = <4096>;
178 tx-fifo-size = <2048>;
179 phy-mode = "rgmii";
180 phy-address = <0x2>;
181 turbo = "no";
182 phy-map = <0x00000000>;
183 rgmii-device = <&RGMII0>;
184 rgmii-channel = <0>;
185 tah-device = <&TAH0>;
186 tah-channel = <0>;
187 has-inverted-stacr-oc;
188 has-new-stacr-staopc;
189 };
190
191 EMAC1: ethernet@400a1000 {
192 compatible = "ibm,emac4", "ibm-emac4sync";
193 status = "disabled";
194 interrupt-parent = <&EMAC1>;
195 interrupts = <0x0>;
196 #interrupt-cells = <1>;
197 #address-cells = <0>;
198 #size-cells = <0>;
199 interrupt-map = </*Status*/ 0x0 &UIC0 0x14 0x4>;
200 reg = <0x400a1000 0x00000100>;
201 local-mac-address = [000000000000]; /* Filled in by U-Boot */
202 mal-device = <&MAL0>;
203 mal-tx-channel = <1>;
204 mal-rx-channel = <8>;
205 cell-index = <1>;
206 max-frame-size = <9000>;
207 rx-fifo-size = <4096>;
208 tx-fifo-size = <2048>;
209 phy-mode = "rgmii";
210 phy-address = <0x3>;
211 turbo = "no";
212 phy-map = <0x00000000>;
213 rgmii-device = <&RGMII0>;
214 rgmii-channel = <1>;
215 tah-device = <&TAH1>;
216 tah-channel = <0>;
217 has-inverted-stacr-oc;
218 has-new-stacr-staopc;
219 mdio-device = <&EMAC0>;
220 };
221 };
222 };
223
224 chosen {
225 linux,stdout-path = "/plb/opb/serial@50001000";
226 };
227};
diff --git a/arch/powerpc/boot/dts/kmeter1.dts b/arch/powerpc/boot/dts/kmeter1.dts
index d16bae1230f7..983aee185793 100644
--- a/arch/powerpc/boot/dts/kmeter1.dts
+++ b/arch/powerpc/boot/dts/kmeter1.dts
@@ -80,7 +80,7 @@
80 serial0: serial@4500 { 80 serial0: serial@4500 {
81 cell-index = <0>; 81 cell-index = <0>;
82 device_type = "serial"; 82 device_type = "serial";
83 compatible = "ns16550"; 83 compatible = "fsl,ns16550", "ns16550";
84 reg = <0x4500 0x100>; 84 reg = <0x4500 0x100>;
85 clock-frequency = <264000000>; 85 clock-frequency = <264000000>;
86 interrupts = <9 0x8>; 86 interrupts = <9 0x8>;
diff --git a/arch/powerpc/boot/dts/kuroboxHD.dts b/arch/powerpc/boot/dts/kuroboxHD.dts
index 8d725d10882f..0a4545159e80 100644
--- a/arch/powerpc/boot/dts/kuroboxHD.dts
+++ b/arch/powerpc/boot/dts/kuroboxHD.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
84 serial0: serial@80004500 { 84 serial0: serial@80004500 {
85 cell-index = <0>; 85 cell-index = <0>;
86 device_type = "serial"; 86 device_type = "serial";
87 compatible = "ns16550"; 87 compatible = "fsl,ns16550", "ns16550";
88 reg = <0x80004500 0x8>; 88 reg = <0x80004500 0x8>;
89 clock-frequency = <97553800>; 89 clock-frequency = <97553800>;
90 current-speed = <9600>; 90 current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
95 serial1: serial@80004600 { 95 serial1: serial@80004600 {
96 cell-index = <1>; 96 cell-index = <1>;
97 device_type = "serial"; 97 device_type = "serial";
98 compatible = "ns16550"; 98 compatible = "fsl,ns16550", "ns16550";
99 reg = <0x80004600 0x8>; 99 reg = <0x80004600 0x8>;
100 clock-frequency = <97553800>; 100 clock-frequency = <97553800>;
101 current-speed = <57600>; 101 current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/kuroboxHG.dts b/arch/powerpc/boot/dts/kuroboxHG.dts
index b13a11eb81b0..0e758b347cdb 100644
--- a/arch/powerpc/boot/dts/kuroboxHG.dts
+++ b/arch/powerpc/boot/dts/kuroboxHG.dts
@@ -84,7 +84,7 @@ XXXX add flash parts, rtc, ??
84 serial0: serial@80004500 { 84 serial0: serial@80004500 {
85 cell-index = <0>; 85 cell-index = <0>;
86 device_type = "serial"; 86 device_type = "serial";
87 compatible = "ns16550"; 87 compatible = "fsl,ns16550", "ns16550";
88 reg = <0x80004500 0x8>; 88 reg = <0x80004500 0x8>;
89 clock-frequency = <130041000>; 89 clock-frequency = <130041000>;
90 current-speed = <9600>; 90 current-speed = <9600>;
@@ -95,7 +95,7 @@ XXXX add flash parts, rtc, ??
95 serial1: serial@80004600 { 95 serial1: serial@80004600 {
96 cell-index = <1>; 96 cell-index = <1>;
97 device_type = "serial"; 97 device_type = "serial";
98 compatible = "ns16550"; 98 compatible = "fsl,ns16550", "ns16550";
99 reg = <0x80004600 0x8>; 99 reg = <0x80004600 0x8>;
100 clock-frequency = <130041000>; 100 clock-frequency = <130041000>;
101 current-speed = <57600>; 101 current-speed = <57600>;
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 697b3f6b78bf..22b0832b6c31 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -233,7 +233,7 @@
233 serial0: serial@4500 { 233 serial0: serial@4500 {
234 cell-index = <0>; 234 cell-index = <0>;
235 device_type = "serial"; 235 device_type = "serial";
236 compatible = "ns16550"; 236 compatible = "fsl,ns16550", "ns16550";
237 reg = <0x4500 0x100>; 237 reg = <0x4500 0x100>;
238 clock-frequency = <133333333>; 238 clock-frequency = <133333333>;
239 interrupts = <9 0x8>; 239 interrupts = <9 0x8>;
@@ -243,7 +243,7 @@
243 serial1: serial@4600 { 243 serial1: serial@4600 {
244 cell-index = <1>; 244 cell-index = <1>;
245 device_type = "serial"; 245 device_type = "serial";
246 compatible = "ns16550"; 246 compatible = "fsl,ns16550", "ns16550";
247 reg = <0x4600 0x100>; 247 reg = <0x4600 0x100>;
248 clock-frequency = <133333333>; 248 clock-frequency = <133333333>;
249 interrupts = <10 0x8>; 249 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a0bd1881081e..f66d10d95a8d 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -208,7 +208,7 @@
208 serial0: serial@4500 { 208 serial0: serial@4500 {
209 cell-index = <0>; 209 cell-index = <0>;
210 device_type = "serial"; 210 device_type = "serial";
211 compatible = "ns16550"; 211 compatible = "fsl,ns16550", "ns16550";
212 reg = <0x4500 0x100>; 212 reg = <0x4500 0x100>;
213 clock-frequency = <133333333>; 213 clock-frequency = <133333333>;
214 interrupts = <9 0x8>; 214 interrupts = <9 0x8>;
@@ -218,7 +218,7 @@
218 serial1: serial@4600 { 218 serial1: serial@4600 {
219 cell-index = <1>; 219 cell-index = <1>;
220 device_type = "serial"; 220 device_type = "serial";
221 compatible = "ns16550"; 221 compatible = "fsl,ns16550", "ns16550";
222 reg = <0x4600 0x100>; 222 reg = <0x4600 0x100>;
223 clock-frequency = <133333333>; 223 clock-frequency = <133333333>;
224 interrupts = <10 0x8>; 224 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index ac1eb320c7b4..1c836c6c5be6 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -261,7 +261,7 @@
261 serial0: serial@4500 { 261 serial0: serial@4500 {
262 cell-index = <0>; 262 cell-index = <0>;
263 device_type = "serial"; 263 device_type = "serial";
264 compatible = "ns16550"; 264 compatible = "fsl,ns16550", "ns16550";
265 reg = <0x4500 0x100>; 265 reg = <0x4500 0x100>;
266 clock-frequency = <0>; 266 clock-frequency = <0>;
267 interrupts = <9 0x8>; 267 interrupts = <9 0x8>;
@@ -271,7 +271,7 @@
271 serial1: serial@4600 { 271 serial1: serial@4600 {
272 cell-index = <1>; 272 cell-index = <1>;
273 device_type = "serial"; 273 device_type = "serial";
274 compatible = "ns16550"; 274 compatible = "fsl,ns16550", "ns16550";
275 reg = <0x4600 0x100>; 275 reg = <0x4600 0x100>;
276 clock-frequency = <0>; 276 clock-frequency = <0>;
277 interrupts = <10 0x8>; 277 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 4dd08c322979..811848e93aef 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -265,7 +265,7 @@
265 serial0: serial@4500 { 265 serial0: serial@4500 {
266 cell-index = <0>; 266 cell-index = <0>;
267 device_type = "serial"; 267 device_type = "serial";
268 compatible = "ns16550"; 268 compatible = "fsl,ns16550", "ns16550";
269 reg = <0x4500 0x100>; 269 reg = <0x4500 0x100>;
270 clock-frequency = <133333333>; 270 clock-frequency = <133333333>;
271 interrupts = <9 0x8>; 271 interrupts = <9 0x8>;
@@ -275,7 +275,7 @@
275 serial1: serial@4600 { 275 serial1: serial@4600 {
276 cell-index = <1>; 276 cell-index = <1>;
277 device_type = "serial"; 277 device_type = "serial";
278 compatible = "ns16550"; 278 compatible = "fsl,ns16550", "ns16550";
279 reg = <0x4600 0x100>; 279 reg = <0x4600 0x100>;
280 clock-frequency = <133333333>; 280 clock-frequency = <133333333>;
281 interrupts = <10 0x8>; 281 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_mds.dts b/arch/powerpc/boot/dts/mpc832x_mds.dts
index 05ad8c98e527..da9c72ddc343 100644
--- a/arch/powerpc/boot/dts/mpc832x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc832x_mds.dts
@@ -105,7 +105,7 @@
105 serial0: serial@4500 { 105 serial0: serial@4500 {
106 cell-index = <0>; 106 cell-index = <0>;
107 device_type = "serial"; 107 device_type = "serial";
108 compatible = "ns16550"; 108 compatible = "fsl,ns16550", "ns16550";
109 reg = <0x4500 0x100>; 109 reg = <0x4500 0x100>;
110 clock-frequency = <0>; 110 clock-frequency = <0>;
111 interrupts = <9 0x8>; 111 interrupts = <9 0x8>;
@@ -115,7 +115,7 @@
115 serial1: serial@4600 { 115 serial1: serial@4600 {
116 cell-index = <1>; 116 cell-index = <1>;
117 device_type = "serial"; 117 device_type = "serial";
118 compatible = "ns16550"; 118 compatible = "fsl,ns16550", "ns16550";
119 reg = <0x4600 0x100>; 119 reg = <0x4600 0x100>;
120 clock-frequency = <0>; 120 clock-frequency = <0>;
121 interrupts = <10 0x8>; 121 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc832x_rdb.dts b/arch/powerpc/boot/dts/mpc832x_rdb.dts
index f4fadb23ad6f..ff7b15b340a3 100644
--- a/arch/powerpc/boot/dts/mpc832x_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc832x_rdb.dts
@@ -83,7 +83,7 @@
83 serial0: serial@4500 { 83 serial0: serial@4500 {
84 cell-index = <0>; 84 cell-index = <0>;
85 device_type = "serial"; 85 device_type = "serial";
86 compatible = "ns16550"; 86 compatible = "fsl,ns16550", "ns16550";
87 reg = <0x4500 0x100>; 87 reg = <0x4500 0x100>;
88 clock-frequency = <0>; 88 clock-frequency = <0>;
89 interrupts = <9 0x8>; 89 interrupts = <9 0x8>;
@@ -93,7 +93,7 @@
93 serial1: serial@4600 { 93 serial1: serial@4600 {
94 cell-index = <1>; 94 cell-index = <1>;
95 device_type = "serial"; 95 device_type = "serial";
96 compatible = "ns16550"; 96 compatible = "fsl,ns16550", "ns16550";
97 reg = <0x4600 0x100>; 97 reg = <0x4600 0x100>;
98 clock-frequency = <0>; 98 clock-frequency = <0>;
99 interrupts = <10 0x8>; 99 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitx.dts b/arch/powerpc/boot/dts/mpc8349emitx.dts
index 505dc842d808..2608679d0d4a 100644
--- a/arch/powerpc/boot/dts/mpc8349emitx.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitx.dts
@@ -283,7 +283,7 @@
283 serial0: serial@4500 { 283 serial0: serial@4500 {
284 cell-index = <0>; 284 cell-index = <0>;
285 device_type = "serial"; 285 device_type = "serial";
286 compatible = "ns16550"; 286 compatible = "fsl,ns16550", "ns16550";
287 reg = <0x4500 0x100>; 287 reg = <0x4500 0x100>;
288 clock-frequency = <0>; // from bootloader 288 clock-frequency = <0>; // from bootloader
289 interrupts = <9 0x8>; 289 interrupts = <9 0x8>;
@@ -293,7 +293,7 @@
293 serial1: serial@4600 { 293 serial1: serial@4600 {
294 cell-index = <1>; 294 cell-index = <1>;
295 device_type = "serial"; 295 device_type = "serial";
296 compatible = "ns16550"; 296 compatible = "fsl,ns16550", "ns16550";
297 reg = <0x4600 0x100>; 297 reg = <0x4600 0x100>;
298 clock-frequency = <0>; // from bootloader 298 clock-frequency = <0>; // from bootloader
299 interrupts = <10 0x8>; 299 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8349emitxgp.dts b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
index eb732115f016..6cd044d8fb89 100644
--- a/arch/powerpc/boot/dts/mpc8349emitxgp.dts
+++ b/arch/powerpc/boot/dts/mpc8349emitxgp.dts
@@ -189,7 +189,7 @@
189 serial0: serial@4500 { 189 serial0: serial@4500 {
190 cell-index = <0>; 190 cell-index = <0>;
191 device_type = "serial"; 191 device_type = "serial";
192 compatible = "ns16550"; 192 compatible = "fsl,ns16550", "ns16550";
193 reg = <0x4500 0x100>; 193 reg = <0x4500 0x100>;
194 clock-frequency = <0>; // from bootloader 194 clock-frequency = <0>; // from bootloader
195 interrupts = <9 0x8>; 195 interrupts = <9 0x8>;
@@ -199,7 +199,7 @@
199 serial1: serial@4600 { 199 serial1: serial@4600 {
200 cell-index = <1>; 200 cell-index = <1>;
201 device_type = "serial"; 201 device_type = "serial";
202 compatible = "ns16550"; 202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4600 0x100>; 203 reg = <0x4600 0x100>;
204 clock-frequency = <0>; // from bootloader 204 clock-frequency = <0>; // from bootloader
205 interrupts = <10 0x8>; 205 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts
index 230febb9b72f..4552864082c2 100644
--- a/arch/powerpc/boot/dts/mpc834x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc834x_mds.dts
@@ -242,7 +242,7 @@
242 serial0: serial@4500 { 242 serial0: serial@4500 {
243 cell-index = <0>; 243 cell-index = <0>;
244 device_type = "serial"; 244 device_type = "serial";
245 compatible = "ns16550"; 245 compatible = "fsl,ns16550", "ns16550";
246 reg = <0x4500 0x100>; 246 reg = <0x4500 0x100>;
247 clock-frequency = <0>; 247 clock-frequency = <0>;
248 interrupts = <9 0x8>; 248 interrupts = <9 0x8>;
@@ -252,7 +252,7 @@
252 serial1: serial@4600 { 252 serial1: serial@4600 {
253 cell-index = <1>; 253 cell-index = <1>;
254 device_type = "serial"; 254 device_type = "serial";
255 compatible = "ns16550"; 255 compatible = "fsl,ns16550", "ns16550";
256 reg = <0x4600 0x100>; 256 reg = <0x4600 0x100>;
257 clock-frequency = <0>; 257 clock-frequency = <0>;
258 interrupts = <10 0x8>; 258 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 45cfa1c50a2a..c0e450a551bf 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -136,7 +136,7 @@
136 serial0: serial@4500 { 136 serial0: serial@4500 {
137 cell-index = <0>; 137 cell-index = <0>;
138 device_type = "serial"; 138 device_type = "serial";
139 compatible = "ns16550"; 139 compatible = "fsl,ns16550", "ns16550";
140 reg = <0x4500 0x100>; 140 reg = <0x4500 0x100>;
141 clock-frequency = <264000000>; 141 clock-frequency = <264000000>;
142 interrupts = <9 0x8>; 142 interrupts = <9 0x8>;
@@ -146,7 +146,7 @@
146 serial1: serial@4600 { 146 serial1: serial@4600 {
147 cell-index = <1>; 147 cell-index = <1>;
148 device_type = "serial"; 148 device_type = "serial";
149 compatible = "ns16550"; 149 compatible = "fsl,ns16550", "ns16550";
150 reg = <0x4600 0x100>; 150 reg = <0x4600 0x100>;
151 clock-frequency = <264000000>; 151 clock-frequency = <264000000>;
152 interrupts = <10 0x8>; 152 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index bdf4459677b1..b6e9aec1d860 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -102,7 +102,7 @@
102 102
103 serial0: serial@4500 { 103 serial0: serial@4500 {
104 device_type = "serial"; 104 device_type = "serial";
105 compatible = "ns16550"; 105 compatible = "fsl,ns16550", "ns16550";
106 reg = <0x4500 0x100>; 106 reg = <0x4500 0x100>;
107 interrupts = <9 8>; 107 interrupts = <9 8>;
108 interrupt-parent = <&ipic>; 108 interrupt-parent = <&ipic>;
@@ -112,7 +112,7 @@
112 112
113 serial1: serial@4600 { 113 serial1: serial@4600 {
114 device_type = "serial"; 114 device_type = "serial";
115 compatible = "ns16550"; 115 compatible = "fsl,ns16550", "ns16550";
116 reg = <0x4600 0x100>; 116 reg = <0x4600 0x100>;
117 interrupts = <10 8>; 117 interrupts = <10 8>;
118 interrupt-parent = <&ipic>; 118 interrupt-parent = <&ipic>;
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 855782c5e5ec..cfccef57cd1d 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -276,7 +276,7 @@
276 serial0: serial@4500 { 276 serial0: serial@4500 {
277 cell-index = <0>; 277 cell-index = <0>;
278 device_type = "serial"; 278 device_type = "serial";
279 compatible = "ns16550"; 279 compatible = "fsl,ns16550", "ns16550";
280 reg = <0x4500 0x100>; 280 reg = <0x4500 0x100>;
281 clock-frequency = <0>; 281 clock-frequency = <0>;
282 interrupts = <9 0x8>; 282 interrupts = <9 0x8>;
@@ -286,7 +286,7 @@
286 serial1: serial@4600 { 286 serial1: serial@4600 {
287 cell-index = <1>; 287 cell-index = <1>;
288 device_type = "serial"; 288 device_type = "serial";
289 compatible = "ns16550"; 289 compatible = "fsl,ns16550", "ns16550";
290 reg = <0x4600 0x100>; 290 reg = <0x4600 0x100>;
291 clock-frequency = <0>; 291 clock-frequency = <0>;
292 interrupts = <10 0x8>; 292 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index dbc1b988b29d..353deff1b7f6 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -321,7 +321,7 @@
321 serial0: serial@4500 { 321 serial0: serial@4500 {
322 cell-index = <0>; 322 cell-index = <0>;
323 device_type = "serial"; 323 device_type = "serial";
324 compatible = "ns16550"; 324 compatible = "fsl,ns16550", "ns16550";
325 reg = <0x4500 0x100>; 325 reg = <0x4500 0x100>;
326 clock-frequency = <0>; 326 clock-frequency = <0>;
327 interrupts = <9 0x8>; 327 interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
331 serial1: serial@4600 { 331 serial1: serial@4600 {
332 cell-index = <1>; 332 cell-index = <1>;
333 device_type = "serial"; 333 device_type = "serial";
334 compatible = "ns16550"; 334 compatible = "fsl,ns16550", "ns16550";
335 reg = <0x4600 0x100>; 335 reg = <0x4600 0x100>;
336 clock-frequency = <0>; 336 clock-frequency = <0>;
337 interrupts = <10 0x8>; 337 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
index 9ea783056969..ef4a305a0d0c 100644
--- a/arch/powerpc/boot/dts/mpc8377_wlan.dts
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -304,7 +304,7 @@
304 serial0: serial@4500 { 304 serial0: serial@4500 {
305 cell-index = <0>; 305 cell-index = <0>;
306 device_type = "serial"; 306 device_type = "serial";
307 compatible = "ns16550"; 307 compatible = "fsl,ns16550", "ns16550";
308 reg = <0x4500 0x100>; 308 reg = <0x4500 0x100>;
309 clock-frequency = <0>; 309 clock-frequency = <0>;
310 interrupts = <9 0x8>; 310 interrupts = <9 0x8>;
@@ -314,7 +314,7 @@
314 serial1: serial@4600 { 314 serial1: serial@4600 {
315 cell-index = <1>; 315 cell-index = <1>;
316 device_type = "serial"; 316 device_type = "serial";
317 compatible = "ns16550"; 317 compatible = "fsl,ns16550", "ns16550";
318 reg = <0x4600 0x100>; 318 reg = <0x4600 0x100>;
319 clock-frequency = <0>; 319 clock-frequency = <0>;
320 interrupts = <10 0x8>; 320 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index f70cf6000839..538fcb927337 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -315,7 +315,7 @@
315 serial0: serial@4500 { 315 serial0: serial@4500 {
316 cell-index = <0>; 316 cell-index = <0>;
317 device_type = "serial"; 317 device_type = "serial";
318 compatible = "ns16550"; 318 compatible = "fsl,ns16550", "ns16550";
319 reg = <0x4500 0x100>; 319 reg = <0x4500 0x100>;
320 clock-frequency = <0>; 320 clock-frequency = <0>;
321 interrupts = <9 0x8>; 321 interrupts = <9 0x8>;
@@ -325,7 +325,7 @@
325 serial1: serial@4600 { 325 serial1: serial@4600 {
326 cell-index = <1>; 326 cell-index = <1>;
327 device_type = "serial"; 327 device_type = "serial";
328 compatible = "ns16550"; 328 compatible = "fsl,ns16550", "ns16550";
329 reg = <0x4600 0x100>; 329 reg = <0x4600 0x100>;
330 clock-frequency = <0>; 330 clock-frequency = <0>;
331 interrupts = <10 0x8>; 331 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 3447eb9f6e88..32333a908f3d 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -321,7 +321,7 @@
321 serial0: serial@4500 { 321 serial0: serial@4500 {
322 cell-index = <0>; 322 cell-index = <0>;
323 device_type = "serial"; 323 device_type = "serial";
324 compatible = "ns16550"; 324 compatible = "fsl,ns16550", "ns16550";
325 reg = <0x4500 0x100>; 325 reg = <0x4500 0x100>;
326 clock-frequency = <0>; 326 clock-frequency = <0>;
327 interrupts = <9 0x8>; 327 interrupts = <9 0x8>;
@@ -331,7 +331,7 @@
331 serial1: serial@4600 { 331 serial1: serial@4600 {
332 cell-index = <1>; 332 cell-index = <1>;
333 device_type = "serial"; 333 device_type = "serial";
334 compatible = "ns16550"; 334 compatible = "fsl,ns16550", "ns16550";
335 reg = <0x4600 0x100>; 335 reg = <0x4600 0x100>;
336 clock-frequency = <0>; 336 clock-frequency = <0>;
337 interrupts = <10 0x8>; 337 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index 645ec51cc6e1..5387092fdfb4 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -313,7 +313,7 @@
313 serial0: serial@4500 { 313 serial0: serial@4500 {
314 cell-index = <0>; 314 cell-index = <0>;
315 device_type = "serial"; 315 device_type = "serial";
316 compatible = "ns16550"; 316 compatible = "fsl,ns16550", "ns16550";
317 reg = <0x4500 0x100>; 317 reg = <0x4500 0x100>;
318 clock-frequency = <0>; 318 clock-frequency = <0>;
319 interrupts = <9 0x8>; 319 interrupts = <9 0x8>;
@@ -323,7 +323,7 @@
323 serial1: serial@4600 { 323 serial1: serial@4600 {
324 cell-index = <1>; 324 cell-index = <1>;
325 device_type = "serial"; 325 device_type = "serial";
326 compatible = "ns16550"; 326 compatible = "fsl,ns16550", "ns16550";
327 reg = <0x4600 0x100>; 327 reg = <0x4600 0x100>;
328 clock-frequency = <0>; 328 clock-frequency = <0>;
329 interrupts = <10 0x8>; 329 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 15560c619b04..46224c2430ff 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -319,7 +319,7 @@
319 serial0: serial@4500 { 319 serial0: serial@4500 {
320 cell-index = <0>; 320 cell-index = <0>;
321 device_type = "serial"; 321 device_type = "serial";
322 compatible = "ns16550"; 322 compatible = "fsl,ns16550", "ns16550";
323 reg = <0x4500 0x100>; 323 reg = <0x4500 0x100>;
324 clock-frequency = <0>; 324 clock-frequency = <0>;
325 interrupts = <9 0x8>; 325 interrupts = <9 0x8>;
@@ -329,7 +329,7 @@
329 serial1: serial@4600 { 329 serial1: serial@4600 {
330 cell-index = <1>; 330 cell-index = <1>;
331 device_type = "serial"; 331 device_type = "serial";
332 compatible = "ns16550"; 332 compatible = "fsl,ns16550", "ns16550";
333 reg = <0x4600 0x100>; 333 reg = <0x4600 0x100>;
334 clock-frequency = <0>; 334 clock-frequency = <0>;
335 interrupts = <10 0x8>; 335 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index a75c10eed269..c15881574fdc 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,403 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@ffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 spi@7000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "fsl,mpc8536-espi";
115 reg = <0x7000 0x1000>;
116 interrupts = <59 0x2>;
117 interrupt-parent = <&mpic>;
118 fsl,espi-num-chipselects = <4>;
119
120 flash@0 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "spansion,s25sl12801";
124 reg = <0>;
125 spi-max-frequency = <40000000>;
126 partition@u-boot {
127 label = "u-boot";
128 reg = <0x00000000 0x00100000>;
129 read-only;
130 };
131 partition@kernel {
132 label = "kernel";
133 reg = <0x00100000 0x00500000>;
134 read-only;
135 };
136 partition@dtb {
137 label = "dtb";
138 reg = <0x00600000 0x00100000>;
139 read-only;
140 };
141 partition@fs {
142 label = "file system";
143 reg = <0x00700000 0x00900000>;
144 };
145 };
146 flash@1 {
147 compatible = "spansion,s25sl12801";
148 reg = <1>;
149 spi-max-frequency = <40000000>;
150 };
151 flash@2 {
152 compatible = "spansion,s25sl12801";
153 reg = <2>;
154 spi-max-frequency = <40000000>;
155 };
156 flash@3 {
157 compatible = "spansion,s25sl12801";
158 reg = <3>;
159 spi-max-frequency = <40000000>;
160 };
161 };
162
163 dma@21300 {
164 #address-cells = <1>;
165 #size-cells = <1>;
166 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
167 reg = <0x21300 4>;
168 ranges = <0 0x21100 0x200>;
169 cell-index = <0>;
170 dma-channel@0 {
171 compatible = "fsl,mpc8536-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x0 0x80>;
174 cell-index = <0>;
175 interrupt-parent = <&mpic>;
176 interrupts = <20 2>;
177 };
178 dma-channel@80 {
179 compatible = "fsl,mpc8536-dma-channel",
180 "fsl,eloplus-dma-channel";
181 reg = <0x80 0x80>;
182 cell-index = <1>;
183 interrupt-parent = <&mpic>;
184 interrupts = <21 2>;
185 };
186 dma-channel@100 {
187 compatible = "fsl,mpc8536-dma-channel",
188 "fsl,eloplus-dma-channel";
189 reg = <0x100 0x80>;
190 cell-index = <2>;
191 interrupt-parent = <&mpic>;
192 interrupts = <22 2>;
193 };
194 dma-channel@180 {
195 compatible = "fsl,mpc8536-dma-channel",
196 "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
203
204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 phy_type = "ulpi";
212 };
213
214 usb@23000 {
215 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
216 reg = <0x23000 0x1000>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 interrupt-parent = <&mpic>;
220 interrupts = <46 0x2>;
221 phy_type = "ulpi";
222 };
223
224 enet0: ethernet@24000 {
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@0 {
247 interrupt-parent = <&mpic>;
248 interrupts = <10 0x1>;
249 reg = <0>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <10 0x1>;
255 reg = <1>;
256 device_type = "ethernet-phy";
257 };
258 tbi0: tbi-phy@11 {
259 reg = <0x11>;
260 device_type = "tbi-phy";
261 };
262 };
263 };
264
265 enet1: ethernet@26000 {
266 #address-cells = <1>;
267 #size-cells = <1>;
268 cell-index = <1>;
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x26000 0x1000>;
273 ranges = <0x0 0x26000 0x1000>;
274 local-mac-address = [ 00 00 00 00 00 00 ];
275 interrupts = <31 2 32 2 33 2>;
276 interrupt-parent = <&mpic>;
277 tbi-handle = <&tbi1>;
278 phy-handle = <&phy0>;
279 phy-connection-type = "rgmii-id";
280
281 mdio@520 {
282 #address-cells = <1>;
283 #size-cells = <0>;
284 compatible = "fsl,gianfar-tbi";
285 reg = <0x520 0x20>;
286
287 tbi1: tbi-phy@11 {
288 reg = <0x11>;
289 device_type = "tbi-phy";
290 };
291 };
292 };
293
294 usb@2b000 {
295 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
296 reg = <0x2b000 0x1000>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 interrupt-parent = <&mpic>;
300 interrupts = <60 0x2>;
301 dr_mode = "peripheral";
302 phy_type = "ulpi";
303 };
304
305 sdhci@2e000 {
306 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
307 reg = <0x2e000 0x1000>;
308 interrupts = <72 0x2>;
309 interrupt-parent = <&mpic>;
310 clock-frequency = <250000000>;
311 };
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 0x2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 0x2>;
330 interrupt-parent = <&mpic>;
331 };
332
333 crypto@30000 {
334 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
335 "fsl,sec2.1", "fsl,sec2.0";
336 reg = <0x30000 0x10000>;
337 interrupts = <45 2 58 2>;
338 interrupt-parent = <&mpic>;
339 fsl,num-channels = <4>;
340 fsl,channel-fifo-len = <24>;
341 fsl,exec-units-mask = <0x9fe>;
342 fsl,descriptor-types-mask = <0x3ab0ebf>;
343 };
344
345 sata@18000 {
346 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
347 reg = <0x18000 0x1000>;
348 cell-index = <1>;
349 interrupts = <74 0x2>;
350 interrupt-parent = <&mpic>;
351 };
352
353 sata@19000 {
354 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
355 reg = <0x19000 0x1000>;
356 cell-index = <2>;
357 interrupts = <41 0x2>;
358 interrupt-parent = <&mpic>;
359 };
360
361 global-utilities@e0000 { //global utilities block
362 compatible = "fsl,mpc8548-guts";
363 reg = <0xe0000 0x1000>;
364 fsl,has-rstcr;
365 };
366
367 mpic: pic@40000 {
368 clock-frequency = <0>;
369 interrupt-controller;
370 #address-cells = <0>;
371 #interrupt-cells = <2>;
372 reg = <0x40000 0x40000>;
373 compatible = "chrp,open-pic";
374 device_type = "open-pic";
375 big-endian;
376 };
377 38
378 msi@41600 { 39 board_soc: soc: soc@ffe00000 {
379 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0 0xffe00000 0x100000>;
380 reg = <0x41600 0x80>;
381 msi-available-ranges = <0 0x100>;
382 interrupts = <
383 0xe0 0
384 0xe1 0
385 0xe2 0
386 0xe3 0
387 0xe4 0
388 0xe5 0
389 0xe6 0
390 0xe7 0>;
391 interrupt-parent = <&mpic>;
392 };
393 }; 41 };
394 42
395 pci0: pci@ffe08000 { 43 pci0: pci@ffe08000 {
396 compatible = "fsl,mpc8540-pci"; 44 reg = <0 0xffe08000 0 0x1000>;
397 device_type = "pci"; 45 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
46 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
398 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
399 interrupt-map = < 49 interrupt-map = <
400 50
401 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
402 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
403 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
404 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
405 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
406
407 interrupt-parent = <&mpic>;
408 interrupts = <24 0x2>;
409 bus-range = <0 0xff>;
410 ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
411 0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
412 clock-frequency = <66666666>;
413 #interrupt-cells = <1>;
414 #size-cells = <2>;
415 #address-cells = <3>;
416 reg = <0 0xffe08000 0 0x1000>;
417 }; 56 };
418 57
419 pci1: pcie@ffe09000 { 58 pci1: pcie@ffe09000 {
420 compatible = "fsl,mpc8548-pcie";
421 device_type = "pci";
422 #interrupt-cells = <1>;
423 #size-cells = <2>;
424 #address-cells = <3>;
425 reg = <0 0xffe09000 0 0x1000>; 59 reg = <0 0xffe09000 0 0x1000>;
426 bus-range = <0 0xff>;
427 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000 60 ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
428 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
429 clock-frequency = <33333333>;
430 interrupt-parent = <&mpic>;
431 interrupts = <25 0x2>;
432 interrupt-map-mask = <0xf800 0 0 7>;
433 interrupt-map = <
434 /* IDSEL 0x0 */
435 0000 0 0 1 &mpic 4 1
436 0000 0 0 2 &mpic 5 1
437 0000 0 0 3 &mpic 6 1
438 0000 0 0 4 &mpic 7 1
439 >;
440 pcie@0 { 62 pcie@0 {
441 reg = <0 0 0 0 0>;
442 #size-cells = <2>;
443 #address-cells = <3>;
444 device_type = "pci";
445 ranges = <0x02000000 0 0x98000000 63 ranges = <0x02000000 0 0x98000000
446 0x02000000 0 0x98000000 64 0x02000000 0 0x98000000
447 0 0x08000000 65 0 0x08000000
@@ -453,31 +71,10 @@
453 }; 71 };
454 72
455 pci2: pcie@ffe0a000 { 73 pci2: pcie@ffe0a000 {
456 compatible = "fsl,mpc8548-pcie";
457 device_type = "pci";
458 #interrupt-cells = <1>;
459 #size-cells = <2>;
460 #address-cells = <3>;
461 reg = <0 0xffe0a000 0 0x1000>; 74 reg = <0 0xffe0a000 0 0x1000>;
462 bus-range = <0 0xff>;
463 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000 75 ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
464 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
465 clock-frequency = <33333333>;
466 interrupt-parent = <&mpic>;
467 interrupts = <26 0x2>;
468 interrupt-map-mask = <0xf800 0 0 7>;
469 interrupt-map = <
470 /* IDSEL 0x0 */
471 0000 0 0 1 &mpic 0 1
472 0000 0 0 2 &mpic 1 1
473 0000 0 0 3 &mpic 2 1
474 0000 0 0 4 &mpic 3 1
475 >;
476 pcie@0 { 77 pcie@0 {
477 reg = <0 0 0 0 0>;
478 #size-cells = <2>;
479 #address-cells = <3>;
480 device_type = "pci";
481 ranges = <0x02000000 0 0x90000000 78 ranges = <0x02000000 0 0x90000000
482 0x02000000 0 0x90000000 79 0x02000000 0 0x90000000
483 0 0x08000000 80 0 0x08000000
@@ -489,32 +86,10 @@
489 }; 86 };
490 87
491 pci3: pcie@ffe0b000 { 88 pci3: pcie@ffe0b000 {
492 compatible = "fsl,mpc8548-pcie";
493 device_type = "pci";
494 #interrupt-cells = <1>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 reg = <0 0xffe0b000 0 0x1000>; 89 reg = <0 0xffe0b000 0 0x1000>;
498 bus-range = <0 0xff>;
499 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000 90 ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
500 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
501 clock-frequency = <33333333>;
502 interrupt-parent = <&mpic>;
503 interrupts = <27 0x2>;
504 interrupt-map-mask = <0xf800 0 0 7>;
505 interrupt-map = <
506 /* IDSEL 0x0 */
507 0000 0 0 1 &mpic 8 1
508 0000 0 0 2 &mpic 9 1
509 0000 0 0 3 &mpic 10 1
510 0000 0 0 4 &mpic 11 1
511 >;
512
513 pcie@0 { 92 pcie@0 {
514 reg = <0 0 0 0 0>;
515 #size-cells = <2>;
516 #address-cells = <3>;
517 device_type = "pci";
518 ranges = <0x02000000 0 0xa0000000 93 ranges = <0x02000000 0 0xa0000000
519 0x02000000 0 0xa0000000 94 0x02000000 0 0xa0000000
520 0 0x20000000 95 0 0x20000000
@@ -525,3 +100,6 @@
525 }; 100 };
526 }; 101 };
527}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
new file mode 100644
index 000000000000..1462e4cf49d7
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -0,0 +1,141 @@
1/*
2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_soc {
36 i2c@3100 {
37 rtc@68 {
38 compatible = "dallas,ds3232";
39 reg = <0x68>;
40 interrupts = <0 0x1 0 0>;
41 };
42 };
43
44 spi@7000 {
45 flash@0 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "spansion,s25sl12801";
49 reg = <0>;
50 spi-max-frequency = <40000000>;
51 partition@u-boot {
52 label = "u-boot";
53 reg = <0x00000000 0x00100000>;
54 read-only;
55 };
56 partition@kernel {
57 label = "kernel";
58 reg = <0x00100000 0x00500000>;
59 read-only;
60 };
61 partition@dtb {
62 label = "dtb";
63 reg = <0x00600000 0x00100000>;
64 read-only;
65 };
66 partition@fs {
67 label = "file system";
68 reg = <0x00700000 0x00900000>;
69 };
70 };
71 flash@1 {
72 compatible = "spansion,s25sl12801";
73 reg = <1>;
74 spi-max-frequency = <40000000>;
75 };
76 flash@2 {
77 compatible = "spansion,s25sl12801";
78 reg = <2>;
79 spi-max-frequency = <40000000>;
80 };
81 flash@3 {
82 compatible = "spansion,s25sl12801";
83 reg = <3>;
84 spi-max-frequency = <40000000>;
85 };
86 };
87
88 usb@22000 {
89 phy_type = "ulpi";
90 };
91
92 usb@23000 {
93 phy_type = "ulpi";
94 };
95
96 enet0: ethernet@24000 {
97 tbi-handle = <&tbi0>;
98 phy-handle = <&phy1>;
99 phy-connection-type = "rgmii-id";
100 };
101
102 mdio@24520 {
103 phy0: ethernet-phy@0 {
104 interrupts = <10 0x1 0 0>;
105 reg = <0>;
106 device_type = "ethernet-phy";
107 };
108 phy1: ethernet-phy@1 {
109 interrupts = <10 0x1 0 0>;
110 reg = <1>;
111 device_type = "ethernet-phy";
112 };
113 tbi0: tbi-phy@11 {
114 reg = <0x11>;
115 device_type = "tbi-phy";
116 };
117 };
118
119 enet2: ethernet@26000 {
120 tbi-handle = <&tbi1>;
121 phy-handle = <&phy0>;
122 phy-connection-type = "rgmii-id";
123 };
124
125 mdio@26520 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "fsl,gianfar-tbi";
129 reg = <0x26520 0x20>;
130
131 tbi1: tbi-phy@11 {
132 reg = <0x11>;
133 device_type = "tbi-phy";
134 };
135 };
136
137 usb@2b000 {
138 dr_mode = "peripheral";
139 phy_type = "ulpi";
140 };
141};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index d95b26021e62..8f4b929b1d1d 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8536 DS Device Tree Source 2 * MPC8536DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc. 4 * Copyright 2008-2009 Freescale Semiconductor, Inc.
5 * 5 *
@@ -9,24 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8536si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,mpc8536ds"; 15 model = "fsl,mpc8536ds";
16 compatible = "fsl,mpc8536ds"; 16 compatible = "fsl,mpc8536ds";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 pci3 = &pci3;
29 };
30 17
31 cpus { 18 cpus {
32 #cpus = <1>; 19 #cpus = <1>;
@@ -45,351 +32,34 @@
45 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
46 }; 33 };
47 34
48 soc@fffe00000 { 35 lbc: localbus@ffe05000 {
49 #address-cells = <1>; 36 reg = <0 0xffe05000 0 0x1000>;
50 #size-cells = <1>; 37 };
51 device_type = "soc";
52 compatible = "simple-bus";
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 bus-frequency = <0>; // Filled out by uboot.
55
56 ecm-law@0 {
57 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>;
60 };
61
62 ecm@1000 {
63 compatible = "fsl,mpc8536-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>;
65 interrupts = <17 2>;
66 interrupt-parent = <&mpic>;
67 };
68
69 memory-controller@2000 {
70 compatible = "fsl,mpc8536-memory-controller";
71 reg = <0x2000 0x1000>;
72 interrupt-parent = <&mpic>;
73 interrupts = <18 0x2>;
74 };
75
76 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8536-l2-cache-controller";
78 reg = <0x20000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <16 0x2>;
81 };
82
83 i2c@3000 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <0>;
87 compatible = "fsl-i2c";
88 reg = <0x3000 0x100>;
89 interrupts = <43 0x2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 i2c@3100 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 cell-index = <1>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <43 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 rtc@68 {
104 compatible = "dallas,ds3232";
105 reg = <0x68>;
106 interrupts = <0 0x1>;
107 interrupt-parent = <&mpic>;
108 };
109 };
110
111 dma@21300 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
115 reg = <0x21300 4>;
116 ranges = <0 0x21100 0x200>;
117 cell-index = <0>;
118 dma-channel@0 {
119 compatible = "fsl,mpc8536-dma-channel",
120 "fsl,eloplus-dma-channel";
121 reg = <0x0 0x80>;
122 cell-index = <0>;
123 interrupt-parent = <&mpic>;
124 interrupts = <20 2>;
125 };
126 dma-channel@80 {
127 compatible = "fsl,mpc8536-dma-channel",
128 "fsl,eloplus-dma-channel";
129 reg = <0x80 0x80>;
130 cell-index = <1>;
131 interrupt-parent = <&mpic>;
132 interrupts = <21 2>;
133 };
134 dma-channel@100 {
135 compatible = "fsl,mpc8536-dma-channel",
136 "fsl,eloplus-dma-channel";
137 reg = <0x100 0x80>;
138 cell-index = <2>;
139 interrupt-parent = <&mpic>;
140 interrupts = <22 2>;
141 };
142 dma-channel@180 {
143 compatible = "fsl,mpc8536-dma-channel",
144 "fsl,eloplus-dma-channel";
145 reg = <0x180 0x80>;
146 cell-index = <3>;
147 interrupt-parent = <&mpic>;
148 interrupts = <23 2>;
149 };
150 };
151
152 usb@22000 {
153 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
154 reg = <0x22000 0x1000>;
155 #address-cells = <1>;
156 #size-cells = <0>;
157 interrupt-parent = <&mpic>;
158 interrupts = <28 0x2>;
159 phy_type = "ulpi";
160 };
161
162 usb@23000 {
163 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
164 reg = <0x23000 0x1000>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 interrupt-parent = <&mpic>;
168 interrupts = <46 0x2>;
169 phy_type = "ulpi";
170 };
171
172 enet0: ethernet@24000 {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 cell-index = <0>;
176 device_type = "network";
177 model = "eTSEC";
178 compatible = "gianfar";
179 reg = <0x24000 0x1000>;
180 ranges = <0x0 0x24000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <29 2 30 2 34 2>;
183 interrupt-parent = <&mpic>;
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy1>;
186 phy-connection-type = "rgmii-id";
187
188 mdio@520 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,gianfar-mdio";
192 reg = <0x520 0x20>;
193
194 phy0: ethernet-phy@0 {
195 interrupt-parent = <&mpic>;
196 interrupts = <10 0x1>;
197 reg = <0>;
198 device_type = "ethernet-phy";
199 };
200 phy1: ethernet-phy@1 {
201 interrupt-parent = <&mpic>;
202 interrupts = <10 0x1>;
203 reg = <1>;
204 device_type = "ethernet-phy";
205 };
206 tbi0: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211 };
212
213 enet1: ethernet@26000 {
214 #address-cells = <1>;
215 #size-cells = <1>;
216 cell-index = <1>;
217 device_type = "network";
218 model = "eTSEC";
219 compatible = "gianfar";
220 reg = <0x26000 0x1000>;
221 ranges = <0x0 0x26000 0x1000>;
222 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <31 2 32 2 33 2>;
224 interrupt-parent = <&mpic>;
225 tbi-handle = <&tbi1>;
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228
229 mdio@520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-tbi";
233 reg = <0x520 0x20>;
234
235 tbi1: tbi-phy@11 {
236 reg = <0x11>;
237 device_type = "tbi-phy";
238 };
239 };
240 };
241
242 usb@2b000 {
243 compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
244 reg = <0x2b000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupt-parent = <&mpic>;
248 interrupts = <60 0x2>;
249 dr_mode = "peripheral";
250 phy_type = "ulpi";
251 };
252
253 sdhci@2e000 {
254 compatible = "fsl,mpc8536-esdhc", "fsl,esdhc";
255 reg = <0x2e000 0x1000>;
256 interrupts = <72 0x2>;
257 interrupt-parent = <&mpic>;
258 clock-frequency = <250000000>;
259 };
260
261 serial0: serial@4500 {
262 cell-index = <0>;
263 device_type = "serial";
264 compatible = "ns16550";
265 reg = <0x4500 0x100>;
266 clock-frequency = <0>;
267 interrupts = <42 0x2>;
268 interrupt-parent = <&mpic>;
269 };
270
271 serial1: serial@4600 {
272 cell-index = <1>;
273 device_type = "serial";
274 compatible = "ns16550";
275 reg = <0x4600 0x100>;
276 clock-frequency = <0>;
277 interrupts = <42 0x2>;
278 interrupt-parent = <&mpic>;
279 };
280
281 crypto@30000 {
282 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
283 "fsl,sec2.1", "fsl,sec2.0";
284 reg = <0x30000 0x10000>;
285 interrupts = <45 2 58 2>;
286 interrupt-parent = <&mpic>;
287 fsl,num-channels = <4>;
288 fsl,channel-fifo-len = <24>;
289 fsl,exec-units-mask = <0x9fe>;
290 fsl,descriptor-types-mask = <0x3ab0ebf>;
291 };
292
293 sata@18000 {
294 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
295 reg = <0x18000 0x1000>;
296 cell-index = <1>;
297 interrupts = <74 0x2>;
298 interrupt-parent = <&mpic>;
299 };
300
301 sata@19000 {
302 compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
303 reg = <0x19000 0x1000>;
304 cell-index = <2>;
305 interrupts = <41 0x2>;
306 interrupt-parent = <&mpic>;
307 };
308
309 global-utilities@e0000 { //global utilities block
310 compatible = "fsl,mpc8548-guts";
311 reg = <0xe0000 0x1000>;
312 fsl,has-rstcr;
313 };
314
315 mpic: pic@40000 {
316 clock-frequency = <0>;
317 interrupt-controller;
318 #address-cells = <0>;
319 #interrupt-cells = <2>;
320 reg = <0x40000 0x40000>;
321 compatible = "chrp,open-pic";
322 device_type = "open-pic";
323 big-endian;
324 };
325 38
326 msi@41600 { 39 board_soc: soc: soc@fffe00000 {
327 compatible = "fsl,mpc8536-msi", "fsl,mpic-msi"; 40 ranges = <0x0 0xf 0xffe00000 0x100000>;
328 reg = <0x41600 0x80>;
329 msi-available-ranges = <0 0x100>;
330 interrupts = <
331 0xe0 0
332 0xe1 0
333 0xe2 0
334 0xe3 0
335 0xe4 0
336 0xe5 0
337 0xe6 0
338 0xe7 0>;
339 interrupt-parent = <&mpic>;
340 };
341 }; 41 };
342 42
343 pci0: pci@fffe08000 { 43 pci0: pci@ffe08000 {
344 compatible = "fsl,mpc8540-pci"; 44 reg = <0xf 0xffe08000 0 0x1000>;
345 device_type = "pci"; 45 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
46 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
47 clock-frequency = <66666666>;
346 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 48 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-map = < 49 interrupt-map = <
348 50
349 /* IDSEL 0x11 J17 Slot 1 */ 51 /* IDSEL 0x11 J17 Slot 1 */
350 0x8800 0 0 1 &mpic 1 1 52 0x8800 0 0 1 &mpic 1 1 0 0
351 0x8800 0 0 2 &mpic 2 1 53 0x8800 0 0 2 &mpic 2 1 0 0
352 0x8800 0 0 3 &mpic 3 1 54 0x8800 0 0 3 &mpic 3 1 0 0
353 0x8800 0 0 4 &mpic 4 1>; 55 0x8800 0 0 4 &mpic 4 1 0 0>;
354
355 interrupt-parent = <&mpic>;
356 interrupts = <24 0x2>;
357 bus-range = <0 0xff>;
358 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
359 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
360 clock-frequency = <66666666>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <0xf 0xffe08000 0 0x1000>;
365 }; 56 };
366 57
367 pci1: pcie@fffe09000 { 58 pci1: pcie@ffe09000 {
368 compatible = "fsl,mpc8548-pcie";
369 device_type = "pci";
370 #interrupt-cells = <1>;
371 #size-cells = <2>;
372 #address-cells = <3>;
373 reg = <0xf 0xffe09000 0 0x1000>; 59 reg = <0xf 0xffe09000 0 0x1000>;
374 bus-range = <0 0xff>;
375 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000 60 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
376 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>; 61 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
377 clock-frequency = <33333333>;
378 interrupt-parent = <&mpic>;
379 interrupts = <25 0x2>;
380 interrupt-map-mask = <0xf800 0 0 7>;
381 interrupt-map = <
382 /* IDSEL 0x0 */
383 0000 0 0 1 &mpic 4 1
384 0000 0 0 2 &mpic 5 1
385 0000 0 0 3 &mpic 6 1
386 0000 0 0 4 &mpic 7 1
387 >;
388 pcie@0 { 62 pcie@0 {
389 reg = <0 0 0 0 0>;
390 #size-cells = <2>;
391 #address-cells = <3>;
392 device_type = "pci";
393 ranges = <0x02000000 0 0xf8000000 63 ranges = <0x02000000 0 0xf8000000
394 0x02000000 0 0xf8000000 64 0x02000000 0 0xf8000000
395 0 0x08000000 65 0 0x08000000
@@ -401,31 +71,10 @@
401 }; 71 };
402 72
403 pci2: pcie@fffe0a000 { 73 pci2: pcie@fffe0a000 {
404 compatible = "fsl,mpc8548-pcie";
405 device_type = "pci";
406 #interrupt-cells = <1>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 reg = <0xf 0xffe0a000 0 0x1000>; 74 reg = <0xf 0xffe0a000 0 0x1000>;
410 bus-range = <0 0xff>;
411 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000 75 ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
412 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>; 76 0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
413 clock-frequency = <33333333>;
414 interrupt-parent = <&mpic>;
415 interrupts = <26 0x2>;
416 interrupt-map-mask = <0xf800 0 0 7>;
417 interrupt-map = <
418 /* IDSEL 0x0 */
419 0000 0 0 1 &mpic 0 1
420 0000 0 0 2 &mpic 1 1
421 0000 0 0 3 &mpic 2 1
422 0000 0 0 4 &mpic 3 1
423 >;
424 pcie@0 { 77 pcie@0 {
425 reg = <0 0 0 0 0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x02000000 0 0xf8000000 78 ranges = <0x02000000 0 0xf8000000
430 0x02000000 0 0xf8000000 79 0x02000000 0 0xf8000000
431 0 0x08000000 80 0 0x08000000
@@ -437,32 +86,10 @@
437 }; 86 };
438 87
439 pci3: pcie@fffe0b000 { 88 pci3: pcie@fffe0b000 {
440 compatible = "fsl,mpc8548-pcie";
441 device_type = "pci";
442 #interrupt-cells = <1>;
443 #size-cells = <2>;
444 #address-cells = <3>;
445 reg = <0xf 0xffe0b000 0 0x1000>; 89 reg = <0xf 0xffe0b000 0 0x1000>;
446 bus-range = <0 0xff>;
447 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000 90 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
448 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>; 91 0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
449 clock-frequency = <33333333>;
450 interrupt-parent = <&mpic>;
451 interrupts = <27 0x2>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <
454 /* IDSEL 0x0 */
455 0000 0 0 1 &mpic 8 1
456 0000 0 0 2 &mpic 9 1
457 0000 0 0 3 &mpic 10 1
458 0000 0 0 4 &mpic 11 1
459 >;
460
461 pcie@0 { 92 pcie@0 {
462 reg = <0 0 0 0 0>;
463 #size-cells = <2>;
464 #address-cells = <3>;
465 device_type = "pci";
466 ranges = <0x02000000 0 0xe0000000 93 ranges = <0x02000000 0 0xe0000000
467 0x02000000 0 0xe0000000 94 0x02000000 0 0xe0000000
468 0 0x20000000 95 0 0x20000000
@@ -473,3 +100,6 @@
473 }; 100 };
474 }; 101 };
475}; 102};
103
104/include/ "fsl/mpc8536si-post.dtsi"
105/include/ "mpc8536ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8540ads.dts b/arch/powerpc/boot/dts/mpc8540ads.dts
index 8d1bf0fd9268..f99fb110c97f 100644
--- a/arch/powerpc/boot/dts/mpc8540ads.dts
+++ b/arch/powerpc/boot/dts/mpc8540ads.dts
@@ -243,7 +243,7 @@
243 serial0: serial@4500 { 243 serial0: serial@4500 {
244 cell-index = <0>; 244 cell-index = <0>;
245 device_type = "serial"; 245 device_type = "serial";
246 compatible = "ns16550"; 246 compatible = "fsl,ns16550", "ns16550";
247 reg = <0x4500 0x100>; // reg base, size 247 reg = <0x4500 0x100>; // reg base, size
248 clock-frequency = <0>; // should we fill in in uboot? 248 clock-frequency = <0>; // should we fill in in uboot?
249 interrupts = <42 2>; 249 interrupts = <42 2>;
@@ -253,7 +253,7 @@
253 serial1: serial@4600 { 253 serial1: serial@4600 {
254 cell-index = <1>; 254 cell-index = <1>;
255 device_type = "serial"; 255 device_type = "serial";
256 compatible = "ns16550"; 256 compatible = "fsl,ns16550", "ns16550";
257 reg = <0x4600 0x100>; // reg base, size 257 reg = <0x4600 0x100>; // reg base, size
258 clock-frequency = <0>; // should we fill in in uboot? 258 clock-frequency = <0>; // should we fill in in uboot?
259 interrupts = <42 2>; 259 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts
index 87ff96549fac..0f5e93912799 100644
--- a/arch/powerpc/boot/dts/mpc8541cds.dts
+++ b/arch/powerpc/boot/dts/mpc8541cds.dts
@@ -209,7 +209,7 @@
209 serial0: serial@4500 { 209 serial0: serial@4500 {
210 cell-index = <0>; 210 cell-index = <0>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4500 0x100>; // reg base, size 213 reg = <0x4500 0x100>; // reg base, size
214 clock-frequency = <0>; // should we fill in in uboot? 214 clock-frequency = <0>; // should we fill in in uboot?
215 interrupts = <42 2>; 215 interrupts = <42 2>;
@@ -219,7 +219,7 @@
219 serial1: serial@4600 { 219 serial1: serial@4600 {
220 cell-index = <1>; 220 cell-index = <1>;
221 device_type = "serial"; 221 device_type = "serial";
222 compatible = "ns16550"; 222 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4600 0x100>; // reg base, size 223 reg = <0x4600 0x100>; // reg base, size
224 clock-frequency = <0>; // should we fill in in uboot? 224 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 225 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dts b/arch/powerpc/boot/dts/mpc8544ds.dts
index d793968743c9..e934987e882b 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dts
+++ b/arch/powerpc/boot/dts/mpc8544ds.dts
@@ -9,339 +9,52 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8544si-pre.dtsi"
13
13/ { 14/ {
14 model = "MPC8544DS"; 15 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS"; 16 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8544@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
45 };
46 };
47 17
48 memory { 18 memory {
49 device_type = "memory"; 19 device_type = "memory";
50 reg = <0x0 0x0>; // Filled by U-Boot 20 reg = <0 0 0 0>; // Filled by U-Boot
51 }; 21 };
52 22
53 soc8544@e0000000 { 23 lbc: localbus@e0005000 {
54 #address-cells = <1>; 24 reg = <0 0xe0005000 0 0x1000>;
55 #size-cells = <1>; 25 };
56 device_type = "soc";
57 compatible = "simple-bus";
58
59 ranges = <0x0 0xe0000000 0x100000>;
60 bus-frequency = <0>; // Filled out by uboot.
61
62 ecm-law@0 {
63 compatible = "fsl,ecm-law";
64 reg = <0x0 0x1000>;
65 fsl,num-laws = <10>;
66 };
67
68 ecm@1000 {
69 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
70 reg = <0x1000 0x1000>;
71 interrupts = <17 2>;
72 interrupt-parent = <&mpic>;
73 };
74
75 memory-controller@2000 {
76 compatible = "fsl,mpc8544-memory-controller";
77 reg = <0x2000 0x1000>;
78 interrupt-parent = <&mpic>;
79 interrupts = <18 2>;
80 };
81
82 L2: l2-cache-controller@20000 {
83 compatible = "fsl,mpc8544-l2-cache-controller";
84 reg = <0x20000 0x1000>;
85 cache-line-size = <32>; // 32 bytes
86 cache-size = <0x40000>; // L2, 256K
87 interrupt-parent = <&mpic>;
88 interrupts = <16 2>;
89 };
90
91 i2c@3000 {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 cell-index = <0>;
95 compatible = "fsl-i2c";
96 reg = <0x3000 0x100>;
97 interrupts = <43 2>;
98 interrupt-parent = <&mpic>;
99 dfsrr;
100 };
101
102 i2c@3100 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 cell-index = <1>;
106 compatible = "fsl-i2c";
107 reg = <0x3100 0x100>;
108 interrupts = <43 2>;
109 interrupt-parent = <&mpic>;
110 dfsrr;
111 };
112
113 dma@21300 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
117 reg = <0x21300 0x4>;
118 ranges = <0x0 0x21100 0x200>;
119 cell-index = <0>;
120 dma-channel@0 {
121 compatible = "fsl,mpc8544-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x0 0x80>;
124 cell-index = <0>;
125 interrupt-parent = <&mpic>;
126 interrupts = <20 2>;
127 };
128 dma-channel@80 {
129 compatible = "fsl,mpc8544-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x80 0x80>;
132 cell-index = <1>;
133 interrupt-parent = <&mpic>;
134 interrupts = <21 2>;
135 };
136 dma-channel@100 {
137 compatible = "fsl,mpc8544-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x100 0x80>;
140 cell-index = <2>;
141 interrupt-parent = <&mpic>;
142 interrupts = <22 2>;
143 };
144 dma-channel@180 {
145 compatible = "fsl,mpc8544-dma-channel",
146 "fsl,eloplus-dma-channel";
147 reg = <0x180 0x80>;
148 cell-index = <3>;
149 interrupt-parent = <&mpic>;
150 interrupts = <23 2>;
151 };
152 };
153
154 enet0: ethernet@24000 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 cell-index = <0>;
158 device_type = "network";
159 model = "TSEC";
160 compatible = "gianfar";
161 reg = <0x24000 0x1000>;
162 ranges = <0x0 0x24000 0x1000>;
163 local-mac-address = [ 00 00 00 00 00 00 ];
164 interrupts = <29 2 30 2 34 2>;
165 interrupt-parent = <&mpic>;
166 phy-handle = <&phy0>;
167 tbi-handle = <&tbi0>;
168 phy-connection-type = "rgmii-id";
169
170 mdio@520 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 compatible = "fsl,gianfar-mdio";
174 reg = <0x520 0x20>;
175
176 phy0: ethernet-phy@0 {
177 interrupt-parent = <&mpic>;
178 interrupts = <10 1>;
179 reg = <0x0>;
180 device_type = "ethernet-phy";
181 };
182 phy1: ethernet-phy@1 {
183 interrupt-parent = <&mpic>;
184 interrupts = <10 1>;
185 reg = <0x1>;
186 device_type = "ethernet-phy";
187 };
188
189 tbi0: tbi-phy@11 {
190 reg = <0x11>;
191 device_type = "tbi-phy";
192 };
193 };
194 };
195
196 enet1: ethernet@26000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cell-index = <1>;
200 device_type = "network";
201 model = "TSEC";
202 compatible = "gianfar";
203 reg = <0x26000 0x1000>;
204 ranges = <0x0 0x26000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <31 2 32 2 33 2>;
207 interrupt-parent = <&mpic>;
208 phy-handle = <&phy1>;
209 tbi-handle = <&tbi1>;
210 phy-connection-type = "rgmii-id";
211
212 mdio@520 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,gianfar-tbi";
216 reg = <0x520 0x20>;
217
218 tbi1: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 };
223 };
224
225 serial0: serial@4500 {
226 cell-index = <0>;
227 device_type = "serial";
228 compatible = "ns16550";
229 reg = <0x4500 0x100>;
230 clock-frequency = <0>;
231 interrupts = <42 2>;
232 interrupt-parent = <&mpic>;
233 };
234
235 serial1: serial@4600 {
236 cell-index = <1>;
237 device_type = "serial";
238 compatible = "ns16550";
239 reg = <0x4600 0x100>;
240 clock-frequency = <0>;
241 interrupts = <42 2>;
242 interrupt-parent = <&mpic>;
243 };
244
245 global-utilities@e0000 { //global utilities block
246 compatible = "fsl,mpc8548-guts";
247 reg = <0xe0000 0x1000>;
248 fsl,has-rstcr;
249 };
250
251 crypto@30000 {
252 compatible = "fsl,sec2.1", "fsl,sec2.0";
253 reg = <0x30000 0x10000>;
254 interrupts = <45 2>;
255 interrupt-parent = <&mpic>;
256 fsl,num-channels = <4>;
257 fsl,channel-fifo-len = <24>;
258 fsl,exec-units-mask = <0xfe>;
259 fsl,descriptor-types-mask = <0x12b0ebf>;
260 };
261
262 mpic: pic@40000 {
263 interrupt-controller;
264 #address-cells = <0>;
265 #interrupt-cells = <2>;
266 reg = <0x40000 0x40000>;
267 compatible = "chrp,open-pic";
268 device_type = "open-pic";
269 };
270 26
271 msi@41600 { 27 board_soc: soc: soc8544@e0000000 {
272 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi"; 28 ranges = <0x0 0x0 0xe0000000 0x100000>;
273 reg = <0x41600 0x80>;
274 msi-available-ranges = <0 0x100>;
275 interrupts = <
276 0xe0 0
277 0xe1 0
278 0xe2 0
279 0xe3 0
280 0xe4 0
281 0xe5 0
282 0xe6 0
283 0xe7 0>;
284 interrupt-parent = <&mpic>;
285 };
286 }; 29 };
287 30
288 pci0: pci@e0008000 { 31 pci0: pci@e0008000 {
289 compatible = "fsl,mpc8540-pci"; 32 reg = <0 0xe0008000 0 0x1000>;
290 device_type = "pci"; 33 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
34 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
35 clock-frequency = <66666666>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 36 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = < 37 interrupt-map = <
293 38
294 /* IDSEL 0x11 J17 Slot 1 */ 39 /* IDSEL 0x11 J17 Slot 1 */
295 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 40 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
296 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 41 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
297 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 42 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
298 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 43 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
299 44
300 /* IDSEL 0x12 J16 Slot 2 */ 45 /* IDSEL 0x12 J16 Slot 2 */
301 46
302 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 47 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
303 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 48 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
304 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 49 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
305 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>; 50 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
306
307 interrupt-parent = <&mpic>;
308 interrupts = <24 2>;
309 bus-range = <0 255>;
310 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
311 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
312 clock-frequency = <66666666>;
313 #interrupt-cells = <1>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 reg = <0xe0008000 0x1000>;
317 }; 51 };
318 52
319 pci1: pcie@e0009000 { 53 pci1: pcie@e0009000 {
320 compatible = "fsl,mpc8548-pcie"; 54 reg = <0x0 0xe0009000 0x0 0x1000>;
321 device_type = "pci"; 55 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
322 #interrupt-cells = <1>; 56 0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
323 #size-cells = <2>;
324 #address-cells = <3>;
325 reg = <0xe0009000 0x1000>;
326 bus-range = <0 255>;
327 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
328 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
329 clock-frequency = <33333333>;
330 interrupt-parent = <&mpic>;
331 interrupts = <25 2>;
332 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
333 interrupt-map = <
334 /* IDSEL 0x0 */
335 0000 0x0 0x0 0x1 &mpic 0x4 0x1
336 0000 0x0 0x0 0x2 &mpic 0x5 0x1
337 0000 0x0 0x0 0x3 &mpic 0x6 0x1
338 0000 0x0 0x0 0x4 &mpic 0x7 0x1
339 >;
340 pcie@0 { 57 pcie@0 {
341 reg = <0x0 0x0 0x0 0x0 0x0>;
342 #size-cells = <2>;
343 #address-cells = <3>;
344 device_type = "pci";
345 ranges = <0x2000000 0x0 0x80000000 58 ranges = <0x2000000 0x0 0x80000000
346 0x2000000 0x0 0x80000000 59 0x2000000 0x0 0x80000000
347 0x0 0x20000000 60 0x0 0x20000000
@@ -353,31 +66,10 @@
353 }; 66 };
354 67
355 pci2: pcie@e000a000 { 68 pci2: pcie@e000a000 {
356 compatible = "fsl,mpc8548-pcie"; 69 reg = <0x0 0xe000a000 0x0 0x1000>;
357 device_type = "pci"; 70 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
358 #interrupt-cells = <1>; 71 0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
359 #size-cells = <2>;
360 #address-cells = <3>;
361 reg = <0xe000a000 0x1000>;
362 bus-range = <0 255>;
363 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
364 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <26 2>;
368 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
369 interrupt-map = <
370 /* IDSEL 0x0 */
371 0000 0x0 0x0 0x1 &mpic 0x0 0x1
372 0000 0x0 0x0 0x2 &mpic 0x1 0x1
373 0000 0x0 0x0 0x3 &mpic 0x2 0x1
374 0000 0x0 0x0 0x4 &mpic 0x3 0x1
375 >;
376 pcie@0 { 72 pcie@0 {
377 reg = <0x0 0x0 0x0 0x0 0x0>;
378 #size-cells = <2>;
379 #address-cells = <3>;
380 device_type = "pci";
381 ranges = <0x2000000 0x0 0xa0000000 73 ranges = <0x2000000 0x0 0xa0000000
382 0x2000000 0x0 0xa0000000 74 0x2000000 0x0 0xa0000000
383 0x0 0x10000000 75 0x0 0x10000000
@@ -388,44 +80,11 @@
388 }; 80 };
389 }; 81 };
390 82
391 pci3: pcie@e000b000 { 83 board_pci3: pci3: pcie@e000b000 {
392 compatible = "fsl,mpc8548-pcie"; 84 reg = <0x0 0xe000b000 0x0 0x1000>;
393 device_type = "pci"; 85 ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
394 #interrupt-cells = <1>; 86 0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 reg = <0xe000b000 0x1000>;
398 bus-range = <0 255>;
399 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
400 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
401 clock-frequency = <33333333>;
402 interrupt-parent = <&mpic>;
403 interrupts = <27 2>;
404 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
405 interrupt-map = <
406 // IDSEL 0x1c USB
407 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
408 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
409 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
410 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
411
412 // IDSEL 0x1d Audio
413 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
414
415 // IDSEL 0x1e Legacy
416 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
417 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
418
419 // IDSEL 0x1f IDE/SATA
420 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
421 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
422 >;
423
424 pcie@0 { 87 pcie@0 {
425 reg = <0x0 0x0 0x0 0x0 0x0>;
426 #size-cells = <2>;
427 #address-cells = <3>;
428 device_type = "pci";
429 ranges = <0x2000000 0x0 0xb0000000 88 ranges = <0x2000000 0x0 0xb0000000
430 0x2000000 0x0 0xb0000000 89 0x2000000 0x0 0xb0000000
431 0x0 0x100000 90 0x0 0x100000
@@ -433,70 +92,14 @@
433 0x1000000 0x0 0x0 92 0x1000000 0x0 0x0
434 0x1000000 0x0 0x0 93 0x1000000 0x0 0x0
435 0x0 0x100000>; 94 0x0 0x100000>;
436
437 uli1575@0 {
438 reg = <0x0 0x0 0x0 0x0 0x0>;
439 #size-cells = <2>;
440 #address-cells = <3>;
441 ranges = <0x2000000 0x0 0xb0000000
442 0x2000000 0x0 0xb0000000
443 0x0 0x100000
444
445 0x1000000 0x0 0x0
446 0x1000000 0x0 0x0
447 0x0 0x100000>;
448 isa@1e {
449 device_type = "isa";
450 #interrupt-cells = <2>;
451 #size-cells = <1>;
452 #address-cells = <2>;
453 reg = <0xf000 0x0 0x0 0x0 0x0>;
454 ranges = <0x1 0x0
455 0x1000000 0x0 0x0
456 0x1000>;
457 interrupt-parent = <&i8259>;
458
459 i8259: interrupt-controller@20 {
460 reg = <0x1 0x20 0x2
461 0x1 0xa0 0x2
462 0x1 0x4d0 0x2>;
463 interrupt-controller;
464 device_type = "interrupt-controller";
465 #address-cells = <0>;
466 #interrupt-cells = <2>;
467 compatible = "chrp,iic";
468 interrupts = <9 2>;
469 interrupt-parent = <&mpic>;
470 };
471
472 i8042@60 {
473 #size-cells = <0>;
474 #address-cells = <1>;
475 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
476 interrupts = <1 3 12 3>;
477 interrupt-parent = <&i8259>;
478
479 keyboard@0 {
480 reg = <0x0>;
481 compatible = "pnpPNP,303";
482 };
483
484 mouse@1 {
485 reg = <0x1>;
486 compatible = "pnpPNP,f03";
487 };
488 };
489
490 rtc@70 {
491 compatible = "pnpPNP,b00";
492 reg = <0x1 0x70 0x2>;
493 };
494
495 gpio@400 {
496 reg = <0x1 0x400 0x80>;
497 };
498 };
499 };
500 }; 95 };
501 }; 96 };
502}; 97};
98
99/*
100 * mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
101 * for interrupt-map & interrupt-map-mask
102 */
103
104/include/ "fsl/mpc8544si-post.dtsi"
105/include/ "mpc8544ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
new file mode 100644
index 000000000000..270f64b90f4e
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -0,0 +1,161 @@
1/*
2 * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_soc {
36 enet0: ethernet@24000 {
37 phy-handle = <&phy0>;
38 tbi-handle = <&tbi0>;
39 phy-connection-type = "rgmii-id";
40 };
41
42 mdio@24520 {
43 phy0: ethernet-phy@0 {
44 interrupts = <10 1 0 0>;
45 reg = <0x0>;
46 device_type = "ethernet-phy";
47 };
48 phy1: ethernet-phy@1 {
49 interrupts = <10 1 0 0>;
50 reg = <0x1>;
51 device_type = "ethernet-phy";
52 };
53
54 tbi0: tbi-phy@11 {
55 reg = <0x11>;
56 device_type = "tbi-phy";
57 };
58 };
59
60 enet2: ethernet@26000 {
61 phy-handle = <&phy1>;
62 tbi-handle = <&tbi1>;
63 phy-connection-type = "rgmii-id";
64 };
65
66 mdio@26520 {
67 tbi1: tbi-phy@11 {
68 reg = <0x11>;
69 device_type = "tbi-phy";
70 };
71 };
72};
73
74&board_pci3 {
75 pcie@0 {
76 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
77 interrupt-map = <
78 // IDSEL 0x1c USB
79 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
80 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
81 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
82 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
83
84 // IDSEL 0x1d Audio
85 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
86
87 // IDSEL 0x1e Legacy
88 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
89 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
90
91 // IDSEL 0x1f IDE/SATA
92 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
93 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
94 >;
95
96
97 uli1575@0 {
98 reg = <0x0 0x0 0x0 0x0 0x0>;
99 #size-cells = <2>;
100 #address-cells = <3>;
101 ranges = <0x2000000 0x0 0xb0000000
102 0x2000000 0x0 0xb0000000
103 0x0 0x100000
104
105 0x1000000 0x0 0x0
106 0x1000000 0x0 0x0
107 0x0 0x100000>;
108 isa@1e {
109 device_type = "isa";
110 #interrupt-cells = <2>;
111 #size-cells = <1>;
112 #address-cells = <2>;
113 reg = <0xf000 0x0 0x0 0x0 0x0>;
114 ranges = <0x1 0x0 0x1000000 0x0 0x0
115 0x1000>;
116 interrupt-parent = <&i8259>;
117
118 i8259: interrupt-controller@20 {
119 reg = <0x1 0x20 0x2
120 0x1 0xa0 0x2
121 0x1 0x4d0 0x2>;
122 interrupt-controller;
123 device_type = "interrupt-controller";
124 #address-cells = <0>;
125 #interrupt-cells = <2>;
126 compatible = "chrp,iic";
127 interrupts = <9 2 0 0>;
128 interrupt-parent = <&mpic>;
129 };
130
131 i8042@60 {
132 #size-cells = <0>;
133 #address-cells = <1>;
134 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
135 interrupts = <1 3 12 3>;
136 interrupt-parent =
137 <&i8259>;
138
139 keyboard@0 {
140 reg = <0x0>;
141 compatible = "pnpPNP,303";
142 };
143
144 mouse@1 {
145 reg = <0x1>;
146 compatible = "pnpPNP,f03";
147 };
148 };
149
150 rtc@70 {
151 compatible = "pnpPNP,b00";
152 reg = <0x1 0x70 0x2>;
153 };
154
155 gpio@400 {
156 reg = <0x1 0x400 0x80>;
157 };
158 };
159 };
160 };
161};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index a17a5572fb73..07b8dae0f46e 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -9,13 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8548si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8548CDS"; 15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS"; 16 compatible = "MPC8548CDS", "MPC85xxCDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -29,76 +27,19 @@
29 pci2 = &pci2; 27 pci2 = &pci2;
30 }; 28 };
31 29
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8548@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // 33 MHz, from uboot
44 bus-frequency = <0>; // 166 MHz
45 clock-frequency = <0>; // 825 MHz, from uboot
46 next-level-cache = <&L2>;
47 };
48 };
49
50 memory { 30 memory {
51 device_type = "memory"; 31 device_type = "memory";
52 reg = <0x0 0x8000000>; // 128M at 0x0 32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
53 }; 33 };
54 34
55 soc8548@e0000000 { 35 lbc: localbus@e0005000 {
56 #address-cells = <1>; 36 reg = <0 0xe0005000 0 0x1000>;
57 #size-cells = <1>; 37 };
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xe0000000 0x100000>;
61 bus-frequency = <0>;
62
63 ecm-law@0 {
64 compatible = "fsl,ecm-law";
65 reg = <0x0 0x1000>;
66 fsl,num-laws = <10>;
67 };
68
69 ecm@1000 {
70 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
71 reg = <0x1000 0x1000>;
72 interrupts = <17 2>;
73 interrupt-parent = <&mpic>;
74 };
75
76 memory-controller@2000 {
77 compatible = "fsl,mpc8548-memory-controller";
78 reg = <0x2000 0x1000>;
79 interrupt-parent = <&mpic>;
80 interrupts = <18 2>;
81 };
82 38
83 L2: l2-cache-controller@20000 { 39 soc: soc8548@e0000000 {
84 compatible = "fsl,mpc8548-l2-cache-controller"; 40 ranges = <0 0x0 0xe0000000 0x100000>;
85 reg = <0x20000 0x1000>;
86 cache-line-size = <32>; // 32 bytes
87 cache-size = <0x80000>; // L2, 512K
88 interrupt-parent = <&mpic>;
89 interrupts = <16 2>;
90 };
91 41
92 i2c@3000 { 42 i2c@3000 {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 cell-index = <0>;
96 compatible = "fsl-i2c";
97 reg = <0x3000 0x100>;
98 interrupts = <43 2>;
99 interrupt-parent = <&mpic>;
100 dfsrr;
101
102 eeprom@50 { 43 eeprom@50 {
103 compatible = "atmel,24c64"; 44 compatible = "atmel,24c64";
104 reg = <0x50>; 45 reg = <0x50>;
@@ -116,351 +57,178 @@
116 }; 57 };
117 58
118 i2c@3100 { 59 i2c@3100 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 cell-index = <1>;
122 compatible = "fsl-i2c";
123 reg = <0x3100 0x100>;
124 interrupts = <43 2>;
125 interrupt-parent = <&mpic>;
126 dfsrr;
127
128 eeprom@50 { 60 eeprom@50 {
129 compatible = "atmel,24c64"; 61 compatible = "atmel,24c64";
130 reg = <0x50>; 62 reg = <0x50>;
131 }; 63 };
132 }; 64 };
133 65
134 dma@21300 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
138 reg = <0x21300 0x4>;
139 ranges = <0x0 0x21100 0x200>;
140 cell-index = <0>;
141 dma-channel@0 {
142 compatible = "fsl,mpc8548-dma-channel",
143 "fsl,eloplus-dma-channel";
144 reg = <0x0 0x80>;
145 cell-index = <0>;
146 interrupt-parent = <&mpic>;
147 interrupts = <20 2>;
148 };
149 dma-channel@80 {
150 compatible = "fsl,mpc8548-dma-channel",
151 "fsl,eloplus-dma-channel";
152 reg = <0x80 0x80>;
153 cell-index = <1>;
154 interrupt-parent = <&mpic>;
155 interrupts = <21 2>;
156 };
157 dma-channel@100 {
158 compatible = "fsl,mpc8548-dma-channel",
159 "fsl,eloplus-dma-channel";
160 reg = <0x100 0x80>;
161 cell-index = <2>;
162 interrupt-parent = <&mpic>;
163 interrupts = <22 2>;
164 };
165 dma-channel@180 {
166 compatible = "fsl,mpc8548-dma-channel",
167 "fsl,eloplus-dma-channel";
168 reg = <0x180 0x80>;
169 cell-index = <3>;
170 interrupt-parent = <&mpic>;
171 interrupts = <23 2>;
172 };
173 };
174
175 enet0: ethernet@24000 { 66 enet0: ethernet@24000 {
176 #address-cells = <1>;
177 #size-cells = <1>;
178 cell-index = <0>;
179 device_type = "network";
180 model = "eTSEC";
181 compatible = "gianfar";
182 reg = <0x24000 0x1000>;
183 ranges = <0x0 0x24000 0x1000>;
184 local-mac-address = [ 00 00 00 00 00 00 ];
185 interrupts = <29 2 30 2 34 2>;
186 interrupt-parent = <&mpic>;
187 tbi-handle = <&tbi0>; 67 tbi-handle = <&tbi0>;
188 phy-handle = <&phy0>; 68 phy-handle = <&phy0>;
69 };
189 70
190 mdio@520 { 71 mdio@24520 {
191 #address-cells = <1>; 72 phy0: ethernet-phy@0 {
192 #size-cells = <0>; 73 interrupts = <5 1 0 0>;
193 compatible = "fsl,gianfar-mdio"; 74 reg = <0x0>;
194 reg = <0x520 0x20>; 75 device_type = "ethernet-phy";
195 76 };
196 phy0: ethernet-phy@0 { 77 phy1: ethernet-phy@1 {
197 interrupt-parent = <&mpic>; 78 interrupts = <5 1 0 0>;
198 interrupts = <5 1>; 79 reg = <0x1>;
199 reg = <0x0>; 80 device_type = "ethernet-phy";
200 device_type = "ethernet-phy"; 81 };
201 }; 82 phy2: ethernet-phy@2 {
202 phy1: ethernet-phy@1 { 83 interrupts = <5 1 0 0>;
203 interrupt-parent = <&mpic>; 84 reg = <0x2>;
204 interrupts = <5 1>; 85 device_type = "ethernet-phy";
205 reg = <0x1>; 86 };
206 device_type = "ethernet-phy"; 87 phy3: ethernet-phy@3 {
207 }; 88 interrupts = <5 1 0 0>;
208 phy2: ethernet-phy@2 { 89 reg = <0x3>;
209 interrupt-parent = <&mpic>; 90 device_type = "ethernet-phy";
210 interrupts = <5 1>; 91 };
211 reg = <0x2>; 92 tbi0: tbi-phy@11 {
212 device_type = "ethernet-phy"; 93 reg = <0x11>;
213 }; 94 device_type = "tbi-phy";
214 phy3: ethernet-phy@3 {
215 interrupt-parent = <&mpic>;
216 interrupts = <5 1>;
217 reg = <0x3>;
218 device_type = "ethernet-phy";
219 };
220 tbi0: tbi-phy@11 {
221 reg = <0x11>;
222 device_type = "tbi-phy";
223 };
224 }; 95 };
225 }; 96 };
226 97
227 enet1: ethernet@25000 { 98 enet1: ethernet@25000 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 cell-index = <1>;
231 device_type = "network";
232 model = "eTSEC";
233 compatible = "gianfar";
234 reg = <0x25000 0x1000>;
235 ranges = <0x0 0x25000 0x1000>;
236 local-mac-address = [ 00 00 00 00 00 00 ];
237 interrupts = <35 2 36 2 40 2>;
238 interrupt-parent = <&mpic>;
239 tbi-handle = <&tbi1>; 99 tbi-handle = <&tbi1>;
240 phy-handle = <&phy1>; 100 phy-handle = <&phy1>;
101 };
241 102
242 mdio@520 { 103 mdio@25520 {
243 #address-cells = <1>; 104 tbi1: tbi-phy@11 {
244 #size-cells = <0>; 105 reg = <0x11>;
245 compatible = "fsl,gianfar-tbi"; 106 device_type = "tbi-phy";
246 reg = <0x520 0x20>;
247
248 tbi1: tbi-phy@11 {
249 reg = <0x11>;
250 device_type = "tbi-phy";
251 };
252 }; 107 };
253 }; 108 };
254 109
255 enet2: ethernet@26000 { 110 enet2: ethernet@26000 {
256 #address-cells = <1>;
257 #size-cells = <1>;
258 cell-index = <2>;
259 device_type = "network";
260 model = "eTSEC";
261 compatible = "gianfar";
262 reg = <0x26000 0x1000>;
263 ranges = <0x0 0x26000 0x1000>;
264 local-mac-address = [ 00 00 00 00 00 00 ];
265 interrupts = <31 2 32 2 33 2>;
266 interrupt-parent = <&mpic>;
267 tbi-handle = <&tbi2>; 111 tbi-handle = <&tbi2>;
268 phy-handle = <&phy2>; 112 phy-handle = <&phy2>;
113 };
269 114
270 mdio@520 { 115 mdio@26520 {
271 #address-cells = <1>; 116 tbi2: tbi-phy@11 {
272 #size-cells = <0>; 117 reg = <0x11>;
273 compatible = "fsl,gianfar-tbi"; 118 device_type = "tbi-phy";
274 reg = <0x520 0x20>;
275
276 tbi2: tbi-phy@11 {
277 reg = <0x11>;
278 device_type = "tbi-phy";
279 };
280 }; 119 };
281 }; 120 };
282 121
283 enet3: ethernet@27000 { 122 enet3: ethernet@27000 {
284 #address-cells = <1>;
285 #size-cells = <1>;
286 cell-index = <3>;
287 device_type = "network";
288 model = "eTSEC";
289 compatible = "gianfar";
290 reg = <0x27000 0x1000>;
291 ranges = <0x0 0x27000 0x1000>;
292 local-mac-address = [ 00 00 00 00 00 00 ];
293 interrupts = <37 2 38 2 39 2>;
294 interrupt-parent = <&mpic>;
295 tbi-handle = <&tbi3>; 123 tbi-handle = <&tbi3>;
296 phy-handle = <&phy3>; 124 phy-handle = <&phy3>;
297
298 mdio@520 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "fsl,gianfar-tbi";
302 reg = <0x520 0x20>;
303
304 tbi3: tbi-phy@11 {
305 reg = <0x11>;
306 device_type = "tbi-phy";
307 };
308 };
309 };
310
311 serial0: serial@4500 {
312 cell-index = <0>;
313 device_type = "serial";
314 compatible = "ns16550";
315 reg = <0x4500 0x100>; // reg base, size
316 clock-frequency = <0>; // should we fill in in uboot?
317 interrupts = <42 2>;
318 interrupt-parent = <&mpic>;
319 };
320
321 serial1: serial@4600 {
322 cell-index = <1>;
323 device_type = "serial";
324 compatible = "ns16550";
325 reg = <0x4600 0x100>; // reg base, size
326 clock-frequency = <0>; // should we fill in in uboot?
327 interrupts = <42 2>;
328 interrupt-parent = <&mpic>;
329 }; 125 };
330 126
331 global-utilities@e0000 { //global utilities reg 127 mdio@27520 {
332 compatible = "fsl,mpc8548-guts"; 128 tbi3: tbi-phy@11 {
333 reg = <0xe0000 0x1000>; 129 reg = <0x11>;
334 fsl,has-rstcr; 130 device_type = "tbi-phy";
335 }; 131 };
336
337 crypto@30000 {
338 compatible = "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000>;
340 interrupts = <45 2>;
341 interrupt-parent = <&mpic>;
342 fsl,num-channels = <4>;
343 fsl,channel-fifo-len = <24>;
344 fsl,exec-units-mask = <0xfe>;
345 fsl,descriptor-types-mask = <0x12b0ebf>;
346 };
347
348 mpic: pic@40000 {
349 interrupt-controller;
350 #address-cells = <0>;
351 #interrupt-cells = <2>;
352 reg = <0x40000 0x40000>;
353 compatible = "chrp,open-pic";
354 device_type = "open-pic";
355 }; 132 };
356 }; 133 };
357 134
358 pci0: pci@e0008000 { 135 pci0: pci@e0008000 {
136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
359 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
360 interrupt-map = < 141 interrupt-map = <
361 /* IDSEL 0x4 (PCIX Slot 2) */ 142 /* IDSEL 0x4 (PCIX Slot 2) */
362 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
363 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
364 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
365 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
366 147
367 /* IDSEL 0x5 (PCIX Slot 3) */ 148 /* IDSEL 0x5 (PCIX Slot 3) */
368 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
369 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
370 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
371 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
372 153
373 /* IDSEL 0x6 (PCIX Slot 4) */ 154 /* IDSEL 0x6 (PCIX Slot 4) */
374 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
375 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
376 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
377 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
378 159
379 /* IDSEL 0x8 (PCIX Slot 5) */ 160 /* IDSEL 0x8 (PCIX Slot 5) */
380 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
381 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
382 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
383 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
384 165
385 /* IDSEL 0xC (Tsi310 bridge) */ 166 /* IDSEL 0xC (Tsi310 bridge) */
386 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
387 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
388 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
389 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
390 171
391 /* IDSEL 0x14 (Slot 2) */ 172 /* IDSEL 0x14 (Slot 2) */
392 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
393 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
394 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
395 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
396 177
397 /* IDSEL 0x15 (Slot 3) */ 178 /* IDSEL 0x15 (Slot 3) */
398 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
399 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
400 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
401 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
402 183
403 /* IDSEL 0x16 (Slot 4) */ 184 /* IDSEL 0x16 (Slot 4) */
404 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
405 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
406 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
407 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
408 189
409 /* IDSEL 0x18 (Slot 5) */ 190 /* IDSEL 0x18 (Slot 5) */
410 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
411 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
412 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
413 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
414 195
415 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */ 196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
416 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
417 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
418 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
419 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>; 200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
420
421 interrupt-parent = <&mpic>;
422 interrupts = <24 2>;
423 bus-range = <0 0>;
424 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
425 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
426 clock-frequency = <66666666>;
427 #interrupt-cells = <1>;
428 #size-cells = <2>;
429 #address-cells = <3>;
430 reg = <0xe0008000 0x1000>;
431 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
432 device_type = "pci";
433 201
434 pci_bridge@1c { 202 pci_bridge@1c {
435 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
436 interrupt-map = < 204 interrupt-map = <
437 205
438 /* IDSEL 0x00 (PrPMC Site) */ 206 /* IDSEL 0x00 (PrPMC Site) */
439 0000 0x0 0x0 0x1 &mpic 0x0 0x1 207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
440 0000 0x0 0x0 0x2 &mpic 0x1 0x1 208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
441 0000 0x0 0x0 0x3 &mpic 0x2 0x1 209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
442 0000 0x0 0x0 0x4 &mpic 0x3 0x1 210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
443 211
444 /* IDSEL 0x04 (VIA chip) */ 212 /* IDSEL 0x04 (VIA chip) */
445 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
446 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
447 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
448 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
449 217
450 /* IDSEL 0x05 (8139) */ 218 /* IDSEL 0x05 (8139) */
451 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
452 220
453 /* IDSEL 0x06 (Slot 6) */ 221 /* IDSEL 0x06 (Slot 6) */
454 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
455 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
456 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
457 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
458 226
459 /* IDESL 0x07 (Slot 7) */ 227 /* IDESL 0x07 (Slot 7) */
460 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
461 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
462 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
463 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>; 231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
464 232
465 reg = <0xe000 0x0 0x0 0x0 0x0>; 233 reg = <0xe000 0x0 0x0 0x0 0x0>;
466 #interrupt-cells = <1>; 234 #interrupt-cells = <1>;
@@ -492,7 +260,7 @@
492 #address-cells = <0>; 260 #address-cells = <0>;
493 #interrupt-cells = <2>; 261 #interrupt-cells = <2>;
494 compatible = "chrp,iic"; 262 compatible = "chrp,iic";
495 interrupts = <0 1>; 263 interrupts = <0 1 0 0>;
496 interrupt-parent = <&mpic>; 264 interrupt-parent = <&mpic>;
497 }; 265 };
498 266
@@ -505,56 +273,25 @@
505 }; 273 };
506 274
507 pci1: pci@e0009000 { 275 pci1: pci@e0009000 {
276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
508 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
509 interrupt-map = < 281 interrupt-map = <
510 282
511 /* IDSEL 0x15 */ 283 /* IDSEL 0x15 */
512 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
513 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
514 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
515 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>; 287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
516
517 interrupt-parent = <&mpic>;
518 interrupts = <25 2>;
519 bus-range = <0 0>;
520 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
521 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
522 clock-frequency = <66666666>;
523 #interrupt-cells = <1>;
524 #size-cells = <2>;
525 #address-cells = <3>;
526 reg = <0xe0009000 0x1000>;
527 compatible = "fsl,mpc8540-pci";
528 device_type = "pci";
529 }; 288 };
530 289
531 pci2: pcie@e000a000 { 290 pci2: pcie@e000a000 {
532 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 291 reg = <0 0xe000a000 0 0x1000>;
533 interrupt-map = < 292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
534 293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
535 /* IDSEL 0x0 (PEX) */
536 00000 0x0 0x0 0x1 &mpic 0x0 0x1
537 00000 0x0 0x0 0x2 &mpic 0x1 0x1
538 00000 0x0 0x0 0x3 &mpic 0x2 0x1
539 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
540
541 interrupt-parent = <&mpic>;
542 interrupts = <26 2>;
543 bus-range = <0 255>;
544 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
545 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
546 clock-frequency = <33333333>;
547 #interrupt-cells = <1>;
548 #size-cells = <2>;
549 #address-cells = <3>;
550 reg = <0xe000a000 0x1000>;
551 compatible = "fsl,mpc8548-pcie";
552 device_type = "pci";
553 pcie@0 { 294 pcie@0 {
554 reg = <0x0 0x0 0x0 0x0 0x0>;
555 #size-cells = <2>;
556 #address-cells = <3>;
557 device_type = "pci";
558 ranges = <0x2000000 0x0 0xa0000000 295 ranges = <0x2000000 0x0 0xa0000000
559 0x2000000 0x0 0xa0000000 296 0x2000000 0x0 0xa0000000
560 0x0 0x20000000 297 0x0 0x20000000
@@ -565,3 +302,5 @@
565 }; 302 };
566 }; 303 };
567}; 304};
305
306/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
index 5c5614f9eb17..fe10438613d6 100644
--- a/arch/powerpc/boot/dts/mpc8555cds.dts
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -209,7 +209,7 @@
209 serial0: serial@4500 { 209 serial0: serial@4500 {
210 cell-index = <0>; 210 cell-index = <0>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4500 0x100>; // reg base, size 213 reg = <0x4500 0x100>; // reg base, size
214 clock-frequency = <0>; // should we fill in in uboot? 214 clock-frequency = <0>; // should we fill in in uboot?
215 interrupts = <42 2>; 215 interrupts = <42 2>;
@@ -219,7 +219,7 @@
219 serial1: serial@4600 { 219 serial1: serial@4600 {
220 cell-index = <1>; 220 cell-index = <1>;
221 device_type = "serial"; 221 device_type = "serial";
222 compatible = "ns16550"; 222 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4600 0x100>; // reg base, size 223 reg = <0x4600 0x100>; // reg base, size
224 clock-frequency = <0>; // should we fill in in uboot? 224 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 225 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 647daf8e7291..09598bb5d443 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -9,60 +9,25 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8568si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8568EMDS"; 15 model = "MPC8568EMDS";
16 compatible = "MPC8568EMDS", "MPC85xxMDS"; 16 compatible = "MPC8568EMDS", "MPC85xxMDS";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 17
20 aliases { 18 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0; 19 pci0 = &pci0;
28 pci1 = &pci1; 20 pci1 = &pci1;
29 rapidio0 = &rio0; 21 rapidio0 = &rio;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8568@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 sleep = <&pmc 0x00008000 // core
44 &pmc 0x00004000>; // timebase
45 timebase-frequency = <0>;
46 bus-frequency = <0>;
47 clock-frequency = <0>;
48 next-level-cache = <&L2>;
49 };
50 }; 22 };
51 23
52 memory { 24 memory {
53 device_type = "memory"; 25 device_type = "memory";
54 reg = <0x0 0x10000000>; 26 reg = <0x0 0x0 0x0 0x0>;
55 }; 27 };
56 28
57 localbus@e0005000 { 29 lbc: localbus@e0005000 {
58 #address-cells = <2>; 30 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>;
60 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
61 "simple-bus";
62 reg = <0xe0005000 0x1000>;
63 interrupt-parent = <&mpic>;
64 interrupts = <19 2>;
65
66 ranges = <0x0 0x0 0xfe000000 0x02000000 31 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000 32 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000 33 0x2 0x0 0xf0000000 0x04000000
@@ -104,288 +69,65 @@
104 }; 69 };
105 }; 70 };
106 71
107 soc8568@e0000000 { 72 soc: soc8568@e0000000 {
108 #address-cells = <1>; 73 ranges = <0x0 0x0 0xe0000000 0x100000>;
109 #size-cells = <1>;
110 device_type = "soc";
111 compatible = "simple-bus";
112 ranges = <0x0 0xe0000000 0x100000>;
113 bus-frequency = <0>;
114
115 ecm-law@0 {
116 compatible = "fsl,ecm-law";
117 reg = <0x0 0x1000>;
118 fsl,num-laws = <10>;
119 };
120
121 ecm@1000 {
122 compatible = "fsl,mpc8568-ecm", "fsl,ecm";
123 reg = <0x1000 0x1000>;
124 interrupts = <17 2>;
125 interrupt-parent = <&mpic>;
126 };
127
128 memory-controller@2000 {
129 compatible = "fsl,mpc8568-memory-controller";
130 reg = <0x2000 0x1000>;
131 interrupt-parent = <&mpic>;
132 interrupts = <18 2>;
133 };
134
135 L2: l2-cache-controller@20000 {
136 compatible = "fsl,mpc8568-l2-cache-controller";
137 reg = <0x20000 0x1000>;
138 cache-line-size = <32>; // 32 bytes
139 cache-size = <0x80000>; // L2, 512K
140 interrupt-parent = <&mpic>;
141 interrupts = <16 2>;
142 };
143 74
144 i2c-sleep-nexus { 75 i2c-sleep-nexus {
145 #address-cells = <1>;
146 #size-cells = <1>;
147 compatible = "simple-bus";
148 sleep = <&pmc 0x00000004>;
149 ranges;
150
151 i2c@3000 { 76 i2c@3000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 cell-index = <0>;
155 compatible = "fsl-i2c";
156 reg = <0x3000 0x100>;
157 interrupts = <43 2>;
158 interrupt-parent = <&mpic>;
159 dfsrr;
160
161 rtc@68 { 77 rtc@68 {
162 compatible = "dallas,ds1374"; 78 compatible = "dallas,ds1374";
163 reg = <0x68>; 79 reg = <0x68>;
164 interrupts = <3 1>; 80 interrupts = <3 1 0 0>;
165 interrupt-parent = <&mpic>;
166 }; 81 };
167 }; 82 };
83 };
168 84
169 i2c@3100 { 85 enet0: ethernet@24000 {
170 #address-cells = <1>; 86 tbi-handle = <&tbi0>;
171 #size-cells = <0>; 87 phy-handle = <&phy2>;
172 cell-index = <1>;
173 compatible = "fsl-i2c";
174 reg = <0x3100 0x100>;
175 interrupts = <43 2>;
176 interrupt-parent = <&mpic>;
177 dfsrr;
178 };
179 }; 88 };
180 89
181 dma@21300 { 90 mdio@24520 {
182 #address-cells = <1>; 91 phy0: ethernet-phy@7 {
183 #size-cells = <1>; 92 interrupts = <1 1 0 0>;
184 compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma"; 93 reg = <0x7>;
185 reg = <0x21300 0x4>; 94 device_type = "ethernet-phy";
186 ranges = <0x0 0x21100 0x200>;
187 cell-index = <0>;
188 sleep = <&pmc 0x00000400>;
189
190 dma-channel@0 {
191 compatible = "fsl,mpc8568-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x0 0x80>;
194 cell-index = <0>;
195 interrupt-parent = <&mpic>;
196 interrupts = <20 2>;
197 }; 95 };
198 dma-channel@80 { 96 phy1: ethernet-phy@1 {
199 compatible = "fsl,mpc8568-dma-channel", 97 interrupts = <2 1 0 0>;
200 "fsl,eloplus-dma-channel"; 98 reg = <0x1>;
201 reg = <0x80 0x80>; 99 device_type = "ethernet-phy";
202 cell-index = <1>;
203 interrupt-parent = <&mpic>;
204 interrupts = <21 2>;
205 }; 100 };
206 dma-channel@100 { 101 phy2: ethernet-phy@2 {
207 compatible = "fsl,mpc8568-dma-channel", 102 interrupts = <1 1 0 0>;
208 "fsl,eloplus-dma-channel"; 103 reg = <0x2>;
209 reg = <0x100 0x80>; 104 device_type = "ethernet-phy";
210 cell-index = <2>;
211 interrupt-parent = <&mpic>;
212 interrupts = <22 2>;
213 }; 105 };
214 dma-channel@180 { 106 phy3: ethernet-phy@3 {
215 compatible = "fsl,mpc8568-dma-channel", 107 interrupts = <2 1 0 0>;
216 "fsl,eloplus-dma-channel"; 108 reg = <0x3>;
217 reg = <0x180 0x80>; 109 device_type = "ethernet-phy";
218 cell-index = <3>;
219 interrupt-parent = <&mpic>;
220 interrupts = <23 2>;
221 }; 110 };
222 }; 111 tbi0: tbi-phy@11 {
223 112 reg = <0x11>;
224 enet0: ethernet@24000 { 113 device_type = "tbi-phy";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 cell-index = <0>;
228 device_type = "network";
229 model = "eTSEC";
230 compatible = "gianfar";
231 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <29 2 30 2 34 2>;
235 interrupt-parent = <&mpic>;
236 tbi-handle = <&tbi0>;
237 phy-handle = <&phy2>;
238 sleep = <&pmc 0x00000080>;
239
240 mdio@520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-mdio";
244 reg = <0x520 0x20>;
245
246 phy0: ethernet-phy@7 {
247 interrupt-parent = <&mpic>;
248 interrupts = <1 1>;
249 reg = <0x7>;
250 device_type = "ethernet-phy";
251 };
252 phy1: ethernet-phy@1 {
253 interrupt-parent = <&mpic>;
254 interrupts = <2 1>;
255 reg = <0x1>;
256 device_type = "ethernet-phy";
257 };
258 phy2: ethernet-phy@2 {
259 interrupt-parent = <&mpic>;
260 interrupts = <1 1>;
261 reg = <0x2>;
262 device_type = "ethernet-phy";
263 };
264 phy3: ethernet-phy@3 {
265 interrupt-parent = <&mpic>;
266 interrupts = <2 1>;
267 reg = <0x3>;
268 device_type = "ethernet-phy";
269 };
270 tbi0: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 }; 114 };
275 }; 115 };
276 116
277 enet1: ethernet@25000 { 117 enet1: ethernet@25000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <1>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x25000 0x1000>;
285 ranges = <0x0 0x25000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <35 2 36 2 40 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi1>; 118 tbi-handle = <&tbi1>;
290 phy-handle = <&phy3>; 119 phy-handle = <&phy3>;
291 sleep = <&pmc 0x00000040>; 120 sleep = <&pmc 0x00000040>;
292
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
298
299 tbi1: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 }; 121 };
305 122
306 duart-sleep-nexus { 123 mdio@25520 {
307 #address-cells = <1>; 124 tbi1: tbi-phy@11 {
308 #size-cells = <1>; 125 reg = <0x11>;
309 compatible = "simple-bus"; 126 device_type = "tbi-phy";
310 sleep = <&pmc 0x00000002>;
311 ranges;
312
313 serial0: serial@4500 {
314 cell-index = <0>;
315 device_type = "serial";
316 compatible = "ns16550";
317 reg = <0x4500 0x100>;
318 clock-frequency = <0>;
319 interrupts = <42 2>;
320 interrupt-parent = <&mpic>;
321 };
322
323 serial1: serial@4600 {
324 cell-index = <1>;
325 device_type = "serial";
326 compatible = "ns16550";
327 reg = <0x4600 0x100>;
328 clock-frequency = <0>;
329 interrupts = <42 2>;
330 interrupt-parent = <&mpic>;
331 }; 127 };
332 }; 128 };
333 129
334 global-utilities@e0000 {
335 #address-cells = <1>;
336 #size-cells = <1>;
337 compatible = "fsl,mpc8568-guts", "fsl,mpc8548-guts";
338 reg = <0xe0000 0x1000>;
339 ranges = <0 0xe0000 0x1000>;
340 fsl,has-rstcr;
341
342 pmc: power@70 {
343 compatible = "fsl,mpc8568-pmc",
344 "fsl,mpc8548-pmc";
345 reg = <0x70 0x20>;
346 };
347 };
348
349 crypto@30000 {
350 compatible = "fsl,sec2.1", "fsl,sec2.0";
351 reg = <0x30000 0x10000>;
352 interrupts = <45 2>;
353 interrupt-parent = <&mpic>;
354 fsl,num-channels = <4>;
355 fsl,channel-fifo-len = <24>;
356 fsl,exec-units-mask = <0xfe>;
357 fsl,descriptor-types-mask = <0x12b0ebf>;
358 sleep = <&pmc 0x01000000>;
359 };
360
361 mpic: pic@40000 {
362 interrupt-controller;
363 #address-cells = <0>;
364 #interrupt-cells = <2>;
365 reg = <0x40000 0x40000>;
366 compatible = "chrp,open-pic";
367 device_type = "open-pic";
368 };
369
370 msi@41600 {
371 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
372 reg = <0x41600 0x80>;
373 msi-available-ranges = <0 0x100>;
374 interrupts = <
375 0xe0 0
376 0xe1 0
377 0xe2 0
378 0xe3 0
379 0xe4 0
380 0xe5 0
381 0xe6 0
382 0xe7 0>;
383 interrupt-parent = <&mpic>;
384 };
385
386 par_io@e0100 { 130 par_io@e0100 {
387 reg = <0xe0100 0x100>;
388 device_type = "par_io";
389 num-ports = <7>; 131 num-ports = <7>;
390 132
391 pio1: ucc_pin@01 { 133 pio1: ucc_pin@01 {
@@ -448,57 +190,21 @@
448 }; 190 };
449 }; 191 };
450 192
451 qe@e0080000 { 193 qe: qe@e0080000 {
452 #address-cells = <1>; 194 ranges = <0x0 0x0 0xe0080000 0x40000>;
453 #size-cells = <1>; 195 reg = <0x0 0xe0080000 0x0 0x480>;
454 device_type = "qe";
455 compatible = "fsl,qe";
456 ranges = <0x0 0xe0080000 0x40000>;
457 reg = <0xe0080000 0x480>;
458 sleep = <&pmc 0x00000800>;
459 brg-frequency = <0>;
460 bus-frequency = <396000000>;
461 fsl,qe-num-riscs = <2>;
462 fsl,qe-num-snums = <28>;
463
464 muram@10000 {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "fsl,qe-muram", "fsl,cpm-muram";
468 ranges = <0x0 0x10000 0x10000>;
469
470 data-only@0 {
471 compatible = "fsl,qe-muram-data",
472 "fsl,cpm-muram-data";
473 reg = <0x0 0x10000>;
474 };
475 };
476 196
477 spi@4c0 { 197 spi@4c0 {
478 cell-index = <0>;
479 compatible = "fsl,spi";
480 reg = <0x4c0 0x40>;
481 interrupts = <2>;
482 interrupt-parent = <&qeic>;
483 mode = "cpu"; 198 mode = "cpu";
484 }; 199 };
485 200
486 spi@500 { 201 spi@500 {
487 cell-index = <1>;
488 compatible = "fsl,spi";
489 reg = <0x500 0x40>;
490 interrupts = <1>;
491 interrupt-parent = <&qeic>;
492 mode = "cpu"; 202 mode = "cpu";
493 }; 203 };
494 204
495 enet2: ucc@2000 { 205 enet2: ucc@2000 {
496 device_type = "network"; 206 device_type = "network";
497 compatible = "ucc_geth"; 207 compatible = "ucc_geth";
498 cell-index = <1>;
499 reg = <0x2000 0x200>;
500 interrupts = <32>;
501 interrupt-parent = <&qeic>;
502 local-mac-address = [ 00 00 00 00 00 00 ]; 208 local-mac-address = [ 00 00 00 00 00 00 ];
503 rx-clock-name = "none"; 209 rx-clock-name = "none";
504 tx-clock-name = "clk16"; 210 tx-clock-name = "clk16";
@@ -510,10 +216,6 @@
510 enet3: ucc@3000 { 216 enet3: ucc@3000 {
511 device_type = "network"; 217 device_type = "network";
512 compatible = "ucc_geth"; 218 compatible = "ucc_geth";
513 cell-index = <2>;
514 reg = <0x3000 0x200>;
515 interrupts = <33>;
516 interrupt-parent = <&qeic>;
517 local-mac-address = [ 00 00 00 00 00 00 ]; 219 local-mac-address = [ 00 00 00 00 00 00 ];
518 rx-clock-name = "none"; 220 rx-clock-name = "none";
519 tx-clock-name = "clk16"; 221 tx-clock-name = "clk16";
@@ -532,102 +234,57 @@
532 * gianfar's MDIO bus */ 234 * gianfar's MDIO bus */
533 qe_phy0: ethernet-phy@07 { 235 qe_phy0: ethernet-phy@07 {
534 interrupt-parent = <&mpic>; 236 interrupt-parent = <&mpic>;
535 interrupts = <1 1>; 237 interrupts = <1 1 0 0>;
536 reg = <0x7>; 238 reg = <0x7>;
537 device_type = "ethernet-phy"; 239 device_type = "ethernet-phy";
538 }; 240 };
539 qe_phy1: ethernet-phy@01 { 241 qe_phy1: ethernet-phy@01 {
540 interrupt-parent = <&mpic>; 242 interrupt-parent = <&mpic>;
541 interrupts = <2 1>; 243 interrupts = <2 1 0 0>;
542 reg = <0x1>; 244 reg = <0x1>;
543 device_type = "ethernet-phy"; 245 device_type = "ethernet-phy";
544 }; 246 };
545 qe_phy2: ethernet-phy@02 { 247 qe_phy2: ethernet-phy@02 {
546 interrupt-parent = <&mpic>; 248 interrupt-parent = <&mpic>;
547 interrupts = <1 1>; 249 interrupts = <1 1 0 0>;
548 reg = <0x2>; 250 reg = <0x2>;
549 device_type = "ethernet-phy"; 251 device_type = "ethernet-phy";
550 }; 252 };
551 qe_phy3: ethernet-phy@03 { 253 qe_phy3: ethernet-phy@03 {
552 interrupt-parent = <&mpic>; 254 interrupt-parent = <&mpic>;
553 interrupts = <2 1>; 255 interrupts = <2 1 0 0>;
554 reg = <0x3>; 256 reg = <0x3>;
555 device_type = "ethernet-phy"; 257 device_type = "ethernet-phy";
556 }; 258 };
557 }; 259 };
558
559 qeic: interrupt-controller@80 {
560 interrupt-controller;
561 compatible = "fsl,qe-ic";
562 #address-cells = <0>;
563 #interrupt-cells = <1>;
564 reg = <0x80 0x80>;
565 big-endian;
566 interrupts = <46 2 46 2>; //high:30 low:30
567 interrupt-parent = <&mpic>;
568 };
569
570 }; 260 };
571 261
572 pci0: pci@e0008000 { 262 pci0: pci@e0008000 {
263 reg = <0x0 0xe0008000 0x0 0x1000>;
264 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
265 0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
266 clock-frequency = <66666666>;
573 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 267 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
574 interrupt-map = < 268 interrupt-map = <
575 /* IDSEL 0x12 AD18 */ 269 /* IDSEL 0x12 AD18 */
576 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 270 0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
577 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 271 0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
578 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 272 0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
579 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 273 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
580 274
581 /* IDSEL 0x13 AD19 */ 275 /* IDSEL 0x13 AD19 */
582 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 276 0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
583 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 277 0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
584 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 278 0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
585 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>; 279 0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
586
587 interrupt-parent = <&mpic>;
588 interrupts = <24 2>;
589 bus-range = <0 255>;
590 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
591 0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
592 sleep = <&pmc 0x80000000>;
593 clock-frequency = <66666666>;
594 #interrupt-cells = <1>;
595 #size-cells = <2>;
596 #address-cells = <3>;
597 reg = <0xe0008000 0x1000>;
598 compatible = "fsl,mpc8540-pci";
599 device_type = "pci";
600 }; 280 };
601 281
602 /* PCI Express */ 282 /* PCI Express */
603 pci1: pcie@e000a000 { 283 pci1: pcie@e000a000 {
604 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 284 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
605 interrupt-map = < 285 0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
606 286 reg = <0x0 0xe000a000 0x0 0x1000>;
607 /* IDSEL 0x0 (PEX) */
608 00000 0x0 0x0 0x1 &mpic 0x0 0x1
609 00000 0x0 0x0 0x2 &mpic 0x1 0x1
610 00000 0x0 0x0 0x3 &mpic 0x2 0x1
611 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
612
613 interrupt-parent = <&mpic>;
614 interrupts = <26 2>;
615 bus-range = <0 255>;
616 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
617 0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
618 sleep = <&pmc 0x20000000>;
619 clock-frequency = <33333333>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 reg = <0xe000a000 0x1000>;
624 compatible = "fsl,mpc8548-pcie";
625 device_type = "pci";
626 pcie@0 { 287 pcie@0 {
627 reg = <0x0 0x0 0x0 0x0 0x0>;
628 #size-cells = <2>;
629 #address-cells = <3>;
630 device_type = "pci";
631 ranges = <0x2000000 0x0 0xa0000000 288 ranges = <0x2000000 0x0 0xa0000000
632 0x2000000 0x0 0xa0000000 289 0x2000000 0x0 0xa0000000
633 0x0 0x10000000 290 0x0 0x10000000
@@ -638,22 +295,11 @@
638 }; 295 };
639 }; 296 };
640 297
641 rio0: rapidio@e00c00000 { 298 rio: rapidio@e00c00000 {
642 #address-cells = <2>; 299 reg = <0x0 0xe00c0000 0x0 0x20000>;
643 #size-cells = <2>; 300 port1 {
644 compatible = "fsl,mpc8568-rapidio", "fsl,rapidio-delta"; 301 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
645 reg = <0xe00c0000 0x20000>; 302 };
646 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
647 interrupts = <48 2 /* error */
648 49 2 /* bell_outb */
649 50 2 /* bell_inb */
650 53 2 /* msg1_tx */
651 54 2 /* msg1_rx */
652 55 2 /* msg2_tx */
653 56 2 /* msg2_rx */>;
654 interrupt-parent = <&mpic>;
655 sleep = <&pmc 0x00080000 /* controller */
656 &pmc 0x00040000>; /* message unit */
657 }; 303 };
658 304
659 leds { 305 leds {
@@ -672,3 +318,5 @@
672 }; 318 };
673 }; 319 };
674}; 320};
321
322/include/ "fsl/mpc8568si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts b/arch/powerpc/boot/dts/mpc8569mds.dts
index 8b72eaff5b03..7e283c891b7f 100644
--- a/arch/powerpc/boot/dts/mpc8569mds.dts
+++ b/arch/powerpc/boot/dts/mpc8569mds.dts
@@ -9,66 +9,36 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8569si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8569EMDS"; 15 model = "MPC8569EMDS";
16 compatible = "fsl,MPC8569EMDS"; 16 compatible = "fsl,MPC8569EMDS";
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 interrupt-parent = <&mpic>;
19 20
20 aliases { 21 aliases {
21 serial0 = &serial0;
22 serial1 = &serial1;
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2; 22 ethernet2 = &enet2;
26 ethernet3 = &enet3; 23 ethernet3 = &enet3;
27 ethernet5 = &enet5; 24 ethernet5 = &enet5;
28 ethernet7 = &enet7; 25 ethernet7 = &enet7;
29 pci1 = &pci1; 26 rapidio0 = &rio;
30 rapidio0 = &rio0;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 PowerPC,8569@0 {
38 device_type = "cpu";
39 reg = <0x0>;
40 d-cache-line-size = <32>; // 32 bytes
41 i-cache-line-size = <32>; // 32 bytes
42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
44 sleep = <&pmc 0x00008000 // core
45 &pmc 0x00004000>; // timebase
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 next-level-cache = <&L2>;
50 };
51 }; 27 };
52 28
53 memory { 29 memory {
54 device_type = "memory"; 30 device_type = "memory";
55 }; 31 };
56 32
57 localbus@e0005000 { 33 lbc: localbus@e0005000 {
58 #address-cells = <2>; 34 reg = <0x0 0xe0005000 0x0 0x1000>;
59 #size-cells = <1>; 35
60 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; 36 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
61 reg = <0xe0005000 0x1000>; 37 0x1 0x0 0x0 0xf8000000 0x00008000
62 interrupts = <19 2>; 38 0x2 0x0 0x0 0xf0000000 0x04000000
63 interrupt-parent = <&mpic>; 39 0x3 0x0 0x0 0xfc000000 0x00008000
64 sleep = <&pmc 0x08000000>; 40 0x4 0x0 0x0 0xf8008000 0x00008000
65 41 0x5 0x0 0x0 0xf8010000 0x00008000>;
66 ranges = <0x0 0x0 0xfe000000 0x02000000
67 0x1 0x0 0xf8000000 0x00008000
68 0x2 0x0 0xf0000000 0x04000000
69 0x3 0x0 0xfc000000 0x00008000
70 0x4 0x0 0xf8008000 0x00008000
71 0x5 0x0 0xf8010000 0x00008000>;
72 42
73 nor@0,0 { 43 nor@0,0 {
74 #address-cells = <1>; 44 #address-cells = <1>;
@@ -133,220 +103,25 @@
133 }; 103 };
134 }; 104 };
135 105
136 soc@e0000000 { 106 soc: soc@e0000000 {
137 #address-cells = <1>; 107 ranges = <0x0 0x0 0xe0000000 0x100000>;
138 #size-cells = <1>;
139 device_type = "soc";
140 compatible = "fsl,mpc8569-immr", "simple-bus";
141 ranges = <0x0 0xe0000000 0x100000>;
142 bus-frequency = <0>;
143
144 ecm-law@0 {
145 compatible = "fsl,ecm-law";
146 reg = <0x0 0x1000>;
147 fsl,num-laws = <10>;
148 };
149
150 ecm@1000 {
151 compatible = "fsl,mpc8569-ecm", "fsl,ecm";
152 reg = <0x1000 0x1000>;
153 interrupts = <17 2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 memory-controller@2000 {
158 compatible = "fsl,mpc8569-memory-controller";
159 reg = <0x2000 0x1000>;
160 interrupt-parent = <&mpic>;
161 interrupts = <18 2>;
162 };
163 108
164 i2c-sleep-nexus { 109 i2c-sleep-nexus {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 compatible = "simple-bus";
168 sleep = <&pmc 0x00000004>;
169 ranges;
170
171 i2c@3000 { 110 i2c@3000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 cell-index = <0>;
175 compatible = "fsl-i2c";
176 reg = <0x3000 0x100>;
177 interrupts = <43 2>;
178 interrupt-parent = <&mpic>;
179 dfsrr;
180
181 rtc@68 { 111 rtc@68 {
182 compatible = "dallas,ds1374"; 112 compatible = "dallas,ds1374";
183 reg = <0x68>; 113 reg = <0x68>;
184 interrupts = <3 1>; 114 interrupts = <3 1 0 0>;
185 interrupt-parent = <&mpic>;
186 }; 115 };
187 }; 116 };
188
189 i2c@3100 {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 cell-index = <1>;
193 compatible = "fsl-i2c";
194 reg = <0x3100 0x100>;
195 interrupts = <43 2>;
196 interrupt-parent = <&mpic>;
197 dfsrr;
198 };
199 };
200
201 duart-sleep-nexus {
202 #address-cells = <1>;
203 #size-cells = <1>;
204 compatible = "simple-bus";
205 sleep = <&pmc 0x00000002>;
206 ranges;
207
208 serial0: serial@4500 {
209 cell-index = <0>;
210 device_type = "serial";
211 compatible = "ns16550";
212 reg = <0x4500 0x100>;
213 clock-frequency = <0>;
214 interrupts = <42 2>;
215 interrupt-parent = <&mpic>;
216 };
217
218 serial1: serial@4600 {
219 cell-index = <1>;
220 device_type = "serial";
221 compatible = "ns16550";
222 reg = <0x4600 0x100>;
223 clock-frequency = <0>;
224 interrupts = <42 2>;
225 interrupt-parent = <&mpic>;
226 };
227 };
228
229 L2: l2-cache-controller@20000 {
230 compatible = "fsl,mpc8569-l2-cache-controller";
231 reg = <0x20000 0x1000>;
232 cache-line-size = <32>; // 32 bytes
233 cache-size = <0x80000>; // L2, 512K
234 interrupt-parent = <&mpic>;
235 interrupts = <16 2>;
236 }; 117 };
237 118
238 dma@21300 { 119 sdhc@2e000 {
239 #address-cells = <1>;
240 #size-cells = <1>;
241 compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
242 reg = <0x21300 0x4>;
243 ranges = <0x0 0x21100 0x200>;
244 cell-index = <0>;
245 dma-channel@0 {
246 compatible = "fsl,mpc8569-dma-channel",
247 "fsl,eloplus-dma-channel";
248 reg = <0x0 0x80>;
249 cell-index = <0>;
250 interrupt-parent = <&mpic>;
251 interrupts = <20 2>;
252 };
253 dma-channel@80 {
254 compatible = "fsl,mpc8569-dma-channel",
255 "fsl,eloplus-dma-channel";
256 reg = <0x80 0x80>;
257 cell-index = <1>;
258 interrupt-parent = <&mpic>;
259 interrupts = <21 2>;
260 };
261 dma-channel@100 {
262 compatible = "fsl,mpc8569-dma-channel",
263 "fsl,eloplus-dma-channel";
264 reg = <0x100 0x80>;
265 cell-index = <2>;
266 interrupt-parent = <&mpic>;
267 interrupts = <22 2>;
268 };
269 dma-channel@180 {
270 compatible = "fsl,mpc8569-dma-channel",
271 "fsl,eloplus-dma-channel";
272 reg = <0x180 0x80>;
273 cell-index = <3>;
274 interrupt-parent = <&mpic>;
275 interrupts = <23 2>;
276 };
277 };
278
279 sdhci@2e000 {
280 compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
281 reg = <0x2e000 0x1000>;
282 interrupts = <72 0x8>;
283 interrupt-parent = <&mpic>;
284 sleep = <&pmc 0x00200000>;
285 /* Filled in by U-Boot */
286 clock-frequency = <0>;
287 status = "disabled"; 120 status = "disabled";
288 sdhci,1-bit-only; 121 sdhci,1-bit-only;
289 }; 122 };
290 123
291 crypto@30000 {
292 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
293 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
294 reg = <0x30000 0x10000>;
295 interrupts = <45 2 58 2>;
296 interrupt-parent = <&mpic>;
297 fsl,num-channels = <4>;
298 fsl,channel-fifo-len = <24>;
299 fsl,exec-units-mask = <0xbfe>;
300 fsl,descriptor-types-mask = <0x3ab0ebf>;
301 sleep = <&pmc 0x01000000>;
302 };
303
304 mpic: pic@40000 {
305 interrupt-controller;
306 #address-cells = <0>;
307 #interrupt-cells = <2>;
308 reg = <0x40000 0x40000>;
309 compatible = "chrp,open-pic";
310 device_type = "open-pic";
311 };
312
313 msi@41600 {
314 compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
315 reg = <0x41600 0x80>;
316 msi-available-ranges = <0 0x100>;
317 interrupts = <
318 0xe0 0
319 0xe1 0
320 0xe2 0
321 0xe3 0
322 0xe4 0
323 0xe5 0
324 0xe6 0
325 0xe7 0>;
326 interrupt-parent = <&mpic>;
327 };
328
329 global-utilities@e0000 {
330 #address-cells = <1>;
331 #size-cells = <1>;
332 compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts";
333 reg = <0xe0000 0x1000>;
334 ranges = <0 0xe0000 0x1000>;
335 fsl,has-rstcr;
336
337 pmc: power@70 {
338 compatible = "fsl,mpc8569-pmc",
339 "fsl,mpc8548-pmc";
340 reg = <0x70 0x20>;
341 };
342 };
343
344 par_io@e0100 { 124 par_io@e0100 {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 reg = <0xe0100 0x100>;
348 ranges = <0x0 0xe0100 0x100>;
349 device_type = "par_io";
350 num-ports = <7>; 125 num-ports = <7>;
351 126
352 qe_pio_e: gpio-controller@80 { 127 qe_pio_e: gpio-controller@80 {
@@ -447,47 +222,11 @@
447 }; 222 };
448 }; 223 };
449 224
450 qe@e0080000 { 225 qe: qe@e0080000 {
451 #address-cells = <1>; 226 ranges = <0x0 0x0 0xe0080000 0x40000>;
452 #size-cells = <1>; 227 reg = <0x0 0xe0080000 0x0 0x480>;
453 device_type = "qe";
454 compatible = "fsl,qe";
455 ranges = <0x0 0xe0080000 0x40000>;
456 reg = <0xe0080000 0x480>;
457 sleep = <&pmc 0x00000800>;
458 brg-frequency = <0>;
459 bus-frequency = <0>;
460 fsl,qe-num-riscs = <4>;
461 fsl,qe-num-snums = <46>;
462
463 qeic: interrupt-controller@80 {
464 interrupt-controller;
465 compatible = "fsl,qe-ic";
466 #address-cells = <0>;
467 #interrupt-cells = <1>;
468 reg = <0x80 0x80>;
469 interrupts = <46 2 46 2>; //high:30 low:30
470 interrupt-parent = <&mpic>;
471 };
472
473 timer@440 {
474 compatible = "fsl,mpc8569-qe-gtm",
475 "fsl,qe-gtm", "fsl,gtm";
476 reg = <0x440 0x40>;
477 interrupts = <12 13 14 15>;
478 interrupt-parent = <&qeic>;
479 /* Filled in by U-Boot */
480 clock-frequency = <0>;
481 };
482 228
483 spi@4c0 { 229 spi@4c0 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
487 reg = <0x4c0 0x40>;
488 cell-index = <0>;
489 interrupts = <2>;
490 interrupt-parent = <&qeic>;
491 gpios = <&qe_pio_e 30 0>; 230 gpios = <&qe_pio_e 30 0>;
492 mode = "cpu-qe"; 231 mode = "cpu-qe";
493 232
@@ -499,20 +238,10 @@
499 }; 238 };
500 239
501 spi@500 { 240 spi@500 {
502 cell-index = <1>;
503 compatible = "fsl,spi";
504 reg = <0x500 0x40>;
505 interrupts = <1>;
506 interrupt-parent = <&qeic>;
507 mode = "cpu"; 241 mode = "cpu";
508 }; 242 };
509 243
510 usb@6c0 { 244 usb@6c0 {
511 compatible = "fsl,mpc8569-qe-usb",
512 "fsl,mpc8323-qe-usb";
513 reg = <0x6c0 0x40 0x8b00 0x100>;
514 interrupts = <11>;
515 interrupt-parent = <&qeic>;
516 fsl,fullspeed-clock = "clk5"; 245 fsl,fullspeed-clock = "clk5";
517 fsl,lowspeed-clock = "brg10"; 246 fsl,lowspeed-clock = "brg10";
518 gpios = <&qe_pio_f 3 0 /* USBOE */ 247 gpios = <&qe_pio_f 3 0 /* USBOE */
@@ -527,10 +256,6 @@
527 enet0: ucc@2000 { 256 enet0: ucc@2000 {
528 device_type = "network"; 257 device_type = "network";
529 compatible = "ucc_geth"; 258 compatible = "ucc_geth";
530 cell-index = <1>;
531 reg = <0x2000 0x200>;
532 interrupts = <32>;
533 interrupt-parent = <&qeic>;
534 local-mac-address = [ 00 00 00 00 00 00 ]; 259 local-mac-address = [ 00 00 00 00 00 00 ];
535 rx-clock-name = "none"; 260 rx-clock-name = "none";
536 tx-clock-name = "clk12"; 261 tx-clock-name = "clk12";
@@ -548,35 +273,33 @@
548 273
549 qe_phy0: ethernet-phy@07 { 274 qe_phy0: ethernet-phy@07 {
550 interrupt-parent = <&mpic>; 275 interrupt-parent = <&mpic>;
551 interrupts = <1 1>; 276 interrupts = <1 1 0 0>;
552 reg = <0x7>; 277 reg = <0x7>;
553 device_type = "ethernet-phy"; 278 device_type = "ethernet-phy";
554 }; 279 };
555 qe_phy1: ethernet-phy@01 { 280 qe_phy1: ethernet-phy@01 {
556 interrupt-parent = <&mpic>; 281 interrupt-parent = <&mpic>;
557 interrupts = <2 1>; 282 interrupts = <2 1 0 0>;
558 reg = <0x1>; 283 reg = <0x1>;
559 device_type = "ethernet-phy"; 284 device_type = "ethernet-phy";
560 }; 285 };
561 qe_phy2: ethernet-phy@02 { 286 qe_phy2: ethernet-phy@02 {
562 interrupt-parent = <&mpic>; 287 interrupt-parent = <&mpic>;
563 interrupts = <3 1>; 288 interrupts = <3 1 0 0>;
564 reg = <0x2>; 289 reg = <0x2>;
565 device_type = "ethernet-phy"; 290 device_type = "ethernet-phy";
566 }; 291 };
567 qe_phy3: ethernet-phy@03 { 292 qe_phy3: ethernet-phy@03 {
568 interrupt-parent = <&mpic>; 293 interrupt-parent = <&mpic>;
569 interrupts = <4 1>; 294 interrupts = <4 1 0 0>;
570 reg = <0x3>; 295 reg = <0x3>;
571 device_type = "ethernet-phy"; 296 device_type = "ethernet-phy";
572 }; 297 };
573 qe_phy5: ethernet-phy@04 { 298 qe_phy5: ethernet-phy@04 {
574 interrupt-parent = <&mpic>;
575 reg = <0x04>; 299 reg = <0x04>;
576 device_type = "ethernet-phy"; 300 device_type = "ethernet-phy";
577 }; 301 };
578 qe_phy7: ethernet-phy@06 { 302 qe_phy7: ethernet-phy@06 {
579 interrupt-parent = <&mpic>;
580 reg = <0x6>; 303 reg = <0x6>;
581 device_type = "ethernet-phy"; 304 device_type = "ethernet-phy";
582 }; 305 };
@@ -610,10 +333,6 @@
610 enet2: ucc@2200 { 333 enet2: ucc@2200 {
611 device_type = "network"; 334 device_type = "network";
612 compatible = "ucc_geth"; 335 compatible = "ucc_geth";
613 cell-index = <3>;
614 reg = <0x2200 0x200>;
615 interrupts = <34>;
616 interrupt-parent = <&qeic>;
617 local-mac-address = [ 00 00 00 00 00 00 ]; 336 local-mac-address = [ 00 00 00 00 00 00 ];
618 rx-clock-name = "none"; 337 rx-clock-name = "none";
619 tx-clock-name = "clk12"; 338 tx-clock-name = "clk12";
@@ -637,10 +356,6 @@
637 enet1: ucc@3000 { 356 enet1: ucc@3000 {
638 device_type = "network"; 357 device_type = "network";
639 compatible = "ucc_geth"; 358 compatible = "ucc_geth";
640 cell-index = <2>;
641 reg = <0x3000 0x200>;
642 interrupts = <33>;
643 interrupt-parent = <&qeic>;
644 local-mac-address = [ 00 00 00 00 00 00 ]; 359 local-mac-address = [ 00 00 00 00 00 00 ];
645 rx-clock-name = "none"; 360 rx-clock-name = "none";
646 tx-clock-name = "clk17"; 361 tx-clock-name = "clk17";
@@ -664,10 +379,6 @@
664 enet3: ucc@3200 { 379 enet3: ucc@3200 {
665 device_type = "network"; 380 device_type = "network";
666 compatible = "ucc_geth"; 381 compatible = "ucc_geth";
667 cell-index = <4>;
668 reg = <0x3200 0x200>;
669 interrupts = <35>;
670 interrupt-parent = <&qeic>;
671 local-mac-address = [ 00 00 00 00 00 00 ]; 382 local-mac-address = [ 00 00 00 00 00 00 ];
672 rx-clock-name = "none"; 383 rx-clock-name = "none";
673 tx-clock-name = "clk17"; 384 tx-clock-name = "clk17";
@@ -691,10 +402,6 @@
691 enet5: ucc@3400 { 402 enet5: ucc@3400 {
692 device_type = "network"; 403 device_type = "network";
693 compatible = "ucc_geth"; 404 compatible = "ucc_geth";
694 cell-index = <6>;
695 reg = <0x3400 0x200>;
696 interrupts = <41>;
697 interrupt-parent = <&qeic>;
698 local-mac-address = [ 00 00 00 00 00 00 ]; 405 local-mac-address = [ 00 00 00 00 00 00 ];
699 rx-clock-name = "none"; 406 rx-clock-name = "none";
700 tx-clock-name = "none"; 407 tx-clock-name = "none";
@@ -706,10 +413,6 @@
706 enet7: ucc@3600 { 413 enet7: ucc@3600 {
707 device_type = "network"; 414 device_type = "network";
708 compatible = "ucc_geth"; 415 compatible = "ucc_geth";
709 cell-index = <8>;
710 reg = <0x3600 0x200>;
711 interrupts = <43>;
712 interrupt-parent = <&qeic>;
713 local-mac-address = [ 00 00 00 00 00 00 ]; 416 local-mac-address = [ 00 00 00 00 00 00 ];
714 rx-clock-name = "none"; 417 rx-clock-name = "none";
715 tx-clock-name = "none"; 418 tx-clock-name = "none";
@@ -717,50 +420,14 @@
717 phy-handle = <&qe_phy7>; 420 phy-handle = <&qe_phy7>;
718 phy-connection-type = "sgmii"; 421 phy-connection-type = "sgmii";
719 }; 422 };
720
721 muram@10000 {
722 #address-cells = <1>;
723 #size-cells = <1>;
724 compatible = "fsl,qe-muram", "fsl,cpm-muram";
725 ranges = <0x0 0x10000 0x20000>;
726
727 data-only@0 {
728 compatible = "fsl,qe-muram-data",
729 "fsl,cpm-muram-data";
730 reg = <0x0 0x20000>;
731 };
732 };
733
734 }; 423 };
735 424
736 /* PCI Express */ 425 /* PCI Express */
737 pci1: pcie@e000a000 { 426 pci1: pcie@e000a000 {
738 compatible = "fsl,mpc8548-pcie"; 427 reg = <0x0 0xe000a000 0x0 0x1000>;
739 device_type = "pci"; 428 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
740 #interrupt-cells = <1>; 429 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xe000a000 0x1000>;
744 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
745 interrupt-map = <
746 /* IDSEL 0x0 (PEX) */
747 00000 0x0 0x0 0x1 &mpic 0x0 0x1
748 00000 0x0 0x0 0x2 &mpic 0x1 0x1
749 00000 0x0 0x0 0x3 &mpic 0x2 0x1
750 00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
751
752 interrupt-parent = <&mpic>;
753 interrupts = <26 2>;
754 bus-range = <0 255>;
755 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
756 0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
757 sleep = <&pmc 0x20000000>;
758 clock-frequency = <33333333>;
759 pcie@0 { 430 pcie@0 {
760 reg = <0x0 0x0 0x0 0x0 0x0>;
761 #size-cells = <2>;
762 #address-cells = <3>;
763 device_type = "pci";
764 ranges = <0x2000000 0x0 0xa0000000 431 ranges = <0x2000000 0x0 0xa0000000
765 0x2000000 0x0 0xa0000000 432 0x2000000 0x0 0xa0000000
766 0x0 0x10000000 433 0x0 0x10000000
@@ -771,20 +438,15 @@
771 }; 438 };
772 }; 439 };
773 440
774 rio0: rapidio@e00c00000 { 441 rio: rapidio@e00c00000 {
775 #address-cells = <2>; 442 reg = <0x0 0xe00c0000 0x0 0x20000>;
776 #size-cells = <2>; 443 port1 {
777 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta"; 444 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
778 reg = <0xe00c0000 0x20000>; 445 };
779 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>; 446 port2 {
780 interrupts = <48 2 /* error */ 447 status = "disabled";
781 49 2 /* bell_outb */ 448 };
782 50 2 /* bell_inb */
783 53 2 /* msg1_tx */
784 54 2 /* msg1_rx */
785 55 2 /* msg2_tx */
786 56 2 /* msg2_rx */>;
787 interrupt-parent = <&mpic>;
788 sleep = <&pmc 0x00080000>;
789 }; 449 };
790}; 450};
451
452/include/ "fsl/mpc8569si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index f6c04d25e916..0c9f2955deb4 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -9,67 +9,18 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8572si-pre.dtsi"
13
13/ { 14/ {
14 model = "fsl,MPC8572DS"; 15 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS"; 16 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61 17
62 memory { 18 memory {
63 device_type = "memory"; 19 device_type = "memory";
64 }; 20 };
65 21
66 localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0 0xffe05000 0 0x1000>; 23 reg = <0 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73 24
74 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 25 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
75 0x1 0x0 0x0 0xe0000000 0x08000000 26 0x1 0x0 0x0 0xe0000000 0x08000000
@@ -78,601 +29,17 @@
78 0x4 0x0 0x0 0xffa40000 0x00040000 29 0x4 0x0 0x0 0xffa40000 0x00040000
79 0x5 0x0 0x0 0xffa80000 0x00040000 30 0x5 0x0 0x0 0xffa80000 0x00040000
80 0x6 0x0 0x0 0xffac0000 0x00040000>; 31 0x6 0x0 0x0 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 }; 32 };
178 33
179 soc8572@ffe00000 { 34 board_soc: soc: soc8572@ffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0 0xffe00000 0x100000>; 35 ranges = <0x0 0 0xffe00000 0x100000>;
185 bus-frequency = <0>; // Filled out by uboot.
186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
200 memory-controller@2000 {
201 compatible = "fsl,mpc8572-memory-controller";
202 reg = <0x2000 0x1000>;
203 interrupt-parent = <&mpic>;
204 interrupts = <18 2>;
205 };
206
207 memory-controller@6000 {
208 compatible = "fsl,mpc8572-memory-controller";
209 reg = <0x6000 0x1000>;
210 interrupt-parent = <&mpic>;
211 interrupts = <18 2>;
212 };
213
214 L2: l2-cache-controller@20000 {
215 compatible = "fsl,mpc8572-l2-cache-controller";
216 reg = <0x20000 0x1000>;
217 cache-line-size = <32>; // 32 bytes
218 cache-size = <0x100000>; // L2, 1M
219 interrupt-parent = <&mpic>;
220 interrupts = <16 2>;
221 };
222
223 i2c@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cell-index = <0>;
227 compatible = "fsl-i2c";
228 reg = <0x3000 0x100>;
229 interrupts = <43 2>;
230 interrupt-parent = <&mpic>;
231 dfsrr;
232 };
233
234 i2c@3100 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
239 reg = <0x3100 0x100>;
240 interrupts = <43 2>;
241 interrupt-parent = <&mpic>;
242 dfsrr;
243 };
244
245 dma@c300 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
249 reg = <0xc300 0x4>;
250 ranges = <0x0 0xc100 0x200>;
251 cell-index = <1>;
252 dma-channel@0 {
253 compatible = "fsl,mpc8572-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x0 0x80>;
256 cell-index = <0>;
257 interrupt-parent = <&mpic>;
258 interrupts = <76 2>;
259 };
260 dma-channel@80 {
261 compatible = "fsl,mpc8572-dma-channel",
262 "fsl,eloplus-dma-channel";
263 reg = <0x80 0x80>;
264 cell-index = <1>;
265 interrupt-parent = <&mpic>;
266 interrupts = <77 2>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,mpc8572-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupt-parent = <&mpic>;
274 interrupts = <78 2>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,mpc8572-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupt-parent = <&mpic>;
282 interrupts = <79 2>;
283 };
284 };
285
286 dma@21300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0x21300 0x4>;
291 ranges = <0x0 0x21100 0x200>;
292 cell-index = <0>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <20 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <21 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <22 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <23 2>;
324 };
325 };
326
327 ptp_clock@24E00 {
328 compatible = "fsl,etsec-ptp";
329 reg = <0x24E00 0xB0>;
330 interrupts = <68 2 69 2 70 2 71 2>;
331 interrupt-parent = < &mpic >;
332 fsl,tclk-period = <5>;
333 fsl,tmr-prsc = <200>;
334 fsl,tmr-add = <0xAAAAAAAB>;
335 fsl,tmr-fiper1 = <0x3B9AC9FB>;
336 fsl,tmr-fiper2 = <0x3B9AC9FB>;
337 fsl,max-adj = <499999999>;
338 };
339
340 enet0: ethernet@24000 {
341 #address-cells = <1>;
342 #size-cells = <1>;
343 cell-index = <0>;
344 device_type = "network";
345 model = "eTSEC";
346 compatible = "gianfar";
347 reg = <0x24000 0x1000>;
348 ranges = <0x0 0x24000 0x1000>;
349 local-mac-address = [ 00 00 00 00 00 00 ];
350 interrupts = <29 2 30 2 34 2>;
351 interrupt-parent = <&mpic>;
352 tbi-handle = <&tbi0>;
353 phy-handle = <&phy0>;
354 phy-connection-type = "rgmii-id";
355
356 mdio@520 {
357 #address-cells = <1>;
358 #size-cells = <0>;
359 compatible = "fsl,gianfar-mdio";
360 reg = <0x520 0x20>;
361
362 phy0: ethernet-phy@0 {
363 interrupt-parent = <&mpic>;
364 interrupts = <10 1>;
365 reg = <0x0>;
366 };
367 phy1: ethernet-phy@1 {
368 interrupt-parent = <&mpic>;
369 interrupts = <10 1>;
370 reg = <0x1>;
371 };
372 phy2: ethernet-phy@2 {
373 interrupt-parent = <&mpic>;
374 interrupts = <10 1>;
375 reg = <0x2>;
376 };
377 phy3: ethernet-phy@3 {
378 interrupt-parent = <&mpic>;
379 interrupts = <10 1>;
380 reg = <0x3>;
381 };
382
383 tbi0: tbi-phy@11 {
384 reg = <0x11>;
385 device_type = "tbi-phy";
386 };
387 };
388 };
389
390 enet1: ethernet@25000 {
391 #address-cells = <1>;
392 #size-cells = <1>;
393 cell-index = <1>;
394 device_type = "network";
395 model = "eTSEC";
396 compatible = "gianfar";
397 reg = <0x25000 0x1000>;
398 ranges = <0x0 0x25000 0x1000>;
399 local-mac-address = [ 00 00 00 00 00 00 ];
400 interrupts = <35 2 36 2 40 2>;
401 interrupt-parent = <&mpic>;
402 tbi-handle = <&tbi1>;
403 phy-handle = <&phy1>;
404 phy-connection-type = "rgmii-id";
405
406 mdio@520 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "fsl,gianfar-tbi";
410 reg = <0x520 0x20>;
411
412 tbi1: tbi-phy@11 {
413 reg = <0x11>;
414 device_type = "tbi-phy";
415 };
416 };
417 };
418
419 enet2: ethernet@26000 {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 cell-index = <2>;
423 device_type = "network";
424 model = "eTSEC";
425 compatible = "gianfar";
426 reg = <0x26000 0x1000>;
427 ranges = <0x0 0x26000 0x1000>;
428 local-mac-address = [ 00 00 00 00 00 00 ];
429 interrupts = <31 2 32 2 33 2>;
430 interrupt-parent = <&mpic>;
431 tbi-handle = <&tbi2>;
432 phy-handle = <&phy2>;
433 phy-connection-type = "rgmii-id";
434
435 mdio@520 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "fsl,gianfar-tbi";
439 reg = <0x520 0x20>;
440
441 tbi2: tbi-phy@11 {
442 reg = <0x11>;
443 device_type = "tbi-phy";
444 };
445 };
446 };
447
448 enet3: ethernet@27000 {
449 #address-cells = <1>;
450 #size-cells = <1>;
451 cell-index = <3>;
452 device_type = "network";
453 model = "eTSEC";
454 compatible = "gianfar";
455 reg = <0x27000 0x1000>;
456 ranges = <0x0 0x27000 0x1000>;
457 local-mac-address = [ 00 00 00 00 00 00 ];
458 interrupts = <37 2 38 2 39 2>;
459 interrupt-parent = <&mpic>;
460 tbi-handle = <&tbi3>;
461 phy-handle = <&phy3>;
462 phy-connection-type = "rgmii-id";
463
464 mdio@520 {
465 #address-cells = <1>;
466 #size-cells = <0>;
467 compatible = "fsl,gianfar-tbi";
468 reg = <0x520 0x20>;
469
470 tbi3: tbi-phy@11 {
471 reg = <0x11>;
472 device_type = "tbi-phy";
473 };
474 };
475 };
476
477 serial0: serial@4500 {
478 cell-index = <0>;
479 device_type = "serial";
480 compatible = "ns16550";
481 reg = <0x4500 0x100>;
482 clock-frequency = <0>;
483 interrupts = <42 2>;
484 interrupt-parent = <&mpic>;
485 };
486
487 serial1: serial@4600 {
488 cell-index = <1>;
489 device_type = "serial";
490 compatible = "ns16550";
491 reg = <0x4600 0x100>;
492 clock-frequency = <0>;
493 interrupts = <42 2>;
494 interrupt-parent = <&mpic>;
495 };
496
497 global-utilities@e0000 { //global utilities block
498 compatible = "fsl,mpc8572-guts";
499 reg = <0xe0000 0x1000>;
500 fsl,has-rstcr;
501 };
502
503 msi@41600 {
504 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
505 reg = <0x41600 0x80>;
506 msi-available-ranges = <0 0x100>;
507 interrupts = <
508 0xe0 0
509 0xe1 0
510 0xe2 0
511 0xe3 0
512 0xe4 0
513 0xe5 0
514 0xe6 0
515 0xe7 0>;
516 interrupt-parent = <&mpic>;
517 };
518
519 crypto@30000 {
520 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
521 "fsl,sec2.1", "fsl,sec2.0";
522 reg = <0x30000 0x10000>;
523 interrupts = <45 2 58 2>;
524 interrupt-parent = <&mpic>;
525 fsl,num-channels = <4>;
526 fsl,channel-fifo-len = <24>;
527 fsl,exec-units-mask = <0x9fe>;
528 fsl,descriptor-types-mask = <0x3ab0ebf>;
529 };
530
531 mpic: pic@40000 {
532 interrupt-controller;
533 #address-cells = <0>;
534 #interrupt-cells = <2>;
535 reg = <0x40000 0x40000>;
536 compatible = "chrp,open-pic";
537 device_type = "open-pic";
538 };
539 }; 36 };
540 37
541 pci0: pcie@ffe08000 { 38 board_pci0: pci0: pcie@ffe08000 {
542 compatible = "fsl,mpc8548-pcie";
543 device_type = "pci";
544 #interrupt-cells = <1>;
545 #size-cells = <2>;
546 #address-cells = <3>;
547 reg = <0 0xffe08000 0 0x1000>; 39 reg = <0 0xffe08000 0 0x1000>;
548 bus-range = <0 255>;
549 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 40 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
550 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>; 41 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
551 clock-frequency = <33333333>;
552 interrupt-parent = <&mpic>;
553 interrupts = <24 2>;
554 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
555 interrupt-map = <
556 /* IDSEL 0x11 func 0 - PCI slot 1 */
557 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
558 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
559 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
560 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
561
562 /* IDSEL 0x11 func 1 - PCI slot 1 */
563 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
564 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
565 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
566 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
567
568 /* IDSEL 0x11 func 2 - PCI slot 1 */
569 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
570 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
571 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
572 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
573
574 /* IDSEL 0x11 func 3 - PCI slot 1 */
575 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
576 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
577 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
578 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
579
580 /* IDSEL 0x11 func 4 - PCI slot 1 */
581 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
582 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
583 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
584 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
585
586 /* IDSEL 0x11 func 5 - PCI slot 1 */
587 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
588 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
589 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
590 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
591
592 /* IDSEL 0x11 func 6 - PCI slot 1 */
593 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
594 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
595 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
596 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
597
598 /* IDSEL 0x11 func 7 - PCI slot 1 */
599 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
600 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
601 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
602 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
603
604 /* IDSEL 0x12 func 0 - PCI slot 2 */
605 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
606 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
607 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
608 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
609
610 /* IDSEL 0x12 func 1 - PCI slot 2 */
611 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
612 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
613 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
614 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
615
616 /* IDSEL 0x12 func 2 - PCI slot 2 */
617 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
618 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
619 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
620 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
621
622 /* IDSEL 0x12 func 3 - PCI slot 2 */
623 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
624 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
625 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
626 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
627
628 /* IDSEL 0x12 func 4 - PCI slot 2 */
629 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
630 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
631 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
632 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
633
634 /* IDSEL 0x12 func 5 - PCI slot 2 */
635 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
636 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
637 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
638 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
639
640 /* IDSEL 0x12 func 6 - PCI slot 2 */
641 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
642 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
643 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
644 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
645
646 /* IDSEL 0x12 func 7 - PCI slot 2 */
647 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
648 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
649 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
650 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
651
652 // IDSEL 0x1c USB
653 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
654 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
655 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
656 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
657
658 // IDSEL 0x1d Audio
659 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
660
661 // IDSEL 0x1e Legacy
662 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
663 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
664
665 // IDSEL 0x1f IDE/SATA
666 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
667 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
668
669 >;
670
671 pcie@0 { 42 pcie@0 {
672 reg = <0x0 0x0 0x0 0x0 0x0>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 device_type = "pci";
676 ranges = <0x2000000 0x0 0x80000000 43 ranges = <0x2000000 0x0 0x80000000
677 0x2000000 0x0 0x80000000 44 0x2000000 0x0 0x80000000
678 0x0 0x20000000 45 0x0 0x20000000
@@ -680,99 +47,14 @@
680 0x1000000 0x0 0x0 47 0x1000000 0x0 0x0
681 0x1000000 0x0 0x0 48 0x1000000 0x0 0x0
682 0x0 0x10000>; 49 0x0 0x10000>;
683 uli1575@0 {
684 reg = <0x0 0x0 0x0 0x0 0x0>;
685 #size-cells = <2>;
686 #address-cells = <3>;
687 ranges = <0x2000000 0x0 0x80000000
688 0x2000000 0x0 0x80000000
689 0x0 0x20000000
690
691 0x1000000 0x0 0x0
692 0x1000000 0x0 0x0
693 0x0 0x10000>;
694 isa@1e {
695 device_type = "isa";
696 #interrupt-cells = <2>;
697 #size-cells = <1>;
698 #address-cells = <2>;
699 reg = <0xf000 0x0 0x0 0x0 0x0>;
700 ranges = <0x1 0x0 0x1000000 0x0 0x0
701 0x1000>;
702 interrupt-parent = <&i8259>;
703
704 i8259: interrupt-controller@20 {
705 reg = <0x1 0x20 0x2
706 0x1 0xa0 0x2
707 0x1 0x4d0 0x2>;
708 interrupt-controller;
709 device_type = "interrupt-controller";
710 #address-cells = <0>;
711 #interrupt-cells = <2>;
712 compatible = "chrp,iic";
713 interrupts = <9 2>;
714 interrupt-parent = <&mpic>;
715 };
716
717 i8042@60 {
718 #size-cells = <0>;
719 #address-cells = <1>;
720 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
721 interrupts = <1 3 12 3>;
722 interrupt-parent =
723 <&i8259>;
724
725 keyboard@0 {
726 reg = <0x0>;
727 compatible = "pnpPNP,303";
728 };
729
730 mouse@1 {
731 reg = <0x1>;
732 compatible = "pnpPNP,f03";
733 };
734 };
735
736 rtc@70 {
737 compatible = "pnpPNP,b00";
738 reg = <0x1 0x70 0x2>;
739 };
740
741 gpio@400 {
742 reg = <0x1 0x400 0x80>;
743 };
744 };
745 };
746 }; 50 };
747
748 }; 51 };
749 52
750 pci1: pcie@ffe09000 { 53 pci1: pcie@ffe09000 {
751 compatible = "fsl,mpc8548-pcie";
752 device_type = "pci";
753 #interrupt-cells = <1>;
754 #size-cells = <2>;
755 #address-cells = <3>;
756 reg = <0 0xffe09000 0 0x1000>; 54 reg = <0 0xffe09000 0 0x1000>;
757 bus-range = <0 255>;
758 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 55 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
759 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>; 56 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
760 clock-frequency = <33333333>;
761 interrupt-parent = <&mpic>;
762 interrupts = <25 2>;
763 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
764 interrupt-map = <
765 /* IDSEL 0x0 */
766 0000 0x0 0x0 0x1 &mpic 0x4 0x1
767 0000 0x0 0x0 0x2 &mpic 0x5 0x1
768 0000 0x0 0x0 0x3 &mpic 0x6 0x1
769 0000 0x0 0x0 0x4 &mpic 0x7 0x1
770 >;
771 pcie@0 { 57 pcie@0 {
772 reg = <0x0 0x0 0x0 0x0 0x0>;
773 #size-cells = <2>;
774 #address-cells = <3>;
775 device_type = "pci";
776 ranges = <0x2000000 0x0 0xa0000000 58 ranges = <0x2000000 0x0 0xa0000000
777 0x2000000 0x0 0xa0000000 59 0x2000000 0x0 0xa0000000
778 0x0 0x20000000 60 0x0 0x20000000
@@ -784,31 +66,10 @@
784 }; 66 };
785 67
786 pci2: pcie@ffe0a000 { 68 pci2: pcie@ffe0a000 {
787 compatible = "fsl,mpc8548-pcie";
788 device_type = "pci";
789 #interrupt-cells = <1>;
790 #size-cells = <2>;
791 #address-cells = <3>;
792 reg = <0 0xffe0a000 0 0x1000>; 69 reg = <0 0xffe0a000 0 0x1000>;
793 bus-range = <0 255>;
794 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 70 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
795 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>; 71 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
796 clock-frequency = <33333333>;
797 interrupt-parent = <&mpic>;
798 interrupts = <26 2>;
799 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
800 interrupt-map = <
801 /* IDSEL 0x0 */
802 0000 0x0 0x0 0x1 &mpic 0x0 0x1
803 0000 0x0 0x0 0x2 &mpic 0x1 0x1
804 0000 0x0 0x0 0x3 &mpic 0x2 0x1
805 0000 0x0 0x0 0x4 &mpic 0x3 0x1
806 >;
807 pcie@0 { 72 pcie@0 {
808 reg = <0x0 0x0 0x0 0x0 0x0>;
809 #size-cells = <2>;
810 #address-cells = <3>;
811 device_type = "pci";
812 ranges = <0x2000000 0x0 0xc0000000 73 ranges = <0x2000000 0x0 0xc0000000
813 0x2000000 0x0 0xc0000000 74 0x2000000 0x0 0xc0000000
814 0x0 0x20000000 75 0x0 0x20000000
@@ -819,3 +80,11 @@
819 }; 80 };
820 }; 81 };
821}; 82};
83
84/*
85 * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
86 * for interrupt-map & interrupt-map-mask
87 */
88
89/include/ "fsl/mpc8572si-post.dtsi"
90/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
new file mode 100644
index 000000000000..c3d4fac0532a
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -0,0 +1,397 @@
1/*
2 * MPC8572DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
46 read-only;
47 };
48
49 diagnostic@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 read-only;
52 };
53
54 dink@3e00000 {
55 reg = <0x03e00000 0x00200000>;
56 read-only;
57 };
58
59 kernel@4000000 {
60 reg = <0x04000000 0x00400000>;
61 read-only;
62 };
63
64 jffs2@4400000 {
65 reg = <0x04400000 0x03b00000>;
66 };
67
68 dtb@7f00000 {
69 reg = <0x07f00000 0x00080000>;
70 read-only;
71 };
72
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
76 };
77 };
78
79 nand@2,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,mpc8572-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <0x2 0x0 0x40000>;
85
86 u-boot@0 {
87 reg = <0x0 0x02000000>;
88 read-only;
89 };
90
91 jffs2@2000000 {
92 reg = <0x02000000 0x10000000>;
93 };
94
95 ramdisk@12000000 {
96 reg = <0x12000000 0x08000000>;
97 read-only;
98 };
99
100 kernel@1a000000 {
101 reg = <0x1a000000 0x04000000>;
102 };
103
104 dtb@1e000000 {
105 reg = <0x1e000000 0x01000000>;
106 read-only;
107 };
108
109 empty@1f000000 {
110 reg = <0x1f000000 0x21000000>;
111 };
112 };
113
114 nand@4,0 {
115 compatible = "fsl,mpc8572-fcm-nand",
116 "fsl,elbc-fcm-nand";
117 reg = <0x4 0x0 0x40000>;
118 };
119
120 nand@5,0 {
121 compatible = "fsl,mpc8572-fcm-nand",
122 "fsl,elbc-fcm-nand";
123 reg = <0x5 0x0 0x40000>;
124 };
125
126 nand@6,0 {
127 compatible = "fsl,mpc8572-fcm-nand",
128 "fsl,elbc-fcm-nand";
129 reg = <0x6 0x0 0x40000>;
130 };
131};
132
133&board_soc {
134 enet0: ethernet@24000 {
135 tbi-handle = <&tbi0>;
136 phy-handle = <&phy0>;
137 phy-connection-type = "rgmii-id";
138 };
139
140 mdio@24520 {
141 phy0: ethernet-phy@0 {
142 interrupts = <10 1 0 0>;
143 reg = <0x0>;
144 };
145 phy1: ethernet-phy@1 {
146 interrupts = <10 1 0 0>;
147 reg = <0x1>;
148 };
149 phy2: ethernet-phy@2 {
150 interrupts = <10 1 0 0>;
151 reg = <0x2>;
152 };
153 phy3: ethernet-phy@3 {
154 interrupts = <10 1 0 0>;
155 reg = <0x3>;
156 };
157
158 tbi0: tbi-phy@11 {
159 reg = <0x11>;
160 device_type = "tbi-phy";
161 };
162 };
163
164 ptp_clock@24e00 {
165 fsl,tclk-period = <5>;
166 fsl,tmr-prsc = <200>;
167 fsl,tmr-add = <0xAAAAAAAB>;
168 fsl,tmr-fiper1 = <0x3B9AC9FB>;
169 fsl,tmr-fiper2 = <0x3B9AC9FB>;
170 fsl,max-adj = <499999999>;
171 };
172
173 enet1: ethernet@25000 {
174 tbi-handle = <&tbi1>;
175 phy-handle = <&phy1>;
176 phy-connection-type = "rgmii-id";
177
178 };
179
180 mdio@25520 {
181 tbi1: tbi-phy@11 {
182 reg = <0x11>;
183 device_type = "tbi-phy";
184 };
185 };
186
187 enet2: ethernet@26000 {
188 tbi-handle = <&tbi2>;
189 phy-handle = <&phy2>;
190 phy-connection-type = "rgmii-id";
191
192 };
193 mdio@26520 {
194 tbi2: tbi-phy@11 {
195 reg = <0x11>;
196 device_type = "tbi-phy";
197 };
198 };
199
200 enet3: ethernet@27000 {
201 tbi-handle = <&tbi3>;
202 phy-handle = <&phy3>;
203 phy-connection-type = "rgmii-id";
204 };
205
206 mdio@27520 {
207 tbi3: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
210 };
211 };
212};
213
214&board_pci0 {
215 pcie@0 {
216 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
217 interrupt-map = <
218 /* IDSEL 0x11 func 0 - PCI slot 1 */
219 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
220 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
221 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
222 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
223
224 /* IDSEL 0x11 func 1 - PCI slot 1 */
225 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
226 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
227 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
228 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
229
230 /* IDSEL 0x11 func 2 - PCI slot 1 */
231 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
232 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
233 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
234 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
235
236 /* IDSEL 0x11 func 3 - PCI slot 1 */
237 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
238 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
239 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
240 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
241
242 /* IDSEL 0x11 func 4 - PCI slot 1 */
243 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
244 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
245 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
246 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
247
248 /* IDSEL 0x11 func 5 - PCI slot 1 */
249 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
250 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
251 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
252 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
253
254 /* IDSEL 0x11 func 6 - PCI slot 1 */
255 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
256 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
257 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
258 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
259
260 /* IDSEL 0x11 func 7 - PCI slot 1 */
261 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
262 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
263 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
264 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
265
266 /* IDSEL 0x12 func 0 - PCI slot 2 */
267 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
268 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
269 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
270 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
271
272 /* IDSEL 0x12 func 1 - PCI slot 2 */
273 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
274 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
275 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
276 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
277
278 /* IDSEL 0x12 func 2 - PCI slot 2 */
279 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
280 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
281 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
282 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
283
284 /* IDSEL 0x12 func 3 - PCI slot 2 */
285 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
286 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
287 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
288 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
289
290 /* IDSEL 0x12 func 4 - PCI slot 2 */
291 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
292 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
293 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
294 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
295
296 /* IDSEL 0x12 func 5 - PCI slot 2 */
297 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
298 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
299 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
300 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
301
302 /* IDSEL 0x12 func 6 - PCI slot 2 */
303 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
304 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
305 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
306 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
307
308 /* IDSEL 0x12 func 7 - PCI slot 2 */
309 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
310 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
311 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
312 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1 0 0
313
314 // IDSEL 0x1c USB
315 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
316 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
317 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
318 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
319
320 // IDSEL 0x1d Audio
321 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
322
323 // IDSEL 0x1e Legacy
324 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
325 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
326
327 // IDSEL 0x1f IDE/SATA
328 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
329 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
330 >;
331
332
333 uli1575@0 {
334 reg = <0x0 0x0 0x0 0x0 0x0>;
335 #size-cells = <2>;
336 #address-cells = <3>;
337 ranges = <0x2000000 0x0 0x80000000
338 0x2000000 0x0 0x80000000
339 0x0 0x20000000
340
341 0x1000000 0x0 0x0
342 0x1000000 0x0 0x0
343 0x0 0x10000>;
344 isa@1e {
345 device_type = "isa";
346 #interrupt-cells = <2>;
347 #size-cells = <1>;
348 #address-cells = <2>;
349 reg = <0xf000 0x0 0x0 0x0 0x0>;
350 ranges = <0x1 0x0 0x1000000 0x0 0x0
351 0x1000>;
352 interrupt-parent = <&i8259>;
353
354 i8259: interrupt-controller@20 {
355 reg = <0x1 0x20 0x2
356 0x1 0xa0 0x2
357 0x1 0x4d0 0x2>;
358 interrupt-controller;
359 device_type = "interrupt-controller";
360 #address-cells = <0>;
361 #interrupt-cells = <2>;
362 compatible = "chrp,iic";
363 interrupts = <9 2 0 0>;
364 interrupt-parent = <&mpic>;
365 };
366
367 i8042@60 {
368 #size-cells = <0>;
369 #address-cells = <1>;
370 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
371 interrupts = <1 3 12 3>;
372 interrupt-parent =
373 <&i8259>;
374
375 keyboard@0 {
376 reg = <0x0>;
377 compatible = "pnpPNP,303";
378 };
379
380 mouse@1 {
381 reg = <0x1>;
382 compatible = "pnpPNP,f03";
383 };
384 };
385
386 rtc@70 {
387 compatible = "pnpPNP,b00";
388 reg = <0x1 0x70 0x2>;
389 };
390
391 gpio@400 {
392 reg = <0x1 0x400 0x80>;
393 };
394 };
395 };
396 };
397};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_36b.dts b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
index f6365db3b97d..6c3d0b305e1b 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_36b.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * MPC8572 DS Device Tree Source 2 * MPC8572DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc. 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 * 5 *
@@ -9,67 +9,18 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/mpc8572si-pre.dtsi"
13
13/ { 14/ {
14 model = "fsl,MPC8572DS"; 15 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS"; 16 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
47
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
61 17
62 memory { 18 memory {
63 device_type = "memory"; 19 device_type = "memory";
64 }; 20 };
65 21
66 localbus@fffe05000 { 22 board_lbc: lbc: localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>; 23 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
73 24
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 25 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000 26 0x1 0x0 0xf 0xe0000000 0x08000000
@@ -78,588 +29,17 @@
78 0x4 0x0 0xf 0xffa40000 0x00040000 29 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000 30 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>; 31 0x6 0x0 0xf 0xffac0000 0x00040000>;
81
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
89
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
94
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
99
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
104
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
109
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
113
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
118
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
124
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
131
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
136
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
140
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
145
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
149
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
154
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
159
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
165
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
171
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 }; 32 };
178 33
179 soc8572@fffe00000 { 34 board_soc: soc: soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>; 35 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 bus-frequency = <0>; // Filled out by uboot.
186
187 ecm-law@0 {
188 compatible = "fsl,ecm-law";
189 reg = <0x0 0x1000>;
190 fsl,num-laws = <12>;
191 };
192
193 ecm@1000 {
194 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
195 reg = <0x1000 0x1000>;
196 interrupts = <17 2>;
197 interrupt-parent = <&mpic>;
198 };
199
200 memory-controller@2000 {
201 compatible = "fsl,mpc8572-memory-controller";
202 reg = <0x2000 0x1000>;
203 interrupt-parent = <&mpic>;
204 interrupts = <18 2>;
205 };
206
207 memory-controller@6000 {
208 compatible = "fsl,mpc8572-memory-controller";
209 reg = <0x6000 0x1000>;
210 interrupt-parent = <&mpic>;
211 interrupts = <18 2>;
212 };
213
214 L2: l2-cache-controller@20000 {
215 compatible = "fsl,mpc8572-l2-cache-controller";
216 reg = <0x20000 0x1000>;
217 cache-line-size = <32>; // 32 bytes
218 cache-size = <0x100000>; // L2, 1M
219 interrupt-parent = <&mpic>;
220 interrupts = <16 2>;
221 };
222
223 i2c@3000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 cell-index = <0>;
227 compatible = "fsl-i2c";
228 reg = <0x3000 0x100>;
229 interrupts = <43 2>;
230 interrupt-parent = <&mpic>;
231 dfsrr;
232 };
233
234 i2c@3100 {
235 #address-cells = <1>;
236 #size-cells = <0>;
237 cell-index = <1>;
238 compatible = "fsl-i2c";
239 reg = <0x3100 0x100>;
240 interrupts = <43 2>;
241 interrupt-parent = <&mpic>;
242 dfsrr;
243 };
244
245 dma@c300 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
249 reg = <0xc300 0x4>;
250 ranges = <0x0 0xc100 0x200>;
251 cell-index = <1>;
252 dma-channel@0 {
253 compatible = "fsl,mpc8572-dma-channel",
254 "fsl,eloplus-dma-channel";
255 reg = <0x0 0x80>;
256 cell-index = <0>;
257 interrupt-parent = <&mpic>;
258 interrupts = <76 2>;
259 };
260 dma-channel@80 {
261 compatible = "fsl,mpc8572-dma-channel",
262 "fsl,eloplus-dma-channel";
263 reg = <0x80 0x80>;
264 cell-index = <1>;
265 interrupt-parent = <&mpic>;
266 interrupts = <77 2>;
267 };
268 dma-channel@100 {
269 compatible = "fsl,mpc8572-dma-channel",
270 "fsl,eloplus-dma-channel";
271 reg = <0x100 0x80>;
272 cell-index = <2>;
273 interrupt-parent = <&mpic>;
274 interrupts = <78 2>;
275 };
276 dma-channel@180 {
277 compatible = "fsl,mpc8572-dma-channel",
278 "fsl,eloplus-dma-channel";
279 reg = <0x180 0x80>;
280 cell-index = <3>;
281 interrupt-parent = <&mpic>;
282 interrupts = <79 2>;
283 };
284 };
285
286 dma@21300 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
290 reg = <0x21300 0x4>;
291 ranges = <0x0 0x21100 0x200>;
292 cell-index = <0>;
293 dma-channel@0 {
294 compatible = "fsl,mpc8572-dma-channel",
295 "fsl,eloplus-dma-channel";
296 reg = <0x0 0x80>;
297 cell-index = <0>;
298 interrupt-parent = <&mpic>;
299 interrupts = <20 2>;
300 };
301 dma-channel@80 {
302 compatible = "fsl,mpc8572-dma-channel",
303 "fsl,eloplus-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupt-parent = <&mpic>;
307 interrupts = <21 2>;
308 };
309 dma-channel@100 {
310 compatible = "fsl,mpc8572-dma-channel",
311 "fsl,eloplus-dma-channel";
312 reg = <0x100 0x80>;
313 cell-index = <2>;
314 interrupt-parent = <&mpic>;
315 interrupts = <22 2>;
316 };
317 dma-channel@180 {
318 compatible = "fsl,mpc8572-dma-channel",
319 "fsl,eloplus-dma-channel";
320 reg = <0x180 0x80>;
321 cell-index = <3>;
322 interrupt-parent = <&mpic>;
323 interrupts = <23 2>;
324 };
325 };
326
327 enet0: ethernet@24000 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 cell-index = <0>;
331 device_type = "network";
332 model = "eTSEC";
333 compatible = "gianfar";
334 reg = <0x24000 0x1000>;
335 ranges = <0x0 0x24000 0x1000>;
336 local-mac-address = [ 00 00 00 00 00 00 ];
337 interrupts = <29 2 30 2 34 2>;
338 interrupt-parent = <&mpic>;
339 tbi-handle = <&tbi0>;
340 phy-handle = <&phy0>;
341 phy-connection-type = "rgmii-id";
342
343 mdio@520 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,gianfar-mdio";
347 reg = <0x520 0x20>;
348
349 phy0: ethernet-phy@0 {
350 interrupt-parent = <&mpic>;
351 interrupts = <10 1>;
352 reg = <0x0>;
353 };
354 phy1: ethernet-phy@1 {
355 interrupt-parent = <&mpic>;
356 interrupts = <10 1>;
357 reg = <0x1>;
358 };
359 phy2: ethernet-phy@2 {
360 interrupt-parent = <&mpic>;
361 interrupts = <10 1>;
362 reg = <0x2>;
363 };
364 phy3: ethernet-phy@3 {
365 interrupt-parent = <&mpic>;
366 interrupts = <10 1>;
367 reg = <0x3>;
368 };
369
370 tbi0: tbi-phy@11 {
371 reg = <0x11>;
372 device_type = "tbi-phy";
373 };
374 };
375 };
376
377 enet1: ethernet@25000 {
378 #address-cells = <1>;
379 #size-cells = <1>;
380 cell-index = <1>;
381 device_type = "network";
382 model = "eTSEC";
383 compatible = "gianfar";
384 reg = <0x25000 0x1000>;
385 ranges = <0x0 0x25000 0x1000>;
386 local-mac-address = [ 00 00 00 00 00 00 ];
387 interrupts = <35 2 36 2 40 2>;
388 interrupt-parent = <&mpic>;
389 tbi-handle = <&tbi1>;
390 phy-handle = <&phy1>;
391 phy-connection-type = "rgmii-id";
392
393 mdio@520 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "fsl,gianfar-tbi";
397 reg = <0x520 0x20>;
398
399 tbi1: tbi-phy@11 {
400 reg = <0x11>;
401 device_type = "tbi-phy";
402 };
403 };
404 };
405
406 enet2: ethernet@26000 {
407 #address-cells = <1>;
408 #size-cells = <1>;
409 cell-index = <2>;
410 device_type = "network";
411 model = "eTSEC";
412 compatible = "gianfar";
413 reg = <0x26000 0x1000>;
414 ranges = <0x0 0x26000 0x1000>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
416 interrupts = <31 2 32 2 33 2>;
417 interrupt-parent = <&mpic>;
418 tbi-handle = <&tbi2>;
419 phy-handle = <&phy2>;
420 phy-connection-type = "rgmii-id";
421
422 mdio@520 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,gianfar-tbi";
426 reg = <0x520 0x20>;
427
428 tbi2: tbi-phy@11 {
429 reg = <0x11>;
430 device_type = "tbi-phy";
431 };
432 };
433 };
434
435 enet3: ethernet@27000 {
436 #address-cells = <1>;
437 #size-cells = <1>;
438 cell-index = <3>;
439 device_type = "network";
440 model = "eTSEC";
441 compatible = "gianfar";
442 reg = <0x27000 0x1000>;
443 ranges = <0x0 0x27000 0x1000>;
444 local-mac-address = [ 00 00 00 00 00 00 ];
445 interrupts = <37 2 38 2 39 2>;
446 interrupt-parent = <&mpic>;
447 tbi-handle = <&tbi3>;
448 phy-handle = <&phy3>;
449 phy-connection-type = "rgmii-id";
450
451 mdio@520 {
452 #address-cells = <1>;
453 #size-cells = <0>;
454 compatible = "fsl,gianfar-tbi";
455 reg = <0x520 0x20>;
456
457 tbi3: tbi-phy@11 {
458 reg = <0x11>;
459 device_type = "tbi-phy";
460 };
461 };
462 };
463
464 serial0: serial@4500 {
465 cell-index = <0>;
466 device_type = "serial";
467 compatible = "ns16550";
468 reg = <0x4500 0x100>;
469 clock-frequency = <0>;
470 interrupts = <42 2>;
471 interrupt-parent = <&mpic>;
472 };
473
474 serial1: serial@4600 {
475 cell-index = <1>;
476 device_type = "serial";
477 compatible = "ns16550";
478 reg = <0x4600 0x100>;
479 clock-frequency = <0>;
480 interrupts = <42 2>;
481 interrupt-parent = <&mpic>;
482 };
483
484 global-utilities@e0000 { //global utilities block
485 compatible = "fsl,mpc8572-guts";
486 reg = <0xe0000 0x1000>;
487 fsl,has-rstcr;
488 };
489
490 msi@41600 {
491 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
492 reg = <0x41600 0x80>;
493 msi-available-ranges = <0 0x100>;
494 interrupts = <
495 0xe0 0
496 0xe1 0
497 0xe2 0
498 0xe3 0
499 0xe4 0
500 0xe5 0
501 0xe6 0
502 0xe7 0>;
503 interrupt-parent = <&mpic>;
504 };
505
506 crypto@30000 {
507 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
508 "fsl,sec2.1", "fsl,sec2.0";
509 reg = <0x30000 0x10000>;
510 interrupts = <45 2 58 2>;
511 interrupt-parent = <&mpic>;
512 fsl,num-channels = <4>;
513 fsl,channel-fifo-len = <24>;
514 fsl,exec-units-mask = <0x9fe>;
515 fsl,descriptor-types-mask = <0x3ab0ebf>;
516 };
517
518 mpic: pic@40000 {
519 interrupt-controller;
520 #address-cells = <0>;
521 #interrupt-cells = <2>;
522 reg = <0x40000 0x40000>;
523 compatible = "chrp,open-pic";
524 device_type = "open-pic";
525 };
526 }; 36 };
527 37
528 pci0: pcie@fffe08000 { 38 board_pci0: pci0: pcie@fffe08000 {
529 compatible = "fsl,mpc8548-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xffe08000 0 0x1000>; 39 reg = <0xf 0xffe08000 0 0x1000>;
535 bus-range = <0 255>;
536 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000 40 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>; 41 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
538 clock-frequency = <33333333>;
539 interrupt-parent = <&mpic>;
540 interrupts = <24 2>;
541 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
542 interrupt-map = <
543 /* IDSEL 0x11 func 0 - PCI slot 1 */
544 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
545 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
546 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
547 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
548
549 /* IDSEL 0x11 func 1 - PCI slot 1 */
550 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
551 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
552 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
553 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
554
555 /* IDSEL 0x11 func 2 - PCI slot 1 */
556 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
557 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
558 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
559 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
560
561 /* IDSEL 0x11 func 3 - PCI slot 1 */
562 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
563 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
564 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
565 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
566
567 /* IDSEL 0x11 func 4 - PCI slot 1 */
568 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
569 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
570 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
571 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
572
573 /* IDSEL 0x11 func 5 - PCI slot 1 */
574 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
575 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
576 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
577 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
578
579 /* IDSEL 0x11 func 6 - PCI slot 1 */
580 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
581 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
582 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
583 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
584
585 /* IDSEL 0x11 func 7 - PCI slot 1 */
586 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
587 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
588 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
589 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
590
591 /* IDSEL 0x12 func 0 - PCI slot 2 */
592 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
593 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
594 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
595 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
596
597 /* IDSEL 0x12 func 1 - PCI slot 2 */
598 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
599 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
600 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
601 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
602
603 /* IDSEL 0x12 func 2 - PCI slot 2 */
604 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
605 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
606 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
607 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
608
609 /* IDSEL 0x12 func 3 - PCI slot 2 */
610 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
611 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
612 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
613 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
614
615 /* IDSEL 0x12 func 4 - PCI slot 2 */
616 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
617 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
618 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
619 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
620
621 /* IDSEL 0x12 func 5 - PCI slot 2 */
622 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
623 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
624 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
625 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
626
627 /* IDSEL 0x12 func 6 - PCI slot 2 */
628 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
629 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
630 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
631 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
632
633 /* IDSEL 0x12 func 7 - PCI slot 2 */
634 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
635 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
636 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
637 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
638
639 // IDSEL 0x1c USB
640 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
641 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
642 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
643 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
644
645 // IDSEL 0x1d Audio
646 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
647
648 // IDSEL 0x1e Legacy
649 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
650 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
651
652 // IDSEL 0x1f IDE/SATA
653 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
654 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
655
656 >;
657
658 pcie@0 { 42 pcie@0 {
659 reg = <0x0 0x0 0x0 0x0 0x0>;
660 #size-cells = <2>;
661 #address-cells = <3>;
662 device_type = "pci";
663 ranges = <0x2000000 0x0 0xe0000000 43 ranges = <0x2000000 0x0 0xe0000000
664 0x2000000 0x0 0xe0000000 44 0x2000000 0x0 0xe0000000
665 0x0 0x20000000 45 0x0 0x20000000
@@ -667,99 +47,14 @@
667 0x1000000 0x0 0x0 47 0x1000000 0x0 0x0
668 0x1000000 0x0 0x0 48 0x1000000 0x0 0x0
669 0x0 0x10000>; 49 0x0 0x10000>;
670 uli1575@0 {
671 reg = <0x0 0x0 0x0 0x0 0x0>;
672 #size-cells = <2>;
673 #address-cells = <3>;
674 ranges = <0x2000000 0x0 0xe0000000
675 0x2000000 0x0 0xe0000000
676 0x0 0x20000000
677
678 0x1000000 0x0 0x0
679 0x1000000 0x0 0x0
680 0x0 0x10000>;
681 isa@1e {
682 device_type = "isa";
683 #interrupt-cells = <2>;
684 #size-cells = <1>;
685 #address-cells = <2>;
686 reg = <0xf000 0x0 0x0 0x0 0x0>;
687 ranges = <0x1 0x0 0x1000000 0x0 0x0
688 0x1000>;
689 interrupt-parent = <&i8259>;
690
691 i8259: interrupt-controller@20 {
692 reg = <0x1 0x20 0x2
693 0x1 0xa0 0x2
694 0x1 0x4d0 0x2>;
695 interrupt-controller;
696 device_type = "interrupt-controller";
697 #address-cells = <0>;
698 #interrupt-cells = <2>;
699 compatible = "chrp,iic";
700 interrupts = <9 2>;
701 interrupt-parent = <&mpic>;
702 };
703
704 i8042@60 {
705 #size-cells = <0>;
706 #address-cells = <1>;
707 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
708 interrupts = <1 3 12 3>;
709 interrupt-parent =
710 <&i8259>;
711
712 keyboard@0 {
713 reg = <0x0>;
714 compatible = "pnpPNP,303";
715 };
716
717 mouse@1 {
718 reg = <0x1>;
719 compatible = "pnpPNP,f03";
720 };
721 };
722
723 rtc@70 {
724 compatible = "pnpPNP,b00";
725 reg = <0x1 0x70 0x2>;
726 };
727
728 gpio@400 {
729 reg = <0x1 0x400 0x80>;
730 };
731 };
732 };
733 }; 50 };
734
735 }; 51 };
736 52
737 pci1: pcie@fffe09000 { 53 pci1: pcie@fffe09000 {
738 compatible = "fsl,mpc8548-pcie";
739 device_type = "pci";
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 reg = <0xf 0xffe09000 0 0x1000>; 54 reg = <0xf 0xffe09000 0 0x1000>;
744 bus-range = <0 255>;
745 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 55 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
746 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>; 56 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
747 clock-frequency = <33333333>;
748 interrupt-parent = <&mpic>;
749 interrupts = <25 2>;
750 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
751 interrupt-map = <
752 /* IDSEL 0x0 */
753 0000 0x0 0x0 0x1 &mpic 0x4 0x1
754 0000 0x0 0x0 0x2 &mpic 0x5 0x1
755 0000 0x0 0x0 0x3 &mpic 0x6 0x1
756 0000 0x0 0x0 0x4 &mpic 0x7 0x1
757 >;
758 pcie@0 { 57 pcie@0 {
759 reg = <0x0 0x0 0x0 0x0 0x0>;
760 #size-cells = <2>;
761 #address-cells = <3>;
762 device_type = "pci";
763 ranges = <0x2000000 0x0 0xe0000000 58 ranges = <0x2000000 0x0 0xe0000000
764 0x2000000 0x0 0xe0000000 59 0x2000000 0x0 0xe0000000
765 0x0 0x20000000 60 0x0 0x20000000
@@ -771,31 +66,10 @@
771 }; 66 };
772 67
773 pci2: pcie@fffe0a000 { 68 pci2: pcie@fffe0a000 {
774 compatible = "fsl,mpc8548-pcie";
775 device_type = "pci";
776 #interrupt-cells = <1>;
777 #size-cells = <2>;
778 #address-cells = <3>;
779 reg = <0xf 0xffe0a000 0 0x1000>; 69 reg = <0xf 0xffe0a000 0 0x1000>;
780 bus-range = <0 255>;
781 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000 70 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
782 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>; 71 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
783 clock-frequency = <33333333>;
784 interrupt-parent = <&mpic>;
785 interrupts = <26 2>;
786 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
787 interrupt-map = <
788 /* IDSEL 0x0 */
789 0000 0x0 0x0 0x1 &mpic 0x0 0x1
790 0000 0x0 0x0 0x2 &mpic 0x1 0x1
791 0000 0x0 0x0 0x3 &mpic 0x2 0x1
792 0000 0x0 0x0 0x4 &mpic 0x3 0x1
793 >;
794 pcie@0 { 72 pcie@0 {
795 reg = <0x0 0x0 0x0 0x0 0x0>;
796 #size-cells = <2>;
797 #address-cells = <3>;
798 device_type = "pci";
799 ranges = <0x2000000 0x0 0xe0000000 73 ranges = <0x2000000 0x0 0xe0000000
800 0x2000000 0x0 0xe0000000 74 0x2000000 0x0 0xe0000000
801 0x0 0x20000000 75 0x0 0x20000000
@@ -806,3 +80,11 @@
806 }; 80 };
807 }; 81 };
808}; 82};
83
84/*
85 * mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
86 * for interrupt-map & interrupt-map-mask
87 */
88
89/include/ "fsl/mpc8572si-post.dtsi"
90/include/ "mpc8572ds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 3375c2ab0c32..d34d12712125 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -14,494 +14,69 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/dts-v1/; 17/include/ "mpc8572ds.dts"
18
18/ { 19/ {
19 model = "fsl,MPC8572DS"; 20 model = "fsl,MPC8572DS";
20 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 serial0 = &serial0;
28 pci0 = &pci0;
29 pci1 = &pci1;
30 };
31 22
32 cpus { 23 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8572@0 { 24 PowerPC,8572@0 {
37 device_type = "cpu";
38 reg = <0x0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 }; 25 };
48 26 PowerPC,8572@1 {
27 status = "disabled";
28 };
49 }; 29 };
50 30
51 memory { 31 localbus@ffe05000 {
52 device_type = "memory"; 32 status = "disabled";
53 reg = <0x0 0x0>; // Filled by U-Boot
54 }; 33 };
55 34
56 soc8572@ffe00000 { 35 soc8572@ffe00000 {
57 #address-cells = <1>; 36 serial@4600 {
58 #size-cells = <1>; 37 status = "disabled";
59 device_type = "soc";
60 compatible = "simple-bus";
61 ranges = <0x0 0xffe00000 0x100000>;
62 bus-frequency = <0>; // Filled out by uboot.
63
64 ecm-law@0 {
65 compatible = "fsl,ecm-law";
66 reg = <0x0 0x1000>;
67 fsl,num-laws = <12>;
68 }; 38 };
69 39 dma@c300 {
70 ecm@1000 { 40 status = "disabled";
71 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
72 reg = <0x1000 0x1000>;
73 interrupts = <17 2>;
74 interrupt-parent = <&mpic>;
75 }; 41 };
76 42 gpio-controller@f000 {
77 memory-controller@2000 {
78 compatible = "fsl,mpc8572-memory-controller";
79 reg = <0x2000 0x1000>;
80 interrupt-parent = <&mpic>;
81 interrupts = <18 2>;
82 }; 43 };
83 44 l2-cache-controller@20000 {
84 memory-controller@6000 {
85 compatible = "fsl,mpc8572-memory-controller";
86 reg = <0x6000 0x1000>;
87 interrupt-parent = <&mpic>;
88 interrupts = <18 2>;
89 };
90
91 L2: l2-cache-controller@20000 {
92 compatible = "fsl,mpc8572-l2-cache-controller";
93 reg = <0x20000 0x1000>;
94 cache-line-size = <32>; // 32 bytes
95 cache-size = <0x80000>; // L2, 512K 45 cache-size = <0x80000>; // L2, 512K
96 interrupt-parent = <&mpic>;
97 interrupts = <16 2>;
98 }; 46 };
99 47 ethernet@26000 {
100 i2c@3000 { 48 status = "disabled";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 cell-index = <0>;
104 compatible = "fsl-i2c";
105 reg = <0x3000 0x100>;
106 interrupts = <43 2>;
107 interrupt-parent = <&mpic>;
108 dfsrr;
109 }; 49 };
110 50 mdio@26520 {
111 i2c@3100 { 51 status = "disabled";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 cell-index = <1>;
115 compatible = "fsl-i2c";
116 reg = <0x3100 0x100>;
117 interrupts = <43 2>;
118 interrupt-parent = <&mpic>;
119 dfsrr;
120 }; 52 };
121 53 ethernet@27000 {
122 dma@21300 { 54 status = "disabled";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
126 reg = <0x21300 0x4>;
127 ranges = <0x0 0x21100 0x200>;
128 cell-index = <0>;
129 dma-channel@0 {
130 compatible = "fsl,mpc8572-dma-channel",
131 "fsl,eloplus-dma-channel";
132 reg = <0x0 0x80>;
133 cell-index = <0>;
134 interrupt-parent = <&mpic>;
135 interrupts = <20 2>;
136 };
137 dma-channel@80 {
138 compatible = "fsl,mpc8572-dma-channel",
139 "fsl,eloplus-dma-channel";
140 reg = <0x80 0x80>;
141 cell-index = <1>;
142 interrupt-parent = <&mpic>;
143 interrupts = <21 2>;
144 };
145 dma-channel@100 {
146 compatible = "fsl,mpc8572-dma-channel",
147 "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <22 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,mpc8572-dma-channel",
155 "fsl,eloplus-dma-channel";
156 reg = <0x180 0x80>;
157 cell-index = <3>;
158 interrupt-parent = <&mpic>;
159 interrupts = <23 2>;
160 };
161 }; 55 };
162 56 mdio@27520 {
163 enet0: ethernet@24000 { 57 status = "disabled";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 cell-index = <0>;
167 device_type = "network";
168 model = "eTSEC";
169 compatible = "gianfar";
170 reg = <0x24000 0x1000>;
171 ranges = <0x0 0x24000 0x1000>;
172 local-mac-address = [ 00 00 00 00 00 00 ];
173 interrupts = <29 2 30 2 34 2>;
174 interrupt-parent = <&mpic>;
175 phy-handle = <&phy0>;
176 phy-connection-type = "rgmii-id";
177
178 mdio@520 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,gianfar-mdio";
182 reg = <0x520 0x20>;
183
184 phy0: ethernet-phy@0 {
185 interrupt-parent = <&mpic>;
186 interrupts = <10 1>;
187 reg = <0x0>;
188 };
189 phy1: ethernet-phy@1 {
190 interrupt-parent = <&mpic>;
191 interrupts = <10 1>;
192 reg = <0x1>;
193 };
194 };
195 }; 58 };
196 59 pic@40000 {
197 enet1: ethernet@25000 { 60 protected-sources = <
198 cell-index = <1>; 61 31 32 33 37 38 39 /* enet2 enet3 */
199 device_type = "network"; 62 76 77 78 79 26 42 /* dma2 pci2 serial*/
200 model = "eTSEC"; 63 0xe4 0xe5 0xe6 0xe7 /* msi */
201 compatible = "gianfar"; 64 >;
202 reg = <0x25000 0x1000>;
203 local-mac-address = [ 00 00 00 00 00 00 ];
204 interrupts = <35 2 36 2 40 2>;
205 interrupt-parent = <&mpic>;
206 phy-handle = <&phy1>;
207 phy-connection-type = "rgmii-id";
208 };
209
210 serial0: serial@4500 {
211 cell-index = <0>;
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 }; 65 };
217 66
218 msi@41600 { 67 msi@41600 {
219 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
220 reg = <0x41600 0x80>;
221 msi-available-ranges = <0 0x80>; 68 msi-available-ranges = <0 0x80>;
222 interrupts = < 69 interrupts = <
223 0xe0 0 70 0xe0 0
224 0xe1 0 71 0xe1 0
225 0xe2 0 72 0xe2 0
226 0xe3 0>; 73 0xe3 0>;
227 interrupt-parent = <&mpic>;
228 };
229
230 global-utilities@e0000 { //global utilities block
231 compatible = "fsl,mpc8572-guts";
232 reg = <0xe0000 0x1000>;
233 fsl,has-rstcr;
234 };
235
236 crypto@30000 {
237 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
238 "fsl,sec2.1", "fsl,sec2.0";
239 reg = <0x30000 0x10000>;
240 interrupts = <45 2 58 2>;
241 interrupt-parent = <&mpic>;
242 fsl,num-channels = <4>;
243 fsl,channel-fifo-len = <24>;
244 fsl,exec-units-mask = <0x9fe>;
245 fsl,descriptor-types-mask = <0x3ab0ebf>;
246 };
247
248 mpic: pic@40000 {
249 interrupt-controller;
250 #address-cells = <0>;
251 #interrupt-cells = <2>;
252 reg = <0x40000 0x40000>;
253 compatible = "chrp,open-pic";
254 device_type = "open-pic";
255 protected-sources = <
256 31 32 33 37 38 39 /* enet2 enet3 */
257 76 77 78 79 26 42 /* dma2 pci2 serial*/
258 0xe4 0xe5 0xe6 0xe7 /* msi */
259 >;
260 }; 74 };
261 }; 75 timer@42100 {
262 76 status = "disabled";
263 pci0: pcie@ffe08000 {
264 compatible = "fsl,mpc8548-pcie";
265 device_type = "pci";
266 #interrupt-cells = <1>;
267 #size-cells = <2>;
268 #address-cells = <3>;
269 reg = <0xffe08000 0x1000>;
270 bus-range = <0 255>;
271 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
272 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
273 clock-frequency = <33333333>;
274 interrupt-parent = <&mpic>;
275 interrupts = <24 2>;
276 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
277 interrupt-map = <
278 /* IDSEL 0x11 func 0 - PCI slot 1 */
279 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
280 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
281 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
282 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
283
284 /* IDSEL 0x11 func 1 - PCI slot 1 */
285 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
286 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
287 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
288 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
289
290 /* IDSEL 0x11 func 2 - PCI slot 1 */
291 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
292 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
293 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
294 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
295
296 /* IDSEL 0x11 func 3 - PCI slot 1 */
297 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
298 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
299 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
300 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
301
302 /* IDSEL 0x11 func 4 - PCI slot 1 */
303 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
304 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
305 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
306 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
307
308 /* IDSEL 0x11 func 5 - PCI slot 1 */
309 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
310 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
311 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
312 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
313
314 /* IDSEL 0x11 func 6 - PCI slot 1 */
315 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
316 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
317 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
318 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
319
320 /* IDSEL 0x11 func 7 - PCI slot 1 */
321 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
322 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
323 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
324 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
325
326 /* IDSEL 0x12 func 0 - PCI slot 2 */
327 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
328 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
329 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
330 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
331
332 /* IDSEL 0x12 func 1 - PCI slot 2 */
333 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
334 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
335 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
336 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
337
338 /* IDSEL 0x12 func 2 - PCI slot 2 */
339 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
340 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
341 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
342 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
343
344 /* IDSEL 0x12 func 3 - PCI slot 2 */
345 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
346 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
347 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
348 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
349
350 /* IDSEL 0x12 func 4 - PCI slot 2 */
351 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
352 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
353 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
354 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
355
356 /* IDSEL 0x12 func 5 - PCI slot 2 */
357 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
358 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
359 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
360 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
361
362 /* IDSEL 0x12 func 6 - PCI slot 2 */
363 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
364 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
365 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
366 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
367
368 /* IDSEL 0x12 func 7 - PCI slot 2 */
369 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
370 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
371 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
372 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
373
374 // IDSEL 0x1c USB
375 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
376 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
377 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
378 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
379
380 // IDSEL 0x1d Audio
381 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
382
383 // IDSEL 0x1e Legacy
384 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
385 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
386
387 // IDSEL 0x1f IDE/SATA
388 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
389 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
390
391 >;
392
393 pcie@0 {
394 reg = <0x0 0x0 0x0 0x0 0x0>;
395 #size-cells = <2>;
396 #address-cells = <3>;
397 device_type = "pci";
398 ranges = <0x2000000 0x0 0x80000000
399 0x2000000 0x0 0x80000000
400 0x0 0x20000000
401
402 0x1000000 0x0 0x0
403 0x1000000 0x0 0x0
404 0x0 0x10000>;
405 uli1575@0 {
406 reg = <0x0 0x0 0x0 0x0 0x0>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 ranges = <0x2000000 0x0 0x80000000
410 0x2000000 0x0 0x80000000
411 0x0 0x20000000
412
413 0x1000000 0x0 0x0
414 0x1000000 0x0 0x0
415 0x0 0x10000>;
416 isa@1e {
417 device_type = "isa";
418 #interrupt-cells = <2>;
419 #size-cells = <1>;
420 #address-cells = <2>;
421 reg = <0xf000 0x0 0x0 0x0 0x0>;
422 ranges = <0x1 0x0 0x1000000 0x0 0x0
423 0x1000>;
424 interrupt-parent = <&i8259>;
425
426 i8259: interrupt-controller@20 {
427 reg = <0x1 0x20 0x2
428 0x1 0xa0 0x2
429 0x1 0x4d0 0x2>;
430 interrupt-controller;
431 device_type = "interrupt-controller";
432 #address-cells = <0>;
433 #interrupt-cells = <2>;
434 compatible = "chrp,iic";
435 interrupts = <9 2>;
436 interrupt-parent = <&mpic>;
437 };
438
439 i8042@60 {
440 #size-cells = <0>;
441 #address-cells = <1>;
442 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
443 interrupts = <1 3 12 3>;
444 interrupt-parent =
445 <&i8259>;
446
447 keyboard@0 {
448 reg = <0x0>;
449 compatible = "pnpPNP,303";
450 };
451
452 mouse@1 {
453 reg = <0x1>;
454 compatible = "pnpPNP,f03";
455 };
456 };
457
458 rtc@70 {
459 compatible = "pnpPNP,b00";
460 reg = <0x1 0x70 0x2>;
461 };
462
463 gpio@400 {
464 reg = <0x1 0x400 0x80>;
465 };
466 };
467 };
468 }; 77 };
469
470 }; 78 };
471 79 pcie@ffe0a000 {
472 pci1: pcie@ffe09000 { 80 status = "disabled";
473 compatible = "fsl,mpc8548-pcie";
474 device_type = "pci";
475 #interrupt-cells = <1>;
476 #size-cells = <2>;
477 #address-cells = <3>;
478 reg = <0xffe09000 0x1000>;
479 bus-range = <0 255>;
480 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
481 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
482 clock-frequency = <33333333>;
483 interrupt-parent = <&mpic>;
484 interrupts = <25 2>;
485 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
486 interrupt-map = <
487 /* IDSEL 0x0 */
488 0000 0x0 0x0 0x1 &mpic 0x4 0x1
489 0000 0x0 0x0 0x2 &mpic 0x5 0x1
490 0000 0x0 0x0 0x3 &mpic 0x6 0x1
491 0000 0x0 0x0 0x4 &mpic 0x7 0x1
492 >;
493 pcie@0 {
494 reg = <0x0 0x0 0x0 0x0 0x0>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 device_type = "pci";
498 ranges = <0x2000000 0x0 0xa0000000
499 0x2000000 0x0 0xa0000000
500 0x0 0x20000000
501
502 0x1000000 0x0 0x0
503 0x1000000 0x0 0x0
504 0x0 0x10000>;
505 };
506 }; 81 };
507}; 82};
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index e7b477f6a3fe..d6a8fafc0d0d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -15,169 +15,74 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/dts-v1/; 18/include/ "mpc8572ds.dts"
19
19/ { 20/ {
20 model = "fsl,MPC8572DS"; 21 model = "fsl,MPC8572DS";
21 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 22 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 aliases {
26 ethernet2 = &enet2;
27 ethernet3 = &enet3;
28 serial0 = &serial0;
29 pci2 = &pci2;
30 };
31 23
32 cpus { 24 cpus {
33 #address-cells = <1>; 25 PowerPC,8572@0 {
34 #size-cells = <0>; 26 status = "disabled";
35 27 };
36 PowerPC,8572@1 { 28 PowerPC,8572@1 {
37 device_type = "cpu";
38 reg = <0x1>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>;
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 }; 29 };
48 }; 30 };
49 31
50 memory { 32 localbus@ffe05000 {
51 device_type = "memory"; 33 status = "disabled";
52 reg = <0x0 0x0>; // Filled by U-Boot
53 }; 34 };
54 35
55 soc8572@ffe00000 { 36 soc8572@ffe00000 {
56 #address-cells = <1>; 37 ecm-law@0 {
57 #size-cells = <1>; 38 status = "disabled";
58 device_type = "soc";
59 compatible = "simple-bus";
60 ranges = <0x0 0xffe00000 0x100000>;
61 bus-frequency = <0>; // Filled out by uboot.
62
63 L2: l2-cache-controller@20000 {
64 compatible = "fsl,mpc8572-l2-cache-controller";
65 reg = <0x20000 0x1000>;
66 cache-line-size = <32>; // 32 bytes
67 cache-size = <0x80000>; // L2, 512K
68 interrupt-parent = <&mpic>;
69 }; 39 };
70 40 ecm@1000 {
71 dma@c300 { 41 status = "disabled";
72 #address-cells = <1>; 42 };
73 #size-cells = <1>; 43 memory-controller@2000 {
74 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 44 status = "disabled";
75 reg = <0xc300 0x4>; 45 };
76 ranges = <0x0 0xc100 0x200>; 46 memory-controller@6000 {
77 cell-index = <0>; 47 status = "disabled";
78 dma-channel@0 { 48 };
79 compatible = "fsl,mpc8572-dma-channel", 49 i2c@3000 {
80 "fsl,eloplus-dma-channel"; 50 status = "disabled";
81 reg = <0x0 0x80>; 51 };
82 cell-index = <0>; 52 i2c@3100 {
83 interrupt-parent = <&mpic>; 53 status = "disabled";
84 interrupts = <76 2>; 54 };
85 }; 55 serial@4500 {
86 dma-channel@80 { 56 status = "disabled";
87 compatible = "fsl,mpc8572-dma-channel", 57 };
88 "fsl,eloplus-dma-channel"; 58 gpio-controller@f000 {
89 reg = <0x80 0x80>; 59 status = "disabled";
90 cell-index = <1>; 60 };
91 interrupt-parent = <&mpic>; 61 l2-cache-controller@20000 {
92 interrupts = <77 2>; 62 cache-size = <0x80000>; // L2, 512K
93 }; 63 };
94 dma-channel@100 { 64 dma@21300 {
95 compatible = "fsl,mpc8572-dma-channel", 65 status = "disabled";
96 "fsl,eloplus-dma-channel"; 66 };
97 reg = <0x100 0x80>; 67 ethernet@24000 {
98 cell-index = <2>; 68 status = "disabled";
99 interrupt-parent = <&mpic>;
100 interrupts = <78 2>;
101 };
102 dma-channel@180 {
103 compatible = "fsl,mpc8572-dma-channel",
104 "fsl,eloplus-dma-channel";
105 reg = <0x180 0x80>;
106 cell-index = <3>;
107 interrupt-parent = <&mpic>;
108 interrupts = <79 2>;
109 };
110 }; 69 };
111
112 mdio@24520 { 70 mdio@24520 {
113 #address-cells = <1>; 71 status = "disabled";
114 #size-cells = <0>;
115 compatible = "fsl,gianfar-mdio";
116 reg = <0x24520 0x20>;
117
118 phy2: ethernet-phy@2 {
119 interrupt-parent = <&mpic>;
120 reg = <0x2>;
121 };
122 phy3: ethernet-phy@3 {
123 interrupt-parent = <&mpic>;
124 reg = <0x3>;
125 };
126 }; 72 };
127 73 ptp_clock@24e00 {
128 enet2: ethernet@26000 { 74 status = "disabled";
129 cell-index = <2>;
130 device_type = "network";
131 model = "eTSEC";
132 compatible = "gianfar";
133 reg = <0x26000 0x1000>;
134 local-mac-address = [ 00 00 00 00 00 00 ];
135 interrupts = <31 2 32 2 33 2>;
136 interrupt-parent = <&mpic>;
137 phy-handle = <&phy2>;
138 phy-connection-type = "rgmii-id";
139 }; 75 };
140 76 ethernet@25000 {
141 enet3: ethernet@27000 { 77 status = "disabled";
142 cell-index = <3>;
143 device_type = "network";
144 model = "eTSEC";
145 compatible = "gianfar";
146 reg = <0x27000 0x1000>;
147 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <37 2 38 2 39 2>;
149 interrupt-parent = <&mpic>;
150 phy-handle = <&phy3>;
151 phy-connection-type = "rgmii-id";
152 }; 78 };
153 79 mdio@25520 {
154 msi@41600 { 80 status = "disabled";
155 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
156 reg = <0x41600 0x80>;
157 msi-available-ranges = <0x80 0x80>;
158 interrupts = <
159 0xe4 0
160 0xe5 0
161 0xe6 0
162 0xe7 0>;
163 interrupt-parent = <&mpic>;
164 }; 81 };
165 82 crypto@30000 {
166 serial0: serial@4600 { 83 status = "disabled";
167 cell-index = <1>;
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <0x4600 0x100>;
171 clock-frequency = <0>;
172 }; 84 };
173 85 pic@40000 {
174 mpic: pic@40000 {
175 interrupt-controller;
176 #address-cells = <0>;
177 #interrupt-cells = <2>;
178 reg = <0x40000 0x40000>;
179 compatible = "chrp,open-pic";
180 device_type = "open-pic";
181 protected-sources = < 86 protected-sources = <
182 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */ 87 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
183 29 30 34 35 36 40 /* enet0 enet1 */ 88 29 30 34 35 36 40 /* enet0 enet1 */
@@ -189,41 +94,25 @@
189 0xe0 0xe1 0xe2 0xe3 /* msi */ 94 0xe0 0xe1 0xe2 0xe3 /* msi */
190 >; 95 >;
191 }; 96 };
192 }; 97 timer@41100 {
193 98 status = "disabled";
194 pci2: pcie@ffe0a000 {
195 compatible = "fsl,mpc8548-pcie";
196 device_type = "pci";
197 #interrupt-cells = <1>;
198 #size-cells = <2>;
199 #address-cells = <3>;
200 reg = <0xffe0a000 0x1000>;
201 bus-range = <0 255>;
202 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
203 0x1000000 0x0 0x0 0xffc20000 0x0 0x10000>;
204 clock-frequency = <33333333>;
205 interrupt-parent = <&mpic>;
206 interrupts = <26 2>;
207 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
208 interrupt-map = <
209 /* IDSEL 0x0 */
210 0000 0x0 0x0 0x1 &mpic 0x0 0x1
211 0000 0x0 0x0 0x2 &mpic 0x1 0x1
212 0000 0x0 0x0 0x3 &mpic 0x2 0x1
213 0000 0x0 0x0 0x4 &mpic 0x3 0x1
214 >;
215 pcie@0 {
216 reg = <0x0 0x0 0x0 0x0 0x0>;
217 #size-cells = <2>;
218 #address-cells = <3>;
219 device_type = "pci";
220 ranges = <0x2000000 0x0 0xc0000000
221 0x2000000 0x0 0xc0000000
222 0x0 0x20000000
223
224 0x1000000 0x0 0x0
225 0x1000000 0x0 0x0
226 0x0 0x10000>;
227 }; 99 };
100 msi@41600 {
101 msi-available-ranges = <0x80 0x80>;
102 interrupts = <
103 0xe4 0
104 0xe5 0
105 0xe6 0
106 0xe7 0>;
107 };
108 global-utilities@e0000 {
109 status = "disabled";
110 };
111 };
112 pcie@ffe08000 {
113 status = "disabled";
114 };
115 pcie@ffe09000 {
116 status = "disabled";
228 }; 117 };
229}; 118};
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 83c3218cb4da..6a109a0ceac9 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -175,7 +175,7 @@
175 serial0: serial@4500 { 175 serial0: serial@4500 {
176 cell-index = <0>; 176 cell-index = <0>;
177 device_type = "serial"; 177 device_type = "serial";
178 compatible = "ns16550"; 178 compatible = "fsl,ns16550", "ns16550";
179 reg = <0x4500 0x100>; 179 reg = <0x4500 0x100>;
180 clock-frequency = <0>; 180 clock-frequency = <0>;
181 interrupts = <42 2>; 181 interrupts = <42 2>;
@@ -186,7 +186,7 @@
186 serial1: serial@4600 { 186 serial1: serial@4600 {
187 cell-index = <1>; 187 cell-index = <1>;
188 device_type = "serial"; 188 device_type = "serial";
189 compatible = "ns16550"; 189 compatible = "fsl,ns16550", "ns16550";
190 reg = <0x4600 0x100>; 190 reg = <0x4600 0x100>;
191 clock-frequency = <0>; 191 clock-frequency = <0>;
192 interrupts = <42 2>; 192 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index 848320e4d3c4..1e8666ccbed8 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -26,13 +26,6 @@
26 serial1 = &serial1; 26 serial1 = &serial1;
27 pci0 = &pci0; 27 pci0 = &pci0;
28 pci1 = &pci1; 28 pci1 = &pci1;
29/*
30 * Only one of Rapid IO or PCI can be present due to HW limitations and
31 * due to the fact that the 2 now share address space in the new memory
32 * map. The most likely case is that we have PCI, so comment out the
33 * rapidio node. Leave it here for reference.
34 */
35 /* rapidio0 = &rapidio0; */
36 }; 29 };
37 30
38 cpus { 31 cpus {
@@ -335,7 +328,7 @@
335 serial0: serial@4500 { 328 serial0: serial@4500 {
336 cell-index = <0>; 329 cell-index = <0>;
337 device_type = "serial"; 330 device_type = "serial";
338 compatible = "ns16550"; 331 compatible = "fsl,ns16550", "ns16550";
339 reg = <0x4500 0x100>; 332 reg = <0x4500 0x100>;
340 clock-frequency = <0>; 333 clock-frequency = <0>;
341 interrupts = <42 2>; 334 interrupts = <42 2>;
@@ -345,7 +338,7 @@
345 serial1: serial@4600 { 338 serial1: serial@4600 {
346 cell-index = <1>; 339 cell-index = <1>;
347 device_type = "serial"; 340 device_type = "serial";
348 compatible = "ns16550"; 341 compatible = "fsl,ns16550", "ns16550";
349 reg = <0x4600 0x100>; 342 reg = <0x4600 0x100>;
350 clock-frequency = <0>; 343 clock-frequency = <0>;
351 interrupts = <28 2>; 344 interrupts = <28 2>;
@@ -361,6 +354,41 @@
361 device_type = "open-pic"; 354 device_type = "open-pic";
362 }; 355 };
363 356
357 rmu: rmu@d3000 {
358 #address-cells = <1>;
359 #size-cells = <1>;
360 compatible = "fsl,srio-rmu";
361 reg = <0xd3000 0x500>;
362 ranges = <0x0 0xd3000 0x500>;
363
364 message-unit@0 {
365 compatible = "fsl,srio-msg-unit";
366 reg = <0x0 0x100>;
367 interrupts = <
368 53 2 /* msg1_tx_irq */
369 54 2>;/* msg1_rx_irq */
370 };
371 message-unit@100 {
372 compatible = "fsl,srio-msg-unit";
373 reg = <0x100 0x100>;
374 interrupts = <
375 55 2 /* msg2_tx_irq */
376 56 2>;/* msg2_rx_irq */
377 };
378 doorbell-unit@400 {
379 compatible = "fsl,srio-dbell-unit";
380 reg = <0x400 0x80>;
381 interrupts = <
382 49 2 /* bell_outb_irq */
383 50 2>;/* bell_inb_irq */
384 };
385 port-write-unit@4e0 {
386 compatible = "fsl,srio-port-write-unit";
387 reg = <0x4e0 0x20>;
388 interrupts = <48 2>;
389 };
390 };
391
364 global-utilities@e0000 { 392 global-utilities@e0000 {
365 compatible = "fsl,mpc8641-guts"; 393 compatible = "fsl,mpc8641-guts";
366 reg = <0xe0000 0x1000>; 394 reg = <0xe0000 0x1000>;
@@ -612,16 +640,27 @@
612 }; 640 };
613 }; 641 };
614/* 642/*
615 rapidio0: rapidio@ffec0000 { 643 * Only one of Rapid IO or PCI can be present due to HW limitations and
644 * due to the fact that the 2 now share address space in the new memory
645 * map. The most likely case is that we have PCI, so comment out the
646 * rapidio node. Leave it here for reference.
647
648 rapidio@ffec0000 {
649 reg = <0xffec0000 0x11000>;
650 compatible = "fsl,srio";
651 interrupt-parent = <&mpic>;
652 interrupts = <48 2>;
616 #address-cells = <2>; 653 #address-cells = <2>;
617 #size-cells = <2>; 654 #size-cells = <2>;
618 compatible = "fsl,rapidio-delta"; 655 fsl,srio-rmu-handle = <&rmu>;
619 reg = <0xffec0000 0x20000>; 656 ranges;
620 ranges = <0 0 0x80000000 0 0x20000000>; 657
621 interrupt-parent = <&mpic>; 658 port1 {
622 // err_irq bell_outb_irq bell_inb_irq 659 #address-cells = <2>;
623 // msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq 660 #size-cells = <2>;
624 interrupts = <48 2 49 2 50 2 53 2 54 2 55 2 56 2>; 661 cell-index = <1>;
662 ranges = <0 0 0x80000000 0 0x20000000>;
663 };
625 }; 664 };
626*/ 665*/
627 666
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
index 8be8e701e1d3..fd4cd4da60b5 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn_36b.dts
@@ -328,7 +328,7 @@
328 serial0: serial@4500 { 328 serial0: serial@4500 {
329 cell-index = <0>; 329 cell-index = <0>;
330 device_type = "serial"; 330 device_type = "serial";
331 compatible = "ns16550"; 331 compatible = "fsl,ns16550", "ns16550";
332 reg = <0x4500 0x100>; 332 reg = <0x4500 0x100>;
333 clock-frequency = <0>; 333 clock-frequency = <0>;
334 interrupts = <42 2>; 334 interrupts = <42 2>;
@@ -338,7 +338,7 @@
338 serial1: serial@4600 { 338 serial1: serial@4600 {
339 cell-index = <1>; 339 cell-index = <1>;
340 device_type = "serial"; 340 device_type = "serial";
341 compatible = "ns16550"; 341 compatible = "fsl,ns16550", "ns16550";
342 reg = <0x4600 0x100>; 342 reg = <0x4600 0x100>;
343 clock-frequency = <0>; 343 clock-frequency = <0>;
344 interrupts = <28 2>; 344 interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/obs600.dts b/arch/powerpc/boot/dts/obs600.dts
new file mode 100644
index 000000000000..18e7d79ee4c3
--- /dev/null
+++ b/arch/powerpc/boot/dts/obs600.dts
@@ -0,0 +1,314 @@
1/*
2 * Device Tree Source for PlatHome OpenBlockS 600 (405EX)
3 *
4 * Copyright 2011 Ben Herrenschmidt, IBM Corp.
5 *
6 * Based on Kilauea by:
7 *
8 * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without
12 * any warranty of any kind, whether express or implied.
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 model = "PlatHome,OpenBlockS 600";
21 compatible = "plathome,obs600";
22 dcr-parent = <&{/cpus/cpu@0}>;
23
24 aliases {
25 ethernet0 = &EMAC0;
26 ethernet1 = &EMAC1;
27 serial0 = &UART0;
28 serial1 = &UART1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 model = "PowerPC,405EX";
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
43 i-cache-size = <16384>; /* 16 kB */
44 d-cache-size = <16384>; /* 16 kB */
45 dcr-controller;
46 dcr-access-method = "native";
47 };
48 };
49
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
53 };
54
55 UIC0: interrupt-controller {
56 compatible = "ibm,uic-405ex", "ibm,uic";
57 interrupt-controller;
58 cell-index = <0>;
59 dcr-reg = <0x0c0 0x009>;
60 #address-cells = <0>;
61 #size-cells = <0>;
62 #interrupt-cells = <2>;
63 };
64
65 UIC1: interrupt-controller1 {
66 compatible = "ibm,uic-405ex","ibm,uic";
67 interrupt-controller;
68 cell-index = <1>;
69 dcr-reg = <0x0d0 0x009>;
70 #address-cells = <0>;
71 #size-cells = <0>;
72 #interrupt-cells = <2>;
73 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
74 interrupt-parent = <&UIC0>;
75 };
76
77 UIC2: interrupt-controller2 {
78 compatible = "ibm,uic-405ex","ibm,uic";
79 interrupt-controller;
80 cell-index = <2>;
81 dcr-reg = <0x0e0 0x009>;
82 #address-cells = <0>;
83 #size-cells = <0>;
84 #interrupt-cells = <2>;
85 interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
86 interrupt-parent = <&UIC0>;
87 };
88
89 CPM0: cpm {
90 compatible = "ibm,cpm";
91 dcr-access-method = "native";
92 dcr-reg = <0x0b0 0x003>;
93 unused-units = <0x00000000>;
94 idle-doze = <0x02000000>;
95 standby = <0xe3e74800>;
96 };
97
98 plb {
99 compatible = "ibm,plb-405ex", "ibm,plb4";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 clock-frequency = <0>; /* Filled in by U-Boot */
104
105 SDRAM0: memory-controller {
106 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
107 dcr-reg = <0x010 0x002>;
108 interrupt-parent = <&UIC2>;
109 interrupts = <0x5 0x4 /* ECC DED Error */
110 0x6 0x4>; /* ECC SEC Error */
111 };
112
113 CRYPTO: crypto@ef700000 {
114 compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
115 reg = <0xef700000 0x80400>;
116 interrupt-parent = <&UIC0>;
117 interrupts = <0x17 0x2>;
118 };
119
120 MAL0: mcmal {
121 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
122 dcr-reg = <0x180 0x062>;
123 num-tx-chans = <2>;
124 num-rx-chans = <2>;
125 interrupt-parent = <&MAL0>;
126 interrupts = <0x0 0x1 0x2 0x3 0x4>;
127 #interrupt-cells = <1>;
128 #address-cells = <0>;
129 #size-cells = <0>;
130 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
131 /*RXEOB*/ 0x1 &UIC0 0xb 0x4
132 /*SERR*/ 0x2 &UIC1 0x0 0x4
133 /*TXDE*/ 0x3 &UIC1 0x1 0x4
134 /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
135 interrupt-map-mask = <0xffffffff>;
136 };
137
138 POB0: opb {
139 compatible = "ibm,opb-405ex", "ibm,opb";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x80000000 0x80000000 0x10000000
143 0xef600000 0xef600000 0x00a00000
144 0xf0000000 0xf0000000 0x10000000>;
145 dcr-reg = <0x0a0 0x005>;
146 clock-frequency = <0>; /* Filled in by U-Boot */
147
148 EBC0: ebc {
149 compatible = "ibm,ebc-405ex", "ibm,ebc";
150 dcr-reg = <0x012 0x002>;
151 #address-cells = <2>;
152 #size-cells = <1>;
153 clock-frequency = <0>; /* Filled in by U-Boot */
154 /* ranges property is supplied by U-Boot */
155 interrupts = <0x5 0x1>;
156 interrupt-parent = <&UIC1>;
157
158 nor_flash@0,0 {
159 compatible = "amd,s29gl512n", "cfi-flash";
160 bank-width = <2>;
161 reg = <0x00000000 0x00000000 0x08000000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164 partition@0 {
165 label = "kernel + initrd";
166 reg = <0x00000000 0x03de0000>;
167 };
168 partition@3de0000 {
169 label = "user config area";
170 reg = <0x03de0000 0x00080000>;
171 };
172 partition@3e60000 {
173 label = "user program area";
174 reg = <0x03e60000 0x04000000>;
175 };
176 partition@7e60000 {
177 label = "flat device tree";
178 reg = <0x07e60000 0x00080000>;
179 };
180 partition@7ee0000 {
181 label = "test program";
182 reg = <0x07ee0000 0x00080000>;
183 };
184 partition@7f60000 {
185 label = "u-boot env";
186 reg = <0x07f60000 0x00040000>;
187 };
188 partition@7fa0000 {
189 label = "u-boot";
190 reg = <0x07fa0000 0x00060000>;
191 };
192 };
193 };
194
195 UART0: serial@ef600200 {
196 device_type = "serial";
197 compatible = "ns16550";
198 reg = <0xef600200 0x00000008>;
199 virtual-reg = <0xef600200>;
200 clock-frequency = <0>; /* Filled in by U-Boot */
201 current-speed = <0>;
202 interrupt-parent = <&UIC0>;
203 interrupts = <0x1a 0x4>;
204 };
205
206 UART1: serial@ef600300 {
207 device_type = "serial";
208 compatible = "ns16550";
209 reg = <0xef600300 0x00000008>;
210 virtual-reg = <0xef600300>;
211 clock-frequency = <0>; /* Filled in by U-Boot */
212 current-speed = <0>;
213 interrupt-parent = <&UIC0>;
214 interrupts = <0x1 0x4>;
215 };
216
217 IIC0: i2c@ef600400 {
218 compatible = "ibm,iic-405ex", "ibm,iic";
219 reg = <0xef600400 0x00000014>;
220 interrupt-parent = <&UIC0>;
221 interrupts = <0x2 0x4>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 rtc@68 {
226 compatible = "dallas,ds1340";
227 reg = <0x68>;
228 };
229 };
230
231 IIC1: i2c@ef600500 {
232 compatible = "ibm,iic-405ex", "ibm,iic";
233 reg = <0xef600500 0x00000014>;
234 interrupt-parent = <&UIC0>;
235 interrupts = <0x7 0x4>;
236 };
237
238 RGMII0: emac-rgmii@ef600b00 {
239 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
240 reg = <0xef600b00 0x00000104>;
241 has-mdio;
242 };
243
244 EMAC0: ethernet@ef600900 {
245 linux,network-index = <0x0>;
246 device_type = "network";
247 compatible = "ibm,emac-405ex", "ibm,emac4sync";
248 interrupt-parent = <&EMAC0>;
249 interrupts = <0x0 0x1>;
250 #interrupt-cells = <1>;
251 #address-cells = <0>;
252 #size-cells = <0>;
253 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
254 /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
255 reg = <0xef600900 0x000000c4>;
256 local-mac-address = [000000000000]; /* Filled in by U-Boot */
257 mal-device = <&MAL0>;
258 mal-tx-channel = <0>;
259 mal-rx-channel = <0>;
260 cell-index = <0>;
261 max-frame-size = <9000>;
262 rx-fifo-size = <4096>;
263 tx-fifo-size = <2048>;
264 rx-fifo-size-gige = <16384>;
265 tx-fifo-size-gige = <16384>;
266 phy-mode = "rgmii";
267 phy-map = <0x00000000>;
268 rgmii-device = <&RGMII0>;
269 rgmii-channel = <0>;
270 has-inverted-stacr-oc;
271 has-new-stacr-staopc;
272 };
273
274 EMAC1: ethernet@ef600a00 {
275 linux,network-index = <0x1>;
276 device_type = "network";
277 compatible = "ibm,emac-405ex", "ibm,emac4sync";
278 interrupt-parent = <&EMAC1>;
279 interrupts = <0x0 0x1>;
280 #interrupt-cells = <1>;
281 #address-cells = <0>;
282 #size-cells = <0>;
283 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
284 /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
285 reg = <0xef600a00 0x000000c4>;
286 local-mac-address = [000000000000]; /* Filled in by U-Boot */
287 mal-device = <&MAL0>;
288 mal-tx-channel = <1>;
289 mal-rx-channel = <1>;
290 cell-index = <1>;
291 max-frame-size = <9000>;
292 rx-fifo-size = <4096>;
293 tx-fifo-size = <2048>;
294 rx-fifo-size-gige = <16384>;
295 tx-fifo-size-gige = <16384>;
296 phy-mode = "rgmii";
297 phy-map = <0x00000000>;
298 rgmii-device = <&RGMII0>;
299 rgmii-channel = <1>;
300 has-inverted-stacr-oc;
301 has-new-stacr-staopc;
302 };
303
304 GPIO: gpio@ef600800 {
305 device_type = "gpio";
306 compatible = "ibm,gpio-405ex", "ibm,ppc4xx-gpio";
307 reg = <0xef600800 0x50>;
308 };
309 };
310 };
311 chosen {
312 linux,stdout-path = "/plb/opb/serial@ef600200";
313 };
314};
diff --git a/arch/powerpc/boot/dts/p1010rdb.dts b/arch/powerpc/boot/dts/p1010rdb.dts
index d6c669c888e9..b868d22984e9 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dts
+++ b/arch/powerpc/boot/dts/p1010rdb.dts
@@ -9,230 +9,33 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1010si.dtsi" 12/include/ "fsl/p1010si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P1010RDB"; 15 model = "fsl,P1010RDB";
16 compatible = "fsl,P1010RDB"; 16 compatible = "fsl,P1010RDB";
17 17
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 can0 = &can0;
27 can1 = &can1;
28 };
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 ifc@ffe1e000 { 22 board_ifc: ifc: ifc@ffe1e000 {
35 /* NOR, NAND Flashes and CPLD on board */ 23 /* NOR, NAND Flashes and CPLD on board */
36 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 24 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
37 0x1 0x0 0x0 0xff800000 0x00010000 25 0x1 0x0 0x0 0xff800000 0x00010000
38 0x3 0x0 0x0 0xffb00000 0x00000020>; 26 0x3 0x0 0x0 0xffb00000 0x00000020>;
39 27 reg = <0x0 0xffe1e000 0 0x2000>;
40 nor@0,0 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 compatible = "cfi-flash";
44 reg = <0x0 0x0 0x2000000>;
45 bank-width = <2>;
46 device-width = <1>;
47
48 partition@40000 {
49 /* 256KB for DTB Image */
50 reg = <0x00040000 0x00040000>;
51 label = "NOR DTB Image";
52 };
53
54 partition@80000 {
55 /* 7 MB for Linux Kernel Image */
56 reg = <0x00080000 0x00700000>;
57 label = "NOR Linux Kernel Image";
58 };
59
60 partition@800000 {
61 /* 20MB for JFFS2 based Root file System */
62 reg = <0x00800000 0x01400000>;
63 label = "NOR JFFS2 Root File System";
64 };
65
66 partition@1f00000 {
67 /* This location must not be altered */
68 /* 512KB for u-boot Bootloader Image */
69 /* 512KB for u-boot Environment Variables */
70 reg = <0x01f00000 0x00100000>;
71 label = "NOR U-Boot Image";
72 read-only;
73 };
74 };
75
76 nand@1,0 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "fsl,ifc-nand";
80 reg = <0x1 0x0 0x10000>;
81
82 partition@0 {
83 /* This location must not be altered */
84 /* 1MB for u-boot Bootloader Image */
85 reg = <0x0 0x00100000>;
86 label = "NAND U-Boot Image";
87 read-only;
88 };
89
90 partition@100000 {
91 /* 1MB for DTB Image */
92 reg = <0x00100000 0x00100000>;
93 label = "NAND DTB Image";
94 };
95
96 partition@200000 {
97 /* 4MB for Linux Kernel Image */
98 reg = <0x00200000 0x00400000>;
99 label = "NAND Linux Kernel Image";
100 };
101
102 partition@600000 {
103 /* 4MB for Compressed Root file System Image */
104 reg = <0x00600000 0x00400000>;
105 label = "NAND Compressed RFS Image";
106 };
107
108 partition@a00000 {
109 /* 15MB for JFFS2 based Root file System */
110 reg = <0x00a00000 0x00f00000>;
111 label = "NAND JFFS2 Root File System";
112 };
113
114 partition@1900000 {
115 /* 7MB for User Area */
116 reg = <0x01900000 0x00700000>;
117 label = "NAND User area";
118 };
119 };
120
121 cpld@3,0 {
122 #address-cells = <1>;
123 #size-cells = <1>;
124 compatible = "fsl,p1010rdb-cpld";
125 reg = <0x3 0x0 0x0000020>;
126 bank-width = <1>;
127 device-width = <1>;
128 };
129 }; 28 };
130 29
131 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
132 spi@7000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
133 flash@0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "spansion,s25sl12801";
137 reg = <0>;
138 spi-max-frequency = <50000000>;
139
140 partition@0 {
141 /* 1MB for u-boot Bootloader Image */
142 /* 1MB for Environment */
143 reg = <0x0 0x00100000>;
144 label = "SPI Flash U-Boot Image";
145 read-only;
146 };
147
148 partition@100000 {
149 /* 512KB for DTB Image */
150 reg = <0x00100000 0x00080000>;
151 label = "SPI Flash DTB Image";
152 };
153
154 partition@180000 {
155 /* 4MB for Linux Kernel Image */
156 reg = <0x00180000 0x00400000>;
157 label = "SPI Flash Linux Kernel Image";
158 };
159
160 partition@580000 {
161 /* 4MB for Compressed RFS Image */
162 reg = <0x00580000 0x00400000>;
163 label = "SPI Flash Compressed RFSImage";
164 };
165
166 partition@980000 {
167 /* 6.5MB for JFFS2 based RFS */
168 reg = <0x00980000 0x00680000>;
169 label = "SPI Flash JFFS2 RFS";
170 };
171 };
172 };
173
174 usb@22000 {
175 phy_type = "utmi";
176 };
177
178 mdio@24000 {
179 phy0: ethernet-phy@0 {
180 interrupt-parent = <&mpic>;
181 interrupts = <3 1>;
182 reg = <0x1>;
183 };
184
185 phy1: ethernet-phy@1 {
186 interrupt-parent = <&mpic>;
187 interrupts = <2 1>;
188 reg = <0x0>;
189 };
190
191 phy2: ethernet-phy@2 {
192 interrupt-parent = <&mpic>;
193 interrupts = <2 1>;
194 reg = <0x2>;
195 };
196 };
197
198 enet0: ethernet@b0000 {
199 phy-handle = <&phy0>;
200 phy-connection-type = "rgmii-id";
201 };
202
203 enet1: ethernet@b1000 {
204 phy-handle = <&phy1>;
205 tbi-handle = <&tbi0>;
206 phy-connection-type = "sgmii";
207 };
208
209 enet2: ethernet@b2000 {
210 phy-handle = <&phy2>;
211 tbi-handle = <&tbi1>;
212 phy-connection-type = "sgmii";
213 };
214 }; 32 };
215 33
216 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
35 reg = <0 0xffe09000 0 0x1000>;
217 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 36 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
218 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 37 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
219 pcie@0 { 38 pcie@0 {
220 reg = <0x0 0x0 0x0 0x0 0x0>;
221 #interrupt-cells = <1>;
222 #size-cells = <2>;
223 #address-cells = <3>;
224 device_type = "pci";
225 interrupt-parent = <&mpic>;
226 interrupts = <16 2>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x4 0x1
231 0000 0x0 0x0 0x2 &mpic 0x5 0x1
232 0000 0x0 0x0 0x3 &mpic 0x6 0x1
233 0000 0x0 0x0 0x4 &mpic 0x7 0x1
234 >;
235
236 ranges = <0x2000000 0x0 0xa0000000 39 ranges = <0x2000000 0x0 0xa0000000
237 0x2000000 0x0 0xa0000000 40 0x2000000 0x0 0xa0000000
238 0x0 0x20000000 41 0x0 0x20000000
@@ -244,24 +47,10 @@
244 }; 47 };
245 48
246 pci1: pcie@ffe0a000 { 49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
247 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
248 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
249 pcie@0 { 53 pcie@0 {
250 reg = <0x0 0x0 0x0 0x0 0x0>;
251 #interrupt-cells = <1>;
252 #size-cells = <2>;
253 #address-cells = <3>;
254 device_type = "pci";
255 interrupt-parent = <&mpic>;
256 interrupts = <16 2>;
257 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
258 interrupt-map = <
259 /* IDSEL 0x0 */
260 0000 0x0 0x0 0x1 &mpic 0x4 0x1
261 0000 0x0 0x0 0x2 &mpic 0x5 0x1
262 0000 0x0 0x0 0x3 &mpic 0x6 0x1
263 0000 0x0 0x0 0x4 &mpic 0x7 0x1
264 >;
265 ranges = <0x2000000 0x0 0x80000000 54 ranges = <0x2000000 0x0 0x80000000
266 0x2000000 0x0 0x80000000 55 0x2000000 0x0 0x80000000
267 0x0 0x20000000 56 0x0 0x20000000
@@ -272,3 +61,6 @@
272 }; 61 };
273 }; 62 };
274}; 63};
64
65/include/ "p1010rdb.dtsi"
66/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
new file mode 100644
index 000000000000..d4c4a7730285
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -0,0 +1,234 @@
1/*
2 * P1010 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_ifc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x2000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@40000 {
45 /* 256KB for DTB Image */
46 reg = <0x00040000 0x00040000>;
47 label = "NOR DTB Image";
48 };
49
50 partition@80000 {
51 /* 7 MB for Linux Kernel Image */
52 reg = <0x00080000 0x00700000>;
53 label = "NOR Linux Kernel Image";
54 };
55
56 partition@800000 {
57 /* 20MB for JFFS2 based Root file System */
58 reg = <0x00800000 0x01400000>;
59 label = "NOR JFFS2 Root File System";
60 };
61
62 partition@1f00000 {
63 /* This location must not be altered */
64 /* 512KB for u-boot Bootloader Image */
65 /* 512KB for u-boot Environment Variables */
66 reg = <0x01f00000 0x00100000>;
67 label = "NOR U-Boot Image";
68 read-only;
69 };
70 };
71
72 nand@1,0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,ifc-nand";
76 reg = <0x1 0x0 0x10000>;
77
78 partition@0 {
79 /* This location must not be altered */
80 /* 1MB for u-boot Bootloader Image */
81 reg = <0x0 0x00100000>;
82 label = "NAND U-Boot Image";
83 read-only;
84 };
85
86 partition@100000 {
87 /* 1MB for DTB Image */
88 reg = <0x00100000 0x00100000>;
89 label = "NAND DTB Image";
90 };
91
92 partition@200000 {
93 /* 4MB for Linux Kernel Image */
94 reg = <0x00200000 0x00400000>;
95 label = "NAND Linux Kernel Image";
96 };
97
98 partition@600000 {
99 /* 4MB for Compressed Root file System Image */
100 reg = <0x00600000 0x00400000>;
101 label = "NAND Compressed RFS Image";
102 };
103
104 partition@a00000 {
105 /* 15MB for JFFS2 based Root file System */
106 reg = <0x00a00000 0x00f00000>;
107 label = "NAND JFFS2 Root File System";
108 };
109
110 partition@1900000 {
111 /* 7MB for User Area */
112 reg = <0x01900000 0x00700000>;
113 label = "NAND User area";
114 };
115 };
116
117 cpld@3,0 {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "fsl,p1010rdb-cpld";
121 reg = <0x3 0x0 0x0000020>;
122 bank-width = <1>;
123 device-width = <1>;
124 };
125};
126
127&board_soc {
128 i2c@3000 {
129 rtc@68 {
130 compatible = "pericom,pt7c4338";
131 reg = <0x68>;
132 };
133 };
134
135 spi@7000 {
136 flash@0 {
137 #address-cells = <1>;
138 #size-cells = <1>;
139 compatible = "spansion,s25sl12801";
140 reg = <0>;
141 spi-max-frequency = <50000000>;
142
143 partition@0 {
144 /* 1MB for u-boot Bootloader Image */
145 /* 1MB for Environment */
146 reg = <0x0 0x00100000>;
147 label = "SPI Flash U-Boot Image";
148 read-only;
149 };
150
151 partition@100000 {
152 /* 512KB for DTB Image */
153 reg = <0x00100000 0x00080000>;
154 label = "SPI Flash DTB Image";
155 };
156
157 partition@180000 {
158 /* 4MB for Linux Kernel Image */
159 reg = <0x00180000 0x00400000>;
160 label = "SPI Flash Linux Kernel Image";
161 };
162
163 partition@580000 {
164 /* 4MB for Compressed RFS Image */
165 reg = <0x00580000 0x00400000>;
166 label = "SPI Flash Compressed RFSImage";
167 };
168
169 partition@980000 {
170 /* 6.5MB for JFFS2 based RFS */
171 reg = <0x00980000 0x00680000>;
172 label = "SPI Flash JFFS2 RFS";
173 };
174 };
175 };
176
177 usb@22000 {
178 phy_type = "utmi";
179 dr_mode = "host";
180 };
181
182 mdio@24000 {
183 phy0: ethernet-phy@0 {
184 interrupts = <3 1 0 0>;
185 reg = <0x1>;
186 };
187
188 phy1: ethernet-phy@1 {
189 interrupts = <2 1 0 0>;
190 reg = <0x0>;
191 };
192
193 phy2: ethernet-phy@2 {
194 interrupts = <2 1 0 0>;
195 reg = <0x2>;
196 };
197
198 tbi-phy@3 {
199 device-type = "tbi-phy";
200 reg = <0x3>;
201 };
202 };
203
204 mdio@25000 {
205 tbi0: tbi-phy@11 {
206 reg = <0x11>;
207 device_type = "tbi-phy";
208 };
209 };
210
211 mdio@26000 {
212 tbi1: tbi-phy@11 {
213 reg = <0x11>;
214 device_type = "tbi-phy";
215 };
216 };
217
218 enet0: ethernet@b0000 {
219 phy-handle = <&phy0>;
220 phy-connection-type = "rgmii-id";
221 };
222
223 enet1: ethernet@b1000 {
224 phy-handle = <&phy1>;
225 tbi-handle = <&tbi0>;
226 phy-connection-type = "sgmii";
227 };
228
229 enet2: ethernet@b2000 {
230 phy-handle = <&phy2>;
231 tbi-handle = <&tbi1>;
232 phy-connection-type = "sgmii";
233 };
234};
diff --git a/arch/powerpc/boot/dts/p1010rdb_36b.dts b/arch/powerpc/boot/dts/p1010rdb_36b.dts
new file mode 100644
index 000000000000..64776f4a4651
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1010rdb_36b.dts
@@ -0,0 +1,89 @@
1/*
2 * P1010 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1010si-pre.dtsi"
36
37/ {
38 model = "fsl,P1010RDB";
39 compatible = "fsl,P1010RDB";
40
41 memory {
42 device_type = "memory";
43 };
44
45 board_ifc: ifc: ifc@fffe1e000 {
46 /* NOR, NAND Flashes and CPLD on board */
47 ranges = <0x0 0x0 0xf 0xee000000 0x02000000
48 0x1 0x0 0xf 0xff800000 0x00010000
49 0x3 0x0 0xf 0xffb00000 0x00000020>;
50 reg = <0xf 0xffe1e000 0 0x2000>;
51 };
52
53 board_soc: soc: soc@fffe00000 {
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@fffe09000 {
58 reg = <0xf 0xffe09000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xc0000000
63 0x2000000 0x0 0xc0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@fffe0a000 {
73 reg = <0xf 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0xc0000000
78 0x2000000 0x0 0xc0000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86};
87
88/include/ "p1010rdb.dtsi"
89/include/ "fsl/p1010si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1010si.dtsi b/arch/powerpc/boot/dts/p1010si.dtsi
deleted file mode 100644
index cabe0a453ae6..000000000000
--- a/arch/powerpc/boot/dts/p1010si.dtsi
+++ /dev/null
@@ -1,374 +0,0 @@
1/*
2 * P1010si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1010";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1010@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27 };
28
29 ifc@ffe1e000 {
30 #address-cells = <2>;
31 #size-cells = <1>;
32 compatible = "fsl,ifc", "simple-bus";
33 reg = <0x0 0xffe1e000 0 0x2000>;
34 interrupts = <16 2 19 2>;
35 interrupt-parent = <&mpic>;
36 };
37
38 soc@ffe00000 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 device_type = "soc";
42 compatible = "fsl,p1010-immr", "simple-bus";
43 ranges = <0x0 0x0 0xffe00000 0x100000>;
44 bus-frequency = <0>; // Filled out by uboot.
45
46 ecm-law@0 {
47 compatible = "fsl,ecm-law";
48 reg = <0x0 0x1000>;
49 fsl,num-laws = <12>;
50 };
51
52 ecm@1000 {
53 compatible = "fsl,p1010-ecm", "fsl,ecm";
54 reg = <0x1000 0x1000>;
55 interrupts = <16 2>;
56 interrupt-parent = <&mpic>;
57 };
58
59 memory-controller@2000 {
60 compatible = "fsl,p1010-memory-controller";
61 reg = <0x2000 0x1000>;
62 interrupt-parent = <&mpic>;
63 interrupts = <16 2>;
64 };
65
66 i2c@3000 {
67 #address-cells = <1>;
68 #size-cells = <0>;
69 cell-index = <0>;
70 compatible = "fsl-i2c";
71 reg = <0x3000 0x100>;
72 interrupts = <43 2>;
73 interrupt-parent = <&mpic>;
74 dfsrr;
75 };
76
77 i2c@3100 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 cell-index = <1>;
81 compatible = "fsl-i2c";
82 reg = <0x3100 0x100>;
83 interrupts = <43 2>;
84 interrupt-parent = <&mpic>;
85 dfsrr;
86 };
87
88 serial0: serial@4500 {
89 cell-index = <0>;
90 device_type = "serial";
91 compatible = "ns16550";
92 reg = <0x4500 0x100>;
93 clock-frequency = <0>;
94 interrupts = <42 2>;
95 interrupt-parent = <&mpic>;
96 };
97
98 serial1: serial@4600 {
99 cell-index = <1>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4600 0x100>;
103 clock-frequency = <0>;
104 interrupts = <42 2>;
105 interrupt-parent = <&mpic>;
106 };
107
108 spi@7000 {
109 #address-cells = <1>;
110 #size-cells = <0>;
111 compatible = "fsl,mpc8536-espi";
112 reg = <0x7000 0x1000>;
113 interrupts = <59 0x2>;
114 interrupt-parent = <&mpic>;
115 fsl,espi-num-chipselects = <1>;
116 };
117
118 gpio: gpio-controller@f000 {
119 #gpio-cells = <2>;
120 compatible = "fsl,mpc8572-gpio";
121 reg = <0xf000 0x100>;
122 interrupts = <47 0x2>;
123 interrupt-parent = <&mpic>;
124 gpio-controller;
125 };
126
127 sata@18000 {
128 compatible = "fsl,pq-sata-v2";
129 reg = <0x18000 0x1000>;
130 cell-index = <1>;
131 interrupts = <74 0x2>;
132 interrupt-parent = <&mpic>;
133 };
134
135 sata@19000 {
136 compatible = "fsl,pq-sata-v2";
137 reg = <0x19000 0x1000>;
138 cell-index = <2>;
139 interrupts = <41 0x2>;
140 interrupt-parent = <&mpic>;
141 };
142
143 can0: can@1c000 {
144 compatible = "fsl,p1010-flexcan";
145 reg = <0x1c000 0x1000>;
146 interrupts = <48 0x2>;
147 interrupt-parent = <&mpic>;
148 };
149
150 can1: can@1d000 {
151 compatible = "fsl,p1010-flexcan";
152 reg = <0x1d000 0x1000>;
153 interrupts = <61 0x2>;
154 interrupt-parent = <&mpic>;
155 };
156
157 L2: l2-cache-controller@20000 {
158 compatible = "fsl,p1010-l2-cache-controller",
159 "fsl,p1014-l2-cache-controller";
160 reg = <0x20000 0x1000>;
161 cache-line-size = <32>; // 32 bytes
162 cache-size = <0x40000>; // L2,256K
163 interrupt-parent = <&mpic>;
164 interrupts = <16 2>;
165 };
166
167 dma@21300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p1010-dma", "fsl,eloplus-dma";
171 reg = <0x21300 0x4>;
172 ranges = <0x0 0x21100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
176 reg = <0x0 0x80>;
177 cell-index = <0>;
178 interrupt-parent = <&mpic>;
179 interrupts = <20 2>;
180 };
181 dma-channel@80 {
182 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
183 reg = <0x80 0x80>;
184 cell-index = <1>;
185 interrupt-parent = <&mpic>;
186 interrupts = <21 2>;
187 };
188 dma-channel@100 {
189 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
190 reg = <0x100 0x80>;
191 cell-index = <2>;
192 interrupt-parent = <&mpic>;
193 interrupts = <22 2>;
194 };
195 dma-channel@180 {
196 compatible = "fsl,p1010-dma-channel", "fsl,eloplus-dma-channel";
197 reg = <0x180 0x80>;
198 cell-index = <3>;
199 interrupt-parent = <&mpic>;
200 interrupts = <23 2>;
201 };
202 };
203
204 usb@22000 {
205 compatible = "fsl-usb2-dr";
206 reg = <0x22000 0x1000>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupt-parent = <&mpic>;
210 interrupts = <28 0x2>;
211 dr_mode = "host";
212 };
213
214 mdio@24000 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,etsec2-mdio";
218 reg = <0x24000 0x1000 0xb0030 0x4>;
219 };
220
221 mdio@25000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
224 compatible = "fsl,etsec2-tbi";
225 reg = <0x25000 0x1000 0xb1030 0x4>;
226 tbi0: tbi-phy@11 {
227 reg = <0x11>;
228 device_type = "tbi-phy";
229 };
230 };
231
232 mdio@26000 {
233 #address-cells = <1>;
234 #size-cells = <0>;
235 compatible = "fsl,etsec2-tbi";
236 reg = <0x26000 0x1000 0xb1030 0x4>;
237 tbi1: tbi-phy@11 {
238 reg = <0x11>;
239 device_type = "tbi-phy";
240 };
241 };
242
243 sdhci@2e000 {
244 compatible = "fsl,esdhc";
245 reg = <0x2e000 0x1000>;
246 interrupts = <72 0x8>;
247 interrupt-parent = <&mpic>;
248 /* Filled in by U-Boot */
249 clock-frequency = <0>;
250 fsl,sdhci-auto-cmd12;
251 };
252
253 enet0: ethernet@b0000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 device_type = "network";
257 model = "eTSEC";
258 compatible = "fsl,etsec2";
259 fsl,num_rx_queues = <0x8>;
260 fsl,num_tx_queues = <0x8>;
261 local-mac-address = [ 00 00 00 00 00 00 ];
262 interrupt-parent = <&mpic>;
263
264 queue-group@0 {
265 #address-cells = <1>;
266 #size-cells = <1>;
267 reg = <0xb0000 0x1000>;
268 fsl,rx-bit-map = <0xff>;
269 fsl,tx-bit-map = <0xff>;
270 interrupts = <29 2 30 2 34 2>;
271 };
272
273 };
274
275 enet1: ethernet@b1000 {
276 #address-cells = <1>;
277 #size-cells = <1>;
278 device_type = "network";
279 model = "eTSEC";
280 compatible = "fsl,etsec2";
281 fsl,num_rx_queues = <0x8>;
282 fsl,num_tx_queues = <0x8>;
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 interrupt-parent = <&mpic>;
285
286 queue-group@0 {
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <0xb1000 0x1000>;
290 fsl,rx-bit-map = <0xff>;
291 fsl,tx-bit-map = <0xff>;
292 interrupts = <35 2 36 2 40 2>;
293 };
294
295 };
296
297 enet2: ethernet@b2000 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 device_type = "network";
301 model = "eTSEC";
302 compatible = "fsl,etsec2";
303 fsl,num_rx_queues = <0x8>;
304 fsl,num_tx_queues = <0x8>;
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 interrupt-parent = <&mpic>;
307
308 queue-group@0 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 reg = <0xb2000 0x1000>;
312 fsl,rx-bit-map = <0xff>;
313 fsl,tx-bit-map = <0xff>;
314 interrupts = <31 2 32 2 33 2>;
315 };
316
317 };
318
319 mpic: pic@40000 {
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <0x40000 0x40000>;
324 compatible = "chrp,open-pic";
325 device_type = "open-pic";
326 };
327
328 msi@41600 {
329 compatible = "fsl,p1010-msi", "fsl,mpic-msi";
330 reg = <0x41600 0x80>;
331 msi-available-ranges = <0 0x100>;
332 interrupts = <
333 0xe0 0
334 0xe1 0
335 0xe2 0
336 0xe3 0
337 0xe4 0
338 0xe5 0
339 0xe6 0
340 0xe7 0>;
341 interrupt-parent = <&mpic>;
342 };
343
344 global-utilities@e0000 { //global utilities block
345 compatible = "fsl,p1010-guts";
346 reg = <0xe0000 0x1000>;
347 fsl,has-rstcr;
348 };
349 };
350
351 pci0: pcie@ffe09000 {
352 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
353 device_type = "pci";
354 #size-cells = <2>;
355 #address-cells = <3>;
356 reg = <0 0xffe09000 0 0x1000>;
357 bus-range = <0 255>;
358 clock-frequency = <33333333>;
359 interrupt-parent = <&mpic>;
360 interrupts = <16 2>;
361 };
362
363 pci1: pcie@ffe0a000 {
364 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3", "fsl,qoriq-pcie-v2.2";
365 device_type = "pci";
366 #size-cells = <2>;
367 #address-cells = <3>;
368 reg = <0 0xffe0a000 0 0x1000>;
369 bus-range = <0 255>;
370 clock-frequency = <33333333>;
371 interrupt-parent = <&mpic>;
372 interrupts = <16 2>;
373 };
374};
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index d6a8ae458137..518bf99b1f50 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,267 +9,33 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p1020si.dtsi" 12/include/ "fsl/p1020si-pre.dtsi"
13
14/ { 13/ {
15 model = "fsl,P1020RDB"; 14 model = "fsl,P1020RDB";
16 compatible = "fsl,P1020RDB"; 15 compatible = "fsl,P1020RDB";
17 16
18 aliases {
19 serial0 = &serial0;
20 serial1 = &serial1;
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 };
27
28 memory { 17 memory {
29 device_type = "memory"; 18 device_type = "memory";
30 }; 19 };
31 20
32 localbus@ffe05000 { 21 board_lbc: lbc: localbus@ffe05000 {
22 reg = <0 0xffe05000 0 0x1000>;
33 23
34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 25 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
36 0x1 0x0 0x0 0xffa00000 0x00040000 26 0x1 0x0 0x0 0xffa00000 0x00040000
37 0x2 0x0 0x0 0xffb00000 0x00020000>; 27 0x2 0x0 0x0 0xffb00000 0x00020000>;
38
39 nor@0,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x0 0x0 0x1000000>;
44 bank-width = <2>;
45 device-width = <1>;
46
47 partition@0 {
48 /* This location must not be altered */
49 /* 256KB for Vitesse 7385 Switch firmware */
50 reg = <0x0 0x00040000>;
51 label = "NOR (RO) Vitesse-7385 Firmware";
52 read-only;
53 };
54
55 partition@40000 {
56 /* 256KB for DTB Image */
57 reg = <0x00040000 0x00040000>;
58 label = "NOR (RO) DTB Image";
59 read-only;
60 };
61
62 partition@80000 {
63 /* 3.5 MB for Linux Kernel Image */
64 reg = <0x00080000 0x00380000>;
65 label = "NOR (RO) Linux Kernel Image";
66 read-only;
67 };
68
69 partition@400000 {
70 /* 11MB for JFFS2 based Root file System */
71 reg = <0x00400000 0x00b00000>;
72 label = "NOR (RW) JFFS2 Root File System";
73 };
74
75 partition@f00000 {
76 /* This location must not be altered */
77 /* 512KB for u-boot Bootloader Image */
78 /* 512KB for u-boot Environment Variables */
79 reg = <0x00f00000 0x00100000>;
80 label = "NOR (RO) U-Boot Image";
81 read-only;
82 };
83 };
84
85 nand@1,0 {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 compatible = "fsl,p1020-fcm-nand",
89 "fsl,elbc-fcm-nand";
90 reg = <0x1 0x0 0x40000>;
91
92 partition@0 {
93 /* This location must not be altered */
94 /* 1MB for u-boot Bootloader Image */
95 reg = <0x0 0x00100000>;
96 label = "NAND (RO) U-Boot Image";
97 read-only;
98 };
99
100 partition@100000 {
101 /* 1MB for DTB Image */
102 reg = <0x00100000 0x00100000>;
103 label = "NAND (RO) DTB Image";
104 read-only;
105 };
106
107 partition@200000 {
108 /* 4MB for Linux Kernel Image */
109 reg = <0x00200000 0x00400000>;
110 label = "NAND (RO) Linux Kernel Image";
111 read-only;
112 };
113
114 partition@600000 {
115 /* 4MB for Compressed Root file System Image */
116 reg = <0x00600000 0x00400000>;
117 label = "NAND (RO) Compressed RFS Image";
118 read-only;
119 };
120
121 partition@a00000 {
122 /* 7MB for JFFS2 based Root file System */
123 reg = <0x00a00000 0x00700000>;
124 label = "NAND (RW) JFFS2 Root File System";
125 };
126
127 partition@1100000 {
128 /* 15MB for JFFS2 based Root file System */
129 reg = <0x01100000 0x00f00000>;
130 label = "NAND (RW) Writable User area";
131 };
132 };
133
134 L2switch@2,0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "vitesse-7385";
138 reg = <0x2 0x0 0x20000>;
139 };
140
141 }; 28 };
142 29
143 soc@ffe00000 { 30 board_soc: soc: soc@ffe00000 {
144 i2c@3000 { 31 ranges = <0x0 0x0 0xffe00000 0x100000>;
145 rtc@68 {
146 compatible = "dallas,ds1339";
147 reg = <0x68>;
148 };
149 };
150
151 spi@7000 {
152
153 fsl_m25p80@0 {
154 #address-cells = <1>;
155 #size-cells = <1>;
156 compatible = "fsl,espi-flash";
157 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>;
161 mode = <0>;
162
163 partition@0 {
164 /* 512KB for u-boot Bootloader Image */
165 reg = <0x0 0x00080000>;
166 label = "SPI (RO) U-Boot Image";
167 read-only;
168 };
169
170 partition@80000 {
171 /* 512KB for DTB Image */
172 reg = <0x00080000 0x00080000>;
173 label = "SPI (RO) DTB Image";
174 read-only;
175 };
176
177 partition@100000 {
178 /* 4MB for Linux Kernel Image */
179 reg = <0x00100000 0x00400000>;
180 label = "SPI (RO) Linux Kernel Image";
181 read-only;
182 };
183
184 partition@500000 {
185 /* 4MB for Compressed RFS Image */
186 reg = <0x00500000 0x00400000>;
187 label = "SPI (RO) Compressed RFS Image";
188 read-only;
189 };
190
191 partition@900000 {
192 /* 7MB for JFFS2 based RFS */
193 reg = <0x00900000 0x00700000>;
194 label = "SPI (RW) JFFS2 RFS";
195 };
196 };
197 };
198
199 mdio@24000 {
200
201 phy0: ethernet-phy@0 {
202 interrupt-parent = <&mpic>;
203 interrupts = <3 1>;
204 reg = <0x0>;
205 };
206
207 phy1: ethernet-phy@1 {
208 interrupt-parent = <&mpic>;
209 interrupts = <2 1>;
210 reg = <0x1>;
211 };
212 };
213
214 mdio@25000 {
215
216 tbi0: tbi-phy@11 {
217 reg = <0x11>;
218 device_type = "tbi-phy";
219 };
220 };
221
222 enet0: ethernet@b0000 {
223 fixed-link = <1 1 1000 0 0>;
224 phy-connection-type = "rgmii-id";
225
226 };
227
228 enet1: ethernet@b1000 {
229 phy-handle = <&phy0>;
230 tbi-handle = <&tbi0>;
231 phy-connection-type = "sgmii";
232
233 };
234
235 enet2: ethernet@b2000 {
236 phy-handle = <&phy1>;
237 phy-connection-type = "rgmii-id";
238
239 };
240
241 usb@22000 {
242 phy_type = "ulpi";
243 };
244
245 /* USB2 is shared with localbus, so it must be disabled
246 by default. We can't put 'status = "disabled";' here
247 since U-Boot doesn't clear the status property when
248 it enables USB2. OTOH, U-Boot does create a new node
249 when there isn't any. So, just comment it out.
250 usb@23000 {
251 phy_type = "ulpi";
252 };
253 */
254
255 }; 32 };
256 33
257 pci0: pcie@ffe09000 { 34 pci0: pcie@ffe09000 {
258 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 35 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
259 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 36 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 37 reg = <0 0xffe09000 0 0x1000>;
261 interrupt-map = <
262 /* IDSEL 0x0 */
263 0000 0x0 0x0 0x1 &mpic 0x4 0x1
264 0000 0x0 0x0 0x2 &mpic 0x5 0x1
265 0000 0x0 0x0 0x3 &mpic 0x6 0x1
266 0000 0x0 0x0 0x4 &mpic 0x7 0x1
267 >;
268 pcie@0 { 38 pcie@0 {
269 reg = <0x0 0x0 0x0 0x0 0x0>;
270 #size-cells = <2>;
271 #address-cells = <3>;
272 device_type = "pci";
273 ranges = <0x2000000 0x0 0xa0000000 39 ranges = <0x2000000 0x0 0xa0000000
274 0x2000000 0x0 0xa0000000 40 0x2000000 0x0 0xa0000000
275 0x0 0x20000000 41 0x0 0x20000000
@@ -281,21 +47,10 @@
281 }; 47 };
282 48
283 pci1: pcie@ffe0a000 { 49 pci1: pcie@ffe0a000 {
50 reg = <0 0xffe0a000 0 0x1000>;
284 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 51 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
285 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 52 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
286 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
287 interrupt-map = <
288 /* IDSEL 0x0 */
289 0000 0x0 0x0 0x1 &mpic 0x0 0x1
290 0000 0x0 0x0 0x2 &mpic 0x1 0x1
291 0000 0x0 0x0 0x3 &mpic 0x2 0x1
292 0000 0x0 0x0 0x4 &mpic 0x3 0x1
293 >;
294 pcie@0 { 53 pcie@0 {
295 reg = <0x0 0x0 0x0 0x0 0x0>;
296 #size-cells = <2>;
297 #address-cells = <3>;
298 device_type = "pci";
299 ranges = <0x2000000 0x0 0x80000000 54 ranges = <0x2000000 0x0 0x80000000
300 0x2000000 0x0 0x80000000 55 0x2000000 0x0 0x80000000
301 0x0 0x20000000 56 0x0 0x20000000
@@ -306,3 +61,6 @@
306 }; 61 };
307 }; 62 };
308}; 63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb.dtsi b/arch/powerpc/boot/dts/p1020rdb.dtsi
new file mode 100644
index 000000000000..b5bd86f4baf2
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb.dtsi
@@ -0,0 +1,247 @@
1/*
2 * P1020 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR (RO) Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR (RO) DTB Image";
56 read-only;
57 };
58
59 partition@80000 {
60 /* 3.5 MB for Linux Kernel Image */
61 reg = <0x00080000 0x00380000>;
62 label = "NOR (RO) Linux Kernel Image";
63 read-only;
64 };
65
66 partition@400000 {
67 /* 11MB for JFFS2 based Root file System */
68 reg = <0x00400000 0x00b00000>;
69 label = "NOR (RW) JFFS2 Root File System";
70 };
71
72 partition@f00000 {
73 /* This location must not be altered */
74 /* 512KB for u-boot Bootloader Image */
75 /* 512KB for u-boot Environment Variables */
76 reg = <0x00f00000 0x00100000>;
77 label = "NOR (RO) U-Boot Image";
78 read-only;
79 };
80 };
81
82 nand@1,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "fsl,p1020-fcm-nand",
86 "fsl,elbc-fcm-nand";
87 reg = <0x1 0x0 0x40000>;
88
89 partition@0 {
90 /* This location must not be altered */
91 /* 1MB for u-boot Bootloader Image */
92 reg = <0x0 0x00100000>;
93 label = "NAND (RO) U-Boot Image";
94 read-only;
95 };
96
97 partition@100000 {
98 /* 1MB for DTB Image */
99 reg = <0x00100000 0x00100000>;
100 label = "NAND (RO) DTB Image";
101 read-only;
102 };
103
104 partition@200000 {
105 /* 4MB for Linux Kernel Image */
106 reg = <0x00200000 0x00400000>;
107 label = "NAND (RO) Linux Kernel Image";
108 read-only;
109 };
110
111 partition@600000 {
112 /* 4MB for Compressed Root file System Image */
113 reg = <0x00600000 0x00400000>;
114 label = "NAND (RO) Compressed RFS Image";
115 read-only;
116 };
117
118 partition@a00000 {
119 /* 7MB for JFFS2 based Root file System */
120 reg = <0x00a00000 0x00700000>;
121 label = "NAND (RW) JFFS2 Root File System";
122 };
123
124 partition@1100000 {
125 /* 15MB for JFFS2 based Root file System */
126 reg = <0x01100000 0x00f00000>;
127 label = "NAND (RW) Writable User area";
128 };
129 };
130
131 L2switch@2,0 {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 compatible = "vitesse-7385";
135 reg = <0x2 0x0 0x20000>;
136 };
137};
138
139&board_soc {
140 i2c@3000 {
141 rtc@68 {
142 compatible = "dallas,ds1339";
143 reg = <0x68>;
144 };
145 };
146
147 spi@7000 {
148 flash@0 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "spansion,s25sl12801";
152 reg = <0>;
153 spi-max-frequency = <40000000>; /* input clock */
154
155 partition@u-boot {
156 /* 512KB for u-boot Bootloader Image */
157 reg = <0x0 0x00080000>;
158 label = "u-boot";
159 read-only;
160 };
161
162 partition@dtb {
163 /* 512KB for DTB Image */
164 reg = <0x00080000 0x00080000>;
165 label = "dtb";
166 read-only;
167 };
168
169 partition@kernel {
170 /* 4MB for Linux Kernel Image */
171 reg = <0x00100000 0x00400000>;
172 label = "kernel";
173 read-only;
174 };
175
176 partition@fs {
177 /* 4MB for Compressed RFS Image */
178 reg = <0x00500000 0x00400000>;
179 label = "file system";
180 read-only;
181 };
182
183 partition@jffs-fs {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "file system jffs2";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 /* USB2 is shared with localbus, so it must be disabled
196 by default. We can't put 'status = "disabled";' here
197 since U-Boot doesn't clear the status property when
198 it enables USB2. OTOH, U-Boot does create a new node
199 when there isn't any. So, just comment it out.
200 usb@23000 {
201 phy_type = "ulpi";
202 };
203 */
204
205 mdio@24000 {
206 phy0: ethernet-phy@0 {
207 interrupt-parent = <&mpic>;
208 interrupts = <3 1>;
209 reg = <0x0>;
210 };
211
212 phy1: ethernet-phy@1 {
213 interrupt-parent = <&mpic>;
214 interrupts = <2 1>;
215 reg = <0x1>;
216 };
217
218 tbi-phy@2 {
219 device_type = "tbi-phy";
220 reg = <0x2>;
221 };
222 };
223
224 mdio@25000 {
225 tbi0: tbi-phy@11 {
226 reg = <0x11>;
227 device_type = "tbi-phy";
228 };
229 };
230
231 enet0: ethernet@b0000 {
232 fixed-link = <1 1 1000 0 0>;
233 phy-connection-type = "rgmii-id";
234
235 };
236
237 enet1: ethernet@b1000 {
238 phy-handle = <&phy0>;
239 tbi-handle = <&tbi0>;
240 phy-connection-type = "sgmii";
241 };
242
243 enet2: ethernet@b2000 {
244 phy-handle = <&phy1>;
245 phy-connection-type = "rgmii-id";
246 };
247};
diff --git a/arch/powerpc/boot/dts/p1020rdb_36b.dts b/arch/powerpc/boot/dts/p1020rdb_36b.dts
new file mode 100644
index 000000000000..bdbdb6097e57
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_36b.dts
@@ -0,0 +1,66 @@
1/*
2 * P1020 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/p1020si-pre.dtsi"
13/ {
14 model = "fsl,P1020RDB";
15 compatible = "fsl,P1020RDB";
16
17 memory {
18 device_type = "memory";
19 };
20
21 board_lbc: lbc: localbus@fffe05000 {
22 reg = <0xf 0xffe05000 0 0x1000>;
23
24 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
25 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
26 0x1 0x0 0xf 0xffa00000 0x00040000
27 0x2 0x0 0xf 0xffb00000 0x00020000>;
28 };
29
30 board_soc: soc: soc@fffe00000 {
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
32 };
33
34 pci0: pcie@fffe09000 {
35 reg = <0xf 0xffe09000 0 0x1000>;
36 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
37 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
38 pcie@0 {
39 ranges = <0x2000000 0x0 0xc0000000
40 0x2000000 0x0 0xc0000000
41 0x0 0x20000000
42
43 0x1000000 0x0 0x0
44 0x1000000 0x0 0x0
45 0x0 0x100000>;
46 };
47 };
48
49 pci1: pcie@fffe0a000 {
50 reg = <0xf 0xffe0a000 0 0x1000>;
51 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
52 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
53 pcie@0 {
54 ranges = <0x2000000 0x0 0x80000000
55 0x2000000 0x0 0x80000000
56 0x0 0x20000000
57
58 0x1000000 0x0 0x0
59 0x1000000 0x0 0x0
60 0x0 0x100000>;
61 };
62 };
63};
64
65/include/ "p1020rdb.dtsi"
66/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
index f0bf7f42f097..41b4585c5da8 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -16,7 +16,7 @@
16 * option) any later version. 16 * option) any later version.
17 */ 17 */
18 18
19/include/ "p1020si.dtsi" 19/include/ "p1020rdb.dts"
20 20
21/ { 21/ {
22 model = "fsl,P1020RDB"; 22 model = "fsl,P1020RDB";
@@ -32,7 +32,7 @@
32 32
33 cpus { 33 cpus {
34 PowerPC,P1020@1 { 34 PowerPC,P1020@1 {
35 status = "disabled"; 35 status = "disabled";
36 }; 36 };
37 }; 37 };
38 38
@@ -45,169 +45,19 @@
45 }; 45 };
46 46
47 soc@ffe00000 { 47 soc@ffe00000 {
48 i2c@3000 {
49 rtc@68 {
50 compatible = "dallas,ds1339";
51 reg = <0x68>;
52 };
53 };
54
55 serial1: serial@4600 { 48 serial1: serial@4600 {
56 status = "disabled"; 49 status = "disabled";
57 }; 50 };
58 51
59 spi@7000 {
60 fsl_m25p80@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,espi-flash";
64 reg = <0>;
65 linux,modalias = "fsl_m25p80";
66 spi-max-frequency = <40000000>;
67
68 partition@0 {
69 /* 512KB for u-boot Bootloader Image */
70 reg = <0x0 0x00080000>;
71 label = "SPI (RO) U-Boot Image";
72 read-only;
73 };
74
75 partition@80000 {
76 /* 512KB for DTB Image */
77 reg = <0x00080000 0x00080000>;
78 label = "SPI (RO) DTB Image";
79 read-only;
80 };
81
82 partition@100000 {
83 /* 4MB for Linux Kernel Image */
84 reg = <0x00100000 0x00400000>;
85 label = "SPI (RO) Linux Kernel Image";
86 read-only;
87 };
88
89 partition@500000 {
90 /* 4MB for Compressed RFS Image */
91 reg = <0x00500000 0x00400000>;
92 label = "SPI (RO) Compressed RFS Image";
93 read-only;
94 };
95
96 partition@900000 {
97 /* 7MB for JFFS2 based RFS */
98 reg = <0x00900000 0x00700000>;
99 label = "SPI (RW) JFFS2 RFS";
100 };
101 };
102 };
103
104 mdio@24000 {
105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
107 interrupts = <3 1>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupt-parent = <&mpic>;
112 interrupts = <2 1>;
113 reg = <0x1>;
114 };
115 };
116
117 mdio@25000 {
118 tbi0: tbi-phy@11 {
119 reg = <0x11>;
120 device_type = "tbi-phy";
121 };
122 };
123
124 enet0: ethernet@b0000 { 52 enet0: ethernet@b0000 {
125 status = "disabled"; 53 status = "disabled";
126 }; 54 };
127 55
128 enet1: ethernet@b1000 {
129 phy-handle = <&phy0>;
130 tbi-handle = <&tbi0>;
131 phy-connection-type = "sgmii";
132 };
133
134 enet2: ethernet@b2000 {
135 phy-handle = <&phy1>;
136 phy-connection-type = "rgmii-id";
137 };
138
139 usb@22000 {
140 phy_type = "ulpi";
141 };
142
143 /* USB2 is shared with localbus, so it must be disabled
144 by default. We can't put 'status = "disabled";' here
145 since U-Boot doesn't clear the status property when
146 it enables USB2. OTOH, U-Boot does create a new node
147 when there isn't any. So, just comment it out.
148 usb@23000 {
149 phy_type = "ulpi";
150 };
151 */
152
153 mpic: pic@40000 { 56 mpic: pic@40000 {
154 protected-sources = < 57 protected-sources = <
155 42 29 30 34 /* serial1, enet0-queue-group0 */ 58 42 29 30 34 /* serial1, enet0-queue-group0 */
156 17 18 24 45 /* enet0-queue-group1, crypto */ 59 17 18 24 45 /* enet0-queue-group1, crypto */
157 >; 60 >;
158 }; 61 };
159
160 };
161
162 pci0: pcie@ffe09000 {
163 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
164 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
165 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
166 interrupt-map = <
167 /* IDSEL 0x0 */
168 0000 0x0 0x0 0x1 &mpic 0x4 0x1
169 0000 0x0 0x0 0x2 &mpic 0x5 0x1
170 0000 0x0 0x0 0x3 &mpic 0x6 0x1
171 0000 0x0 0x0 0x4 &mpic 0x7 0x1
172 >;
173 pcie@0 {
174 reg = <0x0 0x0 0x0 0x0 0x0>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 device_type = "pci";
178 ranges = <0x2000000 0x0 0xa0000000
179 0x2000000 0x0 0xa0000000
180 0x0 0x20000000
181
182 0x1000000 0x0 0x0
183 0x1000000 0x0 0x0
184 0x0 0x100000>;
185 };
186 };
187
188 pci1: pcie@ffe0a000 {
189 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
190 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
191 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
192 interrupt-map = <
193 /* IDSEL 0x0 */
194 0000 0x0 0x0 0x1 &mpic 0x0 0x1
195 0000 0x0 0x0 0x2 &mpic 0x1 0x1
196 0000 0x0 0x0 0x3 &mpic 0x2 0x1
197 0000 0x0 0x0 0x4 &mpic 0x3 0x1
198 >;
199 pcie@0 {
200 reg = <0x0 0x0 0x0 0x0 0x0>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 device_type = "pci";
204 ranges = <0x2000000 0x0 0x80000000
205 0x2000000 0x0 0x80000000
206 0x0 0x20000000
207
208 0x1000000 0x0 0x0
209 0x1000000 0x0 0x0
210 0x0 0x100000>;
211 };
212 }; 62 };
213}; 63};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
index 6ec02204a44e..517453821884 100644
--- a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
@@ -15,7 +15,7 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/include/ "p1020si.dtsi" 18/include/ "p1020rdb.dts"
19 19
20/ { 20/ {
21 model = "fsl,P1020RDB"; 21 model = "fsl,P1020RDB";
@@ -28,7 +28,7 @@
28 28
29 cpus { 29 cpus {
30 PowerPC,P1020@0 { 30 PowerPC,P1020@0 {
31 status = "disabled"; 31 status = "disabled";
32 }; 32 };
33 }; 33 };
34 34
@@ -85,12 +85,6 @@
85 status = "disabled"; 85 status = "disabled";
86 }; 86 };
87 87
88 enet0: ethernet@b0000 {
89 fixed-link = <1 1 1000 0 0>;
90 phy-connection-type = "rgmii-id";
91
92 };
93
94 enet1: ethernet@b1000 { 88 enet1: ethernet@b1000 {
95 status = "disabled"; 89 status = "disabled";
96 }; 90 };
@@ -135,7 +129,6 @@
135 global-utilities@e0000 { //global utilities block 129 global-utilities@e0000 { //global utilities block
136 status = "disabled"; 130 status = "disabled";
137 }; 131 };
138
139 }; 132 };
140 133
141 pci0: pcie@ffe09000 { 134 pci0: pcie@ffe09000 {
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
deleted file mode 100644
index 5c5acb66c3fc..000000000000
--- a/arch/powerpc/boot/dts/p1020si.dtsi
+++ /dev/null
@@ -1,377 +0,0 @@
1/*
2 * P1020si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P1020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p1020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <16 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p1020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <16 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 gpio: gpio-controller@f000 {
126 #gpio-cells = <2>;
127 compatible = "fsl,mpc8572-gpio";
128 reg = <0xf000 0x100>;
129 interrupts = <47 0x2>;
130 interrupt-parent = <&mpic>;
131 gpio-controller;
132 };
133
134 L2: l2-cache-controller@20000 {
135 compatible = "fsl,p1020-l2-cache-controller";
136 reg = <0x20000 0x1000>;
137 cache-line-size = <32>; // 32 bytes
138 cache-size = <0x40000>; // L2,256K
139 interrupt-parent = <&mpic>;
140 interrupts = <16 2>;
141 };
142
143 dma@21300 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,eloplus-dma";
147 reg = <0x21300 0x4>;
148 ranges = <0x0 0x21100 0x200>;
149 cell-index = <0>;
150 dma-channel@0 {
151 compatible = "fsl,eloplus-dma-channel";
152 reg = <0x0 0x80>;
153 cell-index = <0>;
154 interrupt-parent = <&mpic>;
155 interrupts = <20 2>;
156 };
157 dma-channel@80 {
158 compatible = "fsl,eloplus-dma-channel";
159 reg = <0x80 0x80>;
160 cell-index = <1>;
161 interrupt-parent = <&mpic>;
162 interrupts = <21 2>;
163 };
164 dma-channel@100 {
165 compatible = "fsl,eloplus-dma-channel";
166 reg = <0x100 0x80>;
167 cell-index = <2>;
168 interrupt-parent = <&mpic>;
169 interrupts = <22 2>;
170 };
171 dma-channel@180 {
172 compatible = "fsl,eloplus-dma-channel";
173 reg = <0x180 0x80>;
174 cell-index = <3>;
175 interrupt-parent = <&mpic>;
176 interrupts = <23 2>;
177 };
178 };
179
180 mdio@24000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,etsec2-mdio";
184 reg = <0x24000 0x1000 0xb0030 0x4>;
185
186 };
187
188 mdio@25000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,etsec2-tbi";
192 reg = <0x25000 0x1000 0xb1030 0x4>;
193
194 };
195
196 enet0: ethernet@b0000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "fsl,etsec2";
202 fsl,num_rx_queues = <0x8>;
203 fsl,num_tx_queues = <0x8>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupt-parent = <&mpic>;
206
207 queue-group@0 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0xb0000 0x1000>;
211 interrupts = <29 2 30 2 34 2>;
212 };
213
214 queue-group@1 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 reg = <0xb4000 0x1000>;
218 interrupts = <17 2 18 2 24 2>;
219 };
220 };
221
222 enet1: ethernet@b1000 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 device_type = "network";
226 model = "eTSEC";
227 compatible = "fsl,etsec2";
228 fsl,num_rx_queues = <0x8>;
229 fsl,num_tx_queues = <0x8>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 interrupt-parent = <&mpic>;
232
233 queue-group@0 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 reg = <0xb1000 0x1000>;
237 interrupts = <35 2 36 2 40 2>;
238 };
239
240 queue-group@1 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 reg = <0xb5000 0x1000>;
244 interrupts = <51 2 52 2 67 2>;
245 };
246 };
247
248 enet2: ethernet@b2000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "fsl,etsec2";
254 fsl,num_rx_queues = <0x8>;
255 fsl,num_tx_queues = <0x8>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupt-parent = <&mpic>;
258
259 queue-group@0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0xb2000 0x1000>;
263 interrupts = <31 2 32 2 33 2>;
264 };
265
266 queue-group@1 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb6000 0x1000>;
270 interrupts = <25 2 26 2 27 2>;
271 };
272 };
273
274 usb@22000 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "fsl-usb2-dr";
278 reg = <0x22000 0x1000>;
279 interrupt-parent = <&mpic>;
280 interrupts = <28 0x2>;
281 };
282
283 /* USB2 is shared with localbus, so it must be disabled
284 by default. We can't put 'status = "disabled";' here
285 since U-Boot doesn't clear the status property when
286 it enables USB2. OTOH, U-Boot does create a new node
287 when there isn't any. So, just comment it out.
288 usb@23000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl-usb2-dr";
292 reg = <0x23000 0x1000>;
293 interrupt-parent = <&mpic>;
294 interrupts = <46 0x2>;
295 phy_type = "ulpi";
296 };
297 */
298
299 sdhci@2e000 {
300 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
301 reg = <0x2e000 0x1000>;
302 interrupts = <72 0x2>;
303 interrupt-parent = <&mpic>;
304 /* Filled in by U-Boot */
305 clock-frequency = <0>;
306 };
307
308 crypto@30000 {
309 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
310 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
311 reg = <0x30000 0x10000>;
312 interrupts = <45 2 58 2>;
313 interrupt-parent = <&mpic>;
314 fsl,num-channels = <4>;
315 fsl,channel-fifo-len = <24>;
316 fsl,exec-units-mask = <0xbfe>;
317 fsl,descriptor-types-mask = <0x3ab0ebf>;
318 };
319
320 mpic: pic@40000 {
321 interrupt-controller;
322 #address-cells = <0>;
323 #interrupt-cells = <2>;
324 reg = <0x40000 0x40000>;
325 compatible = "chrp,open-pic";
326 device_type = "open-pic";
327 };
328
329 msi@41600 {
330 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
331 reg = <0x41600 0x80>;
332 msi-available-ranges = <0 0x100>;
333 interrupts = <
334 0xe0 0
335 0xe1 0
336 0xe2 0
337 0xe3 0
338 0xe4 0
339 0xe5 0
340 0xe6 0
341 0xe7 0>;
342 interrupt-parent = <&mpic>;
343 };
344
345 global-utilities@e0000 { //global utilities block
346 compatible = "fsl,p1020-guts","fsl,p2020-guts";
347 reg = <0xe0000 0x1000>;
348 fsl,has-rstcr;
349 };
350 };
351
352 pci0: pcie@ffe09000 {
353 compatible = "fsl,mpc8548-pcie";
354 device_type = "pci";
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,mpc8548-pcie";
367 device_type = "pci";
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
371 reg = <0 0xffe0a000 0 0x1000>;
372 bus-range = <0 255>;
373 clock-frequency = <33333333>;
374 interrupt-parent = <&mpic>;
375 interrupts = <16 2>;
376 };
377};
diff --git a/arch/powerpc/boot/dts/p1021mds.dts b/arch/powerpc/boot/dts/p1021mds.dts
index ad5b85269004..d9540791e434 100644
--- a/arch/powerpc/boot/dts/p1021mds.dts
+++ b/arch/powerpc/boot/dts/p1021mds.dts
@@ -9,53 +9,22 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "fsl/p1021si-pre.dtsi"
13/ { 13/ {
14 model = "fsl,P1021"; 14 model = "fsl,P1021";
15 compatible = "fsl,P1021MDS"; 15 compatible = "fsl,P1021MDS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 16
19 aliases { 17 aliases {
20 serial0 = &serial0;
21 serial1 = &serial1;
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3; 18 ethernet3 = &enet3;
26 ethernet4 = &enet4; 19 ethernet4 = &enet4;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 PowerPC,P1021@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 };
40
41 PowerPC,P1021@1 {
42 device_type = "cpu";
43 reg = <0x1>;
44 next-level-cache = <&L2>;
45 };
46 }; 20 };
47 21
48 memory { 22 memory {
49 device_type = "memory"; 23 device_type = "memory";
50 }; 24 };
51 25
52 localbus@ffe05000 { 26 lbc: localbus@ffe05000 {
53 #address-cells = <2>; 27 reg = <0x0 0xffe05000 0x0 0x1000>;
54 #size-cells = <1>;
55 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
56 reg = <0 0xffe05000 0 0x1000>;
57 interrupts = <19 2>;
58 interrupt-parent = <&mpic>;
59 28
60 /* NAND Flash, BCSR, PMC0/1*/ 29 /* NAND Flash, BCSR, PMC0/1*/
61 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000 30 ranges = <0x0 0x0 0x0 0xfc000000 0x02000000
@@ -138,99 +107,26 @@
138 }; 107 };
139 }; 108 };
140 109
141 soc@ffe00000 { 110 soc: soc@ffe00000 {
142
143 #address-cells = <1>;
144 #size-cells = <1>;
145 device_type = "soc";
146 compatible = "fsl,p1021-immr", "simple-bus"; 111 compatible = "fsl,p1021-immr", "simple-bus";
147 ranges = <0x0 0x0 0xffe00000 0x100000>; 112 ranges = <0x0 0x0 0xffe00000 0x100000>;
148 bus-frequency = <0>; // Filled out by uboot.
149
150 ecm-law@0 {
151 compatible = "fsl,ecm-law";
152 reg = <0x0 0x1000>;
153 fsl,num-laws = <12>;
154 };
155
156 ecm@1000 {
157 compatible = "fsl,p1021-ecm", "fsl,ecm";
158 reg = <0x1000 0x1000>;
159 interrupts = <16 2>;
160 interrupt-parent = <&mpic>;
161 };
162
163 memory-controller@2000 {
164 compatible = "fsl,p1021-memory-controller";
165 reg = <0x2000 0x1000>;
166 interrupt-parent = <&mpic>;
167 interrupts = <16 2>;
168 };
169 113
170 i2c@3000 { 114 i2c@3000 {
171 #address-cells = <1>;
172 #size-cells = <0>;
173 cell-index = <0>;
174 compatible = "fsl-i2c";
175 reg = <0x3000 0x100>;
176 interrupts = <43 2>;
177 interrupt-parent = <&mpic>;
178 dfsrr;
179 rtc@68 { 115 rtc@68 {
180 compatible = "dallas,ds1374"; 116 compatible = "dallas,ds1374";
181 reg = <0x68>; 117 reg = <0x68>;
182 }; 118 };
183 }; 119 };
184 120
185 i2c@3100 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 cell-index = <1>;
189 compatible = "fsl-i2c";
190 reg = <0x3100 0x100>;
191 interrupts = <43 2>;
192 interrupt-parent = <&mpic>;
193 dfsrr;
194 };
195
196 serial0: serial@4500 {
197 cell-index = <0>;
198 device_type = "serial";
199 compatible = "ns16550";
200 reg = <0x4500 0x100>;
201 clock-frequency = <0>;
202 interrupts = <42 2>;
203 interrupt-parent = <&mpic>;
204 };
205
206 serial1: serial@4600 {
207 cell-index = <1>;
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0x4600 0x100>;
211 clock-frequency = <0>;
212 interrupts = <42 2>;
213 interrupt-parent = <&mpic>;
214 };
215
216 spi@7000 { 121 spi@7000 {
217 cell-index = <0>; 122
218 #address-cells = <1>; 123 flash@0 {
219 #size-cells = <0>;
220 compatible = "fsl,espi";
221 reg = <0x7000 0x1000>;
222 interrupts = <59 0x2>;
223 interrupt-parent = <&mpic>;
224 espi,num-ss-bits = <4>;
225 mode = "cpu";
226
227 fsl_m25p80@0 {
228 #address-cells = <1>; 124 #address-cells = <1>;
229 #size-cells = <1>; 125 #size-cells = <1>;
230 compatible = "fsl,espi-flash"; 126 compatible = "spansion,s25sl12801";
231 reg = <0>; 127 reg = <0>;
232 linux,modalias = "fsl_m25p80";
233 spi-max-frequency = <40000000>; /* input clock */ 128 spi-max-frequency = <40000000>; /* input clock */
129
234 partition@u-boot { 130 partition@u-boot {
235 label = "u-boot-spi"; 131 label = "u-boot-spi";
236 reg = <0x00000000 0x00100000>; 132 reg = <0x00000000 0x00100000>;
@@ -253,237 +149,49 @@
253 }; 149 };
254 }; 150 };
255 151
256 gpio: gpio-controller@f000 {
257 #gpio-cells = <2>;
258 compatible = "fsl,mpc8572-gpio";
259 reg = <0xf000 0x100>;
260 interrupts = <47 0x2>;
261 interrupt-parent = <&mpic>;
262 gpio-controller;
263 };
264
265 L2: l2-cache-controller@20000 {
266 compatible = "fsl,p1021-l2-cache-controller";
267 reg = <0x20000 0x1000>;
268 cache-line-size = <32>; // 32 bytes
269 cache-size = <0x40000>; // L2,256K
270 interrupt-parent = <&mpic>;
271 interrupts = <16 2>;
272 };
273
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,eloplus-dma-channel";
283 reg = <0x0 0x80>;
284 cell-index = <0>;
285 interrupt-parent = <&mpic>;
286 interrupts = <20 2>;
287 };
288 dma-channel@80 {
289 compatible = "fsl,eloplus-dma-channel";
290 reg = <0x80 0x80>;
291 cell-index = <1>;
292 interrupt-parent = <&mpic>;
293 interrupts = <21 2>;
294 };
295 dma-channel@100 {
296 compatible = "fsl,eloplus-dma-channel";
297 reg = <0x100 0x80>;
298 cell-index = <2>;
299 interrupt-parent = <&mpic>;
300 interrupts = <22 2>;
301 };
302 dma-channel@180 {
303 compatible = "fsl,eloplus-dma-channel";
304 reg = <0x180 0x80>;
305 cell-index = <3>;
306 interrupt-parent = <&mpic>;
307 interrupts = <23 2>;
308 };
309 };
310
311 usb@22000 { 152 usb@22000 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl-usb2-dr";
315 reg = <0x22000 0x1000>;
316 interrupt-parent = <&mpic>;
317 interrupts = <28 0x2>;
318 phy_type = "ulpi"; 153 phy_type = "ulpi";
319 }; 154 };
320 155
321 mdio@24000 { 156 mdio@24000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,etsec2-mdio";
325 reg = <0x24000 0x1000 0xb0030 0x4>;
326
327 phy0: ethernet-phy@0 { 157 phy0: ethernet-phy@0 {
328 interrupt-parent = <&mpic>; 158 interrupts = <1 1 0 0>;
329 interrupts = <1 1>;
330 reg = <0x0>; 159 reg = <0x0>;
331 }; 160 };
332 phy1: ethernet-phy@1 { 161 phy1: ethernet-phy@1 {
333 interrupt-parent = <&mpic>; 162 interrupts = <2 1 0 0>;
334 interrupts = <2 1>;
335 reg = <0x1>; 163 reg = <0x1>;
336 }; 164 };
337 phy4: ethernet-phy@4 { 165 phy4: ethernet-phy@4 {
338 interrupt-parent = <&mpic>;
339 reg = <0x4>; 166 reg = <0x4>;
340 }; 167 };
168 tbi-phy@5 {
169 device_type = "tbi-phy";
170 reg = <0x5>;
171 };
341 }; 172 };
342 173
343 mdio@25000 { 174 mdio@25000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "fsl,etsec2-tbi";
347 reg = <0x25000 0x1000 0xb1030 0x4>;
348 tbi0: tbi-phy@11 { 175 tbi0: tbi-phy@11 {
349 reg = <0x11>; 176 reg = <0x11>;
350 device_type = "tbi-phy"; 177 device_type = "tbi-phy";
351 }; 178 };
352 }; 179 };
353 180
354 enet0: ethernet@B0000 { 181 ethernet@b0000 {
355 #address-cells = <1>;
356 #size-cells = <1>;
357 cell-index = <0>;
358 device_type = "network";
359 model = "eTSEC";
360 compatible = "fsl,etsec2";
361 fsl,num_rx_queues = <0x8>;
362 fsl,num_tx_queues = <0x8>;
363 local-mac-address = [ 00 00 00 00 00 00 ];
364 interrupt-parent = <&mpic>;
365 phy-handle = <&phy0>; 182 phy-handle = <&phy0>;
366 phy-connection-type = "rgmii-id"; 183 phy-connection-type = "rgmii-id";
367 queue-group@0{
368 #address-cells = <1>;
369 #size-cells = <1>;
370 reg = <0xB0000 0x1000>;
371 interrupts = <29 2 30 2 34 2>;
372 };
373 queue-group@1{
374 #address-cells = <1>;
375 #size-cells = <1>;
376 reg = <0xB4000 0x1000>;
377 interrupts = <17 2 18 2 24 2>;
378 };
379 }; 184 };
380 185
381 enet1: ethernet@B1000 { 186 ethernet@b1000 {
382 #address-cells = <1>;
383 #size-cells = <1>;
384 cell-index = <0>;
385 device_type = "network";
386 model = "eTSEC";
387 compatible = "fsl,etsec2";
388 fsl,num_rx_queues = <0x8>;
389 fsl,num_tx_queues = <0x8>;
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 interrupt-parent = <&mpic>;
392 phy-handle = <&phy4>; 187 phy-handle = <&phy4>;
393 tbi-handle = <&tbi0>; 188 tbi-handle = <&tbi0>;
394 phy-connection-type = "sgmii"; 189 phy-connection-type = "sgmii";
395 queue-group@0{
396 #address-cells = <1>;
397 #size-cells = <1>;
398 reg = <0xB1000 0x1000>;
399 interrupts = <35 2 36 2 40 2>;
400 };
401 queue-group@1{
402 #address-cells = <1>;
403 #size-cells = <1>;
404 reg = <0xB5000 0x1000>;
405 interrupts = <51 2 52 2 67 2>;
406 };
407 }; 190 };
408 191
409 enet2: ethernet@B2000 { 192 ethernet@b2000 {
410 #address-cells = <1>;
411 #size-cells = <1>;
412 cell-index = <0>;
413 device_type = "network";
414 model = "eTSEC";
415 compatible = "fsl,etsec2";
416 fsl,num_rx_queues = <0x8>;
417 fsl,num_tx_queues = <0x8>;
418 local-mac-address = [ 00 00 00 00 00 00 ];
419 interrupt-parent = <&mpic>;
420 phy-handle = <&phy1>; 193 phy-handle = <&phy1>;
421 phy-connection-type = "rgmii-id"; 194 phy-connection-type = "rgmii-id";
422 queue-group@0{
423 #address-cells = <1>;
424 #size-cells = <1>;
425 reg = <0xB2000 0x1000>;
426 interrupts = <31 2 32 2 33 2>;
427 };
428 queue-group@1{
429 #address-cells = <1>;
430 #size-cells = <1>;
431 reg = <0xB6000 0x1000>;
432 interrupts = <25 2 26 2 27 2>;
433 };
434 };
435
436 sdhci@2e000 {
437 compatible = "fsl,p1021-esdhc", "fsl,esdhc";
438 reg = <0x2e000 0x1000>;
439 interrupts = <72 0x2>;
440 interrupt-parent = <&mpic>;
441 /* Filled in by U-Boot */
442 clock-frequency = <0>;
443 };
444
445 crypto@30000 {
446 compatible = "fsl,sec3.3", "fsl,sec3.1",
447 "fsl,sec3.0", "fsl,sec2.4",
448 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
449 reg = <0x30000 0x10000>;
450 interrupts = <45 2 58 2>;
451 interrupt-parent = <&mpic>;
452 fsl,num-channels = <4>;
453 fsl,channel-fifo-len = <24>;
454 fsl,exec-units-mask = <0x97c>;
455 fsl,descriptor-types-mask = <0x3a30abf>;
456 };
457
458 mpic: pic@40000 {
459 interrupt-controller;
460 #address-cells = <0>;
461 #interrupt-cells = <2>;
462 reg = <0x40000 0x40000>;
463 compatible = "chrp,open-pic";
464 device_type = "open-pic";
465 };
466
467 msi@41600 {
468 compatible = "fsl,p1021-msi", "fsl,mpic-msi";
469 reg = <0x41600 0x80>;
470 msi-available-ranges = <0 0x100>;
471 interrupts = <
472 0xe0 0
473 0xe1 0
474 0xe2 0
475 0xe3 0
476 0xe4 0
477 0xe5 0
478 0xe6 0
479 0xe7 0>;
480 interrupt-parent = <&mpic>;
481 };
482
483 global-utilities@e0000 { //global utilities block
484 compatible = "fsl,p1021-guts";
485 reg = <0xe0000 0x1000>;
486 fsl,has-rstcr;
487 }; 195 };
488 196
489 par_io@e0100 { 197 par_io@e0100 {
@@ -499,8 +207,7 @@
499 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */ 207 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
500 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */ 208 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
501 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */ 209 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
502 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 210 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
503*/
504 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */ 211 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
505 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */ 212 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
506 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */ 213 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
@@ -535,31 +242,10 @@
535 }; 242 };
536 243
537 pci0: pcie@ffe09000 { 244 pci0: pcie@ffe09000 {
538 compatible = "fsl,mpc8548-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0 0xffe09000 0 0x1000>; 245 reg = <0 0xffe09000 0 0x1000>;
544 bus-range = <0 255>;
545 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 246 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
546 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 247 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
547 clock-frequency = <33333333>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550 interrupt-map-mask = <0xf800 0 0 7>;
551 interrupt-map = <
552 /* IDSEL 0x0 */
553 0000 0 0 1 &mpic 4 1
554 0000 0 0 2 &mpic 5 1
555 0000 0 0 3 &mpic 6 1
556 0000 0 0 4 &mpic 7 1
557 >;
558 pcie@0 { 248 pcie@0 {
559 reg = <0x0 0x0 0x0 0x0 0x0>;
560 #size-cells = <2>;
561 #address-cells = <3>;
562 device_type = "pci";
563 ranges = <0x2000000 0x0 0xa0000000 249 ranges = <0x2000000 0x0 0xa0000000
564 0x2000000 0x0 0xa0000000 250 0x2000000 0x0 0xa0000000
565 0x0 0x20000000 251 0x0 0x20000000
@@ -571,31 +257,10 @@
571 }; 257 };
572 258
573 pci1: pcie@ffe0a000 { 259 pci1: pcie@ffe0a000 {
574 compatible = "fsl,mpc8548-pcie";
575 device_type = "pci";
576 #interrupt-cells = <1>;
577 #size-cells = <2>;
578 #address-cells = <3>;
579 reg = <0 0xffe0a000 0 0x1000>; 260 reg = <0 0xffe0a000 0 0x1000>;
580 bus-range = <0 255>;
581 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 261 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
582 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 262 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
583 clock-frequency = <33333333>;
584 interrupt-parent = <&mpic>;
585 interrupts = <16 2>;
586 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = <
588 /* IDSEL 0x0 */
589 0000 0 0 1 &mpic 0 1
590 0000 0 0 2 &mpic 1 1
591 0000 0 0 3 &mpic 2 1
592 0000 0 0 4 &mpic 3 1
593 >;
594 pcie@0 { 263 pcie@0 {
595 reg = <0x0 0x0 0x0 0x0 0x0>;
596 #size-cells = <2>;
597 #address-cells = <3>;
598 device_type = "pci";
599 ranges = <0x2000000 0x0 0xc0000000 264 ranges = <0x2000000 0x0 0xc0000000
600 0x2000000 0x0 0xc0000000 265 0x2000000 0x0 0xc0000000
601 0x0 0x20000000 266 0x0 0x20000000
@@ -606,36 +271,16 @@
606 }; 271 };
607 }; 272 };
608 273
609 qe@ffe80000 { 274 qe: qe@ffe80000 {
610 #address-cells = <1>;
611 #size-cells = <1>;
612 device_type = "qe";
613 compatible = "fsl,qe";
614 ranges = <0x0 0x0 0xffe80000 0x40000>; 275 ranges = <0x0 0x0 0xffe80000 0x40000>;
615 reg = <0 0xffe80000 0 0x480>; 276 reg = <0 0xffe80000 0 0x480>;
616 brg-frequency = <0>; 277 brg-frequency = <0>;
617 bus-frequency = <0>; 278 bus-frequency = <0>;
618 fsl,qe-num-riscs = <1>;
619 fsl,qe-num-snums = <28>;
620 status = "disabled"; /* no firmware loaded */ 279 status = "disabled"; /* no firmware loaded */
621 280
622 qeic: interrupt-controller@80 {
623 interrupt-controller;
624 compatible = "fsl,qe-ic";
625 #address-cells = <0>;
626 #interrupt-cells = <1>;
627 reg = <0x80 0x80>;
628 interrupts = <63 2 60 2>; //high:47 low:44
629 interrupt-parent = <&mpic>;
630 };
631
632 enet3: ucc@2000 { 281 enet3: ucc@2000 {
633 device_type = "network"; 282 device_type = "network";
634 compatible = "ucc_geth"; 283 compatible = "ucc_geth";
635 cell-index = <1>;
636 reg = <0x2000 0x200>;
637 interrupts = <32>;
638 interrupt-parent = <&qeic>;
639 local-mac-address = [ 00 00 00 00 00 00 ]; 284 local-mac-address = [ 00 00 00 00 00 00 ];
640 rx-clock-name = "clk12"; 285 rx-clock-name = "clk12";
641 tx-clock-name = "clk9"; 286 tx-clock-name = "clk9";
@@ -645,20 +290,15 @@
645 }; 290 };
646 291
647 mdio@2120 { 292 mdio@2120 {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 reg = <0x2120 0x18>;
651 compatible = "fsl,ucc-mdio";
652
653 qe_phy0: ethernet-phy@0 { 293 qe_phy0: ethernet-phy@0 {
654 interrupt-parent = <&mpic>; 294 interrupt-parent = <&mpic>;
655 interrupts = <4 1>; 295 interrupts = <4 1 0 0>;
656 reg = <0x0>; 296 reg = <0x0>;
657 device_type = "ethernet-phy"; 297 device_type = "ethernet-phy";
658 }; 298 };
659 qe_phy1: ethernet-phy@03 { 299 qe_phy1: ethernet-phy@03 {
660 interrupt-parent = <&mpic>; 300 interrupt-parent = <&mpic>;
661 interrupts = <5 1>; 301 interrupts = <5 1 0 0>;
662 reg = <0x3>; 302 reg = <0x3>;
663 device_type = "ethernet-phy"; 303 device_type = "ethernet-phy";
664 }; 304 };
@@ -671,10 +311,6 @@
671 enet4: ucc@2400 { 311 enet4: ucc@2400 {
672 device_type = "network"; 312 device_type = "network";
673 compatible = "ucc_geth"; 313 compatible = "ucc_geth";
674 cell-index = <5>;
675 reg = <0x2400 0x200>;
676 interrupts = <40>;
677 interrupt-parent = <&qeic>;
678 local-mac-address = [ 00 00 00 00 00 00 ]; 314 local-mac-address = [ 00 00 00 00 00 00 ];
679 rx-clock-name = "none"; 315 rx-clock-name = "none";
680 tx-clock-name = "clk13"; 316 tx-clock-name = "clk13";
@@ -682,18 +318,7 @@
682 phy-handle = <&qe_phy1>; 318 phy-handle = <&qe_phy1>;
683 phy-connection-type = "rmii"; 319 phy-connection-type = "rmii";
684 }; 320 };
685
686 muram@10000 {
687 #address-cells = <1>;
688 #size-cells = <1>;
689 compatible = "fsl,qe-muram", "fsl,cpm-muram";
690 ranges = <0x0 0x10000 0x6000>;
691
692 data-only@0 {
693 compatible = "fsl,qe-muram-data",
694 "fsl,cpm-muram-data";
695 reg = <0x0 0x6000>;
696 };
697 };
698 }; 321 };
699}; 322};
323
324/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index b9b8719a6204..ef95717db4bc 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -8,57 +8,36 @@
8 * kind, whether express or implied. 8 * kind, whether express or implied.
9 */ 9 */
10 10
11/dts-v1/; 11/include/ "fsl/p1022si-pre.dtsi"
12/ { 12/ {
13 model = "fsl,P1022"; 13 model = "fsl,P1022DS";
14 compatible = "fsl,P1022DS"; 14 compatible = "fsl,P1022DS";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&mpic>;
18
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1022@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1022@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45 15
46 memory { 16 memory {
47 device_type = "memory"; 17 device_type = "memory";
48 }; 18 };
49 19
50 localbus@fffe05000 { 20 lbc: localbus@fffe05000 {
51 #address-cells = <2>; 21 reg = <0xf 0xffe05000 0 0x1000>;
52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2 0 0>;
56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 22 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 23 0x1 0x0 0xf 0xe0000000 0x08000000
59 0x2 0x0 0x0 0xffa00000 0x00040000 24 0x2 0x0 0xf 0xff800000 0x00040000
60 0x3 0x0 0xf 0xffdf0000 0x00008000>; 25 0x3 0x0 0xf 0xffdf0000 0x00008000>;
61 26
27 /*
28 * This node is used to access the pixis via "indirect" mode,
29 * which is done by writing the pixis register index to chip
30 * select 0 and the value to/from chip select 1. Indirect
31 * mode is the only way to access the pixis when DIU video
32 * is enabled. Note that this assumes that the first column
33 * of the 'ranges' property above is the chip select number.
34 */
35 board-control@0,0 {
36 compatible = "fsl,p1022ds-indirect-pixis";
37 reg = <0x0 0x0 1 /* CS0 */
38 0x1 0x0 1>; /* CS1 */
39 };
40
62 nor@0,0 { 41 nor@0,0 {
63 #address-cells = <1>; 42 #address-cells = <1>;
64 #size-cells = <1>; 43 #size-cells = <1>;
@@ -161,51 +140,10 @@
161 }; 140 };
162 }; 141 };
163 142
164 soc@fffe00000 { 143 soc: soc@fffe00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 device_type = "soc";
168 compatible = "fsl,p1022-immr", "simple-bus";
169 ranges = <0x0 0xf 0xffe00000 0x100000>; 144 ranges = <0x0 0xf 0xffe00000 0x100000>;
170 bus-frequency = <0>; // Filled out by uboot.
171
172 ecm-law@0 {
173 compatible = "fsl,ecm-law";
174 reg = <0x0 0x1000>;
175 fsl,num-laws = <12>;
176 };
177
178 ecm@1000 {
179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>;
181 interrupts = <16 2 0 0>;
182 };
183
184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>;
187 interrupts = <16 2 0 0>;
188 };
189
190 i2c@3000 {
191 #address-cells = <1>;
192 #size-cells = <0>;
193 cell-index = <0>;
194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>;
196 interrupts = <43 2 0 0>;
197 dfsrr;
198 };
199 145
200 i2c@3100 { 146 i2c@3100 {
201 #address-cells = <1>;
202 #size-cells = <0>;
203 cell-index = <1>;
204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>;
206 interrupts = <43 2 0 0>;
207 dfsrr;
208
209 wm8776:codec@1a { 147 wm8776:codec@1a {
210 compatible = "wlf,wm8776"; 148 compatible = "wlf,wm8776";
211 reg = <0x1a>; 149 reg = <0x1a>;
@@ -216,41 +154,14 @@
216 }; 154 };
217 }; 155 };
218 156
219 serial0: serial@4500 {
220 cell-index = <0>;
221 device_type = "serial";
222 compatible = "ns16550";
223 reg = <0x4500 0x100>;
224 clock-frequency = <0>;
225 interrupts = <42 2 0 0>;
226 };
227
228 serial1: serial@4600 {
229 cell-index = <1>;
230 device_type = "serial";
231 compatible = "ns16550";
232 reg = <0x4600 0x100>;
233 clock-frequency = <0>;
234 interrupts = <42 2 0 0>;
235 };
236
237 spi@7000 { 157 spi@7000 {
238 cell-index = <0>; 158 flash@0 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "fsl,espi";
242 reg = <0x7000 0x1000>;
243 interrupts = <59 0x2 0 0>;
244 espi,num-ss-bits = <4>;
245 mode = "cpu";
246
247 fsl_m25p80@0 {
248 #address-cells = <1>; 159 #address-cells = <1>;
249 #size-cells = <1>; 160 #size-cells = <1>;
250 compatible = "fsl,espi-flash"; 161 compatible = "spansion,s25sl12801";
251 reg = <0>; 162 reg = <0>;
252 linux,modalias = "fsl_m25p80";
253 spi-max-frequency = <40000000>; /* input clock */ 163 spi-max-frequency = <40000000>; /* input clock */
164
254 partition@0 { 165 partition@0 {
255 label = "u-boot-spi"; 166 label = "u-boot-spi";
256 reg = <0x00000000 0x00100000>; 167 reg = <0x00000000 0x00100000>;
@@ -274,115 +185,20 @@
274 }; 185 };
275 186
276 ssi@15000 { 187 ssi@15000 {
277 compatible = "fsl,mpc8610-ssi";
278 cell-index = <0>;
279 reg = <0x15000 0x100>;
280 interrupts = <75 2 0 0>;
281 fsl,mode = "i2s-slave"; 188 fsl,mode = "i2s-slave";
282 codec-handle = <&wm8776>; 189 codec-handle = <&wm8776>;
283 fsl,playback-dma = <&dma00>;
284 fsl,capture-dma = <&dma01>;
285 fsl,fifo-depth = <15>;
286 fsl,ssi-asynchronous; 190 fsl,ssi-asynchronous;
287 }; 191 };
288 192
289 dma@c300 {
290 #address-cells = <1>;
291 #size-cells = <1>;
292 compatible = "fsl,eloplus-dma";
293 reg = <0xc300 0x4>;
294 ranges = <0x0 0xc100 0x200>;
295 cell-index = <1>;
296 dma00: dma-channel@0 {
297 compatible = "fsl,ssi-dma-channel";
298 reg = <0x0 0x80>;
299 cell-index = <0>;
300 interrupts = <76 2 0 0>;
301 };
302 dma01: dma-channel@80 {
303 compatible = "fsl,ssi-dma-channel";
304 reg = <0x80 0x80>;
305 cell-index = <1>;
306 interrupts = <77 2 0 0>;
307 };
308 dma-channel@100 {
309 compatible = "fsl,eloplus-dma-channel";
310 reg = <0x100 0x80>;
311 cell-index = <2>;
312 interrupts = <78 2 0 0>;
313 };
314 dma-channel@180 {
315 compatible = "fsl,eloplus-dma-channel";
316 reg = <0x180 0x80>;
317 cell-index = <3>;
318 interrupts = <79 2 0 0>;
319 };
320 };
321
322 gpio: gpio-controller@f000 {
323 #gpio-cells = <2>;
324 compatible = "fsl,mpc8572-gpio";
325 reg = <0xf000 0x100>;
326 interrupts = <47 0x2 0 0>;
327 gpio-controller;
328 };
329
330 L2: l2-cache-controller@20000 {
331 compatible = "fsl,p1022-l2-cache-controller";
332 reg = <0x20000 0x1000>;
333 cache-line-size = <32>; // 32 bytes
334 cache-size = <0x40000>; // L2, 256K
335 interrupts = <16 2 0 0>;
336 };
337
338 dma@21300 {
339 #address-cells = <1>;
340 #size-cells = <1>;
341 compatible = "fsl,eloplus-dma";
342 reg = <0x21300 0x4>;
343 ranges = <0x0 0x21100 0x200>;
344 cell-index = <0>;
345 dma-channel@0 {
346 compatible = "fsl,eloplus-dma-channel";
347 reg = <0x0 0x80>;
348 cell-index = <0>;
349 interrupts = <20 2 0 0>;
350 };
351 dma-channel@80 {
352 compatible = "fsl,eloplus-dma-channel";
353 reg = <0x80 0x80>;
354 cell-index = <1>;
355 interrupts = <21 2 0 0>;
356 };
357 dma-channel@100 {
358 compatible = "fsl,eloplus-dma-channel";
359 reg = <0x100 0x80>;
360 cell-index = <2>;
361 interrupts = <22 2 0 0>;
362 };
363 dma-channel@180 {
364 compatible = "fsl,eloplus-dma-channel";
365 reg = <0x180 0x80>;
366 cell-index = <3>;
367 interrupts = <23 2 0 0>;
368 };
369 };
370
371 usb@22000 { 193 usb@22000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl-usb2-dr";
375 reg = <0x22000 0x1000>;
376 interrupts = <28 0x2 0 0>;
377 phy_type = "ulpi"; 194 phy_type = "ulpi";
378 }; 195 };
379 196
380 mdio@24000 { 197 usb@23000 {
381 #address-cells = <1>; 198 status = "disabled";
382 #size-cells = <0>; 199 };
383 compatible = "fsl,etsec2-mdio";
384 reg = <0x24000 0x1000 0xb0030 0x4>;
385 200
201 mdio@24000 {
386 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
387 interrupts = <3 1 0 0>; 203 interrupts = <3 1 0 0>;
388 reg = <0x1>; 204 reg = <0x1>;
@@ -391,189 +207,28 @@
391 interrupts = <9 1 0 0>; 207 interrupts = <9 1 0 0>;
392 reg = <0x2>; 208 reg = <0x2>;
393 }; 209 };
210 tbi-phy@2 {
211 device_type = "tbi-phy";
212 reg = <0x2>;
213 };
394 }; 214 };
395 215
396 mdio@25000 { 216 ethernet@b0000 {
397 #address-cells = <1>;
398 #size-cells = <0>;
399 compatible = "fsl,etsec2-mdio";
400 reg = <0x25000 0x1000 0xb1030 0x4>;
401 };
402
403 enet0: ethernet@B0000 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 cell-index = <0>;
407 device_type = "network";
408 model = "eTSEC";
409 compatible = "fsl,etsec2";
410 fsl,num_rx_queues = <0x8>;
411 fsl,num_tx_queues = <0x8>;
412 fsl,magic-packet;
413 fsl,wake-on-filer;
414 local-mac-address = [ 00 00 00 00 00 00 ];
415 phy-handle = <&phy0>; 217 phy-handle = <&phy0>;
416 phy-connection-type = "rgmii-id"; 218 phy-connection-type = "rgmii-id";
417 queue-group@0{
418 #address-cells = <1>;
419 #size-cells = <1>;
420 reg = <0xB0000 0x1000>;
421 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
422 };
423 queue-group@1{
424 #address-cells = <1>;
425 #size-cells = <1>;
426 reg = <0xB4000 0x1000>;
427 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
428 };
429 }; 219 };
430 220
431 enet1: ethernet@B1000 { 221 ethernet@b1000 {
432 #address-cells = <1>;
433 #size-cells = <1>;
434 cell-index = <0>;
435 device_type = "network";
436 model = "eTSEC";
437 compatible = "fsl,etsec2";
438 fsl,num_rx_queues = <0x8>;
439 fsl,num_tx_queues = <0x8>;
440 local-mac-address = [ 00 00 00 00 00 00 ];
441 phy-handle = <&phy1>; 222 phy-handle = <&phy1>;
442 phy-connection-type = "rgmii-id"; 223 phy-connection-type = "rgmii-id";
443 queue-group@0{
444 #address-cells = <1>;
445 #size-cells = <1>;
446 reg = <0xB1000 0x1000>;
447 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
448 };
449 queue-group@1{
450 #address-cells = <1>;
451 #size-cells = <1>;
452 reg = <0xB5000 0x1000>;
453 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
454 };
455 };
456
457 sdhci@2e000 {
458 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
459 reg = <0x2e000 0x1000>;
460 interrupts = <72 0x2 0 0>;
461 fsl,sdhci-auto-cmd12;
462 /* Filled in by U-Boot */
463 clock-frequency = <0>;
464 };
465
466 crypto@30000 {
467 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
468 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
469 "fsl,sec2.0";
470 reg = <0x30000 0x10000>;
471 interrupts = <45 2 0 0 58 2 0 0>;
472 fsl,num-channels = <4>;
473 fsl,channel-fifo-len = <24>;
474 fsl,exec-units-mask = <0x97c>;
475 fsl,descriptor-types-mask = <0x3a30abf>;
476 };
477
478 sata@18000 {
479 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
480 reg = <0x18000 0x1000>;
481 cell-index = <1>;
482 interrupts = <74 0x2 0 0>;
483 };
484
485 sata@19000 {
486 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
487 reg = <0x19000 0x1000>;
488 cell-index = <2>;
489 interrupts = <41 0x2 0 0>;
490 };
491
492 power@e0070{
493 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
494 reg = <0xe0070 0x20>;
495 };
496
497 display@10000 {
498 compatible = "fsl,diu", "fsl,p1022-diu";
499 reg = <0x10000 1000>;
500 interrupts = <64 2 0 0>;
501 };
502
503 timer@41100 {
504 compatible = "fsl,mpic-global-timer";
505 reg = <0x41100 0x100 0x41300 4>;
506 interrupts = <0 0 3 0
507 1 0 3 0
508 2 0 3 0
509 3 0 3 0>;
510 };
511
512 timer@42100 {
513 compatible = "fsl,mpic-global-timer";
514 reg = <0x42100 0x100 0x42300 4>;
515 interrupts = <4 0 3 0
516 5 0 3 0
517 6 0 3 0
518 7 0 3 0>;
519 };
520
521 mpic: pic@40000 {
522 interrupt-controller;
523 #address-cells = <0>;
524 #interrupt-cells = <4>;
525 reg = <0x40000 0x40000>;
526 compatible = "fsl,mpic";
527 device_type = "open-pic";
528 };
529
530 msi@41600 {
531 compatible = "fsl,p1022-msi", "fsl,mpic-msi";
532 reg = <0x41600 0x80>;
533 msi-available-ranges = <0 0x100>;
534 interrupts = <
535 0xe0 0 0 0
536 0xe1 0 0 0
537 0xe2 0 0 0
538 0xe3 0 0 0
539 0xe4 0 0 0
540 0xe5 0 0 0
541 0xe6 0 0 0
542 0xe7 0 0 0>;
543 };
544
545 global-utilities@e0000 { //global utilities block
546 compatible = "fsl,p1022-guts";
547 reg = <0xe0000 0x1000>;
548 fsl,has-rstcr;
549 }; 224 };
550 }; 225 };
551 226
552 pci0: pcie@fffe09000 { 227 pci0: pcie@fffe09000 {
553 compatible = "fsl,p1022-pcie";
554 device_type = "pci";
555 #interrupt-cells = <1>;
556 #size-cells = <2>;
557 #address-cells = <3>;
558 reg = <0xf 0xffe09000 0 0x1000>; 228 reg = <0xf 0xffe09000 0 0x1000>;
559 bus-range = <0 255>; 229 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
560 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
561 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 230 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
562 clock-frequency = <33333333>;
563 interrupts = <16 2 0 0>;
564 interrupt-map-mask = <0xf800 0 0 7>;
565 interrupt-map = <
566 /* IDSEL 0x0 */
567 0000 0 0 1 &mpic 4 1
568 0000 0 0 2 &mpic 5 1
569 0000 0 0 3 &mpic 6 1
570 0000 0 0 4 &mpic 7 1
571 >;
572 pcie@0 { 231 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>;
575 #address-cells = <3>;
576 device_type = "pci";
577 ranges = <0x2000000 0x0 0xe0000000 232 ranges = <0x2000000 0x0 0xe0000000
578 0x2000000 0x0 0xe0000000 233 0x2000000 0x0 0xe0000000
579 0x0 0x20000000 234 0x0 0x20000000
@@ -585,30 +240,11 @@
585 }; 240 };
586 241
587 pci1: pcie@fffe0a000 { 242 pci1: pcie@fffe0a000 {
588 compatible = "fsl,p1022-pcie";
589 device_type = "pci";
590 #interrupt-cells = <1>;
591 #size-cells = <2>;
592 #address-cells = <3>;
593 reg = <0xf 0xffe0a000 0 0x1000>; 243 reg = <0xf 0xffe0a000 0 0x1000>;
594 bus-range = <0 255>; 244 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
595 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
596 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 245 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
597 clock-frequency = <33333333>;
598 interrupts = <16 2 0 0>;
599 interrupt-map-mask = <0xf800 0 0 7>;
600 interrupt-map = <
601 /* IDSEL 0x0 */
602 0000 0 0 1 &mpic 0 1
603 0000 0 0 2 &mpic 1 1
604 0000 0 0 3 &mpic 2 1
605 0000 0 0 4 &mpic 3 1
606 >;
607 pcie@0 { 246 pcie@0 {
608 reg = <0x0 0x0 0x0 0x0 0x0>; 247 reg = <0x0 0x0 0x0 0x0 0x0>;
609 #size-cells = <2>;
610 #address-cells = <3>;
611 device_type = "pci";
612 ranges = <0x2000000 0x0 0xe0000000 248 ranges = <0x2000000 0x0 0xe0000000
613 0x2000000 0x0 0xe0000000 249 0x2000000 0x0 0xe0000000
614 0x0 0x20000000 250 0x0 0x20000000
@@ -619,32 +255,11 @@
619 }; 255 };
620 }; 256 };
621 257
622
623 pci2: pcie@fffe0b000 { 258 pci2: pcie@fffe0b000 {
624 compatible = "fsl,p1022-pcie";
625 device_type = "pci";
626 #interrupt-cells = <1>;
627 #size-cells = <2>;
628 #address-cells = <3>;
629 reg = <0xf 0xffe0b000 0 0x1000>; 259 reg = <0xf 0xffe0b000 0 0x1000>;
630 bus-range = <0 255>; 260 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
631 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
632 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 261 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
633 clock-frequency = <33333333>;
634 interrupts = <16 2 0 0>;
635 interrupt-map-mask = <0xf800 0 0 7>;
636 interrupt-map = <
637 /* IDSEL 0x0 */
638 0000 0 0 1 &mpic 8 1
639 0000 0 0 2 &mpic 9 1
640 0000 0 0 3 &mpic 10 1
641 0000 0 0 4 &mpic 11 1
642 >;
643 pcie@0 { 262 pcie@0 {
644 reg = <0x0 0x0 0x0 0x0 0x0>;
645 #size-cells = <2>;
646 #address-cells = <3>;
647 device_type = "pci";
648 ranges = <0x2000000 0x0 0xe0000000 263 ranges = <0x2000000 0x0 0xe0000000
649 0x2000000 0x0 0xe0000000 264 0x2000000 0x0 0xe0000000
650 0x0 0x20000000 265 0x0 0x20000000
@@ -655,3 +270,5 @@
655 }; 270 };
656 }; 271 };
657}; 272};
273
274/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
index d9b776740a67..beb6cb12e59d 100644
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ b/arch/powerpc/boot/dts/p1023rds.dts
@@ -34,137 +34,30 @@
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */ 35 */
36 36
37/dts-v1/; 37/include/ "fsl/p1023si-pre.dtsi"
38 38
39/ { 39/ {
40 model = "fsl,P1023"; 40 model = "fsl,P1023";
41 compatible = "fsl,P1023RDS"; 41 compatible = "fsl,P1023RDS";
42 #address-cells = <2>; 42 #address-cells = <2>;
43 #size-cells = <2>; 43 #size-cells = <2>;
44 44 interrupt-parent = <&mpic>;
45 aliases {
46 serial0 = &serial0;
47 serial1 = &serial1;
48 pci0 = &pci0;
49 pci1 = &pci1;
50 pci2 = &pci2;
51
52 crypto = &crypto;
53 sec_jr0 = &sec_jr0;
54 sec_jr1 = &sec_jr1;
55 sec_jr2 = &sec_jr2;
56 sec_jr3 = &sec_jr3;
57 rtic_a = &rtic_a;
58 rtic_b = &rtic_b;
59 rtic_c = &rtic_c;
60 rtic_d = &rtic_d;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,P1023@0 {
68 device_type = "cpu";
69 reg = <0x0>;
70 next-level-cache = <&L2>;
71 };
72
73 cpu1: PowerPC,P1023@1 {
74 device_type = "cpu";
75 reg = <0x1>;
76 next-level-cache = <&L2>;
77 };
78 };
79 45
80 memory { 46 memory {
81 device_type = "memory"; 47 device_type = "memory";
82 }; 48 };
83 49
84 soc@ff600000 { 50 soc: soc@ff600000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 device_type = "soc";
88 compatible = "fsl,p1023-immr", "simple-bus";
89 ranges = <0x0 0x0 0xff600000 0x200000>; 51 ranges = <0x0 0x0 0xff600000 0x200000>;
90 bus-frequency = <0>; // Filled out by uboot.
91
92 ecm-law@0 {
93 compatible = "fsl,ecm-law";
94 reg = <0x0 0x1000>;
95 fsl,num-laws = <12>;
96 };
97
98 ecm@1000 {
99 compatible = "fsl,p1023-ecm", "fsl,ecm";
100 reg = <0x1000 0x1000>;
101 interrupts = <16 2>;
102 interrupt-parent = <&mpic>;
103 };
104
105 memory-controller@2000 {
106 compatible = "fsl,p1023-memory-controller";
107 reg = <0x2000 0x1000>;
108 interrupt-parent = <&mpic>;
109 interrupts = <16 2>;
110 };
111 52
112 i2c@3000 { 53 i2c@3000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 cell-index = <0>;
116 compatible = "fsl-i2c";
117 reg = <0x3000 0x100>;
118 interrupts = <43 2>;
119 interrupt-parent = <&mpic>;
120 dfsrr;
121 rtc@68 { 54 rtc@68 {
122 compatible = "dallas,ds1374"; 55 compatible = "dallas,ds1374";
123 reg = <0x68>; 56 reg = <0x68>;
124 }; 57 };
125 }; 58 };
126 59
127 i2c@3100 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 cell-index = <1>;
131 compatible = "fsl-i2c";
132 reg = <0x3100 0x100>;
133 interrupts = <43 2>;
134 interrupt-parent = <&mpic>;
135 dfsrr;
136 };
137
138 serial0: serial@4500 {
139 cell-index = <0>;
140 device_type = "serial";
141 compatible = "ns16550";
142 reg = <0x4500 0x100>;
143 clock-frequency = <0>;
144 interrupts = <42 2>;
145 interrupt-parent = <&mpic>;
146 };
147
148 serial1: serial@4600 {
149 cell-index = <1>;
150 device_type = "serial";
151 compatible = "ns16550";
152 reg = <0x4600 0x100>;
153 clock-frequency = <0>;
154 interrupts = <42 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 spi@7000 { 60 spi@7000 {
159 cell-index = <0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,p1023-espi", "fsl,mpc8536-espi";
163 reg = <0x7000 0x1000>;
164 interrupts = <59 0x2>;
165 interrupt-parent = <&mpic>;
166 fsl,espi-num-chipselects = <4>;
167
168 fsl_dataflash@0 { 61 fsl_dataflash@0 {
169 #address-cells = <1>; 62 #address-cells = <1>;
170 #size-cells = <1>; 63 #size-cells = <1>;
@@ -186,197 +79,14 @@
186 }; 79 };
187 }; 80 };
188 81
189 gpio: gpio-controller@f000 {
190 #gpio-cells = <2>;
191 compatible = "fsl,qoriq-gpio";
192 reg = <0xf000 0x100>;
193 interrupts = <47 0x2>;
194 interrupt-parent = <&mpic>;
195 gpio-controller;
196 };
197
198 L2: l2-cache-controller@20000 {
199 compatible = "fsl,p1023-l2-cache-controller";
200 reg = <0x20000 0x1000>;
201 cache-line-size = <32>; // 32 bytes
202 cache-size = <0x40000>; // L2,256K
203 interrupt-parent = <&mpic>;
204 interrupts = <16 2>;
205 };
206
207 dma@21300 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "fsl,eloplus-dma";
211 reg = <0x21300 0x4>;
212 ranges = <0x0 0x21100 0x200>;
213 cell-index = <0>;
214 dma-channel@0 {
215 compatible = "fsl,eloplus-dma-channel";
216 reg = <0x0 0x80>;
217 cell-index = <0>;
218 interrupt-parent = <&mpic>;
219 interrupts = <20 2>;
220 };
221 dma-channel@80 {
222 compatible = "fsl,eloplus-dma-channel";
223 reg = <0x80 0x80>;
224 cell-index = <1>;
225 interrupt-parent = <&mpic>;
226 interrupts = <21 2>;
227 };
228 dma-channel@100 {
229 compatible = "fsl,eloplus-dma-channel";
230 reg = <0x100 0x80>;
231 cell-index = <2>;
232 interrupt-parent = <&mpic>;
233 interrupts = <22 2>;
234 };
235 dma-channel@180 {
236 compatible = "fsl,eloplus-dma-channel";
237 reg = <0x180 0x80>;
238 cell-index = <3>;
239 interrupt-parent = <&mpic>;
240 interrupts = <23 2>;
241 };
242 };
243
244 usb@22000 { 82 usb@22000 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "fsl-usb2-dr";
248 reg = <0x22000 0x1000>;
249 interrupt-parent = <&mpic>;
250 interrupts = <28 0x2>;
251 dr_mode = "host"; 83 dr_mode = "host";
252 phy_type = "ulpi"; 84 phy_type = "ulpi";
253 }; 85 };
254
255 crypto: crypto@300000 {
256 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 reg = <0x30000 0x10000>;
260 ranges = <0 0x30000 0x10000>;
261 interrupt-parent = <&mpic>;
262 interrupts = <58 2>;
263
264 sec_jr0: jr@1000 {
265 compatible = "fsl,sec-v4.2-job-ring",
266 "fsl,sec-v4.0-job-ring";
267 reg = <0x1000 0x1000>;
268 interrupts = <45 2>;
269 };
270
271 sec_jr1: jr@2000 {
272 compatible = "fsl,sec-v4.2-job-ring",
273 "fsl,sec-v4.0-job-ring";
274 reg = <0x2000 0x1000>;
275 interrupts = <45 2>;
276 };
277
278 sec_jr2: jr@3000 {
279 compatible = "fsl,sec-v4.2-job-ring",
280 "fsl,sec-v4.0-job-ring";
281 reg = <0x3000 0x1000>;
282 interrupts = <57 2>;
283 };
284
285 sec_jr3: jr@4000 {
286 compatible = "fsl,sec-v4.2-job-ring",
287 "fsl,sec-v4.0-job-ring";
288 reg = <0x4000 0x1000>;
289 interrupts = <57 2>;
290 };
291
292 rtic@6000 {
293 compatible = "fsl,sec-v4.2-rtic",
294 "fsl,sec-v4.0-rtic";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 reg = <0x6000 0x100>;
298 ranges = <0x0 0x6100 0xe00>;
299
300 rtic_a: rtic-a@0 {
301 compatible = "fsl,sec-v4.2-rtic-memory",
302 "fsl,sec-v4.0-rtic-memory";
303 reg = <0x00 0x20 0x100 0x80>;
304 };
305
306 rtic_b: rtic-b@20 {
307 compatible = "fsl,sec-v4.2-rtic-memory",
308 "fsl,sec-v4.0-rtic-memory";
309 reg = <0x20 0x20 0x200 0x80>;
310 };
311
312 rtic_c: rtic-c@40 {
313 compatible = "fsl,sec-v4.2-rtic-memory",
314 "fsl,sec-v4.0-rtic-memory";
315 reg = <0x40 0x20 0x300 0x80>;
316 };
317
318 rtic_d: rtic-d@60 {
319 compatible = "fsl,sec-v4.2-rtic-memory",
320 "fsl,sec-v4.0-rtic-memory";
321 reg = <0x60 0x20 0x500 0x80>;
322 };
323 };
324 };
325
326 power@e0070{
327 compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc",
328 "fsl,p1022-pmc";
329 reg = <0xe0070 0x20>;
330 etsec1_clk: soc-clk@B0{
331 fsl,pmcdr-mask = <0x00000080>;
332 };
333 etsec2_clk: soc-clk@B1{
334 fsl,pmcdr-mask = <0x00000040>;
335 };
336 etsec3_clk: soc-clk@B2{
337 fsl,pmcdr-mask = <0x00000020>;
338 };
339 };
340
341 mpic: pic@40000 {
342 interrupt-controller;
343 #address-cells = <0>;
344 #interrupt-cells = <2>;
345 reg = <0x40000 0x40000>;
346 compatible = "chrp,open-pic";
347 device_type = "open-pic";
348 };
349
350 msi@41600 {
351 compatible = "fsl,p1023-msi", "fsl,mpic-msi";
352 reg = <0x41600 0x80>;
353 msi-available-ranges = <0 0x100>;
354 interrupts = <
355 0xe0 0
356 0xe1 0
357 0xe2 0
358 0xe3 0
359 0xe4 0
360 0xe5 0
361 0xe6 0
362 0xe7 0>;
363 interrupt-parent = <&mpic>;
364 };
365
366 global-utilities@e0000 { //global utilities block
367 compatible = "fsl,p1023-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 }; 86 };
372 87
373 localbus@ff605000 { 88 lbc: localbus@ff605000 {
374 #address-cells = <2>;
375 #size-cells = <1>;
376 compatible = "fsl,p1023-elbc", "fsl,elbc", "simple-bus";
377 reg = <0 0xff605000 0 0x1000>; 89 reg = <0 0xff605000 0 0x1000>;
378 interrupts = <19 2>;
379 interrupt-parent = <&mpic>;
380 90
381 /* NOR Flash, BCSR */ 91 /* NOR Flash, BCSR */
382 ranges = <0x0 0x0 0x0 0xee000000 0x02000000 92 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
@@ -428,33 +138,18 @@
428 }; 138 };
429 139
430 pci0: pcie@ff60a000 { 140 pci0: pcie@ff60a000 {
431 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
432 cell-index = <1>;
433 device_type = "pci";
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0 0xff60a000 0 0x1000>; 141 reg = <0 0xff60a000 0 0x1000>;
437 bus-range = <0 255>;
438 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 142 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
439 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 143 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
440 clock-frequency = <33333333>;
441 interrupt-parent = <&mpic>;
442 interrupts = <16 2>;
443 pcie@0 { 144 pcie@0 {
444 reg = <0x0 0x0 0x0 0x0 0x0>; 145 /* IRQ[0:3] are pulled up on board, set to active-low */
445 #interrupt-cells = <1>;
446 #size-cells = <2>;
447 #address-cells = <3>;
448 device_type = "pci";
449 interrupt-parent = <&mpic>;
450 interrupts = <16 2>;
451 interrupt-map-mask = <0xf800 0 0 7>; 146 interrupt-map-mask = <0xf800 0 0 7>;
452 interrupt-map = < 147 interrupt-map = <
453 /* IDSEL 0x0 */ 148 /* IDSEL 0x0 */
454 0000 0 0 1 &mpic 0 1 149 0000 0 0 1 &mpic 0 1 0 0
455 0000 0 0 2 &mpic 1 1 150 0000 0 0 2 &mpic 1 1 0 0
456 0000 0 0 3 &mpic 2 1 151 0000 0 0 3 &mpic 2 1 0 0
457 0000 0 0 4 &mpic 3 1 152 0000 0 0 4 &mpic 3 1 0 0
458 >; 153 >;
459 ranges = <0x2000000 0x0 0xc0000000 154 ranges = <0x2000000 0x0 0xc0000000
460 0x2000000 0x0 0xc0000000 155 0x2000000 0x0 0xc0000000
@@ -466,34 +161,22 @@
466 }; 161 };
467 }; 162 };
468 163
469 pci1: pcie@ff609000 { 164 board_pci1: pci1: pcie@ff609000 {
470 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
471 cell-index = <2>;
472 device_type = "pci";
473 #size-cells = <2>;
474 #address-cells = <3>;
475 reg = <0 0xff609000 0 0x1000>; 165 reg = <0 0xff609000 0 0x1000>;
476 bus-range = <0 255>;
477 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 166 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
478 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 167 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
479 clock-frequency = <33333333>;
480 interrupt-parent = <&mpic>;
481 interrupts = <16 2>;
482 pcie@0 { 168 pcie@0 {
483 reg = <0x0 0x0 0x0 0x0 0x0>; 169 /*
484 #interrupt-cells = <1>; 170 * IRQ[4:6] only for PCIe, set to active-high,
485 #size-cells = <2>; 171 * IRQ[7] is pulled up on board, set to active-low
486 #address-cells = <3>; 172 */
487 device_type = "pci";
488 interrupt-parent = <&mpic>;
489 interrupts = <16 2>;
490 interrupt-map-mask = <0xf800 0 0 7>; 173 interrupt-map-mask = <0xf800 0 0 7>;
491 interrupt-map = < 174 interrupt-map = <
492 /* IDSEL 0x0 */ 175 /* IDSEL 0x0 */
493 0000 0 0 1 &mpic 4 1 176 0000 0 0 1 &mpic 4 2 0 0
494 0000 0 0 2 &mpic 5 1 177 0000 0 0 2 &mpic 5 2 0 0
495 0000 0 0 3 &mpic 6 1 178 0000 0 0 3 &mpic 6 2 0 0
496 0000 0 0 4 &mpic 7 1 179 0000 0 0 4 &mpic 7 1 0 0
497 >; 180 >;
498 ranges = <0x2000000 0x0 0xa0000000 181 ranges = <0x2000000 0x0 0xa0000000
499 0x2000000 0x0 0xa0000000 182 0x2000000 0x0 0xa0000000
@@ -506,33 +189,21 @@
506 }; 189 };
507 190
508 pci2: pcie@ff60b000 { 191 pci2: pcie@ff60b000 {
509 cell-index = <3>;
510 compatible = "fsl,p1023-pcie", "fsl,qoriq-pcie-v2.2";
511 device_type = "pci";
512 #size-cells = <2>;
513 #address-cells = <3>;
514 reg = <0 0xff60b000 0 0x1000>; 192 reg = <0 0xff60b000 0 0x1000>;
515 bus-range = <0 255>;
516 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 193 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
517 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 194 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
518 clock-frequency = <33333333>;
519 interrupt-parent = <&mpic>;
520 interrupts = <16 2>;
521 pcie@0 { 195 pcie@0 {
522 reg = <0x0 0x0 0x0 0x0 0x0>; 196 /*
523 #interrupt-cells = <1>; 197 * IRQ[8:10] are pulled up on board, set to active-low
524 #size-cells = <2>; 198 * IRQ[11] only for PCIe, set to active-high,
525 #address-cells = <3>; 199 */
526 device_type = "pci";
527 interrupt-parent = <&mpic>;
528 interrupts = <16 2>;
529 interrupt-map-mask = <0xf800 0 0 7>; 200 interrupt-map-mask = <0xf800 0 0 7>;
530 interrupt-map = < 201 interrupt-map = <
531 /* IDSEL 0x0 */ 202 /* IDSEL 0x0 */
532 0000 0 0 1 &mpic 8 1 203 0000 0 0 1 &mpic 8 1 0 0
533 0000 0 0 2 &mpic 9 1 204 0000 0 0 2 &mpic 9 1 0 0
534 0000 0 0 3 &mpic 10 1 205 0000 0 0 3 &mpic 10 1 0 0
535 0000 0 0 4 &mpic 11 1 206 0000 0 0 4 &mpic 11 2 0 0
536 >; 207 >;
537 ranges = <0x2000000 0x0 0x80000000 208 ranges = <0x2000000 0x0 0x80000000
538 0x2000000 0x0 0x80000000 209 0x2000000 0x0 0x80000000
@@ -544,3 +215,5 @@
544 }; 215 };
545 }; 216 };
546}; 217};
218
219/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 66f03d6477b2..237310cc7e6c 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -9,30 +9,17 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020DS"; 15 model = "fsl,P2020DS";
16 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
17 17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 };
28
29
30 memory { 18 memory {
31 device_type = "memory"; 19 device_type = "memory";
32 }; 20 };
33 21
34 localbus@ffe05000 { 22 board_lbc: lbc: localbus@ffe05000 {
35 compatible = "fsl,elbc", "simple-bus";
36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 23 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
37 0x1 0x0 0x0 0xe0000000 0x08000000 24 0x1 0x0 0x0 0xe0000000 0x08000000
38 0x2 0x0 0x0 0xffa00000 0x00040000 25 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -40,203 +27,18 @@
40 0x4 0x0 0x0 0xffa40000 0x00040000 27 0x4 0x0 0x0 0xffa40000 0x00040000
41 0x5 0x0 0x0 0xffa80000 0x00040000 28 0x5 0x0 0x0 0xffa80000 0x00040000
42 0x6 0x0 0x0 0xffac0000 0x00040000>; 29 0x6 0x0 0x0 0xffac0000 0x00040000>;
43 30 reg = <0 0xffe05000 0 0x1000>;
44 nor@0,0 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "cfi-flash";
48 reg = <0x0 0x0 0x8000000>;
49 bank-width = <2>;
50 device-width = <1>;
51
52 ramdisk@0 {
53 reg = <0x0 0x03000000>;
54 read-only;
55 };
56
57 diagnostic@3000000 {
58 reg = <0x03000000 0x00e00000>;
59 read-only;
60 };
61
62 dink@3e00000 {
63 reg = <0x03e00000 0x00200000>;
64 read-only;
65 };
66
67 kernel@4000000 {
68 reg = <0x04000000 0x00400000>;
69 read-only;
70 };
71
72 jffs2@4400000 {
73 reg = <0x04400000 0x03b00000>;
74 };
75
76 dtb@7f00000 {
77 reg = <0x07f00000 0x00080000>;
78 read-only;
79 };
80
81 u-boot@7f80000 {
82 reg = <0x07f80000 0x00080000>;
83 read-only;
84 };
85 };
86
87 nand@2,0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "fsl,elbc-fcm-nand";
91 reg = <0x2 0x0 0x40000>;
92
93 u-boot@0 {
94 reg = <0x0 0x02000000>;
95 read-only;
96 };
97
98 jffs2@2000000 {
99 reg = <0x02000000 0x10000000>;
100 };
101
102 ramdisk@12000000 {
103 reg = <0x12000000 0x08000000>;
104 read-only;
105 };
106
107 kernel@1a000000 {
108 reg = <0x1a000000 0x04000000>;
109 };
110
111 dtb@1e000000 {
112 reg = <0x1e000000 0x01000000>;
113 read-only;
114 };
115
116 empty@1f000000 {
117 reg = <0x1f000000 0x21000000>;
118 };
119 };
120
121 board-control@3,0 {
122 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
123 reg = <0x3 0x0 0x30>;
124 };
125
126 nand@4,0 {
127 compatible = "fsl,elbc-fcm-nand";
128 reg = <0x4 0x0 0x40000>;
129 };
130
131 nand@5,0 {
132 compatible = "fsl,elbc-fcm-nand";
133 reg = <0x5 0x0 0x40000>;
134 };
135
136 nand@6,0 {
137 compatible = "fsl,elbc-fcm-nand";
138 reg = <0x6 0x0 0x40000>;
139 };
140 }; 31 };
141 32
142 soc@ffe00000 { 33 board_soc: soc: soc@ffe00000 {
143 34 ranges = <0x0 0x0 0xffe00000 0x100000>;
144 usb@22000 {
145 phy_type = "ulpi";
146 };
147
148 mdio@24520 {
149 phy0: ethernet-phy@0 {
150 interrupt-parent = <&mpic>;
151 interrupts = <3 1>;
152 reg = <0x0>;
153 };
154 phy1: ethernet-phy@1 {
155 interrupt-parent = <&mpic>;
156 interrupts = <3 1>;
157 reg = <0x1>;
158 };
159 phy2: ethernet-phy@2 {
160 interrupt-parent = <&mpic>;
161 interrupts = <3 1>;
162 reg = <0x2>;
163 };
164 tbi0: tbi-phy@11 {
165 reg = <0x11>;
166 device_type = "tbi-phy";
167 };
168
169 };
170
171 mdio@25520 {
172 tbi1: tbi-phy@11 {
173 reg = <0x11>;
174 device_type = "tbi-phy";
175 };
176 };
177
178 mdio@26520 {
179 tbi2: tbi-phy@11 {
180 reg = <0x11>;
181 device_type = "tbi-phy";
182 };
183
184 };
185
186 ptp_clock@24E00 {
187 compatible = "fsl,etsec-ptp";
188 reg = <0x24E00 0xB0>;
189 interrupts = <68 2 69 2 70 2>;
190 interrupt-parent = < &mpic >;
191 fsl,tclk-period = <5>;
192 fsl,tmr-prsc = <200>;
193 fsl,tmr-add = <0xCCCCCCCD>;
194 fsl,tmr-fiper1 = <0x3B9AC9FB>;
195 fsl,tmr-fiper2 = <0x0001869B>;
196 fsl,max-adj = <249999999>;
197 };
198
199 enet0: ethernet@24000 {
200 tbi-handle = <&tbi0>;
201 phy-handle = <&phy0>;
202 phy-connection-type = "rgmii-id";
203 };
204
205 enet1: ethernet@25000 {
206 tbi-handle = <&tbi1>;
207 phy-handle = <&phy1>;
208 phy-connection-type = "rgmii-id";
209
210 };
211
212 enet2: ethernet@26000 {
213 tbi-handle = <&tbi2>;
214 phy-handle = <&phy2>;
215 phy-connection-type = "rgmii-id";
216 };
217
218
219 msi@41600 {
220 compatible = "fsl,mpic-msi";
221 };
222 }; 35 };
223 36
224 pci0: pcie@ffe08000 { 37 pci2: pcie@ffe08000 {
225 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 38 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
226 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 39 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
227 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 40 reg = <0 0xffe08000 0 0x1000>;
228 interrupt-map = <
229 /* IDSEL 0x0 */
230 0000 0x0 0x0 0x1 &mpic 0x8 0x1
231 0000 0x0 0x0 0x2 &mpic 0x9 0x1
232 0000 0x0 0x0 0x3 &mpic 0xa 0x1
233 0000 0x0 0x0 0x4 &mpic 0xb 0x1
234 >;
235 pcie@0 { 41 pcie@0 {
236 reg = <0x0 0x0 0x0 0x0 0x0>;
237 #size-cells = <2>;
238 #address-cells = <3>;
239 device_type = "pci";
240 ranges = <0x2000000 0x0 0x80000000 42 ranges = <0x2000000 0x0 0x80000000
241 0x2000000 0x0 0x80000000 43 0x2000000 0x0 0x80000000
242 0x0 0x20000000 44 0x0 0x20000000
@@ -247,61 +49,11 @@
247 }; 49 };
248 }; 50 };
249 51
250 pci1: pcie@ffe09000 { 52 board_pci1: pci1: pcie@ffe09000 {
251 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 53 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
252 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 54 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
253 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 55 reg = <0 0xffe09000 0 0x1000>;
254 interrupt-map = <
255
256 // IDSEL 0x11 func 0 - PCI slot 1
257 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
258 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
259
260 // IDSEL 0x11 func 1 - PCI slot 1
261 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
262 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
263
264 // IDSEL 0x11 func 2 - PCI slot 1
265 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
266 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
267
268 // IDSEL 0x11 func 3 - PCI slot 1
269 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
270 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
271
272 // IDSEL 0x11 func 4 - PCI slot 1
273 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
274 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
275
276 // IDSEL 0x11 func 5 - PCI slot 1
277 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
278 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
279
280 // IDSEL 0x11 func 6 - PCI slot 1
281 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
282 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
283
284 // IDSEL 0x11 func 7 - PCI slot 1
285 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
286 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
287
288 // IDSEL 0x1d Audio
289 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
290
291 // IDSEL 0x1e Legacy
292 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
293 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
294
295 // IDSEL 0x1f IDE/SATA
296 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
297 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
298 >;
299
300 pcie@0 { 56 pcie@0 {
301 reg = <0x0 0x0 0x0 0x0 0x0>;
302 #size-cells = <2>;
303 #address-cells = <3>;
304 device_type = "pci";
305 ranges = <0x2000000 0x0 0xa0000000 57 ranges = <0x2000000 0x0 0xa0000000
306 0x2000000 0x0 0xa0000000 58 0x2000000 0x0 0xa0000000
307 0x0 0x20000000 59 0x0 0x20000000
@@ -309,89 +61,14 @@
309 0x1000000 0x0 0x0 61 0x1000000 0x0 0x0
310 0x1000000 0x0 0x0 62 0x1000000 0x0 0x0
311 0x0 0x10000>; 63 0x0 0x10000>;
312 uli1575@0 {
313 reg = <0x0 0x0 0x0 0x0 0x0>;
314 #size-cells = <2>;
315 #address-cells = <3>;
316 ranges = <0x2000000 0x0 0xa0000000
317 0x2000000 0x0 0xa0000000
318 0x0 0x20000000
319
320 0x1000000 0x0 0x0
321 0x1000000 0x0 0x0
322 0x0 0x10000>;
323 isa@1e {
324 device_type = "isa";
325 #interrupt-cells = <2>;
326 #size-cells = <1>;
327 #address-cells = <2>;
328 reg = <0xf000 0x0 0x0 0x0 0x0>;
329 ranges = <0x1 0x0 0x1000000 0x0 0x0
330 0x1000>;
331 interrupt-parent = <&i8259>;
332
333 i8259: interrupt-controller@20 {
334 reg = <0x1 0x20 0x2
335 0x1 0xa0 0x2
336 0x1 0x4d0 0x2>;
337 interrupt-controller;
338 device_type = "interrupt-controller";
339 #address-cells = <0>;
340 #interrupt-cells = <2>;
341 compatible = "chrp,iic";
342 interrupts = <4 1>;
343 interrupt-parent = <&mpic>;
344 };
345
346 i8042@60 {
347 #size-cells = <0>;
348 #address-cells = <1>;
349 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
350 interrupts = <1 3 12 3>;
351 interrupt-parent =
352 <&i8259>;
353
354 keyboard@0 {
355 reg = <0x0>;
356 compatible = "pnpPNP,303";
357 };
358
359 mouse@1 {
360 reg = <0x1>;
361 compatible = "pnpPNP,f03";
362 };
363 };
364
365 rtc@70 {
366 compatible = "pnpPNP,b00";
367 reg = <0x1 0x70 0x2>;
368 };
369
370 gpio@400 {
371 reg = <0x1 0x400 0x80>;
372 };
373 };
374 };
375 }; 64 };
376
377 }; 65 };
378 66
379 pci2: pcie@ffe0a000 { 67 pci0: pcie@ffe0a000 {
380 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 68 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
381 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 69 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
382 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 70 reg = <0 0xffe0a000 0 0x1000>;
383 interrupt-map = <
384 /* IDSEL 0x0 */
385 0000 0x0 0x0 0x1 &mpic 0x0 0x1
386 0000 0x0 0x0 0x2 &mpic 0x1 0x1
387 0000 0x0 0x0 0x3 &mpic 0x2 0x1
388 0000 0x0 0x0 0x4 &mpic 0x3 0x1
389 >;
390 pcie@0 { 71 pcie@0 {
391 reg = <0x0 0x0 0x0 0x0 0x0>;
392 #size-cells = <2>;
393 #address-cells = <3>;
394 device_type = "pci";
395 ranges = <0x2000000 0x0 0xc0000000 72 ranges = <0x2000000 0x0 0xc0000000
396 0x2000000 0x0 0xc0000000 73 0x2000000 0x0 0xc0000000
397 0x0 0x20000000 74 0x0 0x20000000
@@ -402,3 +79,11 @@
402 }; 79 };
403 }; 80 };
404}; 81};
82
83/*
84 * p2020ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
85 * for interrupt-map & interrupt-map-mask
86 */
87
88/include/ "fsl/p2020si-post.dtsi"
89/include/ "p2020ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
new file mode 100644
index 000000000000..c1cf6cef4dd6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -0,0 +1,316 @@
1/*
2 * P2020DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
46 read-only;
47 };
48
49 diagnostic@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 read-only;
52 };
53
54 dink@3e00000 {
55 reg = <0x03e00000 0x00200000>;
56 read-only;
57 };
58
59 kernel@4000000 {
60 reg = <0x04000000 0x00400000>;
61 read-only;
62 };
63
64 jffs2@4400000 {
65 reg = <0x04400000 0x03b00000>;
66 };
67
68 dtb@7f00000 {
69 reg = <0x07f00000 0x00080000>;
70 read-only;
71 };
72
73 u-boot@7f80000 {
74 reg = <0x07f80000 0x00080000>;
75 read-only;
76 };
77 };
78
79 nand@2,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,elbc-fcm-nand";
83 reg = <0x2 0x0 0x40000>;
84
85 u-boot@0 {
86 reg = <0x0 0x02000000>;
87 read-only;
88 };
89
90 jffs2@2000000 {
91 reg = <0x02000000 0x10000000>;
92 };
93
94 ramdisk@12000000 {
95 reg = <0x12000000 0x08000000>;
96 read-only;
97 };
98
99 kernel@1a000000 {
100 reg = <0x1a000000 0x04000000>;
101 };
102
103 dtb@1e000000 {
104 reg = <0x1e000000 0x01000000>;
105 read-only;
106 };
107
108 empty@1f000000 {
109 reg = <0x1f000000 0x21000000>;
110 };
111 };
112
113 board-control@3,0 {
114 compatible = "fsl,p2020ds-fpga", "fsl,fpga-ngpixis";
115 reg = <0x3 0x0 0x30>;
116 };
117
118 nand@4,0 {
119 compatible = "fsl,elbc-fcm-nand";
120 reg = <0x4 0x0 0x40000>;
121 };
122
123 nand@5,0 {
124 compatible = "fsl,elbc-fcm-nand";
125 reg = <0x5 0x0 0x40000>;
126 };
127
128 nand@6,0 {
129 compatible = "fsl,elbc-fcm-nand";
130 reg = <0x6 0x0 0x40000>;
131 };
132};
133
134&board_soc {
135 usb@22000 {
136 phy_type = "ulpi";
137 };
138
139 mdio@24520 {
140 phy0: ethernet-phy@0 {
141 interrupts = <3 1 0 0>;
142 reg = <0x0>;
143 };
144 phy1: ethernet-phy@1 {
145 interrupts = <3 1 0 0>;
146 reg = <0x1>;
147 };
148 phy2: ethernet-phy@2 {
149 interrupts = <3 1 0 0>;
150 reg = <0x2>;
151 };
152 tbi0: tbi-phy@11 {
153 reg = <0x11>;
154 device_type = "tbi-phy";
155 };
156
157 };
158
159 mdio@25520 {
160 tbi1: tbi-phy@11 {
161 reg = <0x11>;
162 device_type = "tbi-phy";
163 };
164 };
165
166 mdio@26520 {
167 tbi2: tbi-phy@11 {
168 reg = <0x11>;
169 device_type = "tbi-phy";
170 };
171
172 };
173
174 ptp_clock@24e00 {
175 fsl,tclk-period = <5>;
176 fsl,tmr-prsc = <200>;
177 fsl,tmr-add = <0xCCCCCCCD>;
178 fsl,tmr-fiper1 = <0x3B9AC9FB>;
179 fsl,tmr-fiper2 = <0x0001869B>;
180 fsl,max-adj = <249999999>;
181 };
182
183 enet0: ethernet@24000 {
184 tbi-handle = <&tbi0>;
185 phy-handle = <&phy0>;
186 phy-connection-type = "rgmii-id";
187 };
188
189 enet1: ethernet@25000 {
190 tbi-handle = <&tbi1>;
191 phy-handle = <&phy1>;
192 phy-connection-type = "rgmii-id";
193
194 };
195
196 enet2: ethernet@26000 {
197 tbi-handle = <&tbi2>;
198 phy-handle = <&phy2>;
199 phy-connection-type = "rgmii-id";
200 };
201};
202
203&board_pci1 {
204 pcie@0 {
205 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
206 interrupt-map = <
207
208 // IDSEL 0x11 func 0 - PCI slot 1
209 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
210 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
211
212 // IDSEL 0x11 func 1 - PCI slot 1
213 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
214 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
215
216 // IDSEL 0x11 func 2 - PCI slot 1
217 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
218 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
219
220 // IDSEL 0x11 func 3 - PCI slot 1
221 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
222 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
223
224 // IDSEL 0x11 func 4 - PCI slot 1
225 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
226 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
227
228 // IDSEL 0x11 func 5 - PCI slot 1
229 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
230 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
231
232 // IDSEL 0x11 func 6 - PCI slot 1
233 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
234 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
235
236 // IDSEL 0x11 func 7 - PCI slot 1
237 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
238 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
239
240 // IDSEL 0x1d Audio
241 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
242
243 // IDSEL 0x1e Legacy
244 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
245 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
246
247 // IDSEL 0x1f IDE/SATA
248 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
249 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
250 >;
251
252 uli1575@0 {
253 reg = <0x0 0x0 0x0 0x0 0x0>;
254 #size-cells = <2>;
255 #address-cells = <3>;
256 ranges = <0x2000000 0x0 0xa0000000
257 0x2000000 0x0 0xa0000000
258 0x0 0x20000000
259
260 0x1000000 0x0 0x0
261 0x1000000 0x0 0x0
262 0x0 0x10000>;
263 isa@1e {
264 device_type = "isa";
265 #interrupt-cells = <2>;
266 #size-cells = <1>;
267 #address-cells = <2>;
268 reg = <0xf000 0x0 0x0 0x0 0x0>;
269 ranges = <0x1 0x0 0x1000000 0x0 0x0
270 0x1000>;
271 interrupt-parent = <&i8259>;
272
273 i8259: interrupt-controller@20 {
274 reg = <0x1 0x20 0x2
275 0x1 0xa0 0x2
276 0x1 0x4d0 0x2>;
277 interrupt-controller;
278 device_type = "interrupt-controller";
279 #address-cells = <0>;
280 #interrupt-cells = <2>;
281 compatible = "chrp,iic";
282 interrupts = <4 1 0 0>;
283 interrupt-parent = <&mpic>;
284 };
285
286 i8042@60 {
287 #size-cells = <0>;
288 #address-cells = <1>;
289 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
290 interrupts = <1 3 12 3>;
291 interrupt-parent =
292 <&i8259>;
293
294 keyboard@0 {
295 reg = <0x0>;
296 compatible = "pnpPNP,303";
297 };
298
299 mouse@1 {
300 reg = <0x1>;
301 compatible = "pnpPNP,f03";
302 };
303 };
304
305 rtc@70 {
306 compatible = "pnpPNP,b00";
307 reg = <0x1 0x70 0x2>;
308 };
309
310 gpio@400 {
311 reg = <0x1 0x400 0x80>;
312 };
313 };
314 };
315 };
316};
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 1d7a05f3021e..26759a591712 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,7 +9,7 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/include/ "p2020si.dtsi" 12/include/ "fsl/p2020si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "fsl,P2020RDB"; 15 model = "fsl,P2020RDB";
@@ -29,7 +29,8 @@
29 device_type = "memory"; 29 device_type = "memory";
30 }; 30 };
31 31
32 localbus@ffe05000 { 32 lbc: localbus@ffe05000 {
33 reg = <0 0xffe05000 0 0x1000>;
33 34
34 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -140,7 +141,9 @@
140 141
141 }; 142 };
142 143
143 soc@ffe00000 { 144 soc: soc@ffe00000 {
145 ranges = <0x0 0x0 0xffe00000 0x100000>;
146
144 i2c@3000 { 147 i2c@3000 {
145 rtc@68 { 148 rtc@68 {
146 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
@@ -148,17 +151,13 @@
148 }; 151 };
149 }; 152 };
150 153
151 spi@7000 { 154 spi@7000 {
152 155 flash@0 {
153 fsl_m25p80@0 {
154 #address-cells = <1>; 156 #address-cells = <1>;
155 #size-cells = <1>; 157 #size-cells = <1>;
156 compatible = "fsl,espi-flash"; 158 compatible = "spansion,s25sl12801";
157 reg = <0>; 159 reg = <0>;
158 linux,modalias = "fsl_m25p80";
159 modal = "s25sl128b";
160 spi-max-frequency = <50000000>; 160 spi-max-frequency = <50000000>;
161 mode = <0>;
162 161
163 partition@0 { 162 partition@0 {
164 /* 512KB for u-boot Bootloader Image */ 163 /* 512KB for u-boot Bootloader Image */
@@ -202,15 +201,17 @@
202 201
203 mdio@24520 { 202 mdio@24520 {
204 phy0: ethernet-phy@0 { 203 phy0: ethernet-phy@0 {
205 interrupt-parent = <&mpic>; 204 interrupts = <3 1 0 0>;
206 interrupts = <3 1>;
207 reg = <0x0>; 205 reg = <0x0>;
208 }; 206 };
209 phy1: ethernet-phy@1 { 207 phy1: ethernet-phy@1 {
210 interrupt-parent = <&mpic>; 208 interrupts = <3 1 0 0>;
211 interrupts = <3 1>;
212 reg = <0x1>; 209 reg = <0x1>;
213 }; 210 };
211 tbi-phy@2 {
212 device_type = "tbi-phy";
213 reg = <0x2>;
214 };
214 }; 215 };
215 216
216 mdio@25520 { 217 mdio@25520 {
@@ -224,11 +225,7 @@
224 status = "disabled"; 225 status = "disabled";
225 }; 226 };
226 227
227 ptp_clock@24E00 { 228 ptp_clock@24e00 {
228 compatible = "fsl,etsec-ptp";
229 reg = <0x24E00 0xB0>;
230 interrupts = <68 2 69 2 70 2>;
231 interrupt-parent = < &mpic >;
232 fsl,tclk-period = <5>; 229 fsl,tclk-period = <5>;
233 fsl,tmr-prsc = <200>; 230 fsl,tmr-prsc = <200>;
234 fsl,tmr-add = <0xCCCCCCCD>; 231 fsl,tmr-add = <0xCCCCCCCD>;
@@ -252,29 +249,18 @@
252 phy-handle = <&phy1>; 249 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id"; 250 phy-connection-type = "rgmii-id";
254 }; 251 };
255
256 }; 252 };
257 253
258 pci0: pcie@ffe08000 { 254 pci0: pcie@ffe08000 {
255 reg = <0 0xffe08000 0 0x1000>;
259 status = "disabled"; 256 status = "disabled";
260 }; 257 };
261 258
262 pci1: pcie@ffe09000 { 259 pci1: pcie@ffe09000 {
260 reg = <0 0xffe09000 0 0x1000>;
263 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 261 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
264 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 262 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
265 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 263 pcie@0 {
266 interrupt-map = <
267 /* IDSEL 0x0 */
268 0000 0x0 0x0 0x1 &mpic 0x4 0x1
269 0000 0x0 0x0 0x2 &mpic 0x5 0x1
270 0000 0x0 0x0 0x3 &mpic 0x6 0x1
271 0000 0x0 0x0 0x4 &mpic 0x7 0x1
272 >;
273 pcie@0 {
274 reg = <0x0 0x0 0x0 0x0 0x0>;
275 #size-cells = <2>;
276 #address-cells = <3>;
277 device_type = "pci";
278 ranges = <0x2000000 0x0 0xa0000000 264 ranges = <0x2000000 0x0 0xa0000000
279 0x2000000 0x0 0xa0000000 265 0x2000000 0x0 0xa0000000
280 0x0 0x20000000 266 0x0 0x20000000
@@ -286,21 +272,10 @@
286 }; 272 };
287 273
288 pci2: pcie@ffe0a000 { 274 pci2: pcie@ffe0a000 {
275 reg = <0 0xffe0a000 0 0x1000>;
289 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 276 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
290 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 277 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
291 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
292 interrupt-map = <
293 /* IDSEL 0x0 */
294 0000 0x0 0x0 0x1 &mpic 0x0 0x1
295 0000 0x0 0x0 0x2 &mpic 0x1 0x1
296 0000 0x0 0x0 0x3 &mpic 0x2 0x1
297 0000 0x0 0x0 0x4 &mpic 0x3 0x1
298 >;
299 pcie@0 { 278 pcie@0 {
300 reg = <0x0 0x0 0x0 0x0 0x0>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 device_type = "pci";
304 ranges = <0x2000000 0x0 0x80000000 279 ranges = <0x2000000 0x0 0x80000000
305 0x2000000 0x0 0x80000000 280 0x2000000 0x0 0x80000000
306 0x0 0x20000000 281 0x0 0x20000000
@@ -311,3 +286,5 @@
311 }; 286 };
312 }; 287 };
313}; 288};
289
290/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index fc8ddddfccb6..66aac864c4cc 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,28 +14,16 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/include/ "p2020si.dtsi" 17/include/ "p2020rdb.dts"
18 18
19/ { 19/ {
20 model = "fsl,P2020RDB"; 20 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 22
23 aliases {
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 serial0 = &serial0;
27 pci0 = &pci0;
28 };
29
30 cpus { 23 cpus {
31 PowerPC,P2020@1 { 24 PowerPC,P2020@1 {
32 status = "disabled"; 25 status = "disabled";
33 }; 26 };
34
35 };
36
37 memory {
38 device_type = "memory";
39 }; 27 };
40 28
41 localbus@ffe05000 { 29 localbus@ffe05000 {
@@ -43,115 +31,18 @@
43 }; 31 };
44 32
45 soc@ffe00000 { 33 soc@ffe00000 {
46 i2c@3000 {
47 rtc@68 {
48 compatible = "dallas,ds1339";
49 reg = <0x68>;
50 };
51 };
52
53 serial1: serial@4600 { 34 serial1: serial@4600 {
54 status = "disabled"; 35 status = "disabled";
55 }; 36 };
56 37
57 spi@7000 {
58
59 fsl_m25p80@0 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "fsl,espi-flash";
63 reg = <0>;
64 linux,modalias = "fsl_m25p80";
65 modal = "s25sl128b";
66 spi-max-frequency = <50000000>;
67 mode = <0>;
68
69 partition@0 {
70 /* 512KB for u-boot Bootloader Image */
71 reg = <0x0 0x00080000>;
72 label = "SPI (RO) U-Boot Image";
73 read-only;
74 };
75
76 partition@80000 {
77 /* 512KB for DTB Image */
78 reg = <0x00080000 0x00080000>;
79 label = "SPI (RO) DTB Image";
80 read-only;
81 };
82
83 partition@100000 {
84 /* 4MB for Linux Kernel Image */
85 reg = <0x00100000 0x00400000>;
86 label = "SPI (RO) Linux Kernel Image";
87 read-only;
88 };
89
90 partition@500000 {
91 /* 4MB for Compressed RFS Image */
92 reg = <0x00500000 0x00400000>;
93 label = "SPI (RO) Compressed RFS Image";
94 read-only;
95 };
96
97 partition@900000 {
98 /* 7MB for JFFS2 based RFS */
99 reg = <0x00900000 0x00700000>;
100 label = "SPI (RW) JFFS2 RFS";
101 };
102 };
103 };
104
105 dma@c300 { 38 dma@c300 {
106 status = "disabled"; 39 status = "disabled";
107 }; 40 };
108 41
109 usb@22000 {
110 phy_type = "ulpi";
111 };
112
113 mdio@24520 {
114
115 phy0: ethernet-phy@0 {
116 interrupt-parent = <&mpic>;
117 interrupts = <3 1>;
118 reg = <0x0>;
119 };
120 phy1: ethernet-phy@1 {
121 interrupt-parent = <&mpic>;
122 interrupts = <3 1>;
123 reg = <0x1>;
124 };
125 };
126
127 mdio@25520 {
128 tbi0: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 { 42 enet0: ethernet@24000 {
139 status = "disabled"; 43 status = "disabled";
140 }; 44 };
141 45
142 enet1: ethernet@25000 {
143 tbi-handle = <&tbi0>;
144 phy-handle = <&phy0>;
145 phy-connection-type = "sgmii";
146
147 };
148
149 enet2: ethernet@26000 {
150 phy-handle = <&phy1>;
151 phy-connection-type = "rgmii-id";
152 };
153
154
155 mpic: pic@40000 { 46 mpic: pic@40000 {
156 protected-sources = < 47 protected-sources = <
157 42 76 77 78 79 /* serial1 , dma2 */ 48 42 76 77 78 79 /* serial1 , dma2 */
@@ -164,40 +55,12 @@
164 msi@41600 { 55 msi@41600 {
165 status = "disabled"; 56 status = "disabled";
166 }; 57 };
167
168
169 }; 58 };
170 59
171 pci0: pcie@ffe08000 { 60 pci0: pcie@ffe08000 {
172 status = "disabled"; 61 status = "disabled";
173 }; 62 };
174 63
175 pci1: pcie@ffe09000 {
176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
179 interrupt-map = <
180 /* IDSEL 0x0 */
181 0000 0x0 0x0 0x1 &mpic 0x4 0x1
182 0000 0x0 0x0 0x2 &mpic 0x5 0x1
183 0000 0x0 0x0 0x3 &mpic 0x6 0x1
184 0000 0x0 0x0 0x4 &mpic 0x7 0x1
185 >;
186 pcie@0 {
187 reg = <0x0 0x0 0x0 0x0 0x0>;
188 #size-cells = <2>;
189 #address-cells = <3>;
190 device_type = "pci";
191 ranges = <0x2000000 0x0 0xa0000000
192 0x2000000 0x0 0xa0000000
193 0x0 0x20000000
194
195 0x1000000 0x0 0x0
196 0x1000000 0x0 0x0
197 0x0 0x100000>;
198 };
199 };
200
201 pci2: pcie@ffe0a000 { 64 pci2: pcie@ffe0a000 {
202 status = "disabled"; 65 status = "disabled";
203 }; 66 };
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 261c34ba45ec..9bd8ef493dd2 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,28 +15,18 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/include/ "p2020si.dtsi" 18/include/ "p2020rdb.dts"
19 19
20/ { 20/ {
21 model = "fsl,P2020RDB"; 21 model = "fsl,P2020RDB";
22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
23 23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 pci1 = &pci1;
28 };
29
30 cpus { 24 cpus {
31 PowerPC,P2020@0 { 25 PowerPC,P2020@0 {
32 status = "disabled"; 26 status = "disabled";
33 }; 27 };
34 }; 28 };
35 29
36 memory {
37 device_type = "memory";
38 };
39
40 localbus@ffe05000 { 30 localbus@ffe05000 {
41 status = "disabled"; 31 status = "disabled";
42 }; 32 };
@@ -70,55 +60,10 @@
70 status = "disabled"; 60 status = "disabled";
71 }; 61 };
72 62
73 dma@c300 {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 compatible = "fsl,eloplus-dma";
77 reg = <0xc300 0x4>;
78 ranges = <0x0 0xc100 0x200>;
79 cell-index = <1>;
80 dma-channel@0 {
81 compatible = "fsl,eloplus-dma-channel";
82 reg = <0x0 0x80>;
83 cell-index = <0>;
84 interrupt-parent = <&mpic>;
85 interrupts = <76 2>;
86 };
87 dma-channel@80 {
88 compatible = "fsl,eloplus-dma-channel";
89 reg = <0x80 0x80>;
90 cell-index = <1>;
91 interrupt-parent = <&mpic>;
92 interrupts = <77 2>;
93 };
94 dma-channel@100 {
95 compatible = "fsl,eloplus-dma-channel";
96 reg = <0x100 0x80>;
97 cell-index = <2>;
98 interrupt-parent = <&mpic>;
99 interrupts = <78 2>;
100 };
101 dma-channel@180 {
102 compatible = "fsl,eloplus-dma-channel";
103 reg = <0x180 0x80>;
104 cell-index = <3>;
105 interrupt-parent = <&mpic>;
106 interrupts = <79 2>;
107 };
108 };
109
110 gpio: gpio-controller@f000 { 63 gpio: gpio-controller@f000 {
111 status = "disabled"; 64 status = "disabled";
112 }; 65 };
113 66
114 L2: l2-cache-controller@20000 {
115 compatible = "fsl,p2020-l2-cache-controller";
116 reg = <0x20000 0x1000>;
117 cache-line-size = <32>; // 32 bytes
118 cache-size = <0x80000>; // L2,512K
119 interrupt-parent = <&mpic>;
120 };
121
122 dma@21300 { 67 dma@21300 {
123 status = "disabled"; 68 status = "disabled";
124 }; 69 };
@@ -139,12 +84,6 @@
139 status = "disabled"; 84 status = "disabled";
140 }; 85 };
141 86
142 enet0: ethernet@24000 {
143 fixed-link = <1 1 1000 0 0>;
144 phy-connection-type = "rgmii-id";
145
146 };
147
148 enet1: ethernet@25000 { 87 enet1: ethernet@25000 {
149 status = "disabled"; 88 status = "disabled";
150 }; 89 };
@@ -170,22 +109,6 @@
170 >; 109 >;
171 }; 110 };
172 111
173 msi@41600 {
174 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
175 reg = <0x41600 0x80>;
176 msi-available-ranges = <0 0x100>;
177 interrupts = <
178 0xe0 0
179 0xe1 0
180 0xe2 0
181 0xe3 0
182 0xe4 0
183 0xe5 0
184 0xe6 0
185 0xe7 0>;
186 interrupt-parent = <&mpic>;
187 };
188
189 global-utilities@e0000 { //global utilities block 112 global-utilities@e0000 { //global utilities block
190 status = "disabled"; 113 status = "disabled";
191 }; 114 };
@@ -199,30 +122,4 @@
199 pci1: pcie@ffe09000 { 122 pci1: pcie@ffe09000 {
200 status = "disabled"; 123 status = "disabled";
201 }; 124 };
202
203 pci2: pcie@ffe0a000 {
204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
206 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
207 interrupt-map = <
208 /* IDSEL 0x0 */
209 0000 0x0 0x0 0x1 &mpic 0x0 0x1
210 0000 0x0 0x0 0x2 &mpic 0x1 0x1
211 0000 0x0 0x0 0x3 &mpic 0x2 0x1
212 0000 0x0 0x0 0x4 &mpic 0x3 0x1
213 >;
214 pcie@0 {
215 reg = <0x0 0x0 0x0 0x0 0x0>;
216 #size-cells = <2>;
217 #address-cells = <3>;
218 device_type = "pci";
219 ranges = <0x2000000 0x0 0x80000000
220 0x2000000 0x0 0x80000000
221 0x0 0x20000000
222
223 0x1000000 0x0 0x0
224 0x1000000 0x0 0x0
225 0x0 0x100000>;
226 };
227 };
228}; 125};
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
deleted file mode 100644
index 6def17f265d3..000000000000
--- a/arch/powerpc/boot/dts/p2020si.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P2020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P2020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 dma@c300 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,eloplus-dma";
129 reg = <0xc300 0x4>;
130 ranges = <0x0 0xc100 0x200>;
131 cell-index = <1>;
132 dma-channel@0 {
133 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <76 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>;
142 cell-index = <1>;
143 interrupt-parent = <&mpic>;
144 interrupts = <77 2>;
145 };
146 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <78 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>;
156 cell-index = <3>;
157 interrupt-parent = <&mpic>;
158 interrupts = <79 2>;
159 };
160 };
161
162 gpio: gpio-controller@f000 {
163 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>;
167 interrupt-parent = <&mpic>;
168 gpio-controller;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,p2020-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 dma@21300 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "fsl,eloplus-dma";
184 reg = <0x21300 0x4>;
185 ranges = <0x0 0x21100 0x200>;
186 cell-index = <0>;
187 dma-channel@0 {
188 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>;
190 cell-index = <0>;
191 interrupt-parent = <&mpic>;
192 interrupts = <20 2>;
193 };
194 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>;
197 cell-index = <1>;
198 interrupt-parent = <&mpic>;
199 interrupts = <21 2>;
200 };
201 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>;
204 cell-index = <2>;
205 interrupt-parent = <&mpic>;
206 interrupts = <22 2>;
207 };
208 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 usb@22000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>;
223 interrupts = <28 0x2>;
224 };
225
226 mdio@24520 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,gianfar-mdio";
230 reg = <0x24520 0x20>;
231 };
232
233 mdio@25520 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,gianfar-tbi";
237 reg = <0x26520 0x20>;
238 };
239
240 mdio@26520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-tbi";
244 reg = <0x520 0x20>;
245 };
246
247 enet0: ethernet@24000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <0>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>;
258 interrupt-parent = <&mpic>;
259 };
260
261 enet1: ethernet@25000 {
262 #address-cells = <1>;
263 #size-cells = <1>;
264 cell-index = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>;
272 interrupt-parent = <&mpic>;
273
274 };
275
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288
289 };
290
291 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */
297 clock-frequency = <0>;
298 };
299
300 crypto@30000 {
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>;
309 fsl,descriptor-types-mask = <0x3ab0ebf>;
310 };
311
312 mpic: pic@40000 {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <0x40000 0x40000>;
317 compatible = "chrp,open-pic";
318 device_type = "open-pic";
319 };
320
321 msi@41600 {
322 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
323 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>;
325 interrupts = <
326 0xe0 0
327 0xe1 0
328 0xe2 0
329 0xe3 0
330 0xe4 0
331 0xe5 0
332 0xe6 0
333 0xe7 0>;
334 interrupt-parent = <&mpic>;
335 };
336
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,p2020-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
343
344 pci0: pcie@ffe08000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
354 interrupts = <24 2>;
355 };
356
357 pci1: pcie@ffe09000 {
358 compatible = "fsl,mpc8548-pcie";
359 device_type = "pci";
360 #interrupt-cells = <1>;
361 #size-cells = <2>;
362 #address-cells = <3>;
363 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <25 2>;
368 };
369
370 pci2: pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>;
378 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>;
380 interrupts = <26 2>;
381 };
382};
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 79b6895027c0..4f957db01230 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p2041si.dtsi" 35/include/ "fsl/p2041si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P2041RDB"; 38 model = "fsl,P2041RDB";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -106,7 +108,18 @@
106 }; 108 };
107 }; 109 };
108 110
109 localbus@ffe124000 { 111 rio: rapidio@ffe0c0000 {
112 reg = <0xf 0xfe0c0000 0 0x11000>;
113
114 port1 {
115 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
116 };
117 port2 {
118 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
119 };
120 };
121
122 lbc: localbus@ffe124000 {
110 reg = <0xf 0xfe124000 0 0x1000>; 123 reg = <0xf 0xfe124000 0 0x1000>;
111 ranges = <0 0 0xf 0xe8000000 0x08000000>; 124 ranges = <0 0 0xf 0xe8000000 0x08000000>;
112 125
@@ -122,6 +135,7 @@
122 reg = <0xf 0xfe200000 0 0x1000>; 135 reg = <0xf 0xfe200000 0 0x1000>;
123 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 136 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
124 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 137 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
138 fsl,msi = <&msi0>;
125 pcie@0 { 139 pcie@0 {
126 ranges = <0x02000000 0 0xe0000000 140 ranges = <0x02000000 0 0xe0000000
127 0x02000000 0 0xe0000000 141 0x02000000 0 0xe0000000
@@ -137,6 +151,7 @@
137 reg = <0xf 0xfe201000 0 0x1000>; 151 reg = <0xf 0xfe201000 0 0x1000>;
138 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 152 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
139 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 153 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
154 fsl,msi = <&msi1>;
140 pcie@0 { 155 pcie@0 {
141 ranges = <0x02000000 0 0xe0000000 156 ranges = <0x02000000 0 0xe0000000
142 0x02000000 0 0xe0000000 157 0x02000000 0 0xe0000000
@@ -152,6 +167,7 @@
152 reg = <0xf 0xfe202000 0 0x1000>; 167 reg = <0xf 0xfe202000 0 0x1000>;
153 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 168 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
154 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 169 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
170 fsl,msi = <&msi2>;
155 pcie@0 { 171 pcie@0 {
156 ranges = <0x02000000 0 0xe0000000 172 ranges = <0x02000000 0 0xe0000000
157 0x02000000 0 0xe0000000 173 0x02000000 0 0xe0000000
@@ -163,3 +179,5 @@
163 }; 179 };
164 }; 180 };
165}; 181};
182
183/include/ "fsl/p2041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2041si.dtsi b/arch/powerpc/boot/dts/p2041si.dtsi
deleted file mode 100644
index f7492edd0dfd..000000000000
--- a/arch/powerpc/boot/dts/p2041si.dtsi
+++ /dev/null
@@ -1,692 +0,0 @@
1/*
2 * P2041 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P2041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 cpu0: PowerPC,e500mc@0 {
80 device_type = "cpu";
81 reg = <0>;
82 next-level-cache = <&L2_0>;
83 L2_0: l2-cache {
84 next-level-cache = <&cpc>;
85 };
86 };
87 cpu1: PowerPC,e500mc@1 {
88 device_type = "cpu";
89 reg = <1>;
90 next-level-cache = <&L2_1>;
91 L2_1: l2-cache {
92 next-level-cache = <&cpc>;
93 };
94 };
95 cpu2: PowerPC,e500mc@2 {
96 device_type = "cpu";
97 reg = <2>;
98 next-level-cache = <&L2_2>;
99 L2_2: l2-cache {
100 next-level-cache = <&cpc>;
101 };
102 };
103 cpu3: PowerPC,e500mc@3 {
104 device_type = "cpu";
105 reg = <3>;
106 next-level-cache = <&L2_3>;
107 L2_3: l2-cache {
108 next-level-cache = <&cpc>;
109 };
110 };
111 };
112
113 dcsr: dcsr@f00000000 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "fsl,dcsr", "simple-bus";
117
118 dcsr-epu@0 {
119 compatible = "fsl,dcsr-epu";
120 interrupts = <52 2 0 0
121 84 2 0 0
122 85 2 0 0>;
123 interrupt-parent = <&mpic>;
124 reg = <0x0 0x1000>;
125 };
126 dcsr-npc {
127 compatible = "fsl,dcsr-npc";
128 reg = <0x1000 0x1000 0x1000000 0x8000>;
129 };
130 dcsr-nxc@2000 {
131 compatible = "fsl,dcsr-nxc";
132 reg = <0x2000 0x1000>;
133 };
134 dcsr-corenet {
135 compatible = "fsl,dcsr-corenet";
136 reg = <0x8000 0x1000 0xB0000 0x1000>;
137 };
138 dcsr-dpaa@9000 {
139 compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
140 reg = <0x9000 0x1000>;
141 };
142 dcsr-ocn@11000 {
143 compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
144 reg = <0x11000 0x1000>;
145 };
146 dcsr-ddr@12000 {
147 compatible = "fsl,dcsr-ddr";
148 dev-handle = <&ddr>;
149 reg = <0x12000 0x1000>;
150 };
151 dcsr-nal@18000 {
152 compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
153 reg = <0x18000 0x1000>;
154 };
155 dcsr-rcpm@22000 {
156 compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
157 reg = <0x22000 0x1000>;
158 };
159 dcsr-cpu-sb-proxy@40000 {
160 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
161 cpu-handle = <&cpu0>;
162 reg = <0x40000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@41000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu1>;
167 reg = <0x41000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@42000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu2>;
172 reg = <0x42000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@43000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu3>;
177 reg = <0x43000 0x1000>;
178 };
179 };
180
181 soc: soc@ffe000000 {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 device_type = "soc";
185 compatible = "simple-bus";
186 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
187 reg = <0xf 0xfe000000 0 0x00001000>;
188
189 soc-sram-error {
190 compatible = "fsl,soc-sram-error";
191 interrupts = <16 2 1 29>;
192 };
193
194 corenet-law@0 {
195 compatible = "fsl,corenet-law";
196 reg = <0x0 0x1000>;
197 fsl,num-laws = <32>;
198 };
199
200 ddr: memory-controller@8000 {
201 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
202 reg = <0x8000 0x1000>;
203 interrupts = <16 2 1 23>;
204 };
205
206 cpc: l3-cache-controller@10000 {
207 compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
208 reg = <0x10000 0x1000>;
209 interrupts = <16 2 1 27>;
210 };
211
212 corenet-cf@18000 {
213 compatible = "fsl,corenet-cf";
214 reg = <0x18000 0x1000>;
215 interrupts = <16 2 1 31>;
216 fsl,ccf-num-csdids = <32>;
217 fsl,ccf-num-snoopids = <32>;
218 };
219
220 iommu@20000 {
221 compatible = "fsl,pamu-v1.0", "fsl,pamu";
222 reg = <0x20000 0x4000>;
223 interrupts = <
224 24 2 0 0
225 16 2 1 30>;
226 };
227
228 mpic: pic@40000 {
229 clock-frequency = <0>;
230 interrupt-controller;
231 #address-cells = <0>;
232 #interrupt-cells = <4>;
233 reg = <0x40000 0x40000>;
234 compatible = "fsl,mpic", "chrp,open-pic";
235 device_type = "open-pic";
236 };
237
238 msi0: msi@41600 {
239 compatible = "fsl,mpic-msi";
240 reg = <0x41600 0x200>;
241 msi-available-ranges = <0 0x100>;
242 interrupts = <
243 0xe0 0 0 0
244 0xe1 0 0 0
245 0xe2 0 0 0
246 0xe3 0 0 0
247 0xe4 0 0 0
248 0xe5 0 0 0
249 0xe6 0 0 0
250 0xe7 0 0 0>;
251 };
252
253 msi1: msi@41800 {
254 compatible = "fsl,mpic-msi";
255 reg = <0x41800 0x200>;
256 msi-available-ranges = <0 0x100>;
257 interrupts = <
258 0xe8 0 0 0
259 0xe9 0 0 0
260 0xea 0 0 0
261 0xeb 0 0 0
262 0xec 0 0 0
263 0xed 0 0 0
264 0xee 0 0 0
265 0xef 0 0 0>;
266 };
267
268 msi2: msi@41a00 {
269 compatible = "fsl,mpic-msi";
270 reg = <0x41a00 0x200>;
271 msi-available-ranges = <0 0x100>;
272 interrupts = <
273 0xf0 0 0 0
274 0xf1 0 0 0
275 0xf2 0 0 0
276 0xf3 0 0 0
277 0xf4 0 0 0
278 0xf5 0 0 0
279 0xf6 0 0 0
280 0xf7 0 0 0>;
281 };
282
283 guts: global-utilities@e0000 {
284 compatible = "fsl,qoriq-device-config-1.0";
285 reg = <0xe0000 0xe00>;
286 fsl,has-rstcr;
287 #sleep-cells = <1>;
288 fsl,liodn-bits = <12>;
289 };
290
291 pins: global-utilities@e0e00 {
292 compatible = "fsl,qoriq-pin-control-1.0";
293 reg = <0xe0e00 0x200>;
294 #sleep-cells = <2>;
295 };
296
297 clockgen: global-utilities@e1000 {
298 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
299 reg = <0xe1000 0x1000>;
300 clock-frequency = <0>;
301 };
302
303 rcpm: global-utilities@e2000 {
304 compatible = "fsl,qoriq-rcpm-1.0";
305 reg = <0xe2000 0x1000>;
306 #sleep-cells = <1>;
307 };
308
309 sfp: sfp@e8000 {
310 compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
311 reg = <0xe8000 0x1000>;
312 };
313
314 serdes: serdes@ea000 {
315 compatible = "fsl,p2041-serdes";
316 reg = <0xea000 0x1000>;
317 };
318
319 dma0: dma@100300 {
320 #address-cells = <1>;
321 #size-cells = <1>;
322 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
323 reg = <0x100300 0x4>;
324 ranges = <0x0 0x100100 0x200>;
325 cell-index = <0>;
326 dma-channel@0 {
327 compatible = "fsl,p2041-dma-channel",
328 "fsl,eloplus-dma-channel";
329 reg = <0x0 0x80>;
330 cell-index = <0>;
331 interrupts = <28 2 0 0>;
332 };
333 dma-channel@80 {
334 compatible = "fsl,p2041-dma-channel",
335 "fsl,eloplus-dma-channel";
336 reg = <0x80 0x80>;
337 cell-index = <1>;
338 interrupts = <29 2 0 0>;
339 };
340 dma-channel@100 {
341 compatible = "fsl,p2041-dma-channel",
342 "fsl,eloplus-dma-channel";
343 reg = <0x100 0x80>;
344 cell-index = <2>;
345 interrupts = <30 2 0 0>;
346 };
347 dma-channel@180 {
348 compatible = "fsl,p2041-dma-channel",
349 "fsl,eloplus-dma-channel";
350 reg = <0x180 0x80>;
351 cell-index = <3>;
352 interrupts = <31 2 0 0>;
353 };
354 };
355
356 dma1: dma@101300 {
357 #address-cells = <1>;
358 #size-cells = <1>;
359 compatible = "fsl,p2041-dma", "fsl,eloplus-dma";
360 reg = <0x101300 0x4>;
361 ranges = <0x0 0x101100 0x200>;
362 cell-index = <1>;
363 dma-channel@0 {
364 compatible = "fsl,p2041-dma-channel",
365 "fsl,eloplus-dma-channel";
366 reg = <0x0 0x80>;
367 cell-index = <0>;
368 interrupts = <32 2 0 0>;
369 };
370 dma-channel@80 {
371 compatible = "fsl,p2041-dma-channel",
372 "fsl,eloplus-dma-channel";
373 reg = <0x80 0x80>;
374 cell-index = <1>;
375 interrupts = <33 2 0 0>;
376 };
377 dma-channel@100 {
378 compatible = "fsl,p2041-dma-channel",
379 "fsl,eloplus-dma-channel";
380 reg = <0x100 0x80>;
381 cell-index = <2>;
382 interrupts = <34 2 0 0>;
383 };
384 dma-channel@180 {
385 compatible = "fsl,p2041-dma-channel",
386 "fsl,eloplus-dma-channel";
387 reg = <0x180 0x80>;
388 cell-index = <3>;
389 interrupts = <35 2 0 0>;
390 };
391 };
392
393 spi@110000 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "fsl,p2041-espi", "fsl,mpc8536-espi";
397 reg = <0x110000 0x1000>;
398 interrupts = <53 0x2 0 0>;
399 fsl,espi-num-chipselects = <4>;
400 };
401
402 sdhc: sdhc@114000 {
403 compatible = "fsl,p2041-esdhc", "fsl,esdhc";
404 reg = <0x114000 0x1000>;
405 interrupts = <48 2 0 0>;
406 sdhci,auto-cmd12;
407 clock-frequency = <0>;
408 };
409
410 i2c@118000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 cell-index = <0>;
414 compatible = "fsl-i2c";
415 reg = <0x118000 0x100>;
416 interrupts = <38 2 0 0>;
417 dfsrr;
418 };
419
420 i2c@118100 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 cell-index = <1>;
424 compatible = "fsl-i2c";
425 reg = <0x118100 0x100>;
426 interrupts = <38 2 0 0>;
427 dfsrr;
428 };
429
430 i2c@119000 {
431 #address-cells = <1>;
432 #size-cells = <0>;
433 cell-index = <2>;
434 compatible = "fsl-i2c";
435 reg = <0x119000 0x100>;
436 interrupts = <39 2 0 0>;
437 dfsrr;
438 };
439
440 i2c@119100 {
441 #address-cells = <1>;
442 #size-cells = <0>;
443 cell-index = <3>;
444 compatible = "fsl-i2c";
445 reg = <0x119100 0x100>;
446 interrupts = <39 2 0 0>;
447 dfsrr;
448 };
449
450 serial0: serial@11c500 {
451 cell-index = <0>;
452 device_type = "serial";
453 compatible = "ns16550";
454 reg = <0x11c500 0x100>;
455 clock-frequency = <0>;
456 interrupts = <36 2 0 0>;
457 };
458
459 serial1: serial@11c600 {
460 cell-index = <1>;
461 device_type = "serial";
462 compatible = "ns16550";
463 reg = <0x11c600 0x100>;
464 clock-frequency = <0>;
465 interrupts = <36 2 0 0>;
466 };
467
468 serial2: serial@11d500 {
469 cell-index = <2>;
470 device_type = "serial";
471 compatible = "ns16550";
472 reg = <0x11d500 0x100>;
473 clock-frequency = <0>;
474 interrupts = <37 2 0 0>;
475 };
476
477 serial3: serial@11d600 {
478 cell-index = <3>;
479 device_type = "serial";
480 compatible = "ns16550";
481 reg = <0x11d600 0x100>;
482 clock-frequency = <0>;
483 interrupts = <37 2 0 0>;
484 };
485
486 gpio0: gpio@130000 {
487 compatible = "fsl,p2041-gpio", "fsl,qoriq-gpio";
488 reg = <0x130000 0x1000>;
489 interrupts = <55 2 0 0>;
490 #gpio-cells = <2>;
491 gpio-controller;
492 };
493
494 usb0: usb@210000 {
495 compatible = "fsl,p2041-usb2-mph",
496 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
497 reg = <0x210000 0x1000>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 interrupts = <44 0x2 0 0>;
501 phy_type = "utmi";
502 port0;
503 };
504
505 usb1: usb@211000 {
506 compatible = "fsl,p2041-usb2-dr",
507 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
508 reg = <0x211000 0x1000>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 interrupts = <45 0x2 0 0>;
512 phy_type = "utmi";
513 };
514
515 sata@220000 {
516 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
517 reg = <0x220000 0x1000>;
518 interrupts = <68 0x2 0 0>;
519 };
520
521 sata@221000 {
522 compatible = "fsl,p2041-sata", "fsl,pq-sata-v2";
523 reg = <0x221000 0x1000>;
524 interrupts = <69 0x2 0 0>;
525 };
526
527 crypto: crypto@300000 {
528 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 reg = <0x300000 0x10000>;
532 ranges = <0 0x300000 0x10000>;
533 interrupts = <92 2 0 0>;
534
535 sec_jr0: jr@1000 {
536 compatible = "fsl,sec-v4.2-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x1000 0x1000>;
539 interrupts = <88 2 0 0>;
540 };
541
542 sec_jr1: jr@2000 {
543 compatible = "fsl,sec-v4.2-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x2000 0x1000>;
546 interrupts = <89 2 0 0>;
547 };
548
549 sec_jr2: jr@3000 {
550 compatible = "fsl,sec-v4.2-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x3000 0x1000>;
553 interrupts = <90 2 0 0>;
554 };
555
556 sec_jr3: jr@4000 {
557 compatible = "fsl,sec-v4.2-job-ring",
558 "fsl,sec-v4.0-job-ring";
559 reg = <0x4000 0x1000>;
560 interrupts = <91 2 0 0>;
561 };
562
563 rtic@6000 {
564 compatible = "fsl,sec-v4.2-rtic",
565 "fsl,sec-v4.0-rtic";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 reg = <0x6000 0x100>;
569 ranges = <0x0 0x6100 0xe00>;
570
571 rtic_a: rtic-a@0 {
572 compatible = "fsl,sec-v4.2-rtic-memory",
573 "fsl,sec-v4.0-rtic-memory";
574 reg = <0x00 0x20 0x100 0x80>;
575 };
576
577 rtic_b: rtic-b@20 {
578 compatible = "fsl,sec-v4.2-rtic-memory",
579 "fsl,sec-v4.0-rtic-memory";
580 reg = <0x20 0x20 0x200 0x80>;
581 };
582
583 rtic_c: rtic-c@40 {
584 compatible = "fsl,sec-v4.2-rtic-memory",
585 "fsl,sec-v4.0-rtic-memory";
586 reg = <0x40 0x20 0x300 0x80>;
587 };
588
589 rtic_d: rtic-d@60 {
590 compatible = "fsl,sec-v4.2-rtic-memory",
591 "fsl,sec-v4.0-rtic-memory";
592 reg = <0x60 0x20 0x500 0x80>;
593 };
594 };
595 };
596
597 sec_mon: sec_mon@314000 {
598 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
599 reg = <0x314000 0x1000>;
600 interrupts = <93 2 0 0>;
601 };
602
603 };
604
605 localbus@ffe124000 {
606 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
607 interrupts = <25 2 0 0>;
608 #address-cells = <2>;
609 #size-cells = <1>;
610 };
611
612 pci0: pcie@ffe200000 {
613 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
614 device_type = "pci";
615 #size-cells = <2>;
616 #address-cells = <3>;
617 bus-range = <0x0 0xff>;
618 clock-frequency = <33333333>;
619 fsl,msi = <&msi0>;
620 interrupts = <16 2 1 15>;
621 pcie@0 {
622 reg = <0 0 0 0 0>;
623 #interrupt-cells = <1>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 device_type = "pci";
627 interrupts = <16 2 1 15>;
628 interrupt-map-mask = <0xf800 0 0 7>;
629 interrupt-map = <
630 /* IDSEL 0x0 */
631 0000 0 0 1 &mpic 40 1 0 0
632 0000 0 0 2 &mpic 1 1 0 0
633 0000 0 0 3 &mpic 2 1 0 0
634 0000 0 0 4 &mpic 3 1 0 0
635 >;
636 };
637 };
638
639 pci1: pcie@ffe201000 {
640 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
641 device_type = "pci";
642 #size-cells = <2>;
643 #address-cells = <3>;
644 bus-range = <0 0xff>;
645 clock-frequency = <33333333>;
646 fsl,msi = <&msi1>;
647 interrupts = <16 2 1 14>;
648 pcie@0 {
649 reg = <0 0 0 0 0>;
650 #interrupt-cells = <1>;
651 #size-cells = <2>;
652 #address-cells = <3>;
653 device_type = "pci";
654 interrupts = <16 2 1 14>;
655 interrupt-map-mask = <0xf800 0 0 7>;
656 interrupt-map = <
657 /* IDSEL 0x0 */
658 0000 0 0 1 &mpic 41 1 0 0
659 0000 0 0 2 &mpic 5 1 0 0
660 0000 0 0 3 &mpic 6 1 0 0
661 0000 0 0 4 &mpic 7 1 0 0
662 >;
663 };
664 };
665
666 pci2: pcie@ffe202000 {
667 compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
668 device_type = "pci";
669 #size-cells = <2>;
670 #address-cells = <3>;
671 bus-range = <0x0 0xff>;
672 clock-frequency = <33333333>;
673 fsl,msi = <&msi2>;
674 interrupts = <16 2 1 13>;
675 pcie@0 {
676 reg = <0 0 0 0 0>;
677 #interrupt-cells = <1>;
678 #size-cells = <2>;
679 #address-cells = <3>;
680 device_type = "pci";
681 interrupts = <16 2 1 13>;
682 interrupt-map-mask = <0xf800 0 0 7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0000 0 0 1 &mpic 42 1 0 0
686 0000 0 0 2 &mpic 9 1 0 0
687 0000 0 0 3 &mpic 10 1 0 0
688 0000 0 0 4 &mpic 11 1 0 0
689 >;
690 };
691 };
692};
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index bbd113b49a8f..f469145abaeb 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p3041si.dtsi" 35/include/ "fsl/p3041si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P3041DS"; 38 model = "fsl,P3041DS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -99,7 +101,18 @@
99 }; 101 };
100 }; 102 };
101 103
102 localbus@ffe124000 { 104 rio: rapidio@ffe0c0000 {
105 reg = <0xf 0xfe0c0000 0 0x11000>;
106
107 port1 {
108 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
109 };
110 port2 {
111 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
112 };
113 };
114
115 lbc: localbus@ffe124000 {
103 reg = <0xf 0xfe124000 0 0x1000>; 116 reg = <0xf 0xfe124000 0 0x1000>;
104 ranges = <0 0 0xf 0xe8000000 0x08000000 117 ranges = <0 0 0xf 0xe8000000 0x08000000
105 2 0 0xf 0xffa00000 0x00040000 118 2 0 0xf 0xffa00000 0x00040000
@@ -160,6 +173,7 @@
160 reg = <0xf 0xfe200000 0 0x1000>; 173 reg = <0xf 0xfe200000 0 0x1000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
176 fsl,msi = <&msi0>;
163 pcie@0 { 177 pcie@0 {
164 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
165 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -175,6 +189,7 @@
175 reg = <0xf 0xfe201000 0 0x1000>; 189 reg = <0xf 0xfe201000 0 0x1000>;
176 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 190 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
177 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 191 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
192 fsl,msi = <&msi1>;
178 pcie@0 { 193 pcie@0 {
179 ranges = <0x02000000 0 0xe0000000 194 ranges = <0x02000000 0 0xe0000000
180 0x02000000 0 0xe0000000 195 0x02000000 0 0xe0000000
@@ -190,6 +205,7 @@
190 reg = <0xf 0xfe202000 0 0x1000>; 205 reg = <0xf 0xfe202000 0 0x1000>;
191 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 206 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
192 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 207 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
208 fsl,msi = <&msi2>;
193 pcie@0 { 209 pcie@0 {
194 ranges = <0x02000000 0 0xe0000000 210 ranges = <0x02000000 0 0xe0000000
195 0x02000000 0 0xe0000000 211 0x02000000 0 0xe0000000
@@ -205,6 +221,7 @@
205 reg = <0xf 0xfe203000 0 0x1000>; 221 reg = <0xf 0xfe203000 0 0x1000>;
206 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 222 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
207 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 223 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
224 fsl,msi = <&msi2>;
208 pcie@0 { 225 pcie@0 {
209 ranges = <0x02000000 0 0xe0000000 226 ranges = <0x02000000 0 0xe0000000
210 0x02000000 0 0xe0000000 227 0x02000000 0 0xe0000000
@@ -216,3 +233,5 @@
216 }; 233 };
217 }; 234 };
218}; 235};
236
237/include/ "fsl/p3041si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3041si.dtsi b/arch/powerpc/boot/dts/p3041si.dtsi
deleted file mode 100644
index 87130b732bc7..000000000000
--- a/arch/powerpc/boot/dts/p3041si.dtsi
+++ /dev/null
@@ -1,729 +0,0 @@
1/*
2 * P3041 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3041";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74
75/*
76 rio0 = &rapidio0;
77 */
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: PowerPC,e500mc@0 {
85 device_type = "cpu";
86 reg = <0>;
87 next-level-cache = <&L2_0>;
88 L2_0: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu1: PowerPC,e500mc@1 {
93 device_type = "cpu";
94 reg = <1>;
95 next-level-cache = <&L2_1>;
96 L2_1: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 cpu2: PowerPC,e500mc@2 {
101 device_type = "cpu";
102 reg = <2>;
103 next-level-cache = <&L2_2>;
104 L2_2: l2-cache {
105 next-level-cache = <&cpc>;
106 };
107 };
108 cpu3: PowerPC,e500mc@3 {
109 device_type = "cpu";
110 reg = <3>;
111 next-level-cache = <&L2_3>;
112 L2_3: l2-cache {
113 next-level-cache = <&cpc>;
114 };
115 };
116 };
117
118 dcsr: dcsr@f00000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,dcsr", "simple-bus";
122
123 dcsr-epu@0 {
124 compatible = "fsl,dcsr-epu";
125 interrupts = <52 2 0 0
126 84 2 0 0
127 85 2 0 0>;
128 interrupt-parent = <&mpic>;
129 reg = <0x0 0x1000>;
130 };
131 dcsr-npc {
132 compatible = "fsl,dcsr-npc";
133 reg = <0x1000 0x1000 0x1000000 0x8000>;
134 };
135 dcsr-nxc@2000 {
136 compatible = "fsl,dcsr-nxc";
137 reg = <0x2000 0x1000>;
138 };
139 dcsr-corenet {
140 compatible = "fsl,dcsr-corenet";
141 reg = <0x8000 0x1000 0xB0000 0x1000>;
142 };
143 dcsr-dpaa@9000 {
144 compatible = "fsl,p43041-dcsr-dpaa", "fsl,dcsr-dpaa";
145 reg = <0x9000 0x1000>;
146 };
147 dcsr-ocn@11000 {
148 compatible = "fsl,p43041-dcsr-ocn", "fsl,dcsr-ocn";
149 reg = <0x11000 0x1000>;
150 };
151 dcsr-ddr@12000 {
152 compatible = "fsl,dcsr-ddr";
153 dev-handle = <&ddr>;
154 reg = <0x12000 0x1000>;
155 };
156 dcsr-nal@18000 {
157 compatible = "fsl,p43041-dcsr-nal", "fsl,dcsr-nal";
158 reg = <0x18000 0x1000>;
159 };
160 dcsr-rcpm@22000 {
161 compatible = "fsl,p43041-dcsr-rcpm", "fsl,dcsr-rcpm";
162 reg = <0x22000 0x1000>;
163 };
164 dcsr-cpu-sb-proxy@40000 {
165 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
166 cpu-handle = <&cpu0>;
167 reg = <0x40000 0x1000>;
168 };
169 dcsr-cpu-sb-proxy@41000 {
170 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
171 cpu-handle = <&cpu1>;
172 reg = <0x41000 0x1000>;
173 };
174 dcsr-cpu-sb-proxy@42000 {
175 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
176 cpu-handle = <&cpu2>;
177 reg = <0x42000 0x1000>;
178 };
179 dcsr-cpu-sb-proxy@43000 {
180 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
181 cpu-handle = <&cpu3>;
182 reg = <0x43000 0x1000>;
183 };
184 };
185
186 soc: soc@ffe000000 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 device_type = "soc";
190 compatible = "simple-bus";
191 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
192 reg = <0xf 0xfe000000 0 0x00001000>;
193
194 soc-sram-error {
195 compatible = "fsl,soc-sram-error";
196 interrupts = <16 2 1 29>;
197 };
198
199 corenet-law@0 {
200 compatible = "fsl,corenet-law";
201 reg = <0x0 0x1000>;
202 fsl,num-laws = <32>;
203 };
204
205 ddr: memory-controller@8000 {
206 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
207 reg = <0x8000 0x1000>;
208 interrupts = <16 2 1 23>;
209 };
210
211 cpc: l3-cache-controller@10000 {
212 compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
213 reg = <0x10000 0x1000>;
214 interrupts = <16 2 1 27>;
215 };
216
217 corenet-cf@18000 {
218 compatible = "fsl,corenet-cf";
219 reg = <0x18000 0x1000>;
220 interrupts = <16 2 1 31>;
221 fsl,ccf-num-csdids = <32>;
222 fsl,ccf-num-snoopids = <32>;
223 };
224
225 iommu@20000 {
226 compatible = "fsl,pamu-v1.0", "fsl,pamu";
227 reg = <0x20000 0x4000>;
228 interrupts = <
229 24 2 0 0
230 16 2 1 30>;
231 };
232
233 mpic: pic@40000 {
234 clock-frequency = <0>;
235 interrupt-controller;
236 #address-cells = <0>;
237 #interrupt-cells = <4>;
238 reg = <0x40000 0x40000>;
239 compatible = "fsl,mpic", "chrp,open-pic";
240 device_type = "open-pic";
241 };
242
243 msi0: msi@41600 {
244 compatible = "fsl,mpic-msi";
245 reg = <0x41600 0x200>;
246 msi-available-ranges = <0 0x100>;
247 interrupts = <
248 0xe0 0 0 0
249 0xe1 0 0 0
250 0xe2 0 0 0
251 0xe3 0 0 0
252 0xe4 0 0 0
253 0xe5 0 0 0
254 0xe6 0 0 0
255 0xe7 0 0 0>;
256 };
257
258 msi1: msi@41800 {
259 compatible = "fsl,mpic-msi";
260 reg = <0x41800 0x200>;
261 msi-available-ranges = <0 0x100>;
262 interrupts = <
263 0xe8 0 0 0
264 0xe9 0 0 0
265 0xea 0 0 0
266 0xeb 0 0 0
267 0xec 0 0 0
268 0xed 0 0 0
269 0xee 0 0 0
270 0xef 0 0 0>;
271 };
272
273 msi2: msi@41a00 {
274 compatible = "fsl,mpic-msi";
275 reg = <0x41a00 0x200>;
276 msi-available-ranges = <0 0x100>;
277 interrupts = <
278 0xf0 0 0 0
279 0xf1 0 0 0
280 0xf2 0 0 0
281 0xf3 0 0 0
282 0xf4 0 0 0
283 0xf5 0 0 0
284 0xf6 0 0 0
285 0xf7 0 0 0>;
286 };
287
288 guts: global-utilities@e0000 {
289 compatible = "fsl,qoriq-device-config-1.0";
290 reg = <0xe0000 0xe00>;
291 fsl,has-rstcr;
292 #sleep-cells = <1>;
293 fsl,liodn-bits = <12>;
294 };
295
296 pins: global-utilities@e0e00 {
297 compatible = "fsl,qoriq-pin-control-1.0";
298 reg = <0xe0e00 0x200>;
299 #sleep-cells = <2>;
300 };
301
302 clockgen: global-utilities@e1000 {
303 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
304 reg = <0xe1000 0x1000>;
305 clock-frequency = <0>;
306 };
307
308 rcpm: global-utilities@e2000 {
309 compatible = "fsl,qoriq-rcpm-1.0";
310 reg = <0xe2000 0x1000>;
311 #sleep-cells = <1>;
312 };
313
314 sfp: sfp@e8000 {
315 compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
316 reg = <0xe8000 0x1000>;
317 };
318
319 serdes: serdes@ea000 {
320 compatible = "fsl,p3041-serdes";
321 reg = <0xea000 0x1000>;
322 };
323
324 dma0: dma@100300 {
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
328 reg = <0x100300 0x4>;
329 ranges = <0x0 0x100100 0x200>;
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,p3041-dma-channel",
333 "fsl,eloplus-dma-channel";
334 reg = <0x0 0x80>;
335 cell-index = <0>;
336 interrupts = <28 2 0 0>;
337 };
338 dma-channel@80 {
339 compatible = "fsl,p3041-dma-channel",
340 "fsl,eloplus-dma-channel";
341 reg = <0x80 0x80>;
342 cell-index = <1>;
343 interrupts = <29 2 0 0>;
344 };
345 dma-channel@100 {
346 compatible = "fsl,p3041-dma-channel",
347 "fsl,eloplus-dma-channel";
348 reg = <0x100 0x80>;
349 cell-index = <2>;
350 interrupts = <30 2 0 0>;
351 };
352 dma-channel@180 {
353 compatible = "fsl,p3041-dma-channel",
354 "fsl,eloplus-dma-channel";
355 reg = <0x180 0x80>;
356 cell-index = <3>;
357 interrupts = <31 2 0 0>;
358 };
359 };
360
361 dma1: dma@101300 {
362 #address-cells = <1>;
363 #size-cells = <1>;
364 compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
365 reg = <0x101300 0x4>;
366 ranges = <0x0 0x101100 0x200>;
367 cell-index = <1>;
368 dma-channel@0 {
369 compatible = "fsl,p3041-dma-channel",
370 "fsl,eloplus-dma-channel";
371 reg = <0x0 0x80>;
372 cell-index = <0>;
373 interrupts = <32 2 0 0>;
374 };
375 dma-channel@80 {
376 compatible = "fsl,p3041-dma-channel",
377 "fsl,eloplus-dma-channel";
378 reg = <0x80 0x80>;
379 cell-index = <1>;
380 interrupts = <33 2 0 0>;
381 };
382 dma-channel@100 {
383 compatible = "fsl,p3041-dma-channel",
384 "fsl,eloplus-dma-channel";
385 reg = <0x100 0x80>;
386 cell-index = <2>;
387 interrupts = <34 2 0 0>;
388 };
389 dma-channel@180 {
390 compatible = "fsl,p3041-dma-channel",
391 "fsl,eloplus-dma-channel";
392 reg = <0x180 0x80>;
393 cell-index = <3>;
394 interrupts = <35 2 0 0>;
395 };
396 };
397
398 spi@110000 {
399 #address-cells = <1>;
400 #size-cells = <0>;
401 compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
402 reg = <0x110000 0x1000>;
403 interrupts = <53 0x2 0 0>;
404 fsl,espi-num-chipselects = <4>;
405 };
406
407 sdhc: sdhc@114000 {
408 compatible = "fsl,p3041-esdhc", "fsl,esdhc";
409 reg = <0x114000 0x1000>;
410 interrupts = <48 2 0 0>;
411 sdhci,auto-cmd12;
412 clock-frequency = <0>;
413 };
414
415 i2c@118000 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 cell-index = <0>;
419 compatible = "fsl-i2c";
420 reg = <0x118000 0x100>;
421 interrupts = <38 2 0 0>;
422 dfsrr;
423 };
424
425 i2c@118100 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 cell-index = <1>;
429 compatible = "fsl-i2c";
430 reg = <0x118100 0x100>;
431 interrupts = <38 2 0 0>;
432 dfsrr;
433 };
434
435 i2c@119000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 cell-index = <2>;
439 compatible = "fsl-i2c";
440 reg = <0x119000 0x100>;
441 interrupts = <39 2 0 0>;
442 dfsrr;
443 };
444
445 i2c@119100 {
446 #address-cells = <1>;
447 #size-cells = <0>;
448 cell-index = <3>;
449 compatible = "fsl-i2c";
450 reg = <0x119100 0x100>;
451 interrupts = <39 2 0 0>;
452 dfsrr;
453 };
454
455 serial0: serial@11c500 {
456 cell-index = <0>;
457 device_type = "serial";
458 compatible = "ns16550";
459 reg = <0x11c500 0x100>;
460 clock-frequency = <0>;
461 interrupts = <36 2 0 0>;
462 };
463
464 serial1: serial@11c600 {
465 cell-index = <1>;
466 device_type = "serial";
467 compatible = "ns16550";
468 reg = <0x11c600 0x100>;
469 clock-frequency = <0>;
470 interrupts = <36 2 0 0>;
471 };
472
473 serial2: serial@11d500 {
474 cell-index = <2>;
475 device_type = "serial";
476 compatible = "ns16550";
477 reg = <0x11d500 0x100>;
478 clock-frequency = <0>;
479 interrupts = <37 2 0 0>;
480 };
481
482 serial3: serial@11d600 {
483 cell-index = <3>;
484 device_type = "serial";
485 compatible = "ns16550";
486 reg = <0x11d600 0x100>;
487 clock-frequency = <0>;
488 interrupts = <37 2 0 0>;
489 };
490
491 gpio0: gpio@130000 {
492 compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
493 reg = <0x130000 0x1000>;
494 interrupts = <55 2 0 0>;
495 #gpio-cells = <2>;
496 gpio-controller;
497 };
498
499 usb0: usb@210000 {
500 compatible = "fsl,p3041-usb2-mph",
501 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
502 reg = <0x210000 0x1000>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 interrupts = <44 0x2 0 0>;
506 phy_type = "utmi";
507 port0;
508 };
509
510 usb1: usb@211000 {
511 compatible = "fsl,p3041-usb2-dr",
512 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
513 reg = <0x211000 0x1000>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 interrupts = <45 0x2 0 0>;
517 dr_mode = "host";
518 phy_type = "utmi";
519 };
520
521 sata@220000 {
522 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
523 reg = <0x220000 0x1000>;
524 interrupts = <68 0x2 0 0>;
525 };
526
527 sata@221000 {
528 compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
529 reg = <0x221000 0x1000>;
530 interrupts = <69 0x2 0 0>;
531 };
532
533 crypto: crypto@300000 {
534 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
535 #address-cells = <1>;
536 #size-cells = <1>;
537 reg = <0x300000 0x10000>;
538 ranges = <0 0x300000 0x10000>;
539 interrupts = <92 2 0 0>;
540
541 sec_jr0: jr@1000 {
542 compatible = "fsl,sec-v4.2-job-ring",
543 "fsl,sec-v4.0-job-ring";
544 reg = <0x1000 0x1000>;
545 interrupts = <88 2 0 0>;
546 };
547
548 sec_jr1: jr@2000 {
549 compatible = "fsl,sec-v4.2-job-ring",
550 "fsl,sec-v4.0-job-ring";
551 reg = <0x2000 0x1000>;
552 interrupts = <89 2 0 0>;
553 };
554
555 sec_jr2: jr@3000 {
556 compatible = "fsl,sec-v4.2-job-ring",
557 "fsl,sec-v4.0-job-ring";
558 reg = <0x3000 0x1000>;
559 interrupts = <90 2 0 0>;
560 };
561
562 sec_jr3: jr@4000 {
563 compatible = "fsl,sec-v4.2-job-ring",
564 "fsl,sec-v4.0-job-ring";
565 reg = <0x4000 0x1000>;
566 interrupts = <91 2 0 0>;
567 };
568
569 rtic@6000 {
570 compatible = "fsl,sec-v4.2-rtic",
571 "fsl,sec-v4.0-rtic";
572 #address-cells = <1>;
573 #size-cells = <1>;
574 reg = <0x6000 0x100>;
575 ranges = <0x0 0x6100 0xe00>;
576
577 rtic_a: rtic-a@0 {
578 compatible = "fsl,sec-v4.2-rtic-memory",
579 "fsl,sec-v4.0-rtic-memory";
580 reg = <0x00 0x20 0x100 0x80>;
581 };
582
583 rtic_b: rtic-b@20 {
584 compatible = "fsl,sec-v4.2-rtic-memory",
585 "fsl,sec-v4.0-rtic-memory";
586 reg = <0x20 0x20 0x200 0x80>;
587 };
588
589 rtic_c: rtic-c@40 {
590 compatible = "fsl,sec-v4.2-rtic-memory",
591 "fsl,sec-v4.0-rtic-memory";
592 reg = <0x40 0x20 0x300 0x80>;
593 };
594
595 rtic_d: rtic-d@60 {
596 compatible = "fsl,sec-v4.2-rtic-memory",
597 "fsl,sec-v4.0-rtic-memory";
598 reg = <0x60 0x20 0x500 0x80>;
599 };
600 };
601 };
602
603 sec_mon: sec_mon@314000 {
604 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
605 reg = <0x314000 0x1000>;
606 interrupts = <93 2 0 0>;
607 };
608 };
609
610/*
611 rapidio0: rapidio@ffe0c0000
612*/
613
614 localbus@ffe124000 {
615 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
616 interrupts = <25 2 0 0>;
617 #address-cells = <2>;
618 #size-cells = <1>;
619 };
620
621 pci0: pcie@ffe200000 {
622 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
623 device_type = "pci";
624 #size-cells = <2>;
625 #address-cells = <3>;
626 bus-range = <0x0 0xff>;
627 clock-frequency = <0x1fca055>;
628 fsl,msi = <&msi0>;
629 interrupts = <16 2 1 15>;
630
631 pcie@0 {
632 reg = <0 0 0 0 0>;
633 #interrupt-cells = <1>;
634 #size-cells = <2>;
635 #address-cells = <3>;
636 device_type = "pci";
637 interrupts = <16 2 1 15>;
638 interrupt-map-mask = <0xf800 0 0 7>;
639 interrupt-map = <
640 /* IDSEL 0x0 */
641 0000 0 0 1 &mpic 40 1 0 0
642 0000 0 0 2 &mpic 1 1 0 0
643 0000 0 0 3 &mpic 2 1 0 0
644 0000 0 0 4 &mpic 3 1 0 0
645 >;
646 };
647 };
648
649 pci1: pcie@ffe201000 {
650 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
651 device_type = "pci";
652 #size-cells = <2>;
653 #address-cells = <3>;
654 bus-range = <0 0xff>;
655 clock-frequency = <0x1fca055>;
656 fsl,msi = <&msi1>;
657 interrupts = <16 2 1 14>;
658 pcie@0 {
659 reg = <0 0 0 0 0>;
660 #interrupt-cells = <1>;
661 #size-cells = <2>;
662 #address-cells = <3>;
663 device_type = "pci";
664 interrupts = <16 2 1 14>;
665 interrupt-map-mask = <0xf800 0 0 7>;
666 interrupt-map = <
667 /* IDSEL 0x0 */
668 0000 0 0 1 &mpic 41 1 0 0
669 0000 0 0 2 &mpic 5 1 0 0
670 0000 0 0 3 &mpic 6 1 0 0
671 0000 0 0 4 &mpic 7 1 0 0
672 >;
673 };
674 };
675
676 pci2: pcie@ffe202000 {
677 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
678 device_type = "pci";
679 #size-cells = <2>;
680 #address-cells = <3>;
681 bus-range = <0x0 0xff>;
682 clock-frequency = <0x1fca055>;
683 fsl,msi = <&msi2>;
684 interrupts = <16 2 1 13>;
685 pcie@0 {
686 reg = <0 0 0 0 0>;
687 #interrupt-cells = <1>;
688 #size-cells = <2>;
689 #address-cells = <3>;
690 device_type = "pci";
691 interrupts = <16 2 1 13>;
692 interrupt-map-mask = <0xf800 0 0 7>;
693 interrupt-map = <
694 /* IDSEL 0x0 */
695 0000 0 0 1 &mpic 42 1 0 0
696 0000 0 0 2 &mpic 9 1 0 0
697 0000 0 0 3 &mpic 10 1 0 0
698 0000 0 0 4 &mpic 11 1 0 0
699 >;
700 };
701 };
702
703 pci3: pcie@ffe203000 {
704 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
705 device_type = "pci";
706 #size-cells = <2>;
707 #address-cells = <3>;
708 bus-range = <0x0 0xff>;
709 clock-frequency = <0x1fca055>;
710 fsl,msi = <&msi2>;
711 interrupts = <16 2 1 12>;
712 pcie@0 {
713 reg = <0 0 0 0 0>;
714 #interrupt-cells = <1>;
715 #size-cells = <2>;
716 #address-cells = <3>;
717 device_type = "pci";
718 interrupts = <16 2 1 12>;
719 interrupt-map-mask = <0xf800 0 0 7>;
720 interrupt-map = <
721 /* IDSEL 0x0 */
722 0000 0 0 1 &mpic 43 1 0 0
723 0000 0 0 2 &mpic 0 1 0 0
724 0000 0 0 3 &mpic 4 1 0 0
725 0000 0 0 4 &mpic 8 1 0 0
726 >;
727 };
728 };
729};
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
index 08b9193213e7..529042e4b9a2 100644
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ b/arch/powerpc/boot/dts/p3060qds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p3060si.dtsi" 35/include/ "fsl/p3060si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P3060QDS"; 38 model = "fsl,P3060QDS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -138,7 +140,7 @@
138 }; 140 };
139 }; 141 };
140 142
141 rapidio@ffe0c0000 { 143 rio: rapidio@ffe0c0000 {
142 reg = <0xf 0xfe0c0000 0 0x11000>; 144 reg = <0xf 0xfe0c0000 0 0x11000>;
143 145
144 port1 { 146 port1 {
@@ -149,7 +151,7 @@
149 }; 151 };
150 }; 152 };
151 153
152 localbus@ffe124000 { 154 lbc: localbus@ffe124000 {
153 reg = <0xf 0xfe124000 0 0x1000>; 155 reg = <0xf 0xfe124000 0 0x1000>;
154 ranges = <0 0 0xf 0xe8000000 0x08000000 156 ranges = <0 0 0xf 0xe8000000 0x08000000
155 2 0 0xf 0xffa00000 0x00040000 157 2 0 0xf 0xffa00000 0x00040000
@@ -210,6 +212,7 @@
210 reg = <0xf 0xfe200000 0 0x1000>; 212 reg = <0xf 0xfe200000 0 0x1000>;
211 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 213 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
212 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 214 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
215 fsl,msi = <&msi0>;
213 pcie@0 { 216 pcie@0 {
214 ranges = <0x02000000 0 0xe0000000 217 ranges = <0x02000000 0 0xe0000000
215 0x02000000 0 0xe0000000 218 0x02000000 0 0xe0000000
@@ -225,6 +228,7 @@
225 reg = <0xf 0xfe201000 0 0x1000>; 228 reg = <0xf 0xfe201000 0 0x1000>;
226 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 229 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
227 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 230 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
231 fsl,msi = <&msi1>;
228 pcie@0 { 232 pcie@0 {
229 ranges = <0x02000000 0 0xe0000000 233 ranges = <0x02000000 0 0xe0000000
230 0x02000000 0 0xe0000000 234 0x02000000 0 0xe0000000
@@ -236,3 +240,5 @@
236 }; 240 };
237 }; 241 };
238}; 242};
243
244/include/ "fsl/p3060si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p3060si.dtsi b/arch/powerpc/boot/dts/p3060si.dtsi
deleted file mode 100644
index 68947e157bbc..000000000000
--- a/arch/powerpc/boot/dts/p3060si.dtsi
+++ /dev/null
@@ -1,719 +0,0 @@
1/*
2 * P3060 Silicon Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P3060";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 usb0 = &usb0;
54 usb1 = &usb1;
55 dma0 = &dma0;
56 dma1 = &dma1;
57 msi0 = &msi0;
58 msi1 = &msi1;
59 msi2 = &msi2;
60
61 crypto = &crypto;
62 sec_jr0 = &sec_jr0;
63 sec_jr1 = &sec_jr1;
64 sec_jr2 = &sec_jr2;
65 sec_jr3 = &sec_jr3;
66 rtic_a = &rtic_a;
67 rtic_b = &rtic_b;
68 rtic_c = &rtic_c;
69 rtic_d = &rtic_d;
70 sec_mon = &sec_mon;
71 };
72
73 cpus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76
77 cpu0: PowerPC,e500mc@0 {
78 device_type = "cpu";
79 reg = <0>;
80 next-level-cache = <&L2_0>;
81 L2_0: l2-cache {
82 next-level-cache = <&cpc>;
83 };
84 };
85 cpu1: PowerPC,e500mc@1 {
86 device_type = "cpu";
87 reg = <1>;
88 next-level-cache = <&L2_1>;
89 L2_1: l2-cache {
90 next-level-cache = <&cpc>;
91 };
92 };
93 cpu4: PowerPC,e500mc@4 {
94 device_type = "cpu";
95 reg = <4>;
96 next-level-cache = <&L2_4>;
97 L2_4: l2-cache {
98 next-level-cache = <&cpc>;
99 };
100 };
101 cpu5: PowerPC,e500mc@5 {
102 device_type = "cpu";
103 reg = <5>;
104 next-level-cache = <&L2_5>;
105 L2_5: l2-cache {
106 next-level-cache = <&cpc>;
107 };
108 };
109 cpu6: PowerPC,e500mc@6 {
110 device_type = "cpu";
111 reg = <6>;
112 next-level-cache = <&L2_6>;
113 L2_6: l2-cache {
114 next-level-cache = <&cpc>;
115 };
116 };
117 cpu7: PowerPC,e500mc@7 {
118 device_type = "cpu";
119 reg = <7>;
120 next-level-cache = <&L2_7>;
121 L2_7: l2-cache {
122 next-level-cache = <&cpc>;
123 };
124 };
125 };
126
127 dcsr: dcsr@f00000000 {
128 #address-cells = <1>;
129 #size-cells = <1>;
130 compatible = "fsl,dcsr", "simple-bus";
131
132 dcsr-epu@0 {
133 compatible = "fsl,dcsr-epu";
134 interrupts = <52 2 0 0
135 84 2 0 0
136 85 2 0 0>;
137 interrupt-parent = <&mpic>;
138 reg = <0x0 0x1000>;
139 };
140 dcsr-npc {
141 compatible = "fsl,dcsr-npc";
142 reg = <0x1000 0x1000 0x1000000 0x8000>;
143 };
144 dcsr-nxc@2000 {
145 compatible = "fsl,dcsr-nxc";
146 reg = <0x2000 0x1000>;
147 };
148 dcsr-corenet {
149 compatible = "fsl,dcsr-corenet";
150 reg = <0x8000 0x1000 0xB0000 0x1000>;
151 };
152 dcsr-dpaa@9000 {
153 compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
154 reg = <0x9000 0x1000>;
155 };
156 dcsr-ocn@11000 {
157 compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
158 reg = <0x11000 0x1000>;
159 };
160 dcsr-ddr@12000 {
161 compatible = "fsl,dcsr-ddr";
162 dev-handle = <&ddr>;
163 reg = <0x12000 0x1000>;
164 };
165 dcsr-nal@18000 {
166 compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
167 reg = <0x18000 0x1000>;
168 };
169 dcsr-rcpm@22000 {
170 compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
171 reg = <0x22000 0x1000>;
172 };
173 dcsr-cpu-sb-proxy@40000 {
174 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
175 cpu-handle = <&cpu0>;
176 reg = <0x40000 0x1000>;
177 };
178 dcsr-cpu-sb-proxy@41000 {
179 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
180 cpu-handle = <&cpu1>;
181 reg = <0x41000 0x1000>;
182 };
183 dcsr-cpu-sb-proxy@44000 {
184 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
185 cpu-handle = <&cpu4>;
186 reg = <0x44000 0x1000>;
187 };
188 dcsr-cpu-sb-proxy@45000 {
189 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
190 cpu-handle = <&cpu5>;
191 reg = <0x45000 0x1000>;
192 };
193 dcsr-cpu-sb-proxy@46000 {
194 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
195 cpu-handle = <&cpu6>;
196 reg = <0x46000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@47000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu7>;
201 reg = <0x47000 0x1000>;
202 };
203 };
204
205 soc: soc@ffe000000 {
206 #address-cells = <1>;
207 #size-cells = <1>;
208 device_type = "soc";
209 compatible = "simple-bus";
210 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
211 reg = <0xf 0xfe000000 0 0x00001000>;
212
213 soc-sram-error {
214 compatible = "fsl,soc-sram-error";
215 interrupts = <16 2 1 29>;
216 };
217
218 corenet-law@0 {
219 compatible = "fsl,corenet-law";
220 reg = <0x0 0x1000>;
221 fsl,num-laws = <32>;
222 };
223
224 ddr: memory-controller@8000 {
225 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
226 reg = <0x8000 0x1000>;
227 interrupts = <16 2 1 23>;
228 };
229
230 cpc: l3-cache-controller@10000 {
231 compatible = "fsl,p3060-l3-cache-controller", "cache";
232 reg = <0x10000 0x1000
233 0x11000 0x1000>;
234 interrupts = <16 2 1 27>;
235 };
236
237 corenet-cf@18000 {
238 compatible = "fsl,corenet-cf";
239 reg = <0x18000 0x1000>;
240 interrupts = <16 2 1 31>;
241 fsl,ccf-num-csdids = <32>;
242 fsl,ccf-num-snoopids = <32>;
243 };
244
245 iommu@20000 {
246 compatible = "fsl,pamu-v1.0", "fsl,pamu";
247 reg = <0x20000 0x5000>;
248 interrupts = <
249 24 2 0 0
250 16 2 1 30>;
251 };
252
253 mpic: pic@40000 {
254 clock-frequency = <0>;
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <4>;
258 reg = <0x40000 0x40000>;
259 compatible = "fsl,mpic", "chrp,open-pic";
260 device_type = "open-pic";
261 };
262
263 msi0: msi@41600 {
264 compatible = "fsl,mpic-msi";
265 reg = <0x41600 0x200>;
266 msi-available-ranges = <0 0x100>;
267 interrupts = <
268 0xe0 0 0 0
269 0xe1 0 0 0
270 0xe2 0 0 0
271 0xe3 0 0 0
272 0xe4 0 0 0
273 0xe5 0 0 0
274 0xe6 0 0 0
275 0xe7 0 0 0>;
276 };
277
278 msi1: msi@41800 {
279 compatible = "fsl,mpic-msi";
280 reg = <0x41800 0x200>;
281 msi-available-ranges = <0 0x100>;
282 interrupts = <
283 0xe8 0 0 0
284 0xe9 0 0 0
285 0xea 0 0 0
286 0xeb 0 0 0
287 0xec 0 0 0
288 0xed 0 0 0
289 0xee 0 0 0
290 0xef 0 0 0>;
291 };
292
293 msi2: msi@41a00 {
294 compatible = "fsl,mpic-msi";
295 reg = <0x41a00 0x200>;
296 msi-available-ranges = <0 0x100>;
297 interrupts = <
298 0xf0 0 0 0
299 0xf1 0 0 0
300 0xf2 0 0 0
301 0xf3 0 0 0
302 0xf4 0 0 0
303 0xf5 0 0 0
304 0xf6 0 0 0
305 0xf7 0 0 0>;
306 };
307
308 rmu: rmu@d3000 {
309 #address-cells = <1>;
310 #size-cells = <1>;
311 compatible = "fsl,srio-rmu";
312 reg = <0xd3000 0x500>;
313 ranges = <0x0 0xd3000 0x500>;
314
315 message-unit@0 {
316 compatible = "fsl,srio-msg-unit";
317 reg = <0x0 0x100>;
318 interrupts = <
319 60 2 0 0 /* msg1_tx_irq */
320 61 2 0 0>;/* msg1_rx_irq */
321 };
322 message-unit@100 {
323 compatible = "fsl,srio-msg-unit";
324 reg = <0x100 0x100>;
325 interrupts = <
326 62 2 0 0 /* msg2_tx_irq */
327 63 2 0 0>;/* msg2_rx_irq */
328 };
329 doorbell-unit@400 {
330 compatible = "fsl,srio-dbell-unit";
331 reg = <0x400 0x80>;
332 interrupts = <
333 56 2 0 0 /* bell_outb_irq */
334 57 2 0 0>;/* bell_inb_irq */
335 };
336 port-write-unit@4e0 {
337 compatible = "fsl,srio-port-write-unit";
338 reg = <0x4e0 0x20>;
339 interrupts = <16 2 1 11>;
340 };
341 };
342
343 guts: global-utilities@e0000 {
344 compatible = "fsl,qoriq-device-config-1.0";
345 reg = <0xe0000 0xe00>;
346 fsl,has-rstcr;
347 #sleep-cells = <1>;
348 fsl,liodn-bits = <12>;
349 };
350
351 pins: global-utilities@e0e00 {
352 compatible = "fsl,qoriq-pin-control-1.0";
353 reg = <0xe0e00 0x200>;
354 #sleep-cells = <2>;
355 };
356
357 clockgen: global-utilities@e1000 {
358 compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
359 reg = <0xe1000 0x1000>;
360 clock-frequency = <0>;
361 };
362
363 rcpm: global-utilities@e2000 {
364 compatible = "fsl,qoriq-rcpm-1.0";
365 reg = <0xe2000 0x1000>;
366 #sleep-cells = <1>;
367 };
368
369 sfp: sfp@e8000 {
370 compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
371 reg = <0xe8000 0x1000>;
372 };
373
374 serdes: serdes@ea000 {
375 compatible = "fsl,p3060-serdes";
376 reg = <0xea000 0x1000>;
377 };
378
379 dma0: dma@100300 {
380 #address-cells = <1>;
381 #size-cells = <1>;
382 compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
383 reg = <0x100300 0x4>;
384 ranges = <0x0 0x100100 0x200>;
385 cell-index = <0>;
386 dma-channel@0 {
387 compatible = "fsl,p3060-dma-channel",
388 "fsl,eloplus-dma-channel";
389 reg = <0x0 0x80>;
390 cell-index = <0>;
391 interrupts = <28 2 0 0>;
392 };
393 dma-channel@80 {
394 compatible = "fsl,p3060-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x80 0x80>;
397 cell-index = <1>;
398 interrupts = <29 2 0 0>;
399 };
400 dma-channel@100 {
401 compatible = "fsl,p3060-dma-channel",
402 "fsl,eloplus-dma-channel";
403 reg = <0x100 0x80>;
404 cell-index = <2>;
405 interrupts = <30 2 0 0>;
406 };
407 dma-channel@180 {
408 compatible = "fsl,p3060-dma-channel",
409 "fsl,eloplus-dma-channel";
410 reg = <0x180 0x80>;
411 cell-index = <3>;
412 interrupts = <31 2 0 0>;
413 };
414 };
415
416 dma1: dma@101300 {
417 #address-cells = <1>;
418 #size-cells = <1>;
419 compatible = "fsl,p3060-dma", "fsl,eloplus-dma";
420 reg = <0x101300 0x4>;
421 ranges = <0x0 0x101100 0x200>;
422 cell-index = <1>;
423 dma-channel@0 {
424 compatible = "fsl,p3060-dma-channel",
425 "fsl,eloplus-dma-channel";
426 reg = <0x0 0x80>;
427 cell-index = <0>;
428 interrupts = <32 2 0 0>;
429 };
430 dma-channel@80 {
431 compatible = "fsl,p3060-dma-channel",
432 "fsl,eloplus-dma-channel";
433 reg = <0x80 0x80>;
434 cell-index = <1>;
435 interrupts = <33 2 0 0>;
436 };
437 dma-channel@100 {
438 compatible = "fsl,p3060-dma-channel",
439 "fsl,eloplus-dma-channel";
440 reg = <0x100 0x80>;
441 cell-index = <2>;
442 interrupts = <34 2 0 0>;
443 };
444 dma-channel@180 {
445 compatible = "fsl,p3060-dma-channel",
446 "fsl,eloplus-dma-channel";
447 reg = <0x180 0x80>;
448 cell-index = <3>;
449 interrupts = <35 2 0 0>;
450 };
451 };
452
453 spi@110000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "fsl,p3060-espi", "fsl,mpc8536-espi";
457 reg = <0x110000 0x1000>;
458 interrupts = <53 0x2 0 0>;
459 fsl,espi-num-chipselects = <4>;
460 };
461
462 i2c@118000 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 cell-index = <0>;
466 compatible = "fsl-i2c";
467 reg = <0x118000 0x100>;
468 interrupts = <38 2 0 0>;
469 dfsrr;
470 };
471
472 i2c@118100 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 cell-index = <1>;
476 compatible = "fsl-i2c";
477 reg = <0x118100 0x100>;
478 interrupts = <38 2 0 0>;
479 dfsrr;
480 };
481
482 i2c@119000 {
483 #address-cells = <1>;
484 #size-cells = <0>;
485 cell-index = <2>;
486 compatible = "fsl-i2c";
487 reg = <0x119000 0x100>;
488 interrupts = <39 2 0 0>;
489 dfsrr;
490 };
491
492 i2c@119100 {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 cell-index = <3>;
496 compatible = "fsl-i2c";
497 reg = <0x119100 0x100>;
498 interrupts = <39 2 0 0>;
499 dfsrr;
500 };
501
502 serial0: serial@11c500 {
503 cell-index = <0>;
504 device_type = "serial";
505 compatible = "ns16550";
506 reg = <0x11c500 0x100>;
507 clock-frequency = <0>;
508 interrupts = <36 2 0 0>;
509 };
510
511 serial1: serial@11c600 {
512 cell-index = <1>;
513 device_type = "serial";
514 compatible = "ns16550";
515 reg = <0x11c600 0x100>;
516 clock-frequency = <0>;
517 interrupts = <36 2 0 0>;
518 };
519
520 serial2: serial@11d500 {
521 cell-index = <2>;
522 device_type = "serial";
523 compatible = "ns16550";
524 reg = <0x11d500 0x100>;
525 clock-frequency = <0>;
526 interrupts = <37 2 0 0>;
527 };
528
529 serial3: serial@11d600 {
530 cell-index = <3>;
531 device_type = "serial";
532 compatible = "ns16550";
533 reg = <0x11d600 0x100>;
534 clock-frequency = <0>;
535 interrupts = <37 2 0 0>;
536 };
537
538 gpio0: gpio@130000 {
539 compatible = "fsl,p3060-gpio", "fsl,qoriq-gpio";
540 reg = <0x130000 0x1000>;
541 interrupts = <55 2 0 0>;
542 #gpio-cells = <2>;
543 gpio-controller;
544 };
545
546 usb0: usb@210000 {
547 compatible = "fsl,p3060-usb2-mph",
548 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
549 reg = <0x210000 0x1000>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 interrupts = <44 0x2 0 0>;
553 };
554
555 usb1: usb@211000 {
556 compatible = "fsl,p3060-usb2-dr",
557 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
558 reg = <0x211000 0x1000>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 interrupts = <45 0x2 0 0>;
562 };
563
564 crypto: crypto@300000 {
565 compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 reg = <0x300000 0x10000>;
569 ranges = <0 0x300000 0x10000>;
570 interrupt-parent = <&mpic>;
571 interrupts = <92 2 0 0>;
572
573 sec_jr0: jr@1000 {
574 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
575 reg = <0x1000 0x1000>;
576 interrupt-parent = <&mpic>;
577 interrupts = <88 2 0 0>;
578 };
579
580 sec_jr1: jr@2000 {
581 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
582 reg = <0x2000 0x1000>;
583 interrupt-parent = <&mpic>;
584 interrupts = <89 2 0 0>;
585 };
586
587 sec_jr2: jr@3000 {
588 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
589 reg = <0x3000 0x1000>;
590 interrupt-parent = <&mpic>;
591 interrupts = <90 2 0 0>;
592 };
593
594 sec_jr3: jr@4000 {
595 compatible = "fsl,sec-v4.1-job-ring", "fsl,sec-v4.0-job-ring";
596 reg = <0x4000 0x1000>;
597 interrupt-parent = <&mpic>;
598 interrupts = <91 2 0 0>;
599 };
600
601 rtic@6000 {
602 compatible = "fsl,sec-v4.1-rtic", "fsl,sec-v4.0-rtic";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 reg = <0x6000 0x100>;
606 ranges = <0x0 0x6100 0xe00>;
607
608 rtic_a: rtic-a@0 {
609 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
610 reg = <0x00 0x20 0x100 0x80>;
611 };
612
613 rtic_b: rtic-b@20 {
614 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
615 reg = <0x20 0x20 0x200 0x80>;
616 };
617
618 rtic_c: rtic-c@40 {
619 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
620 reg = <0x40 0x20 0x300 0x80>;
621 };
622
623 rtic_d: rtic-d@60 {
624 compatible = "fsl,sec-v4.1-rtic-memory", "fsl,sec-v4.0-rtic-memory";
625 reg = <0x60 0x20 0x500 0x80>;
626 };
627 };
628 };
629
630 sec_mon: sec_mon@314000 {
631 compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
632 reg = <0x314000 0x1000>;
633 interrupt-parent = <&mpic>;
634 interrupts = <93 2 0 0>;
635 };
636 };
637
638 rapidio@ffe0c0000 {
639 compatible = "fsl,srio";
640 interrupts = <16 2 1 11>;
641 #address-cells = <2>;
642 #size-cells = <2>;
643 fsl,srio-rmu-handle = <&rmu>;
644 ranges;
645
646 port1 {
647 #address-cells = <2>;
648 #size-cells = <2>;
649 cell-index = <1>;
650 };
651
652 port2 {
653 #address-cells = <2>;
654 #size-cells = <2>;
655 cell-index = <2>;
656 };
657 };
658
659 localbus@ffe124000 {
660 compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
661 interrupts = <25 2 0 0>;
662 #address-cells = <2>;
663 #size-cells = <1>;
664 };
665
666 pci0: pcie@ffe200000 {
667 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
668 device_type = "pci";
669 #size-cells = <2>;
670 #address-cells = <3>;
671 bus-range = <0x0 0xff>;
672 clock-frequency = <33333333>;
673 fsl,msi = <&msi0>;
674 interrupts = <16 2 1 15>;
675 pcie@0 {
676 reg = <0 0 0 0 0>;
677 #interrupt-cells = <1>;
678 #size-cells = <2>;
679 #address-cells = <3>;
680 device_type = "pci";
681 interrupts = <16 2 1 15>;
682 interrupt-map-mask = <0xf800 0 0 7>;
683 interrupt-map = <
684 /* IDSEL 0x0 */
685 0000 0 0 1 &mpic 40 1 0 0
686 0000 0 0 2 &mpic 1 1 0 0
687 0000 0 0 3 &mpic 2 1 0 0
688 0000 0 0 4 &mpic 3 1 0 0
689 >;
690 };
691 };
692
693 pci1: pcie@ffe201000 {
694 compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
695 device_type = "pci";
696 #size-cells = <2>;
697 #address-cells = <3>;
698 bus-range = <0 0xff>;
699 clock-frequency = <33333333>;
700 fsl,msi = <&msi1>;
701 interrupts = <16 2 1 14>;
702 pcie@0 {
703 reg = <0 0 0 0 0>;
704 #interrupt-cells = <1>;
705 #size-cells = <2>;
706 #address-cells = <3>;
707 device_type = "pci";
708 interrupts = <16 2 1 14>;
709 interrupt-map-mask = <0xf800 0 0 7>;
710 interrupt-map = <
711 /* IDSEL 0x0 */
712 0000 0 0 1 &mpic 41 1 0 0
713 0000 0 0 2 &mpic 5 1 0 0
714 0000 0 0 3 &mpic 6 1 0 0
715 0000 0 0 4 &mpic 7 1 0 0
716 >;
717 };
718 };
719};
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index c7916dc28014..6d60e54e50a0 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p4080si.dtsi" 35/include/ "fsl/p4080si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P4080DS"; 38 model = "fsl,P4080DS";
@@ -50,6 +50,9 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
55
53 spi@110000 { 56 spi@110000 {
54 flash@0 { 57 flash@0 {
55 #address-cells = <1>; 58 #address-cells = <1>;
@@ -105,12 +108,18 @@
105 }; 108 };
106 }; 109 };
107 110
108 rapidio0: rapidio@ffe0c0000 { 111 rio: rapidio@ffe0c0000 {
109 reg = <0xf 0xfe0c0000 0 0x20000>; 112 reg = <0xf 0xfe0c0000 0 0x11000>;
110 ranges = <0 0 0xc 0x20000000 0 0x01000000>; 113
114 port1 {
115 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
116 };
117 port2 {
118 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
119 };
111 }; 120 };
112 121
113 localbus@ffe124000 { 122 lbc: localbus@ffe124000 {
114 reg = <0xf 0xfe124000 0 0x1000>; 123 reg = <0xf 0xfe124000 0 0x1000>;
115 ranges = <0 0 0xf 0xe8000000 0x08000000 124 ranges = <0 0 0xf 0xe8000000 0x08000000
116 3 0 0xf 0xffdf0000 0x00008000>; 125 3 0 0xf 0xffdf0000 0x00008000>;
@@ -132,6 +141,7 @@
132 reg = <0xf 0xfe200000 0 0x1000>; 141 reg = <0xf 0xfe200000 0 0x1000>;
133 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 142 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
134 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 143 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
144 fsl,msi = <&msi0>;
135 pcie@0 { 145 pcie@0 {
136 ranges = <0x02000000 0 0xe0000000 146 ranges = <0x02000000 0 0xe0000000
137 0x02000000 0 0xe0000000 147 0x02000000 0 0xe0000000
@@ -147,6 +157,7 @@
147 reg = <0xf 0xfe201000 0 0x1000>; 157 reg = <0xf 0xfe201000 0 0x1000>;
148 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 158 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
149 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 159 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
160 fsl,msi = <&msi1>;
150 pcie@0 { 161 pcie@0 {
151 ranges = <0x02000000 0 0xe0000000 162 ranges = <0x02000000 0 0xe0000000
152 0x02000000 0 0xe0000000 163 0x02000000 0 0xe0000000
@@ -162,6 +173,7 @@
162 reg = <0xf 0xfe202000 0 0x1000>; 173 reg = <0xf 0xfe202000 0 0x1000>;
163 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
164 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
176 fsl,msi = <&msi2>;
165 pcie@0 { 177 pcie@0 {
166 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
167 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -174,3 +186,5 @@
174 }; 186 };
175 187
176}; 188};
189
190/include/ "fsl/p4080si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p4080si.dtsi b/arch/powerpc/boot/dts/p4080si.dtsi
deleted file mode 100644
index f20c01ab2473..000000000000
--- a/arch/powerpc/boot/dts/p4080si.dtsi
+++ /dev/null
@@ -1,755 +0,0 @@
1/*
2 * P4080 Silicon Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P4080";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 usb0 = &usb0;
55 usb1 = &usb1;
56 dma0 = &dma0;
57 dma1 = &dma1;
58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
62
63 crypto = &crypto;
64 sec_jr0 = &sec_jr0;
65 sec_jr1 = &sec_jr1;
66 sec_jr2 = &sec_jr2;
67 sec_jr3 = &sec_jr3;
68 rtic_a = &rtic_a;
69 rtic_b = &rtic_b;
70 rtic_c = &rtic_c;
71 rtic_d = &rtic_d;
72 sec_mon = &sec_mon;
73
74 rio0 = &rapidio0;
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu0: PowerPC,e500mc@0 {
82 device_type = "cpu";
83 reg = <0>;
84 next-level-cache = <&L2_0>;
85 L2_0: l2-cache {
86 next-level-cache = <&cpc>;
87 };
88 };
89 cpu1: PowerPC,e500mc@1 {
90 device_type = "cpu";
91 reg = <1>;
92 next-level-cache = <&L2_1>;
93 L2_1: l2-cache {
94 next-level-cache = <&cpc>;
95 };
96 };
97 cpu2: PowerPC,e500mc@2 {
98 device_type = "cpu";
99 reg = <2>;
100 next-level-cache = <&L2_2>;
101 L2_2: l2-cache {
102 next-level-cache = <&cpc>;
103 };
104 };
105 cpu3: PowerPC,e500mc@3 {
106 device_type = "cpu";
107 reg = <3>;
108 next-level-cache = <&L2_3>;
109 L2_3: l2-cache {
110 next-level-cache = <&cpc>;
111 };
112 };
113 cpu4: PowerPC,e500mc@4 {
114 device_type = "cpu";
115 reg = <4>;
116 next-level-cache = <&L2_4>;
117 L2_4: l2-cache {
118 next-level-cache = <&cpc>;
119 };
120 };
121 cpu5: PowerPC,e500mc@5 {
122 device_type = "cpu";
123 reg = <5>;
124 next-level-cache = <&L2_5>;
125 L2_5: l2-cache {
126 next-level-cache = <&cpc>;
127 };
128 };
129 cpu6: PowerPC,e500mc@6 {
130 device_type = "cpu";
131 reg = <6>;
132 next-level-cache = <&L2_6>;
133 L2_6: l2-cache {
134 next-level-cache = <&cpc>;
135 };
136 };
137 cpu7: PowerPC,e500mc@7 {
138 device_type = "cpu";
139 reg = <7>;
140 next-level-cache = <&L2_7>;
141 L2_7: l2-cache {
142 next-level-cache = <&cpc>;
143 };
144 };
145 };
146
147 dcsr: dcsr@f00000000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "fsl,dcsr", "simple-bus";
151
152 dcsr-epu@0 {
153 compatible = "fsl,dcsr-epu";
154 interrupts = <52 2 0 0
155 84 2 0 0
156 85 2 0 0>;
157 interrupt-parent = <&mpic>;
158 reg = <0x0 0x1000>;
159 };
160 dcsr-npc {
161 compatible = "fsl,dcsr-npc";
162 reg = <0x1000 0x1000 0x1000000 0x8000>;
163 };
164 dcsr-nxc@2000 {
165 compatible = "fsl,dcsr-nxc";
166 reg = <0x2000 0x1000>;
167 };
168 dcsr-corenet {
169 compatible = "fsl,dcsr-corenet";
170 reg = <0x8000 0x1000 0xB0000 0x1000>;
171 };
172 dcsr-dpaa@9000 {
173 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
174 reg = <0x9000 0x1000>;
175 };
176 dcsr-ocn@11000 {
177 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
178 reg = <0x11000 0x1000>;
179 };
180 dcsr-ddr@12000 {
181 compatible = "fsl,dcsr-ddr";
182 dev-handle = <&ddr1>;
183 reg = <0x12000 0x1000>;
184 };
185 dcsr-ddr@13000 {
186 compatible = "fsl,dcsr-ddr";
187 dev-handle = <&ddr2>;
188 reg = <0x13000 0x1000>;
189 };
190 dcsr-nal@18000 {
191 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
192 reg = <0x18000 0x1000>;
193 };
194 dcsr-rcpm@22000 {
195 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
196 reg = <0x22000 0x1000>;
197 };
198 dcsr-cpu-sb-proxy@40000 {
199 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
200 cpu-handle = <&cpu0>;
201 reg = <0x40000 0x1000>;
202 };
203 dcsr-cpu-sb-proxy@41000 {
204 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
205 cpu-handle = <&cpu1>;
206 reg = <0x41000 0x1000>;
207 };
208 dcsr-cpu-sb-proxy@42000 {
209 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
210 cpu-handle = <&cpu2>;
211 reg = <0x42000 0x1000>;
212 };
213 dcsr-cpu-sb-proxy@43000 {
214 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
215 cpu-handle = <&cpu3>;
216 reg = <0x43000 0x1000>;
217 };
218 dcsr-cpu-sb-proxy@44000 {
219 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
220 cpu-handle = <&cpu4>;
221 reg = <0x44000 0x1000>;
222 };
223 dcsr-cpu-sb-proxy@45000 {
224 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
225 cpu-handle = <&cpu5>;
226 reg = <0x45000 0x1000>;
227 };
228 dcsr-cpu-sb-proxy@46000 {
229 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
230 cpu-handle = <&cpu6>;
231 reg = <0x46000 0x1000>;
232 };
233 dcsr-cpu-sb-proxy@47000 {
234 compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
235 cpu-handle = <&cpu7>;
236 reg = <0x47000 0x1000>;
237 };
238 };
239
240 soc: soc@ffe000000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 device_type = "soc";
244 compatible = "simple-bus";
245 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
246 reg = <0xf 0xfe000000 0 0x00001000>;
247
248 soc-sram-error {
249 compatible = "fsl,soc-sram-error";
250 interrupts = <16 2 1 29>;
251 };
252
253 corenet-law@0 {
254 compatible = "fsl,corenet-law";
255 reg = <0x0 0x1000>;
256 fsl,num-laws = <32>;
257 };
258
259 ddr1: memory-controller@8000 {
260 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
261 reg = <0x8000 0x1000>;
262 interrupts = <16 2 1 23>;
263 };
264
265 ddr2: memory-controller@9000 {
266 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
267 reg = <0x9000 0x1000>;
268 interrupts = <16 2 1 22>;
269 };
270
271 cpc: l3-cache-controller@10000 {
272 compatible = "fsl,p4080-l3-cache-controller", "cache";
273 reg = <0x10000 0x1000
274 0x11000 0x1000>;
275 interrupts = <16 2 1 27
276 16 2 1 26>;
277 };
278
279 corenet-cf@18000 {
280 compatible = "fsl,corenet-cf";
281 reg = <0x18000 0x1000>;
282 interrupts = <16 2 1 31>;
283 fsl,ccf-num-csdids = <32>;
284 fsl,ccf-num-snoopids = <32>;
285 };
286
287 iommu@20000 {
288 compatible = "fsl,pamu-v1.0", "fsl,pamu";
289 reg = <0x20000 0x5000>;
290 interrupts = <
291 24 2 0 0
292 16 2 1 30>;
293 };
294
295 mpic: pic@40000 {
296 clock-frequency = <0>;
297 interrupt-controller;
298 #address-cells = <0>;
299 #interrupt-cells = <4>;
300 reg = <0x40000 0x40000>;
301 compatible = "fsl,mpic", "chrp,open-pic";
302 device_type = "open-pic";
303 };
304
305 msi0: msi@41600 {
306 compatible = "fsl,mpic-msi";
307 reg = <0x41600 0x200>;
308 msi-available-ranges = <0 0x100>;
309 interrupts = <
310 0xe0 0 0 0
311 0xe1 0 0 0
312 0xe2 0 0 0
313 0xe3 0 0 0
314 0xe4 0 0 0
315 0xe5 0 0 0
316 0xe6 0 0 0
317 0xe7 0 0 0>;
318 };
319
320 msi1: msi@41800 {
321 compatible = "fsl,mpic-msi";
322 reg = <0x41800 0x200>;
323 msi-available-ranges = <0 0x100>;
324 interrupts = <
325 0xe8 0 0 0
326 0xe9 0 0 0
327 0xea 0 0 0
328 0xeb 0 0 0
329 0xec 0 0 0
330 0xed 0 0 0
331 0xee 0 0 0
332 0xef 0 0 0>;
333 };
334
335 msi2: msi@41a00 {
336 compatible = "fsl,mpic-msi";
337 reg = <0x41a00 0x200>;
338 msi-available-ranges = <0 0x100>;
339 interrupts = <
340 0xf0 0 0 0
341 0xf1 0 0 0
342 0xf2 0 0 0
343 0xf3 0 0 0
344 0xf4 0 0 0
345 0xf5 0 0 0
346 0xf6 0 0 0
347 0xf7 0 0 0>;
348 };
349
350 guts: global-utilities@e0000 {
351 compatible = "fsl,qoriq-device-config-1.0";
352 reg = <0xe0000 0xe00>;
353 fsl,has-rstcr;
354 #sleep-cells = <1>;
355 fsl,liodn-bits = <12>;
356 };
357
358 pins: global-utilities@e0e00 {
359 compatible = "fsl,qoriq-pin-control-1.0";
360 reg = <0xe0e00 0x200>;
361 #sleep-cells = <2>;
362 };
363
364 clockgen: global-utilities@e1000 {
365 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
366 reg = <0xe1000 0x1000>;
367 clock-frequency = <0>;
368 };
369
370 rcpm: global-utilities@e2000 {
371 compatible = "fsl,qoriq-rcpm-1.0";
372 reg = <0xe2000 0x1000>;
373 #sleep-cells = <1>;
374 };
375
376 sfp: sfp@e8000 {
377 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
378 reg = <0xe8000 0x1000>;
379 };
380
381 serdes: serdes@ea000 {
382 compatible = "fsl,p4080-serdes";
383 reg = <0xea000 0x1000>;
384 };
385
386 dma0: dma@100300 {
387 #address-cells = <1>;
388 #size-cells = <1>;
389 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
390 reg = <0x100300 0x4>;
391 ranges = <0x0 0x100100 0x200>;
392 cell-index = <0>;
393 dma-channel@0 {
394 compatible = "fsl,p4080-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x0 0x80>;
397 cell-index = <0>;
398 interrupts = <28 2 0 0>;
399 };
400 dma-channel@80 {
401 compatible = "fsl,p4080-dma-channel",
402 "fsl,eloplus-dma-channel";
403 reg = <0x80 0x80>;
404 cell-index = <1>;
405 interrupts = <29 2 0 0>;
406 };
407 dma-channel@100 {
408 compatible = "fsl,p4080-dma-channel",
409 "fsl,eloplus-dma-channel";
410 reg = <0x100 0x80>;
411 cell-index = <2>;
412 interrupts = <30 2 0 0>;
413 };
414 dma-channel@180 {
415 compatible = "fsl,p4080-dma-channel",
416 "fsl,eloplus-dma-channel";
417 reg = <0x180 0x80>;
418 cell-index = <3>;
419 interrupts = <31 2 0 0>;
420 };
421 };
422
423 dma1: dma@101300 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
427 reg = <0x101300 0x4>;
428 ranges = <0x0 0x101100 0x200>;
429 cell-index = <1>;
430 dma-channel@0 {
431 compatible = "fsl,p4080-dma-channel",
432 "fsl,eloplus-dma-channel";
433 reg = <0x0 0x80>;
434 cell-index = <0>;
435 interrupts = <32 2 0 0>;
436 };
437 dma-channel@80 {
438 compatible = "fsl,p4080-dma-channel",
439 "fsl,eloplus-dma-channel";
440 reg = <0x80 0x80>;
441 cell-index = <1>;
442 interrupts = <33 2 0 0>;
443 };
444 dma-channel@100 {
445 compatible = "fsl,p4080-dma-channel",
446 "fsl,eloplus-dma-channel";
447 reg = <0x100 0x80>;
448 cell-index = <2>;
449 interrupts = <34 2 0 0>;
450 };
451 dma-channel@180 {
452 compatible = "fsl,p4080-dma-channel",
453 "fsl,eloplus-dma-channel";
454 reg = <0x180 0x80>;
455 cell-index = <3>;
456 interrupts = <35 2 0 0>;
457 };
458 };
459
460 spi@110000 {
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
464 reg = <0x110000 0x1000>;
465 interrupts = <53 0x2 0 0>;
466 fsl,espi-num-chipselects = <4>;
467 };
468
469 sdhc: sdhc@114000 {
470 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
471 reg = <0x114000 0x1000>;
472 interrupts = <48 2 0 0>;
473 voltage-ranges = <3300 3300>;
474 sdhci,auto-cmd12;
475 clock-frequency = <0>;
476 };
477
478 i2c@118000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 cell-index = <0>;
482 compatible = "fsl-i2c";
483 reg = <0x118000 0x100>;
484 interrupts = <38 2 0 0>;
485 dfsrr;
486 };
487
488 i2c@118100 {
489 #address-cells = <1>;
490 #size-cells = <0>;
491 cell-index = <1>;
492 compatible = "fsl-i2c";
493 reg = <0x118100 0x100>;
494 interrupts = <38 2 0 0>;
495 dfsrr;
496 };
497
498 i2c@119000 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 cell-index = <2>;
502 compatible = "fsl-i2c";
503 reg = <0x119000 0x100>;
504 interrupts = <39 2 0 0>;
505 dfsrr;
506 };
507
508 i2c@119100 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 cell-index = <3>;
512 compatible = "fsl-i2c";
513 reg = <0x119100 0x100>;
514 interrupts = <39 2 0 0>;
515 dfsrr;
516 };
517
518 serial0: serial@11c500 {
519 cell-index = <0>;
520 device_type = "serial";
521 compatible = "ns16550";
522 reg = <0x11c500 0x100>;
523 clock-frequency = <0>;
524 interrupts = <36 2 0 0>;
525 };
526
527 serial1: serial@11c600 {
528 cell-index = <1>;
529 device_type = "serial";
530 compatible = "ns16550";
531 reg = <0x11c600 0x100>;
532 clock-frequency = <0>;
533 interrupts = <36 2 0 0>;
534 };
535
536 serial2: serial@11d500 {
537 cell-index = <2>;
538 device_type = "serial";
539 compatible = "ns16550";
540 reg = <0x11d500 0x100>;
541 clock-frequency = <0>;
542 interrupts = <37 2 0 0>;
543 };
544
545 serial3: serial@11d600 {
546 cell-index = <3>;
547 device_type = "serial";
548 compatible = "ns16550";
549 reg = <0x11d600 0x100>;
550 clock-frequency = <0>;
551 interrupts = <37 2 0 0>;
552 };
553
554 gpio0: gpio@130000 {
555 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
556 reg = <0x130000 0x1000>;
557 interrupts = <55 2 0 0>;
558 #gpio-cells = <2>;
559 gpio-controller;
560 };
561
562 usb0: usb@210000 {
563 compatible = "fsl,p4080-usb2-mph",
564 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
565 reg = <0x210000 0x1000>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 interrupts = <44 0x2 0 0>;
569 };
570
571 usb1: usb@211000 {
572 compatible = "fsl,p4080-usb2-dr",
573 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
574 reg = <0x211000 0x1000>;
575 #address-cells = <1>;
576 #size-cells = <0>;
577 interrupts = <45 0x2 0 0>;
578 };
579
580 crypto: crypto@300000 {
581 compatible = "fsl,sec-v4.0";
582 #address-cells = <1>;
583 #size-cells = <1>;
584 reg = <0x300000 0x10000>;
585 ranges = <0 0x300000 0x10000>;
586 interrupt-parent = <&mpic>;
587 interrupts = <92 2 0 0>;
588
589 sec_jr0: jr@1000 {
590 compatible = "fsl,sec-v4.0-job-ring";
591 reg = <0x1000 0x1000>;
592 interrupt-parent = <&mpic>;
593 interrupts = <88 2 0 0>;
594 };
595
596 sec_jr1: jr@2000 {
597 compatible = "fsl,sec-v4.0-job-ring";
598 reg = <0x2000 0x1000>;
599 interrupt-parent = <&mpic>;
600 interrupts = <89 2 0 0>;
601 };
602
603 sec_jr2: jr@3000 {
604 compatible = "fsl,sec-v4.0-job-ring";
605 reg = <0x3000 0x1000>;
606 interrupt-parent = <&mpic>;
607 interrupts = <90 2 0 0>;
608 };
609
610 sec_jr3: jr@4000 {
611 compatible = "fsl,sec-v4.0-job-ring";
612 reg = <0x4000 0x1000>;
613 interrupt-parent = <&mpic>;
614 interrupts = <91 2 0 0>;
615 };
616
617 rtic@6000 {
618 compatible = "fsl,sec-v4.0-rtic";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 reg = <0x6000 0x100>;
622 ranges = <0x0 0x6100 0xe00>;
623
624 rtic_a: rtic-a@0 {
625 compatible = "fsl,sec-v4.0-rtic-memory";
626 reg = <0x00 0x20 0x100 0x80>;
627 };
628
629 rtic_b: rtic-b@20 {
630 compatible = "fsl,sec-v4.0-rtic-memory";
631 reg = <0x20 0x20 0x200 0x80>;
632 };
633
634 rtic_c: rtic-c@40 {
635 compatible = "fsl,sec-v4.0-rtic-memory";
636 reg = <0x40 0x20 0x300 0x80>;
637 };
638
639 rtic_d: rtic-d@60 {
640 compatible = "fsl,sec-v4.0-rtic-memory";
641 reg = <0x60 0x20 0x500 0x80>;
642 };
643 };
644 };
645
646 sec_mon: sec_mon@314000 {
647 compatible = "fsl,sec-v4.0-mon";
648 reg = <0x314000 0x1000>;
649 interrupt-parent = <&mpic>;
650 interrupts = <93 2 0 0>;
651 };
652 };
653
654 rapidio0: rapidio@ffe0c0000 {
655 #address-cells = <2>;
656 #size-cells = <2>;
657 compatible = "fsl,rapidio-delta";
658 interrupts = <
659 16 2 1 11 /* err_irq */
660 56 2 0 0 /* bell_outb_irq */
661 57 2 0 0 /* bell_inb_irq */
662 60 2 0 0 /* msg1_tx_irq */
663 61 2 0 0 /* msg1_rx_irq */
664 62 2 0 0 /* msg2_tx_irq */
665 63 2 0 0>; /* msg2_rx_irq */
666 };
667
668 localbus@ffe124000 {
669 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
670 interrupts = <25 2 0 0>;
671 #address-cells = <2>;
672 #size-cells = <1>;
673 };
674
675 pci0: pcie@ffe200000 {
676 compatible = "fsl,p4080-pcie";
677 device_type = "pci";
678 #size-cells = <2>;
679 #address-cells = <3>;
680 bus-range = <0x0 0xff>;
681 clock-frequency = <0x1fca055>;
682 fsl,msi = <&msi0>;
683 interrupts = <16 2 1 15>;
684 pcie@0 {
685 reg = <0 0 0 0 0>;
686 #interrupt-cells = <1>;
687 #size-cells = <2>;
688 #address-cells = <3>;
689 device_type = "pci";
690 interrupts = <16 2 1 15>;
691 interrupt-map-mask = <0xf800 0 0 7>;
692 interrupt-map = <
693 /* IDSEL 0x0 */
694 0000 0 0 1 &mpic 40 1 0 0
695 0000 0 0 2 &mpic 1 1 0 0
696 0000 0 0 3 &mpic 2 1 0 0
697 0000 0 0 4 &mpic 3 1 0 0
698 >;
699 };
700 };
701
702 pci1: pcie@ffe201000 {
703 compatible = "fsl,p4080-pcie";
704 device_type = "pci";
705 #size-cells = <2>;
706 #address-cells = <3>;
707 bus-range = <0 0xff>;
708 clock-frequency = <0x1fca055>;
709 fsl,msi = <&msi1>;
710 interrupts = <16 2 1 14>;
711 pcie@0 {
712 reg = <0 0 0 0 0>;
713 #interrupt-cells = <1>;
714 #size-cells = <2>;
715 #address-cells = <3>;
716 device_type = "pci";
717 interrupts = <16 2 1 14>;
718 interrupt-map-mask = <0xf800 0 0 7>;
719 interrupt-map = <
720 /* IDSEL 0x0 */
721 0000 0 0 1 &mpic 41 1 0 0
722 0000 0 0 2 &mpic 5 1 0 0
723 0000 0 0 3 &mpic 6 1 0 0
724 0000 0 0 4 &mpic 7 1 0 0
725 >;
726 };
727 };
728
729 pci2: pcie@ffe202000 {
730 compatible = "fsl,p4080-pcie";
731 device_type = "pci";
732 #size-cells = <2>;
733 #address-cells = <3>;
734 bus-range = <0x0 0xff>;
735 clock-frequency = <0x1fca055>;
736 fsl,msi = <&msi2>;
737 interrupts = <16 2 1 13>;
738 pcie@0 {
739 reg = <0 0 0 0 0>;
740 #interrupt-cells = <1>;
741 #size-cells = <2>;
742 #address-cells = <3>;
743 device_type = "pci";
744 interrupts = <16 2 1 13>;
745 interrupt-map-mask = <0xf800 0 0 7>;
746 interrupt-map = <
747 /* IDSEL 0x0 */
748 0000 0 0 1 &mpic 42 1 0 0
749 0000 0 0 2 &mpic 9 1 0 0
750 0000 0 0 3 &mpic 10 1 0 0
751 0000 0 0 4 &mpic 11 1 0 0
752 >;
753 };
754 };
755};
diff --git a/arch/powerpc/boot/dts/p5020ds.dts b/arch/powerpc/boot/dts/p5020ds.dts
index e6d40999ccd7..1c250684c902 100644
--- a/arch/powerpc/boot/dts/p5020ds.dts
+++ b/arch/powerpc/boot/dts/p5020ds.dts
@@ -32,7 +32,7 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35/include/ "p5020si.dtsi" 35/include/ "fsl/p5020si-pre.dtsi"
36 36
37/ { 37/ {
38 model = "fsl,P5020DS"; 38 model = "fsl,P5020DS";
@@ -50,6 +50,8 @@
50 }; 50 };
51 51
52 soc: soc@ffe000000 { 52 soc: soc@ffe000000 {
53 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
54 reg = <0xf 0xfe000000 0 0x00001000>;
53 spi@110000 { 55 spi@110000 {
54 flash@0 { 56 flash@0 {
55 #address-cells = <1>; 57 #address-cells = <1>;
@@ -99,7 +101,18 @@
99 }; 101 };
100 }; 102 };
101 103
102 localbus@ffe124000 { 104 rio: rapidio@ffe0c0000 {
105 reg = <0xf 0xfe0c0000 0 0x11000>;
106
107 port1 {
108 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
109 };
110 port2 {
111 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
112 };
113 };
114
115 lbc: localbus@ffe124000 {
103 reg = <0xf 0xfe124000 0 0x1000>; 116 reg = <0xf 0xfe124000 0 0x1000>;
104 ranges = <0 0 0xf 0xe8000000 0x08000000 117 ranges = <0 0 0xf 0xe8000000 0x08000000
105 2 0 0xf 0xffa00000 0x00040000 118 2 0 0xf 0xffa00000 0x00040000
@@ -160,7 +173,7 @@
160 reg = <0xf 0xfe200000 0 0x1000>; 173 reg = <0xf 0xfe200000 0 0x1000>;
161 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 174 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
162 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 175 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
163 176 fsl,msi = <&msi0>;
164 pcie@0 { 177 pcie@0 {
165 ranges = <0x02000000 0 0xe0000000 178 ranges = <0x02000000 0 0xe0000000
166 0x02000000 0 0xe0000000 179 0x02000000 0 0xe0000000
@@ -176,6 +189,7 @@
176 reg = <0xf 0xfe201000 0 0x1000>; 189 reg = <0xf 0xfe201000 0 0x1000>;
177 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 190 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
178 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 191 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
192 fsl,msi = <&msi1>;
179 pcie@0 { 193 pcie@0 {
180 ranges = <0x02000000 0 0xe0000000 194 ranges = <0x02000000 0 0xe0000000
181 0x02000000 0 0xe0000000 195 0x02000000 0 0xe0000000
@@ -191,6 +205,7 @@
191 reg = <0xf 0xfe202000 0 0x1000>; 205 reg = <0xf 0xfe202000 0 0x1000>;
192 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 206 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
193 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 207 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
208 fsl,msi = <&msi2>;
194 pcie@0 { 209 pcie@0 {
195 ranges = <0x02000000 0 0xe0000000 210 ranges = <0x02000000 0 0xe0000000
196 0x02000000 0 0xe0000000 211 0x02000000 0 0xe0000000
@@ -206,6 +221,7 @@
206 reg = <0xf 0xfe203000 0 0x1000>; 221 reg = <0xf 0xfe203000 0 0x1000>;
207 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 222 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
208 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 223 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
224 fsl,msi = <&msi2>;
209 pcie@0 { 225 pcie@0 {
210 ranges = <0x02000000 0 0xe0000000 226 ranges = <0x02000000 0 0xe0000000
211 0x02000000 0 0xe0000000 227 0x02000000 0 0xe0000000
@@ -217,3 +233,5 @@
217 }; 233 };
218 }; 234 };
219}; 235};
236
237/include/ "fsl/p5020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p5020si.dtsi b/arch/powerpc/boot/dts/p5020si.dtsi
deleted file mode 100644
index e7948ad71fa3..000000000000
--- a/arch/powerpc/boot/dts/p5020si.dtsi
+++ /dev/null
@@ -1,716 +0,0 @@
1/*
2 * P5020 Silicon Device Tree Source
3 *
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,P5020";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 pci1 = &pci1;
53 pci2 = &pci2;
54 pci3 = &pci3;
55 usb0 = &usb0;
56 usb1 = &usb1;
57 dma0 = &dma0;
58 dma1 = &dma1;
59 sdhc = &sdhc;
60 msi0 = &msi0;
61 msi1 = &msi1;
62 msi2 = &msi2;
63
64 crypto = &crypto;
65 sec_jr0 = &sec_jr0;
66 sec_jr1 = &sec_jr1;
67 sec_jr2 = &sec_jr2;
68 sec_jr3 = &sec_jr3;
69 rtic_a = &rtic_a;
70 rtic_b = &rtic_b;
71 rtic_c = &rtic_c;
72 rtic_d = &rtic_d;
73 sec_mon = &sec_mon;
74
75/*
76 rio0 = &rapidio0;
77 */
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: PowerPC,e5500@0 {
85 device_type = "cpu";
86 reg = <0>;
87 next-level-cache = <&L2_0>;
88 L2_0: l2-cache {
89 next-level-cache = <&cpc>;
90 };
91 };
92 cpu1: PowerPC,e5500@1 {
93 device_type = "cpu";
94 reg = <1>;
95 next-level-cache = <&L2_1>;
96 L2_1: l2-cache {
97 next-level-cache = <&cpc>;
98 };
99 };
100 };
101
102 dcsr: dcsr@f00000000 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,dcsr", "simple-bus";
106
107 dcsr-epu@0 {
108 compatible = "fsl,dcsr-epu";
109 interrupts = <52 2 0 0
110 84 2 0 0
111 85 2 0 0>;
112 interrupt-parent = <&mpic>;
113 reg = <0x0 0x1000>;
114 };
115 dcsr-npc {
116 compatible = "fsl,dcsr-npc";
117 reg = <0x1000 0x1000 0x1000000 0x8000>;
118 };
119 dcsr-nxc@2000 {
120 compatible = "fsl,dcsr-nxc";
121 reg = <0x2000 0x1000>;
122 };
123 dcsr-corenet {
124 compatible = "fsl,dcsr-corenet";
125 reg = <0x8000 0x1000 0xB0000 0x1000>;
126 };
127 dcsr-dpaa@9000 {
128 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
129 reg = <0x9000 0x1000>;
130 };
131 dcsr-ocn@11000 {
132 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
133 reg = <0x11000 0x1000>;
134 };
135 dcsr-ddr@12000 {
136 compatible = "fsl,dcsr-ddr";
137 dev-handle = <&ddr1>;
138 reg = <0x12000 0x1000>;
139 };
140 dcsr-ddr@13000 {
141 compatible = "fsl,dcsr-ddr";
142 dev-handle = <&ddr2>;
143 reg = <0x13000 0x1000>;
144 };
145 dcsr-nal@18000 {
146 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
147 reg = <0x18000 0x1000>;
148 };
149 dcsr-rcpm@22000 {
150 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
151 reg = <0x22000 0x1000>;
152 };
153 dcsr-cpu-sb-proxy@40000 {
154 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
155 cpu-handle = <&cpu0>;
156 reg = <0x40000 0x1000>;
157 };
158 dcsr-cpu-sb-proxy@41000 {
159 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
160 cpu-handle = <&cpu1>;
161 reg = <0x41000 0x1000>;
162 };
163 };
164
165 soc: soc@ffe000000 {
166 #address-cells = <1>;
167 #size-cells = <1>;
168 device_type = "soc";
169 compatible = "simple-bus";
170 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
171 reg = <0xf 0xfe000000 0 0x00001000>;
172
173 soc-sram-error {
174 compatible = "fsl,soc-sram-error";
175 interrupts = <16 2 1 29>;
176 };
177
178 corenet-law@0 {
179 compatible = "fsl,corenet-law";
180 reg = <0x0 0x1000>;
181 fsl,num-laws = <32>;
182 };
183
184 ddr1: memory-controller@8000 {
185 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
186 reg = <0x8000 0x1000>;
187 interrupts = <16 2 1 23>;
188 };
189
190 ddr2: memory-controller@9000 {
191 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
192 reg = <0x9000 0x1000>;
193 interrupts = <16 2 1 22>;
194 };
195
196 cpc: l3-cache-controller@10000 {
197 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
198 reg = <0x10000 0x1000
199 0x11000 0x1000>;
200 interrupts = <16 2 1 27
201 16 2 1 26>;
202 };
203
204 corenet-cf@18000 {
205 compatible = "fsl,corenet-cf";
206 reg = <0x18000 0x1000>;
207 interrupts = <16 2 1 31>;
208 fsl,ccf-num-csdids = <32>;
209 fsl,ccf-num-snoopids = <32>;
210 };
211
212 iommu@20000 {
213 compatible = "fsl,pamu-v1.0", "fsl,pamu";
214 reg = <0x20000 0x4000>;
215 interrupts = <
216 24 2 0 0
217 16 2 1 30>;
218 };
219
220 mpic: pic@40000 {
221 clock-frequency = <0>;
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <4>;
225 reg = <0x40000 0x40000>;
226 compatible = "fsl,mpic", "chrp,open-pic";
227 device_type = "open-pic";
228 };
229
230 msi0: msi@41600 {
231 compatible = "fsl,mpic-msi";
232 reg = <0x41600 0x200>;
233 msi-available-ranges = <0 0x100>;
234 interrupts = <
235 0xe0 0 0 0
236 0xe1 0 0 0
237 0xe2 0 0 0
238 0xe3 0 0 0
239 0xe4 0 0 0
240 0xe5 0 0 0
241 0xe6 0 0 0
242 0xe7 0 0 0>;
243 };
244
245 msi1: msi@41800 {
246 compatible = "fsl,mpic-msi";
247 reg = <0x41800 0x200>;
248 msi-available-ranges = <0 0x100>;
249 interrupts = <
250 0xe8 0 0 0
251 0xe9 0 0 0
252 0xea 0 0 0
253 0xeb 0 0 0
254 0xec 0 0 0
255 0xed 0 0 0
256 0xee 0 0 0
257 0xef 0 0 0>;
258 };
259
260 msi2: msi@41a00 {
261 compatible = "fsl,mpic-msi";
262 reg = <0x41a00 0x200>;
263 msi-available-ranges = <0 0x100>;
264 interrupts = <
265 0xf0 0 0 0
266 0xf1 0 0 0
267 0xf2 0 0 0
268 0xf3 0 0 0
269 0xf4 0 0 0
270 0xf5 0 0 0
271 0xf6 0 0 0
272 0xf7 0 0 0>;
273 };
274
275 guts: global-utilities@e0000 {
276 compatible = "fsl,qoriq-device-config-1.0";
277 reg = <0xe0000 0xe00>;
278 fsl,has-rstcr;
279 #sleep-cells = <1>;
280 fsl,liodn-bits = <12>;
281 };
282
283 pins: global-utilities@e0e00 {
284 compatible = "fsl,qoriq-pin-control-1.0";
285 reg = <0xe0e00 0x200>;
286 #sleep-cells = <2>;
287 };
288
289 clockgen: global-utilities@e1000 {
290 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
291 reg = <0xe1000 0x1000>;
292 clock-frequency = <0>;
293 };
294
295 rcpm: global-utilities@e2000 {
296 compatible = "fsl,qoriq-rcpm-1.0";
297 reg = <0xe2000 0x1000>;
298 #sleep-cells = <1>;
299 };
300
301 sfp: sfp@e8000 {
302 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
303 reg = <0xe8000 0x1000>;
304 };
305
306 serdes: serdes@ea000 {
307 compatible = "fsl,p5020-serdes";
308 reg = <0xea000 0x1000>;
309 };
310
311 dma0: dma@100300 {
312 #address-cells = <1>;
313 #size-cells = <1>;
314 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
315 reg = <0x100300 0x4>;
316 ranges = <0x0 0x100100 0x200>;
317 cell-index = <0>;
318 dma-channel@0 {
319 compatible = "fsl,p5020-dma-channel",
320 "fsl,eloplus-dma-channel";
321 reg = <0x0 0x80>;
322 cell-index = <0>;
323 interrupts = <28 2 0 0>;
324 };
325 dma-channel@80 {
326 compatible = "fsl,p5020-dma-channel",
327 "fsl,eloplus-dma-channel";
328 reg = <0x80 0x80>;
329 cell-index = <1>;
330 interrupts = <29 2 0 0>;
331 };
332 dma-channel@100 {
333 compatible = "fsl,p5020-dma-channel",
334 "fsl,eloplus-dma-channel";
335 reg = <0x100 0x80>;
336 cell-index = <2>;
337 interrupts = <30 2 0 0>;
338 };
339 dma-channel@180 {
340 compatible = "fsl,p5020-dma-channel",
341 "fsl,eloplus-dma-channel";
342 reg = <0x180 0x80>;
343 cell-index = <3>;
344 interrupts = <31 2 0 0>;
345 };
346 };
347
348 dma1: dma@101300 {
349 #address-cells = <1>;
350 #size-cells = <1>;
351 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
352 reg = <0x101300 0x4>;
353 ranges = <0x0 0x101100 0x200>;
354 cell-index = <1>;
355 dma-channel@0 {
356 compatible = "fsl,p5020-dma-channel",
357 "fsl,eloplus-dma-channel";
358 reg = <0x0 0x80>;
359 cell-index = <0>;
360 interrupts = <32 2 0 0>;
361 };
362 dma-channel@80 {
363 compatible = "fsl,p5020-dma-channel",
364 "fsl,eloplus-dma-channel";
365 reg = <0x80 0x80>;
366 cell-index = <1>;
367 interrupts = <33 2 0 0>;
368 };
369 dma-channel@100 {
370 compatible = "fsl,p5020-dma-channel",
371 "fsl,eloplus-dma-channel";
372 reg = <0x100 0x80>;
373 cell-index = <2>;
374 interrupts = <34 2 0 0>;
375 };
376 dma-channel@180 {
377 compatible = "fsl,p5020-dma-channel",
378 "fsl,eloplus-dma-channel";
379 reg = <0x180 0x80>;
380 cell-index = <3>;
381 interrupts = <35 2 0 0>;
382 };
383 };
384
385 spi@110000 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
389 reg = <0x110000 0x1000>;
390 interrupts = <53 0x2 0 0>;
391 fsl,espi-num-chipselects = <4>;
392 };
393
394 sdhc: sdhc@114000 {
395 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
396 reg = <0x114000 0x1000>;
397 interrupts = <48 2 0 0>;
398 sdhci,auto-cmd12;
399 clock-frequency = <0>;
400 };
401
402 i2c@118000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 cell-index = <0>;
406 compatible = "fsl-i2c";
407 reg = <0x118000 0x100>;
408 interrupts = <38 2 0 0>;
409 dfsrr;
410 };
411
412 i2c@118100 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 cell-index = <1>;
416 compatible = "fsl-i2c";
417 reg = <0x118100 0x100>;
418 interrupts = <38 2 0 0>;
419 dfsrr;
420 };
421
422 i2c@119000 {
423 #address-cells = <1>;
424 #size-cells = <0>;
425 cell-index = <2>;
426 compatible = "fsl-i2c";
427 reg = <0x119000 0x100>;
428 interrupts = <39 2 0 0>;
429 dfsrr;
430 };
431
432 i2c@119100 {
433 #address-cells = <1>;
434 #size-cells = <0>;
435 cell-index = <3>;
436 compatible = "fsl-i2c";
437 reg = <0x119100 0x100>;
438 interrupts = <39 2 0 0>;
439 dfsrr;
440 };
441
442 serial0: serial@11c500 {
443 cell-index = <0>;
444 device_type = "serial";
445 compatible = "ns16550";
446 reg = <0x11c500 0x100>;
447 clock-frequency = <0>;
448 interrupts = <36 2 0 0>;
449 };
450
451 serial1: serial@11c600 {
452 cell-index = <1>;
453 device_type = "serial";
454 compatible = "ns16550";
455 reg = <0x11c600 0x100>;
456 clock-frequency = <0>;
457 interrupts = <36 2 0 0>;
458 };
459
460 serial2: serial@11d500 {
461 cell-index = <2>;
462 device_type = "serial";
463 compatible = "ns16550";
464 reg = <0x11d500 0x100>;
465 clock-frequency = <0>;
466 interrupts = <37 2 0 0>;
467 };
468
469 serial3: serial@11d600 {
470 cell-index = <3>;
471 device_type = "serial";
472 compatible = "ns16550";
473 reg = <0x11d600 0x100>;
474 clock-frequency = <0>;
475 interrupts = <37 2 0 0>;
476 };
477
478 gpio0: gpio@130000 {
479 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
480 reg = <0x130000 0x1000>;
481 interrupts = <55 2 0 0>;
482 #gpio-cells = <2>;
483 gpio-controller;
484 };
485
486 usb0: usb@210000 {
487 compatible = "fsl,p5020-usb2-mph",
488 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
489 reg = <0x210000 0x1000>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 interrupts = <44 0x2 0 0>;
493 phy_type = "utmi";
494 port0;
495 };
496
497 usb1: usb@211000 {
498 compatible = "fsl,p5020-usb2-dr",
499 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
500 reg = <0x211000 0x1000>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 interrupts = <45 0x2 0 0>;
504 dr_mode = "host";
505 phy_type = "utmi";
506 };
507
508 sata@220000 {
509 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
510 reg = <0x220000 0x1000>;
511 interrupts = <68 0x2 0 0>;
512 };
513
514 sata@221000 {
515 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
516 reg = <0x221000 0x1000>;
517 interrupts = <69 0x2 0 0>;
518 };
519
520 crypto: crypto@300000 {
521 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 reg = <0x300000 0x10000>;
525 ranges = <0 0x300000 0x10000>;
526 interrupts = <92 2 0 0>;
527
528 sec_jr0: jr@1000 {
529 compatible = "fsl,sec-v4.2-job-ring",
530 "fsl,sec-v4.0-job-ring";
531 reg = <0x1000 0x1000>;
532 interrupts = <88 2 0 0>;
533 };
534
535 sec_jr1: jr@2000 {
536 compatible = "fsl,sec-v4.2-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x2000 0x1000>;
539 interrupts = <89 2 0 0>;
540 };
541
542 sec_jr2: jr@3000 {
543 compatible = "fsl,sec-v4.2-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x3000 0x1000>;
546 interrupts = <90 2 0 0>;
547 };
548
549 sec_jr3: jr@4000 {
550 compatible = "fsl,sec-v4.2-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x4000 0x1000>;
553 interrupts = <91 2 0 0>;
554 };
555
556 rtic@6000 {
557 compatible = "fsl,sec-v4.2-rtic",
558 "fsl,sec-v4.0-rtic";
559 #address-cells = <1>;
560 #size-cells = <1>;
561 reg = <0x6000 0x100>;
562 ranges = <0x0 0x6100 0xe00>;
563
564 rtic_a: rtic-a@0 {
565 compatible = "fsl,sec-v4.2-rtic-memory",
566 "fsl,sec-v4.0-rtic-memory";
567 reg = <0x00 0x20 0x100 0x80>;
568 };
569
570 rtic_b: rtic-b@20 {
571 compatible = "fsl,sec-v4.2-rtic-memory",
572 "fsl,sec-v4.0-rtic-memory";
573 reg = <0x20 0x20 0x200 0x80>;
574 };
575
576 rtic_c: rtic-c@40 {
577 compatible = "fsl,sec-v4.2-rtic-memory",
578 "fsl,sec-v4.0-rtic-memory";
579 reg = <0x40 0x20 0x300 0x80>;
580 };
581
582 rtic_d: rtic-d@60 {
583 compatible = "fsl,sec-v4.2-rtic-memory",
584 "fsl,sec-v4.0-rtic-memory";
585 reg = <0x60 0x20 0x500 0x80>;
586 };
587 };
588 };
589
590 sec_mon: sec_mon@314000 {
591 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
592 reg = <0x314000 0x1000>;
593 interrupts = <93 2 0 0>;
594 };
595 };
596
597/*
598 rapidio0: rapidio@ffe0c0000
599*/
600
601 localbus@ffe124000 {
602 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
603 interrupts = <25 2 0 0>;
604 #address-cells = <2>;
605 #size-cells = <1>;
606 };
607
608 pci0: pcie@ffe200000 {
609 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
610 device_type = "pci";
611 #size-cells = <2>;
612 #address-cells = <3>;
613 bus-range = <0x0 0xff>;
614 clock-frequency = <0x1fca055>;
615 fsl,msi = <&msi0>;
616 interrupts = <16 2 1 15>;
617
618 pcie@0 {
619 reg = <0 0 0 0 0>;
620 #interrupt-cells = <1>;
621 #size-cells = <2>;
622 #address-cells = <3>;
623 device_type = "pci";
624 interrupts = <16 2 1 15>;
625 interrupt-map-mask = <0xf800 0 0 7>;
626 interrupt-map = <
627 /* IDSEL 0x0 */
628 0000 0 0 1 &mpic 40 1 0 0
629 0000 0 0 2 &mpic 1 1 0 0
630 0000 0 0 3 &mpic 2 1 0 0
631 0000 0 0 4 &mpic 3 1 0 0
632 >;
633 };
634 };
635
636 pci1: pcie@ffe201000 {
637 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
638 device_type = "pci";
639 #size-cells = <2>;
640 #address-cells = <3>;
641 bus-range = <0 0xff>;
642 clock-frequency = <0x1fca055>;
643 fsl,msi = <&msi1>;
644 interrupts = <16 2 1 14>;
645 pcie@0 {
646 reg = <0 0 0 0 0>;
647 #interrupt-cells = <1>;
648 #size-cells = <2>;
649 #address-cells = <3>;
650 device_type = "pci";
651 interrupts = <16 2 1 14>;
652 interrupt-map-mask = <0xf800 0 0 7>;
653 interrupt-map = <
654 /* IDSEL 0x0 */
655 0000 0 0 1 &mpic 41 1 0 0
656 0000 0 0 2 &mpic 5 1 0 0
657 0000 0 0 3 &mpic 6 1 0 0
658 0000 0 0 4 &mpic 7 1 0 0
659 >;
660 };
661 };
662
663 pci2: pcie@ffe202000 {
664 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
665 device_type = "pci";
666 #size-cells = <2>;
667 #address-cells = <3>;
668 bus-range = <0x0 0xff>;
669 clock-frequency = <0x1fca055>;
670 fsl,msi = <&msi2>;
671 interrupts = <16 2 1 13>;
672 pcie@0 {
673 reg = <0 0 0 0 0>;
674 #interrupt-cells = <1>;
675 #size-cells = <2>;
676 #address-cells = <3>;
677 device_type = "pci";
678 interrupts = <16 2 1 13>;
679 interrupt-map-mask = <0xf800 0 0 7>;
680 interrupt-map = <
681 /* IDSEL 0x0 */
682 0000 0 0 1 &mpic 42 1 0 0
683 0000 0 0 2 &mpic 9 1 0 0
684 0000 0 0 3 &mpic 10 1 0 0
685 0000 0 0 4 &mpic 11 1 0 0
686 >;
687 };
688 };
689
690 pci3: pcie@ffe203000 {
691 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
692 device_type = "pci";
693 #size-cells = <2>;
694 #address-cells = <3>;
695 bus-range = <0x0 0xff>;
696 clock-frequency = <0x1fca055>;
697 fsl,msi = <&msi2>;
698 interrupts = <16 2 1 12>;
699 pcie@0 {
700 reg = <0 0 0 0 0>;
701 #interrupt-cells = <1>;
702 #size-cells = <2>;
703 #address-cells = <3>;
704 device_type = "pci";
705 interrupts = <16 2 1 12>;
706 interrupt-map-mask = <0xf800 0 0 7>;
707 interrupt-map = <
708 /* IDSEL 0x0 */
709 0000 0 0 1 &mpic 43 1 0 0
710 0000 0 0 2 &mpic 0 1 0 0
711 0000 0 0 3 &mpic 4 1 0 0
712 0000 0 0 4 &mpic 8 1 0 0
713 >;
714 };
715 };
716};
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 0dc90f9bd814..b1e45a8537a5 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -222,7 +222,7 @@
222 serial0: serial@4500 { 222 serial0: serial@4500 {
223 cell-index = <0>; 223 cell-index = <0>;
224 device_type = "serial"; 224 device_type = "serial";
225 compatible = "ns16550"; 225 compatible = "fsl,ns16550", "ns16550";
226 reg = <0x4500 0x100>; 226 reg = <0x4500 0x100>;
227 clock-frequency = <0>; 227 clock-frequency = <0>;
228 interrupts = <9 0x8>; 228 interrupts = <9 0x8>;
@@ -232,7 +232,7 @@
232 serial1: serial@4600 { 232 serial1: serial@4600 {
233 cell-index = <1>; 233 cell-index = <1>;
234 device_type = "serial"; 234 device_type = "serial";
235 compatible = "ns16550"; 235 compatible = "fsl,ns16550", "ns16550";
236 reg = <0x4600 0x100>; 236 reg = <0x4600 0x100>;
237 clock-frequency = <0>; 237 clock-frequency = <0>;
238 interrupts = <10 0x8>; 238 interrupts = <10 0x8>;
diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts
index 94a332251710..77be77116c2e 100644
--- a/arch/powerpc/boot/dts/sbc8548.dts
+++ b/arch/powerpc/boot/dts/sbc8548.dts
@@ -316,7 +316,7 @@
316 serial0: serial@4500 { 316 serial0: serial@4500 {
317 cell-index = <0>; 317 cell-index = <0>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4500 0x100>; // reg base, size 320 reg = <0x4500 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 interrupts = <0x2a 0x2>; 322 interrupts = <0x2a 0x2>;
@@ -326,7 +326,7 @@
326 serial1: serial@4600 { 326 serial1: serial@4600 {
327 cell-index = <1>; 327 cell-index = <1>;
328 device_type = "serial"; 328 device_type = "serial";
329 compatible = "ns16550"; 329 compatible = "fsl,ns16550", "ns16550";
330 reg = <0x4600 0x100>; // reg base, size 330 reg = <0x4600 0x100>; // reg base, size
331 clock-frequency = <0>; // should we fill in in uboot? 331 clock-frequency = <0>; // should we fill in in uboot?
332 interrupts = <0x2a 0x2>; 332 interrupts = <0x2a 0x2>;
diff --git a/arch/powerpc/boot/dts/sbc8641d.dts b/arch/powerpc/boot/dts/sbc8641d.dts
index ee5538feb455..56bebce87842 100644
--- a/arch/powerpc/boot/dts/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/sbc8641d.dts
@@ -347,7 +347,7 @@
347 serial0: serial@4500 { 347 serial0: serial@4500 {
348 cell-index = <0>; 348 cell-index = <0>;
349 device_type = "serial"; 349 device_type = "serial";
350 compatible = "ns16550"; 350 compatible = "fsl,ns16550", "ns16550";
351 reg = <0x4500 0x100>; 351 reg = <0x4500 0x100>;
352 clock-frequency = <0>; 352 clock-frequency = <0>;
353 interrupts = <42 2>; 353 interrupts = <42 2>;
@@ -357,7 +357,7 @@
357 serial1: serial@4600 { 357 serial1: serial@4600 {
358 cell-index = <1>; 358 cell-index = <1>;
359 device_type = "serial"; 359 device_type = "serial";
360 compatible = "ns16550"; 360 compatible = "fsl,ns16550", "ns16550";
361 reg = <0x4600 0x100>; 361 reg = <0x4600 0x100>;
362 clock-frequency = <0>; 362 clock-frequency = <0>;
363 interrupts = <28 2>; 363 interrupts = <28 2>;
diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts
index 38c35404bdc3..134a5ff917e1 100644
--- a/arch/powerpc/boot/dts/socrates.dts
+++ b/arch/powerpc/boot/dts/socrates.dts
@@ -199,7 +199,7 @@
199 serial0: serial@4500 { 199 serial0: serial@4500 {
200 cell-index = <0>; 200 cell-index = <0>;
201 device_type = "serial"; 201 device_type = "serial";
202 compatible = "ns16550"; 202 compatible = "fsl,ns16550", "ns16550";
203 reg = <0x4500 0x100>; 203 reg = <0x4500 0x100>;
204 clock-frequency = <0>; 204 clock-frequency = <0>;
205 interrupts = <42 2>; 205 interrupts = <42 2>;
@@ -209,7 +209,7 @@
209 serial1: serial@4600 { 209 serial1: serial@4600 {
210 cell-index = <1>; 210 cell-index = <1>;
211 device_type = "serial"; 211 device_type = "serial";
212 compatible = "ns16550"; 212 compatible = "fsl,ns16550", "ns16550";
213 reg = <0x4600 0x100>; 213 reg = <0x4600 0x100>;
214 clock-frequency = <0>; 214 clock-frequency = <0>;
215 interrupts = <42 2>; 215 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts
index eab680ce10da..2a555738517e 100644
--- a/arch/powerpc/boot/dts/storcenter.dts
+++ b/arch/powerpc/boot/dts/storcenter.dts
@@ -74,7 +74,7 @@
74 serial0: serial@4500 { 74 serial0: serial@4500 {
75 cell-index = <0>; 75 cell-index = <0>;
76 device_type = "serial"; 76 device_type = "serial";
77 compatible = "ns16550"; 77 compatible = "fsl,ns16550", "ns16550";
78 reg = <0x4500 0x20>; 78 reg = <0x4500 0x20>;
79 clock-frequency = <97553800>; /* Hz */ 79 clock-frequency = <97553800>; /* Hz */
80 current-speed = <115200>; 80 current-speed = <115200>;
@@ -85,7 +85,7 @@
85 serial1: serial@4600 { 85 serial1: serial@4600 {
86 cell-index = <1>; 86 cell-index = <1>;
87 device_type = "serial"; 87 device_type = "serial";
88 compatible = "ns16550"; 88 compatible = "fsl,ns16550", "ns16550";
89 reg = <0x4600 0x20>; 89 reg = <0x4600 0x20>;
90 clock-frequency = <97553800>; /* Hz */ 90 clock-frequency = <97553800>; /* Hz */
91 current-speed = <9600>; 91 current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/stxssa8555.dts b/arch/powerpc/boot/dts/stxssa8555.dts
index 49efd44057d7..4f166b01c1b6 100644
--- a/arch/powerpc/boot/dts/stxssa8555.dts
+++ b/arch/powerpc/boot/dts/stxssa8555.dts
@@ -210,7 +210,7 @@
210 serial0: serial@4500 { 210 serial0: serial@4500 {
211 cell-index = <0>; 211 cell-index = <0>;
212 device_type = "serial"; 212 device_type = "serial";
213 compatible = "ns16550"; 213 compatible = "fsl,ns16550", "ns16550";
214 reg = <0x4500 0x100>; // reg base, size 214 reg = <0x4500 0x100>; // reg base, size
215 clock-frequency = <0>; // should we fill in in uboot? 215 clock-frequency = <0>; // should we fill in in uboot?
216 interrupts = <42 2>; 216 interrupts = <42 2>;
@@ -220,7 +220,7 @@
220 serial1: serial@4600 { 220 serial1: serial@4600 {
221 cell-index = <1>; 221 cell-index = <1>;
222 device_type = "serial"; 222 device_type = "serial";
223 compatible = "ns16550"; 223 compatible = "fsl,ns16550", "ns16550";
224 reg = <0x4600 0x100>; // reg base, size 224 reg = <0x4600 0x100>; // reg base, size
225 clock-frequency = <0>; // should we fill in in uboot? 225 clock-frequency = <0>; // should we fill in in uboot?
226 interrupts = <42 2>; 226 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index 0a4cedbdcb55..ed264d9ae356 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -250,7 +250,7 @@
250 serial0: serial@4500 { 250 serial0: serial@4500 {
251 cell-index = <0>; 251 cell-index = <0>;
252 device_type = "serial"; 252 device_type = "serial";
253 compatible = "ns16550"; 253 compatible = "fsl,ns16550", "ns16550";
254 reg = <0x4500 0x100>; // reg base, size 254 reg = <0x4500 0x100>; // reg base, size
255 clock-frequency = <0>; // should we fill in in uboot? 255 clock-frequency = <0>; // should we fill in in uboot?
256 interrupts = <42 2>; 256 interrupts = <42 2>;
@@ -260,7 +260,7 @@
260 serial1: serial@4600 { 260 serial1: serial@4600 {
261 cell-index = <1>; 261 cell-index = <1>;
262 device_type = "serial"; 262 device_type = "serial";
263 compatible = "ns16550"; 263 compatible = "fsl,ns16550", "ns16550";
264 reg = <0x4600 0x100>; // reg base, size 264 reg = <0x4600 0x100>; // reg base, size
265 clock-frequency = <0>; // should we fill in in uboot? 265 clock-frequency = <0>; // should we fill in in uboot?
266 interrupts = <42 2>; 266 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index f49d09181312..925242115814 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -224,7 +224,7 @@
224 serial0: serial@4500 { 224 serial0: serial@4500 {
225 cell-index = <0>; 225 cell-index = <0>;
226 device_type = "serial"; 226 device_type = "serial";
227 compatible = "ns16550"; 227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size 228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot? 229 clock-frequency = <0>; // should we fill in in uboot?
230 interrupts = <42 2>; 230 interrupts = <42 2>;
@@ -234,7 +234,7 @@
234 serial1: serial@4600 { 234 serial1: serial@4600 {
235 cell-index = <1>; 235 cell-index = <1>;
236 device_type = "serial"; 236 device_type = "serial";
237 compatible = "ns16550"; 237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size 238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot? 239 clock-frequency = <0>; // should we fill in in uboot?
240 interrupts = <42 2>; 240 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 9452c3c05114..6e1ac50852a4 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -305,7 +305,7 @@
305 serial0: serial@4500 { 305 serial0: serial@4500 {
306 cell-index = <0>; 306 cell-index = <0>;
307 device_type = "serial"; 307 device_type = "serial";
308 compatible = "ns16550"; 308 compatible = "fsl,ns16550", "ns16550";
309 reg = <0x4500 0x100>; // reg base, size 309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot? 310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>; 311 current-speed = <115200>;
@@ -316,7 +316,7 @@
316 serial1: serial@4600 { 316 serial1: serial@4600 {
317 cell-index = <1>; 317 cell-index = <1>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4600 0x100>; // reg base, size 320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>; 322 current-speed = <115200>;
@@ -352,7 +352,7 @@
352 ranges = < 352 ranges = <
353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
355 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 355 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770)
356 3 0x0 0xa3010000 0x00008000 // NAND FLASH 356 3 0x0 0xa3010000 0x00008000 // NAND FLASH
357 357
358 >; 358 >;
@@ -393,18 +393,27 @@
393 }; 393 };
394 394
395 /* Note: CAN support needs be enabled in U-Boot */ 395 /* Note: CAN support needs be enabled in U-Boot */
396 can0@2,0 { 396 can@2,0 {
397 compatible = "intel,82527"; // Bosch CC770 397 compatible = "bosch,cc770"; // Bosch CC770
398 reg = <2 0x0 0x100>; 398 reg = <2 0x0 0x100>;
399 interrupts = <4 1>; 399 interrupts = <4 1>;
400 interrupt-parent = <&mpic>; 400 interrupt-parent = <&mpic>;
401 bosch,external-clock-frequency = <16000000>;
402 bosch,disconnect-rx1-input;
403 bosch,disconnect-tx1-output;
404 bosch,iso-low-speed-mux;
405 bosch,clock-out-frequency = <16000000>;
401 }; 406 };
402 407
403 can1@2,100 { 408 can@2,100 {
404 compatible = "intel,82527"; // Bosch CC770 409 compatible = "bosch,cc770"; // Bosch CC770
405 reg = <2 0x100 0x100>; 410 reg = <2 0x100 0x100>;
406 interrupts = <4 1>; 411 interrupts = <4 1>;
407 interrupt-parent = <&mpic>; 412 interrupt-parent = <&mpic>;
413 bosch,external-clock-frequency = <16000000>;
414 bosch,disconnect-rx1-input;
415 bosch,disconnect-tx1-output;
416 bosch,iso-low-speed-mux;
408 }; 417 };
409 418
410 /* Note: NAND support needs to be enabled in U-Boot */ 419 /* Note: NAND support needs to be enabled in U-Boot */
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index 619776f72c90..161e75eac7f7 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -305,7 +305,7 @@
305 serial0: serial@4500 { 305 serial0: serial@4500 {
306 cell-index = <0>; 306 cell-index = <0>;
307 device_type = "serial"; 307 device_type = "serial";
308 compatible = "ns16550"; 308 compatible = "fsl,ns16550", "ns16550";
309 reg = <0x4500 0x100>; // reg base, size 309 reg = <0x4500 0x100>; // reg base, size
310 clock-frequency = <0>; // should we fill in in uboot? 310 clock-frequency = <0>; // should we fill in in uboot?
311 current-speed = <115200>; 311 current-speed = <115200>;
@@ -316,7 +316,7 @@
316 serial1: serial@4600 { 316 serial1: serial@4600 {
317 cell-index = <1>; 317 cell-index = <1>;
318 device_type = "serial"; 318 device_type = "serial";
319 compatible = "ns16550"; 319 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4600 0x100>; // reg base, size 320 reg = <0x4600 0x100>; // reg base, size
321 clock-frequency = <0>; // should we fill in in uboot? 321 clock-frequency = <0>; // should we fill in in uboot?
322 current-speed = <115200>; 322 current-speed = <115200>;
@@ -352,7 +352,7 @@
352 ranges = < 352 ranges = <
353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 353 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 354 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
355 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527) 355 2 0x0 0xe3000000 0x00008000 // CAN (2 x CC770)
356 3 0x0 0xe3010000 0x00008000 // NAND FLASH 356 3 0x0 0xe3010000 0x00008000 // NAND FLASH
357 357
358 >; 358 >;
@@ -393,18 +393,27 @@
393 }; 393 };
394 394
395 /* Note: CAN support needs be enabled in U-Boot */ 395 /* Note: CAN support needs be enabled in U-Boot */
396 can0@2,0 { 396 can@2,0 {
397 compatible = "intel,82527"; // Bosch CC770 397 compatible = "bosch,cc770"; // Bosch CC770
398 reg = <2 0x0 0x100>; 398 reg = <2 0x0 0x100>;
399 interrupts = <4 1>; 399 interrupts = <4 1>;
400 interrupt-parent = <&mpic>; 400 interrupt-parent = <&mpic>;
401 bosch,external-clock-frequency = <16000000>;
402 bosch,disconnect-rx1-input;
403 bosch,disconnect-tx1-output;
404 bosch,iso-low-speed-mux;
405 bosch,clock-out-frequency = <16000000>;
401 }; 406 };
402 407
403 can1@2,100 { 408 can@2,100 {
404 compatible = "intel,82527"; // Bosch CC770 409 compatible = "bosch,cc770"; // Bosch CC770
405 reg = <2 0x100 0x100>; 410 reg = <2 0x100 0x100>;
406 interrupts = <4 1>; 411 interrupts = <4 1>;
407 interrupt-parent = <&mpic>; 412 interrupt-parent = <&mpic>;
413 bosch,external-clock-frequency = <16000000>;
414 bosch,disconnect-rx1-input;
415 bosch,disconnect-tx1-output;
416 bosch,iso-low-speed-mux;
408 }; 417 };
409 418
410 /* Note: NAND support needs to be enabled in U-Boot */ 419 /* Note: NAND support needs to be enabled in U-Boot */
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index 81bad8cd3756..aa6ff0d3dd9a 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -224,7 +224,7 @@
224 serial0: serial@4500 { 224 serial0: serial@4500 {
225 cell-index = <0>; 225 cell-index = <0>;
226 device_type = "serial"; 226 device_type = "serial";
227 compatible = "ns16550"; 227 compatible = "fsl,ns16550", "ns16550";
228 reg = <0x4500 0x100>; // reg base, size 228 reg = <0x4500 0x100>; // reg base, size
229 clock-frequency = <0>; // should we fill in in uboot? 229 clock-frequency = <0>; // should we fill in in uboot?
230 interrupts = <42 2>; 230 interrupts = <42 2>;
@@ -234,7 +234,7 @@
234 serial1: serial@4600 { 234 serial1: serial@4600 {
235 cell-index = <1>; 235 cell-index = <1>;
236 device_type = "serial"; 236 device_type = "serial";
237 compatible = "ns16550"; 237 compatible = "fsl,ns16550", "ns16550";
238 reg = <0x4600 0x100>; // reg base, size 238 reg = <0x4600 0x100>; // reg base, size
239 clock-frequency = <0>; // should we fill in in uboot? 239 clock-frequency = <0>; // should we fill in in uboot?
240 interrupts = <42 2>; 240 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/tqm8xx.dts b/arch/powerpc/boot/dts/tqm8xx.dts
index f6da7ec49a8e..c3dba2518d8c 100644
--- a/arch/powerpc/boot/dts/tqm8xx.dts
+++ b/arch/powerpc/boot/dts/tqm8xx.dts
@@ -57,6 +57,7 @@
57 57
58 ranges = < 58 ranges = <
59 0x0 0x0 0x40000000 0x800000 59 0x0 0x0 0x40000000 0x800000
60 0x3 0x0 0xc0000000 0x200
60 >; 61 >;
61 62
62 flash@0,0 { 63 flash@0,0 {
@@ -67,6 +68,30 @@
67 bank-width = <4>; 68 bank-width = <4>;
68 device-width = <2>; 69 device-width = <2>;
69 }; 70 };
71
72 /* Note: CAN support needs be enabled in U-Boot */
73 can@3,0 {
74 compatible = "intc,82527";
75 reg = <3 0x0 0x80>;
76 interrupts = <8 1>;
77 interrupt-parent = <&PIC>;
78 bosch,external-clock-frequency = <16000000>;
79 bosch,disconnect-rx1-input;
80 bosch,disconnect-tx1-output;
81 bosch,iso-low-speed-mux;
82 bosch,clock-out-frequency = <16000000>;
83 };
84
85 can@3,100 {
86 compatible = "intc,82527";
87 reg = <3 0x100 0x80>;
88 interrupts = <8 1>;
89 interrupt-parent = <&PIC>;
90 bosch,external-clock-frequency = <16000000>;
91 bosch,disconnect-rx1-input;
92 bosch,disconnect-tx1-output;
93 bosch,iso-low-speed-mux;
94 };
70 }; 95 };
71 96
72 soc@fff00000 { 97 soc@fff00000 {
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts
index ac0a617b4299..cc00f4ddd9a7 100644
--- a/arch/powerpc/boot/dts/xcalibur1501.dts
+++ b/arch/powerpc/boot/dts/xcalibur1501.dts
@@ -531,7 +531,7 @@
531 serial0: serial@4500 { 531 serial0: serial@4500 {
532 cell-index = <0>; 532 cell-index = <0>;
533 device_type = "serial"; 533 device_type = "serial";
534 compatible = "ns16550"; 534 compatible = "fsl,ns16550", "ns16550";
535 reg = <0x4500 0x100>; 535 reg = <0x4500 0x100>;
536 clock-frequency = <0>; 536 clock-frequency = <0>;
537 interrupts = <42 2>; 537 interrupts = <42 2>;
@@ -542,7 +542,7 @@
542 serial1: serial@4600 { 542 serial1: serial@4600 {
543 cell-index = <1>; 543 cell-index = <1>;
544 device_type = "serial"; 544 device_type = "serial";
545 compatible = "ns16550"; 545 compatible = "fsl,ns16550", "ns16550";
546 reg = <0x4600 0x100>; 546 reg = <0x4600 0x100>;
547 clock-frequency = <0>; 547 clock-frequency = <0>;
548 interrupts = <42 2>; 548 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5200.dts b/arch/powerpc/boot/dts/xpedite5200.dts
index c41a80c55e47..8fd7b7031357 100644
--- a/arch/powerpc/boot/dts/xpedite5200.dts
+++ b/arch/powerpc/boot/dts/xpedite5200.dts
@@ -333,7 +333,7 @@
333 serial0: serial@4500 { 333 serial0: serial@4500 {
334 cell-index = <0>; 334 cell-index = <0>;
335 device_type = "serial"; 335 device_type = "serial";
336 compatible = "ns16550"; 336 compatible = "fsl,ns16550", "ns16550";
337 reg = <0x4500 0x100>; 337 reg = <0x4500 0x100>;
338 clock-frequency = <0>; 338 clock-frequency = <0>;
339 current-speed = <115200>; 339 current-speed = <115200>;
@@ -344,7 +344,7 @@
344 serial1: serial@4600 { 344 serial1: serial@4600 {
345 cell-index = <1>; 345 cell-index = <1>;
346 device_type = "serial"; 346 device_type = "serial";
347 compatible = "ns16550"; 347 compatible = "fsl,ns16550", "ns16550";
348 reg = <0x4600 0x100>; 348 reg = <0x4600 0x100>;
349 clock-frequency = <0>; 349 clock-frequency = <0>;
350 current-speed = <115200>; 350 current-speed = <115200>;
diff --git a/arch/powerpc/boot/dts/xpedite5200_xmon.dts b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
index c0efcbb45137..0baa8283d08c 100644
--- a/arch/powerpc/boot/dts/xpedite5200_xmon.dts
+++ b/arch/powerpc/boot/dts/xpedite5200_xmon.dts
@@ -337,7 +337,7 @@
337 serial0: serial@4500 { 337 serial0: serial@4500 {
338 cell-index = <0>; 338 cell-index = <0>;
339 device_type = "serial"; 339 device_type = "serial";
340 compatible = "ns16550"; 340 compatible = "fsl,ns16550", "ns16550";
341 reg = <0x4500 0x100>; 341 reg = <0x4500 0x100>;
342 clock-frequency = <0>; 342 clock-frequency = <0>;
343 current-speed = <9600>; 343 current-speed = <9600>;
@@ -348,7 +348,7 @@
348 serial1: serial@4600 { 348 serial1: serial@4600 {
349 cell-index = <1>; 349 cell-index = <1>;
350 device_type = "serial"; 350 device_type = "serial";
351 compatible = "ns16550"; 351 compatible = "fsl,ns16550", "ns16550";
352 reg = <0x4600 0x100>; 352 reg = <0x4600 0x100>;
353 clock-frequency = <0>; 353 clock-frequency = <0>;
354 current-speed = <9600>; 354 current-speed = <9600>;
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts
index db7faf5ebb39..53c1c6a9752f 100644
--- a/arch/powerpc/boot/dts/xpedite5301.dts
+++ b/arch/powerpc/boot/dts/xpedite5301.dts
@@ -441,7 +441,7 @@
441 serial0: serial@4500 { 441 serial0: serial@4500 {
442 cell-index = <0>; 442 cell-index = <0>;
443 device_type = "serial"; 443 device_type = "serial";
444 compatible = "ns16550"; 444 compatible = "fsl,ns16550", "ns16550";
445 reg = <0x4500 0x100>; 445 reg = <0x4500 0x100>;
446 clock-frequency = <0>; 446 clock-frequency = <0>;
447 interrupts = <42 2>; 447 interrupts = <42 2>;
@@ -452,7 +452,7 @@
452 serial1: serial@4600 { 452 serial1: serial@4600 {
453 cell-index = <1>; 453 cell-index = <1>;
454 device_type = "serial"; 454 device_type = "serial";
455 compatible = "ns16550"; 455 compatible = "fsl,ns16550", "ns16550";
456 reg = <0x4600 0x100>; 456 reg = <0x4600 0x100>;
457 clock-frequency = <0>; 457 clock-frequency = <0>;
458 interrupts = <42 2>; 458 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts
index c364ca6ff7d0..215225983150 100644
--- a/arch/powerpc/boot/dts/xpedite5330.dts
+++ b/arch/powerpc/boot/dts/xpedite5330.dts
@@ -477,7 +477,7 @@
477 serial0: serial@4500 { 477 serial0: serial@4500 {
478 cell-index = <0>; 478 cell-index = <0>;
479 device_type = "serial"; 479 device_type = "serial";
480 compatible = "ns16550"; 480 compatible = "fsl,ns16550", "ns16550";
481 reg = <0x4500 0x100>; 481 reg = <0x4500 0x100>;
482 clock-frequency = <0>; 482 clock-frequency = <0>;
483 interrupts = <42 2>; 483 interrupts = <42 2>;
@@ -488,7 +488,7 @@
488 serial1: serial@4600 { 488 serial1: serial@4600 {
489 cell-index = <1>; 489 cell-index = <1>;
490 device_type = "serial"; 490 device_type = "serial";
491 compatible = "ns16550"; 491 compatible = "fsl,ns16550", "ns16550";
492 reg = <0x4600 0x100>; 492 reg = <0x4600 0x100>;
493 clock-frequency = <0>; 493 clock-frequency = <0>;
494 interrupts = <42 2>; 494 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts
index 7a8a4afd56cf..11dbda10d756 100644
--- a/arch/powerpc/boot/dts/xpedite5370.dts
+++ b/arch/powerpc/boot/dts/xpedite5370.dts
@@ -439,7 +439,7 @@
439 serial0: serial@4500 { 439 serial0: serial@4500 {
440 cell-index = <0>; 440 cell-index = <0>;
441 device_type = "serial"; 441 device_type = "serial";
442 compatible = "ns16550"; 442 compatible = "fsl,ns16550", "ns16550";
443 reg = <0x4500 0x100>; 443 reg = <0x4500 0x100>;
444 clock-frequency = <0>; 444 clock-frequency = <0>;
445 interrupts = <42 2>; 445 interrupts = <42 2>;
@@ -450,7 +450,7 @@
450 serial1: serial@4600 { 450 serial1: serial@4600 {
451 cell-index = <1>; 451 cell-index = <1>;
452 device_type = "serial"; 452 device_type = "serial";
453 compatible = "ns16550"; 453 compatible = "fsl,ns16550", "ns16550";
454 reg = <0x4600 0x100>; 454 reg = <0x4600 0x100>;
455 clock-frequency = <0>; 455 clock-frequency = <0>;
456 interrupts = <42 2>; 456 interrupts = <42 2>;
diff --git a/arch/powerpc/boot/treeboot-currituck.c b/arch/powerpc/boot/treeboot-currituck.c
new file mode 100644
index 000000000000..925ae43b7467
--- /dev/null
+++ b/arch/powerpc/boot/treeboot-currituck.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright © 2011 Tony Breeds IBM Corporation
3 *
4 * Based on earlier code:
5 * Copyright (C) Paul Mackerras 1997.
6 *
7 * Matt Porter <mporter@kernel.crashing.org>
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
11 * Copyright (c) 2003, 2004 Zultys Technologies
12 *
13 * Copyright 2007 David Gibson, IBM Corporation.
14 * Copyright 2010 Ben. Herrenschmidt, IBM Corporation.
15 * Copyright © 2011 David Kleikamp IBM Corporation
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 */
22#include <stdarg.h>
23#include <stddef.h>
24#include "types.h"
25#include "elf.h"
26#include "string.h"
27#include "stdio.h"
28#include "page.h"
29#include "ops.h"
30#include "reg.h"
31#include "io.h"
32#include "dcr.h"
33#include "4xx.h"
34#include "44x.h"
35#include "libfdt.h"
36
37BSS_STACK(4096);
38
39#define MAX_RANKS 0x4
40#define DDR3_MR0CF 0x80010011U
41
42static unsigned long long ibm_currituck_memsize;
43static unsigned long long ibm_currituck_detect_memsize(void)
44{
45 u32 reg;
46 unsigned i;
47 unsigned long long memsize = 0;
48
49 for(i = 0; i < MAX_RANKS; i++){
50 reg = mfdcrx(DDR3_MR0CF + i);
51
52 if (!(reg & 1))
53 continue;
54
55 reg &= 0x0000f000;
56 reg >>= 12;
57 memsize += (0x800000ULL << reg);
58 }
59
60 return memsize;
61}
62
63static void ibm_currituck_fixups(void)
64{
65 void *devp = finddevice("/");
66 u32 dma_ranges[7];
67
68 dt_fixup_memory(0x0ULL, ibm_currituck_memsize);
69
70 while ((devp = find_node_by_devtype(devp, "pci"))) {
71 if (getprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges)) < 0) {
72 printf("%s: Failed to get dma-ranges\r\n", __func__);
73 continue;
74 }
75
76 dma_ranges[5] = ibm_currituck_memsize >> 32;
77 dma_ranges[6] = ibm_currituck_memsize & 0xffffffffUL;
78
79 setprop(devp, "dma-ranges", dma_ranges, sizeof(dma_ranges));
80 }
81}
82
83#define SPRN_PIR 0x11E /* Processor Indentification Register */
84void platform_init(void)
85{
86 unsigned long end_of_ram, avail_ram;
87 u32 pir_reg;
88 int node, size;
89 const u32 *timebase;
90
91 ibm_currituck_memsize = ibm_currituck_detect_memsize();
92 if (ibm_currituck_memsize >> 32)
93 end_of_ram = ~0UL;
94 else
95 end_of_ram = ibm_currituck_memsize;
96 avail_ram = end_of_ram - (unsigned long)_end;
97
98 simple_alloc_init(_end, avail_ram, 128, 64);
99 platform_ops.fixups = ibm_currituck_fixups;
100 platform_ops.exit = ibm44x_dbcr_reset;
101 pir_reg = mfspr(SPRN_PIR);
102
103 /* Make sure FDT blob is sane */
104 if (fdt_check_header(_dtb_start) != 0)
105 fatal("Invalid device tree blob\n");
106
107 node = fdt_node_offset_by_prop_value(_dtb_start, -1, "device_type",
108 "cpu", sizeof("cpu"));
109 if (!node)
110 fatal("Cannot find cpu node\n");
111 timebase = fdt_getprop(_dtb_start, node, "timebase-frequency", &size);
112 if (timebase && (size == 4))
113 timebase_period_ns = 1000000000 / *timebase;
114
115 fdt_set_boot_cpuid_phys(_dtb_start, pir_reg);
116 fdt_init(_dtb_start);
117
118 serial_console_init();
119}
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index c74531af72c0..f090e6d2907e 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -163,7 +163,7 @@ coff)
163 link_address='0x500000' 163 link_address='0x500000'
164 pie= 164 pie=
165 ;; 165 ;;
166miboot|uboot) 166miboot|uboot*)
167 # miboot and U-boot want just the bare bits, not an ELF binary 167 # miboot and U-boot want just the bare bits, not an ELF binary
168 ext=bin 168 ext=bin
169 objflags="-O binary" 169 objflags="-O binary"
@@ -244,6 +244,9 @@ gamecube|wii)
244 link_address='0x600000' 244 link_address='0x600000'
245 platformo="$object/$platform-head.o $object/$platform.o" 245 platformo="$object/$platform-head.o $object/$platform.o"
246 ;; 246 ;;
247treeboot-currituck)
248 link_address='0x1000000'
249 ;;
247treeboot-iss4xx-mpic) 250treeboot-iss4xx-mpic)
248 platformo="$object/treeboot-iss4xx.o" 251 platformo="$object/treeboot-iss4xx.o"
249 ;; 252 ;;
@@ -257,6 +260,8 @@ vmz="$tmpdir/`basename \"$kernel\"`.$ext"
257if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then 260if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
258 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$" 261 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
259 262
263 strip_size=$(stat -c %s $vmz.$$)
264
260 if [ -n "$gzip" ]; then 265 if [ -n "$gzip" ]; then
261 gzip -n -f -9 "$vmz.$$" 266 gzip -n -f -9 "$vmz.$$"
262 fi 267 fi
@@ -266,6 +271,24 @@ if [ -z "$cacheit" -o ! -f "$vmz$gzip" -o "$vmz$gzip" -ot "$kernel" ]; then
266 else 271 else
267 vmz="$vmz.$$" 272 vmz="$vmz.$$"
268 fi 273 fi
274else
275 # Calculate the vmlinux.strip size
276 ${CROSS}objcopy $objflags "$kernel" "$vmz.$$"
277 strip_size=$(stat -c %s $vmz.$$)
278 rm -f $vmz.$$
279fi
280
281# Round the size to next higher MB limit
282round_size=$(((strip_size + 0xfffff) & 0xfff00000))
283
284round_size=0x$(printf "%x" $round_size)
285link_addr=$(printf "%d" $link_address)
286
287if [ $link_addr -lt $strip_size ]; then
288 echo "INFO: Uncompressed kernel (size 0x$(printf "%x\n" $strip_size))" \
289 "overlaps the address of the wrapper($link_address)"
290 echo "INFO: Fixing the link_address of wrapper to ($round_size)"
291 link_address=$round_size
269fi 292fi
270 293
271vmz="$vmz$gzip" 294vmz="$vmz$gzip"
@@ -291,6 +314,26 @@ uboot)
291 fi 314 fi
292 exit 0 315 exit 0
293 ;; 316 ;;
317uboot-obs600)
318 rm -f "$ofile"
319 # obs600 wants a multi image with an initrd, so we need to put a fake
320 # one in even when building a "normal" image.
321 if [ -n "$initrd" ]; then
322 real_rd="$initrd"
323 else
324 real_rd=`mktemp`
325 echo "\0" >>"$real_rd"
326 fi
327 ${MKIMAGE} -A ppc -O linux -T multi -C gzip -a $membase -e $membase \
328 $uboot_version -d "$vmz":"$real_rd":"$dtb" "$ofile"
329 if [ -z "$initrd" ]; then
330 rm -f "$real_rd"
331 fi
332 if [ -z "$cacheit" ]; then
333 rm -f "$vmz"
334 fi
335 exit 0
336 ;;
294esac 337esac
295 338
296addsec() { 339addsec() {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 14:28:12 -0400