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authorJohn Bonesio <bones@secretlab.ca>2010-11-17 18:28:56 -0500
committerGrant Likely <grant.likely@secretlab.ca>2011-01-03 18:02:51 -0500
commitc8bf6b52af670496f1e8145600e74a3ef3942a4c (patch)
treeb71d89f0f2092ecfcedf72367b804b05b2229f45 /arch/powerpc/boot/dts/motionpro.dts
parent11946c826d02a16521edc777d88470a6a0fe1441 (diff)
powerpc/5200: dts: refactor dts files
This patch creates mpc5200b.dtsi containing the information for the MPC5200b SoC then modifies all of the dts files for MPC5200b based systems to use mpc5200b.dtsi. Signed-off-by: John Bonesio <bones@secretlab.ca> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/powerpc/boot/dts/motionpro.dts')
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts190
1 files changed, 24 insertions, 166 deletions
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 97cb08598a4a..0b78e89ac69b 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,219 +10,73 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/dts-v1/; 13/include/ "mpc5200b.dtsi"
14 14
15/ { 15/ {
16 model = "promess,motionpro"; 16 model = "promess,motionpro";
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>;
19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 PowerPC,5200@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>;
30 i-cache-line-size = <32>;
31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
33 timebase-frequency = <0>; // from bootloader
34 bus-frequency = <0>; // from bootloader
35 clock-frequency = <0>; // from bootloader
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0x00000000 0x04000000>; // 64MB
42 };
43 18
44 soc5200@f0000000 { 19 soc5200@f0000000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 compatible = "fsl,mpc5200b-immr";
48 ranges = <0 0xf0000000 0x0000c000>;
49 reg = <0xf0000000 0x00000100>;
50 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; // from bootloader
52
53 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55 reg = <0x200 0x38>;
56 };
57
58 mpc5200_pic: interrupt-controller@500 {
59 // 5200 interrupts are encoded into two levels;
60 interrupt-controller;
61 #interrupt-cells = <3>;
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>;
64 };
65
66 timer@600 { // General Purpose Timer 20 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 reg = <0x600 0x10>;
69 interrupts = <1 9 0>;
70 fsl,has-wdt; 21 fsl,has-wdt;
71 }; 22 };
72 23
73 timer@610 { // General Purpose Timer
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>;
77 };
78
79 timer@620 { // General Purpose Timer
80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
81 reg = <0x620 0x10>;
82 interrupts = <1 11 0>;
83 };
84
85 timer@630 { // General Purpose Timer
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
87 reg = <0x630 0x10>;
88 interrupts = <1 12 0>;
89 };
90
91 timer@640 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 reg = <0x640 0x10>;
94 interrupts = <1 13 0>;
95 };
96
97 timer@650 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 reg = <0x650 0x10>;
100 interrupts = <1 14 0>;
101 };
102
103 timer@660 { // Motion-PRO status LED 24 timer@660 { // Motion-PRO status LED
104 compatible = "promess,motionpro-led"; 25 compatible = "promess,motionpro-led";
105 label = "motionpro-statusled"; 26 label = "motionpro-statusled";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 blink-delay = <100>; // 100 msec 27 blink-delay = <100>; // 100 msec
109 }; 28 };
110 29
111 timer@670 { // Motion-PRO ready LED 30 timer@670 { // Motion-PRO ready LED
112 compatible = "promess,motionpro-led"; 31 compatible = "promess,motionpro-led";
113 label = "motionpro-readyled"; 32 label = "motionpro-readyled";
114 reg = <0x670 0x10>;
115 interrupts = <1 16 0>;
116 };
117
118 rtc@800 { // Real time clock
119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
120 reg = <0x800 0x100>;
121 interrupts = <1 5 0 1 6 0>;
122 };
123
124 can@980 {
125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
126 interrupts = <2 18 0>;
127 reg = <0x980 0x80>;
128 }; 33 };
129 34
130 gpio_simple: gpio@b00 { 35 can@900 {
131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 36 status = "disabled";
132 reg = <0xb00 0x40>;
133 interrupts = <1 7 0>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 };
137
138 gpio_wkup: gpio@c00 {
139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
140 reg = <0xc00 0x40>;
141 interrupts = <1 8 0 0 3 0>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145
146 spi@f00 {
147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
148 reg = <0xf00 0x20>;
149 interrupts = <2 13 0 2 14 0>;
150 };
151
152 usb@1000 {
153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
154 reg = <0x1000 0xff>;
155 interrupts = <2 6 0>;
156 };
157
158 dma-controller@1200 {
159 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
160 reg = <0x1200 0x80>;
161 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
162 3 4 0 3 5 0 3 6 0 3 7 0
163 3 8 0 3 9 0 3 10 0 3 11 0
164 3 12 0 3 13 0 3 14 0 3 15 0>;
165 };
166
167 xlb@1f00 {
168 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
169 reg = <0x1f00 0x100>;
170 }; 37 };
171 38
172 psc@2000 { // PSC1 39 psc@2000 { // PSC1
173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
174 reg = <0x2000 0x100>;
175 interrupts = <2 1 0>;
176 }; 41 };
177 42
178 // PSC2 in spi master mode 43 // PSC2 in spi master mode
179 psc@2200 { // PSC2 44 psc@2200 { // PSC2
180 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi"; 45 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
181 cell-index = <1>; 46 cell-index = <1>;
182 reg = <0x2200 0x100>;
183 interrupts = <2 2 0>;
184 }; 47 };
185 48
186 // PSC5 in uart mode 49 psc@2400 { // PSC3
50 status = "disabled";
51 };
52
53 psc@2600 { // PSC4
54 status = "disabled";
55 };
56
187 psc@2800 { // PSC5 57 psc@2800 { // PSC5
188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
189 reg = <0x2800 0x100>; 59 };
190 interrupts = <2 12 0>; 60
61 psc@2c00 { // PSC6
62 status = "disabled";
191 }; 63 };
192 64
193 ethernet@3000 { 65 ethernet@3000 {
194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
195 reg = <0x3000 0x400>;
196 local-mac-address = [ 00 00 00 00 00 00 ];
197 interrupts = <2 5 0>;
198 phy-handle = <&phy0>; 66 phy-handle = <&phy0>;
199 }; 67 };
200 68
201 mdio@3000 { 69 mdio@3000 {
202 #address-cells = <1>;
203 #size-cells = <0>;
204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
207
208 phy0: ethernet-phy@2 { 70 phy0: ethernet-phy@2 {
209 reg = <2>; 71 reg = <2>;
210 }; 72 };
211 }; 73 };
212 74
213 ata@3a00 { 75 i2c@3d00 {
214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 76 status = "disabled";
215 reg = <0x3a00 0x100>;
216 interrupts = <2 7 0>;
217 }; 77 };
218 78
219 i2c@3d40 { 79 i2c@3d40 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
223 reg = <0x3d40 0x40>;
224 interrupts = <2 16 0>;
225
226 rtc@68 { 80 rtc@68 {
227 compatible = "dallas,ds1339"; 81 compatible = "dallas,ds1339";
228 reg = <0x68>; 82 reg = <0x68>;
@@ -235,10 +89,11 @@
235 }; 89 };
236 }; 90 };
237 91
92 pci@f0000d00 {
93 status = "disabled";
94 };
95
238 localbus { 96 localbus {
239 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
240 #address-cells = <2>;
241 #size-cells = <1>;
242 ranges = <0 0 0xff000000 0x01000000 97 ranges = <0 0 0xff000000 0x01000000
243 1 0 0x50000000 0x00010000 98 1 0 0x50000000 0x00010000
244 2 0 0x50010000 0x00010000 99 2 0 0x50010000 0x00010000
@@ -277,6 +132,9 @@
277 reg = <0 0 0x01000000>; 132 reg = <0 0 0x01000000>;
278 bank-width = <2>; 133 bank-width = <2>;
279 device-width = <2>; 134 device-width = <2>;
135 #size-cells = <1>;
136 #address-cells = <1>;
280 }; 137 };
138
281 }; 139 };
282}; 140};