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authorDavid Woodhouse <dwmw2@infradead.org>2007-01-17 18:34:51 -0500
committerDavid Woodhouse <dwmw2@infradead.org>2007-01-17 18:34:51 -0500
commit9cdf083f981b8d37b3212400a359368661385099 (patch)
treeaa15a6a08ad87e650dea40fb59b3180bef0d345b /arch/mips
parente499e01d234a31d59679b7b1e1cf628d917ba49a (diff)
parenta8b3485287731978899ced11f24628c927890e78 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/Kconfig92
-rw-r--r--arch/mips/Makefile19
-rw-r--r--arch/mips/au1000/common/irq.c63
-rw-r--r--arch/mips/au1000/common/pci.c8
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/cobalt/irq.c31
-rw-r--r--arch/mips/cobalt/setup.c16
-rw-r--r--arch/mips/configs/atlas_defconfig2
-rw-r--r--arch/mips/configs/bigsur_defconfig2
-rw-r--r--arch/mips/configs/capcella_defconfig2
-rw-r--r--arch/mips/configs/cobalt_defconfig2
-rw-r--r--arch/mips/configs/db1000_defconfig2
-rw-r--r--arch/mips/configs/db1100_defconfig2
-rw-r--r--arch/mips/configs/db1200_defconfig2
-rw-r--r--arch/mips/configs/db1500_defconfig2
-rw-r--r--arch/mips/configs/db1550_defconfig2
-rw-r--r--arch/mips/configs/ddb5477_defconfig2
-rw-r--r--arch/mips/configs/decstation_defconfig2
-rw-r--r--arch/mips/configs/e55_defconfig2
-rw-r--r--arch/mips/configs/emma2rh_defconfig2
-rw-r--r--arch/mips/configs/ev64120_defconfig2
-rw-r--r--arch/mips/configs/excite_defconfig2
-rw-r--r--arch/mips/configs/ip22_defconfig2
-rw-r--r--arch/mips/configs/ip27_defconfig2
-rw-r--r--arch/mips/configs/ip32_defconfig2
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig2
-rw-r--r--arch/mips/configs/jazz_defconfig2
-rw-r--r--arch/mips/configs/jmr3927_defconfig2
-rw-r--r--arch/mips/configs/lasat200_defconfig2
-rw-r--r--arch/mips/configs/malta_defconfig82
-rw-r--r--arch/mips/configs/mipssim_defconfig2
-rw-r--r--arch/mips/configs/mpc30x_defconfig2
-rw-r--r--arch/mips/configs/ocelot_3_defconfig2
-rw-r--r--arch/mips/configs/ocelot_c_defconfig2
-rw-r--r--arch/mips/configs/ocelot_defconfig2
-rw-r--r--arch/mips/configs/ocelot_g_defconfig2
-rw-r--r--arch/mips/configs/pb1100_defconfig2
-rw-r--r--arch/mips/configs/pb1500_defconfig2
-rw-r--r--arch/mips/configs/pb1550_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig2
-rw-r--r--arch/mips/configs/pnx8550-stb810_defconfig1229
-rw-r--r--arch/mips/configs/pnx8550-v2pci_defconfig2
-rw-r--r--arch/mips/configs/qemu_defconfig2
-rw-r--r--arch/mips/configs/rbhma4500_defconfig2
-rw-r--r--arch/mips/configs/rm200_defconfig2
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig2
-rw-r--r--arch/mips/configs/sead_defconfig2
-rw-r--r--arch/mips/configs/tb0226_defconfig2
-rw-r--r--arch/mips/configs/tb0229_defconfig2
-rw-r--r--arch/mips/configs/tb0287_defconfig2
-rw-r--r--arch/mips/configs/workpad_defconfig2
-rw-r--r--arch/mips/configs/wrppmc_defconfig2
-rw-r--r--arch/mips/configs/yosemite_defconfig2
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c23
-rw-r--r--arch/mips/dec/ecc-berr.c7
-rw-r--r--arch/mips/dec/int-handler.S2
-rw-r--r--arch/mips/dec/ioasic-irq.c74
-rw-r--r--arch/mips/dec/kn01-berr.c2
-rw-r--r--arch/mips/dec/kn02-irq.c58
-rw-r--r--arch/mips/dec/setup.c6
-rw-r--r--arch/mips/dec/time.c4
-rw-r--r--arch/mips/defconfig2
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c42
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c63
-rw-r--r--arch/mips/gt64120/ev64120/irq.c40
-rw-r--r--arch/mips/jazz/irq.c34
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c32
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c4
-rw-r--r--arch/mips/kernel/Makefile3
-rw-r--r--arch/mips/kernel/apm.c2
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c1
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c1
-rw-r--r--arch/mips/kernel/cpu-probe.c19
-rw-r--r--arch/mips/kernel/dma-no-isa.c28
-rw-r--r--arch/mips/kernel/genex.S63
-rw-r--r--arch/mips/kernel/head.S5
-rw-r--r--arch/mips/kernel/i8259.c179
-rw-r--r--arch/mips/kernel/irixelf.c10
-rw-r--r--arch/mips/kernel/irq-msc01.c47
-rw-r--r--arch/mips/kernel/irq-mv6434x.c64
-rw-r--r--arch/mips/kernel/irq-rm7000.c61
-rw-r--r--arch/mips/kernel/irq-rm9000.c55
-rw-r--r--arch/mips/kernel/irq.c34
-rw-r--r--arch/mips/kernel/irq_cpu.c90
-rw-r--r--arch/mips/kernel/kspd.c6
-rw-r--r--arch/mips/kernel/linux32.c586
-rw-r--r--arch/mips/kernel/machine_kexec.c85
-rw-r--r--arch/mips/kernel/mips_ksyms.c2
-rw-r--r--arch/mips/kernel/module.c15
-rw-r--r--arch/mips/kernel/relocate_kernel.S80
-rw-r--r--arch/mips/kernel/reset.c2
-rw-r--r--arch/mips/kernel/rtlx.c6
-rw-r--r--arch/mips/kernel/scall32-o32.S2
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S16
-rw-r--r--arch/mips/kernel/scall64-o32.S2
-rw-r--r--arch/mips/kernel/setup.c87
-rw-r--r--arch/mips/kernel/signal_n32.c1
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smp.c8
-rw-r--r--arch/mips/kernel/smtc.c1
-rw-r--r--arch/mips/kernel/sysirix.c10
-rw-r--r--arch/mips/kernel/time.c66
-rw-r--r--arch/mips/kernel/traps.c72
-rw-r--r--arch/mips/kernel/vmlinux.lds.S2
-rw-r--r--arch/mips/kernel/vpe.c2
-rw-r--r--arch/mips/lasat/interrupt.c43
-rw-r--r--arch/mips/lasat/sysctl.c23
-rw-r--r--arch/mips/lib-32/Makefile2
-rw-r--r--arch/mips/lib-32/csum_partial.S240
-rw-r--r--arch/mips/lib-64/Makefile2
-rw-r--r--arch/mips/lib-64/csum_partial.S242
-rw-r--r--arch/mips/lib/Makefile4
-rw-r--r--arch/mips/lib/csum_partial.S715
-rw-r--r--arch/mips/lib/csum_partial_copy.c49
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c29
-rw-r--r--arch/mips/mips-boards/generic/time.c10
-rw-r--r--arch/mips/mips-boards/malta/Makefile2
-rw-r--r--arch/mips/mips-boards/malta/malta_mtd.c63
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c39
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c4
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c18
-rw-r--r--arch/mips/mm/c-r4k.c22
-rw-r--r--arch/mips/mm/cache.c1
-rw-r--r--arch/mips/mm/dma-coherent.c4
-rw-r--r--arch/mips/mm/dma-ip27.c4
-rw-r--r--arch/mips/mm/dma-ip32.c5
-rw-r--r--arch/mips/mm/dma-noncoherent.c5
-rw-r--r--arch/mips/mm/fault.c4
-rw-r--r--arch/mips/mm/highmem.c10
-rw-r--r--arch/mips/mm/init.c84
-rw-r--r--arch/mips/mm/ioremap.c96
-rw-r--r--arch/mips/mm/pg-r4k.c9
-rw-r--r--arch/mips/mm/pgtable-64.c3
-rw-r--r--arch/mips/mm/tlbex.c55
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c63
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c66
-rw-r--r--arch/mips/oprofile/Makefile1
-rw-r--r--arch/mips/oprofile/common.c3
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c32
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-cobalt.c11
-rw-r--r--arch/mips/pci/fixup-pnx8550.c4
-rw-r--r--arch/mips/pci/ops-gt64111.c16
-rw-r--r--arch/mips/pci/ops-pnx8550.c2
-rw-r--r--arch/mips/philips/pnx8550/common/int.c74
-rw-r--r--arch/mips/philips/pnx8550/common/prom.c20
-rw-r--r--arch/mips/philips/pnx8550/common/time.c45
-rw-r--r--arch/mips/philips/pnx8550/jbs/irqmap.c8
-rw-r--r--arch/mips/philips/pnx8550/stb810/Makefile4
-rw-r--r--arch/mips/philips/pnx8550/stb810/board_setup.c49
-rw-r--r--arch/mips/philips/pnx8550/stb810/irqmap.c23
-rw-r--r--arch/mips/philips/pnx8550/stb810/prom_init.c49
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c33
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c137
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c25
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c37
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c133
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c30
-rw-r--r--arch/mips/sibyte/bcm1480/time.c6
-rw-r--r--arch/mips/sibyte/sb1250/irq.c30
-rw-r--r--arch/mips/sibyte/sb1250/time.c8
-rw-r--r--arch/mips/sibyte/swarm/setup.c8
-rw-r--r--arch/mips/sni/irq.c40
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c190
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c230
-rw-r--r--arch/mips/tx4938/common/irq.c135
-rw-r--r--arch/mips/tx4938/common/setup.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c64
-rw-r--r--arch/mips/vr41xx/common/icu.c62
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c27
172 files changed, 3528 insertions, 3675 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1443024b1c7c..fd2ff0698a85 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -16,6 +16,7 @@ config MIPS_MTX1
16 bool "4G Systems MTX-1 board" 16 bool "4G Systems MTX-1 board"
17 select DMA_NONCOHERENT 17 select DMA_NONCOHERENT
18 select HW_HAS_PCI 18 select HW_HAS_PCI
19 select RESOURCES_64BIT if PCI
19 select SOC_AU1500 20 select SOC_AU1500
20 select SYS_HAS_CPU_MIPS32_R1 21 select SYS_HAS_CPU_MIPS32_R1
21 select SYS_SUPPORTS_LITTLE_ENDIAN 22 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -32,6 +33,7 @@ config MIPS_PB1000
32 select SOC_AU1000 33 select SOC_AU1000
33 select DMA_NONCOHERENT 34 select DMA_NONCOHERENT
34 select HW_HAS_PCI 35 select HW_HAS_PCI
36 select RESOURCES_64BIT if PCI
35 select SWAP_IO_SPACE 37 select SWAP_IO_SPACE
36 select SYS_HAS_CPU_MIPS32_R1 38 select SYS_HAS_CPU_MIPS32_R1
37 select SYS_SUPPORTS_LITTLE_ENDIAN 39 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -41,6 +43,7 @@ config MIPS_PB1100
41 select SOC_AU1100 43 select SOC_AU1100
42 select DMA_NONCOHERENT 44 select DMA_NONCOHERENT
43 select HW_HAS_PCI 45 select HW_HAS_PCI
46 select RESOURCES_64BIT if PCI
44 select SWAP_IO_SPACE 47 select SWAP_IO_SPACE
45 select SYS_HAS_CPU_MIPS32_R1 48 select SYS_HAS_CPU_MIPS32_R1
46 select SYS_SUPPORTS_LITTLE_ENDIAN 49 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -50,6 +53,7 @@ config MIPS_PB1500
50 select SOC_AU1500 53 select SOC_AU1500
51 select DMA_NONCOHERENT 54 select DMA_NONCOHERENT
52 select HW_HAS_PCI 55 select HW_HAS_PCI
56 select RESOURCES_64BIT if PCI
53 select SYS_HAS_CPU_MIPS32_R1 57 select SYS_HAS_CPU_MIPS32_R1
54 select SYS_SUPPORTS_LITTLE_ENDIAN 58 select SYS_SUPPORTS_LITTLE_ENDIAN
55 59
@@ -59,6 +63,7 @@ config MIPS_PB1550
59 select DMA_NONCOHERENT 63 select DMA_NONCOHERENT
60 select HW_HAS_PCI 64 select HW_HAS_PCI
61 select MIPS_DISABLE_OBSOLETE_IDE 65 select MIPS_DISABLE_OBSOLETE_IDE
66 select RESOURCES_64BIT if PCI
62 select SYS_HAS_CPU_MIPS32_R1 67 select SYS_HAS_CPU_MIPS32_R1
63 select SYS_SUPPORTS_LITTLE_ENDIAN 68 select SYS_SUPPORTS_LITTLE_ENDIAN
64 69
@@ -67,6 +72,7 @@ config MIPS_PB1200
67 select SOC_AU1200 72 select SOC_AU1200
68 select DMA_NONCOHERENT 73 select DMA_NONCOHERENT
69 select MIPS_DISABLE_OBSOLETE_IDE 74 select MIPS_DISABLE_OBSOLETE_IDE
75 select RESOURCES_64BIT if PCI
70 select SYS_HAS_CPU_MIPS32_R1 76 select SYS_HAS_CPU_MIPS32_R1
71 select SYS_SUPPORTS_LITTLE_ENDIAN 77 select SYS_SUPPORTS_LITTLE_ENDIAN
72 78
@@ -75,6 +81,7 @@ config MIPS_DB1000
75 select SOC_AU1000 81 select SOC_AU1000
76 select DMA_NONCOHERENT 82 select DMA_NONCOHERENT
77 select HW_HAS_PCI 83 select HW_HAS_PCI
84 select RESOURCES_64BIT if PCI
78 select SYS_HAS_CPU_MIPS32_R1 85 select SYS_HAS_CPU_MIPS32_R1
79 select SYS_SUPPORTS_LITTLE_ENDIAN 86 select SYS_SUPPORTS_LITTLE_ENDIAN
80 87
@@ -91,6 +98,7 @@ config MIPS_DB1500
91 select DMA_NONCOHERENT 98 select DMA_NONCOHERENT
92 select HW_HAS_PCI 99 select HW_HAS_PCI
93 select MIPS_DISABLE_OBSOLETE_IDE 100 select MIPS_DISABLE_OBSOLETE_IDE
101 select RESOURCES_64BIT if PCI
94 select SYS_HAS_CPU_MIPS32_R1 102 select SYS_HAS_CPU_MIPS32_R1
95 select SYS_SUPPORTS_BIG_ENDIAN 103 select SYS_SUPPORTS_BIG_ENDIAN
96 select SYS_SUPPORTS_LITTLE_ENDIAN 104 select SYS_SUPPORTS_LITTLE_ENDIAN
@@ -101,6 +109,7 @@ config MIPS_DB1550
101 select HW_HAS_PCI 109 select HW_HAS_PCI
102 select DMA_NONCOHERENT 110 select DMA_NONCOHERENT
103 select MIPS_DISABLE_OBSOLETE_IDE 111 select MIPS_DISABLE_OBSOLETE_IDE
112 select RESOURCES_64BIT if PCI
104 select SYS_HAS_CPU_MIPS32_R1 113 select SYS_HAS_CPU_MIPS32_R1
105 select SYS_SUPPORTS_LITTLE_ENDIAN 114 select SYS_SUPPORTS_LITTLE_ENDIAN
106 115
@@ -156,6 +165,7 @@ config MIPS_COBALT
156 select SYS_SUPPORTS_32BIT_KERNEL 165 select SYS_SUPPORTS_32BIT_KERNEL
157 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 166 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
158 select SYS_SUPPORTS_LITTLE_ENDIAN 167 select SYS_SUPPORTS_LITTLE_ENDIAN
168 select GENERIC_HARDIRQS_NO__DO_IRQ
159 169
160config MACH_DECSTATION 170config MACH_DECSTATION
161 bool "DECstations" 171 bool "DECstations"
@@ -216,6 +226,7 @@ config MACH_JAZZ
216 select SYS_SUPPORTS_32BIT_KERNEL 226 select SYS_SUPPORTS_32BIT_KERNEL
217 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 227 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
218 select SYS_SUPPORTS_100HZ 228 select SYS_SUPPORTS_100HZ
229 select GENERIC_HARDIRQS_NO__DO_IRQ
219 help 230 help
220 This a family of machines based on the MIPS R4030 chipset which was 231 This a family of machines based on the MIPS R4030 chipset which was
221 used by several vendors to build RISC/os and Windows NT workstations. 232 used by several vendors to build RISC/os and Windows NT workstations.
@@ -233,6 +244,7 @@ config LASAT
233 select SYS_SUPPORTS_32BIT_KERNEL 244 select SYS_SUPPORTS_32BIT_KERNEL
234 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 245 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
235 select SYS_SUPPORTS_LITTLE_ENDIAN 246 select SYS_SUPPORTS_LITTLE_ENDIAN
247 select GENERIC_HARDIRQS_NO__DO_IRQ
236 248
237config MIPS_ATLAS 249config MIPS_ATLAS
238 bool "MIPS Atlas board" 250 bool "MIPS Atlas board"
@@ -256,6 +268,7 @@ config MIPS_ATLAS
256 select SYS_SUPPORTS_BIG_ENDIAN 268 select SYS_SUPPORTS_BIG_ENDIAN
257 select SYS_SUPPORTS_LITTLE_ENDIAN 269 select SYS_SUPPORTS_LITTLE_ENDIAN
258 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL 270 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
271 select GENERIC_HARDIRQS_NO__DO_IRQ
259 help 272 help
260 This enables support for the MIPS Technologies Atlas evaluation 273 This enables support for the MIPS Technologies Atlas evaluation
261 board. 274 board.
@@ -266,8 +279,8 @@ config MIPS_MALTA
266 select BOOT_ELF32 279 select BOOT_ELF32
267 select HAVE_STD_PC_SERIAL_PORT 280 select HAVE_STD_PC_SERIAL_PORT
268 select DMA_NONCOHERENT 281 select DMA_NONCOHERENT
269 select IRQ_CPU
270 select GENERIC_ISA_DMA 282 select GENERIC_ISA_DMA
283 select IRQ_CPU
271 select HW_HAS_PCI 284 select HW_HAS_PCI
272 select I8259 285 select I8259
273 select MIPS_BOARDS_GEN 286 select MIPS_BOARDS_GEN
@@ -410,6 +423,7 @@ config MOMENCO_OCELOT_C
410 select SYS_SUPPORTS_32BIT_KERNEL 423 select SYS_SUPPORTS_32BIT_KERNEL
411 select SYS_SUPPORTS_64BIT_KERNEL 424 select SYS_SUPPORTS_64BIT_KERNEL
412 select SYS_SUPPORTS_BIG_ENDIAN 425 select SYS_SUPPORTS_BIG_ENDIAN
426 select GENERIC_HARDIRQS_NO__DO_IRQ
413 help 427 help
414 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 428 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
415 Momentum Computer <http://www.momenco.com/>. 429 Momentum Computer <http://www.momenco.com/>.
@@ -447,6 +461,11 @@ config PNX8550_JBS
447 select PNX8550 461 select PNX8550
448 select SYS_SUPPORTS_LITTLE_ENDIAN 462 select SYS_SUPPORTS_LITTLE_ENDIAN
449 463
464config PNX8550_STB810
465 bool "Support for Philips PNX8550 based STB810 board"
466 select PNX8550
467 select SYS_SUPPORTS_LITTLE_ENDIAN
468
450config DDB5477 469config DDB5477
451 bool "NEC DDB Vrc-5477" 470 bool "NEC DDB Vrc-5477"
452 select DDB5XXX_COMMON 471 select DDB5XXX_COMMON
@@ -470,6 +489,7 @@ config MACH_VR41XX
470 select SYS_HAS_CPU_VR41XX 489 select SYS_HAS_CPU_VR41XX
471 select SYS_SUPPORTS_32BIT_KERNEL 490 select SYS_SUPPORTS_32BIT_KERNEL
472 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL 491 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
492 select GENERIC_HARDIRQS_NO__DO_IRQ
473 493
474config PMC_YOSEMITE 494config PMC_YOSEMITE
475 bool "PMC-Sierra Yosemite eval board" 495 bool "PMC-Sierra Yosemite eval board"
@@ -503,6 +523,7 @@ config QEMU
503 select SYS_SUPPORTS_BIG_ENDIAN 523 select SYS_SUPPORTS_BIG_ENDIAN
504 select SYS_SUPPORTS_LITTLE_ENDIAN 524 select SYS_SUPPORTS_LITTLE_ENDIAN
505 select ARCH_SPARSEMEM_ENABLE 525 select ARCH_SPARSEMEM_ENABLE
526 select GENERIC_HARDIRQS_NO__DO_IRQ
506 help 527 help
507 Qemu is a software emulator which among other architectures also 528 Qemu is a software emulator which among other architectures also
508 can simulate a MIPS32 4Kc system. This patch adds support for the 529 can simulate a MIPS32 4Kc system. This patch adds support for the
@@ -534,7 +555,7 @@ config SGI_IP22
534 select HW_HAS_EISA 555 select HW_HAS_EISA
535 select IP22_CPU_SCACHE 556 select IP22_CPU_SCACHE
536 select IRQ_CPU 557 select IRQ_CPU
537 select NO_ISA if ISA 558 select GENERIC_ISA_DMA_SUPPORT_BROKEN
538 select SWAP_IO_SPACE 559 select SWAP_IO_SPACE
539 select SYS_HAS_CPU_R4X00 560 select SYS_HAS_CPU_R4X00
540 select SYS_HAS_CPU_R5000 561 select SYS_HAS_CPU_R5000
@@ -560,6 +581,7 @@ config SGI_IP27
560 select SYS_SUPPORTS_BIG_ENDIAN 581 select SYS_SUPPORTS_BIG_ENDIAN
561 select SYS_SUPPORTS_NUMA 582 select SYS_SUPPORTS_NUMA
562 select SYS_SUPPORTS_SMP 583 select SYS_SUPPORTS_SMP
584 select GENERIC_HARDIRQS_NO__DO_IRQ
563 help 585 help
564 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 586 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
565 workstations. To compile a Linux kernel that runs on these, say Y 587 workstations. To compile a Linux kernel that runs on these, say Y
@@ -688,8 +710,8 @@ config SIBYTE_CRHONE
688 select SYS_SUPPORTS_HIGHMEM 710 select SYS_SUPPORTS_HIGHMEM
689 select SYS_SUPPORTS_LITTLE_ENDIAN 711 select SYS_SUPPORTS_LITTLE_ENDIAN
690 712
691config SNI_RM200_PCI 713config SNI_RM
692 bool "SNI RM200 PCI" 714 bool "SNI RM200/300/400"
693 select ARC if CPU_LITTLE_ENDIAN 715 select ARC if CPU_LITTLE_ENDIAN
694 select ARC32 if CPU_LITTLE_ENDIAN 716 select ARC32 if CPU_LITTLE_ENDIAN
695 select ARCH_MAY_HAVE_PC_FDC 717 select ARCH_MAY_HAVE_PC_FDC
@@ -712,8 +734,8 @@ config SNI_RM200_PCI
712 select SYS_SUPPORTS_HIGHMEM 734 select SYS_SUPPORTS_HIGHMEM
713 select SYS_SUPPORTS_LITTLE_ENDIAN 735 select SYS_SUPPORTS_LITTLE_ENDIAN
714 help 736 help
715 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens 737 The SNI RM200/300/400 are MIPS-based machines manufactured by
716 Nixdorf Informationssysteme (SNI), parent company of Pyramid 738 Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
717 Technology and now in turn merged with Fujitsu. Say Y here to 739 Technology and now in turn merged with Fujitsu. Say Y here to
718 support this machine type. 740 support this machine type.
719 741
@@ -741,6 +763,7 @@ config TOSHIBA_RBTX4927
741 select SYS_SUPPORTS_64BIT_KERNEL 763 select SYS_SUPPORTS_64BIT_KERNEL
742 select SYS_SUPPORTS_BIG_ENDIAN 764 select SYS_SUPPORTS_BIG_ENDIAN
743 select TOSHIBA_BOARDS 765 select TOSHIBA_BOARDS
766 select GENERIC_HARDIRQS_NO__DO_IRQ
744 help 767 help
745 This Toshiba board is based on the TX4927 processor. Say Y here to 768 This Toshiba board is based on the TX4927 processor. Say Y here to
746 support this machine type 769 support this machine type
@@ -760,12 +783,30 @@ config TOSHIBA_RBTX4938
760 select SYS_SUPPORTS_LITTLE_ENDIAN 783 select SYS_SUPPORTS_LITTLE_ENDIAN
761 select SYS_SUPPORTS_BIG_ENDIAN 784 select SYS_SUPPORTS_BIG_ENDIAN
762 select TOSHIBA_BOARDS 785 select TOSHIBA_BOARDS
786 select GENERIC_HARDIRQS_NO__DO_IRQ
763 help 787 help
764 This Toshiba board is based on the TX4938 processor. Say Y here to 788 This Toshiba board is based on the TX4938 processor. Say Y here to
765 support this machine type 789 support this machine type
766 790
767endchoice 791endchoice
768 792
793config KEXEC
794 bool "Kexec system call (EXPERIMENTAL)"
795 depends on EXPERIMENTAL
796 help
797 kexec is a system call that implements the ability to shutdown your
798 current kernel, and to start another kernel. It is like a reboot
799 but it is indepedent of the system firmware. And like a reboot
800 you can start any kernel with it, not just Linux.
801
802 The name comes from the similiarity to the exec system call.
803
804 It is an ongoing process to be certain the hardware in a machine
805 is properly shutdown, so do not be surprised if this code does not
806 initially work for you. It may help to enable device hotplugging
807 support. As of this writing the exact hardware interface is
808 strongly in flux, so no good recommendation can be made.
809
769source "arch/mips/ddb5xxx/Kconfig" 810source "arch/mips/ddb5xxx/Kconfig"
770source "arch/mips/gt64120/ev64120/Kconfig" 811source "arch/mips/gt64120/ev64120/Kconfig"
771source "arch/mips/jazz/Kconfig" 812source "arch/mips/jazz/Kconfig"
@@ -789,6 +830,14 @@ config RWSEM_GENERIC_SPINLOCK
789config RWSEM_XCHGADD_ALGORITHM 830config RWSEM_XCHGADD_ALGORITHM
790 bool 831 bool
791 832
833config ARCH_HAS_ILOG2_U32
834 bool
835 default n
836
837config ARCH_HAS_ILOG2_U64
838 bool
839 default n
840
792config GENERIC_FIND_NEXT_BIT 841config GENERIC_FIND_NEXT_BIT
793 bool 842 bool
794 default y 843 default y
@@ -809,6 +858,10 @@ config SCHED_NO_NO_OMIT_FRAME_POINTER
809 bool 858 bool
810 default y 859 default y
811 860
861config GENERIC_HARDIRQS_NO__DO_IRQ
862 bool
863 default n
864
812# 865#
813# Select some configuration options automatically based on user selections. 866# Select some configuration options automatically based on user selections.
814# 867#
@@ -864,8 +917,11 @@ config MIPS_NILE4
864config MIPS_DISABLE_OBSOLETE_IDE 917config MIPS_DISABLE_OBSOLETE_IDE
865 bool 918 bool
866 919
920config GENERIC_ISA_DMA_SUPPORT_BROKEN
921 bool
922
867# 923#
868# Endianess selection. Suffiently obscure so many users don't know what to 924# Endianess selection. Sufficiently obscure so many users don't know what to
869# answer,so we try hard to limit the available choices. Also the use of a 925# answer,so we try hard to limit the available choices. Also the use of a
870# choice statement should be more obvious to the user. 926# choice statement should be more obvious to the user.
871# 927#
@@ -874,7 +930,7 @@ choice
874 help 930 help
875 Some MIPS machines can be configured for either little or big endian 931 Some MIPS machines can be configured for either little or big endian
876 byte order. These modes require different kernels and a different 932 byte order. These modes require different kernels and a different
877 Linux distribution. In general there is one prefered byteorder for a 933 Linux distribution. In general there is one preferred byteorder for a
878 particular system but some systems are just as commonly used in the 934 particular system but some systems are just as commonly used in the
879 one or the other endianess. 935 one or the other endianess.
880 936
@@ -967,6 +1023,7 @@ config SOC_PNX8550
967 select HW_HAS_PCI 1023 select HW_HAS_PCI
968 select SYS_HAS_CPU_MIPS32_R1 1024 select SYS_HAS_CPU_MIPS32_R1
969 select SYS_SUPPORTS_32BIT_KERNEL 1025 select SYS_SUPPORTS_32BIT_KERNEL
1026 select GENERIC_HARDIRQS_NO__DO_IRQ
970 1027
971config SWAP_IO_SPACE 1028config SWAP_IO_SPACE
972 bool 1029 bool
@@ -1024,16 +1081,16 @@ config HAVE_STD_PC_SERIAL_PORT
1024 1081
1025config ARC_CONSOLE 1082config ARC_CONSOLE
1026 bool "ARC console support" 1083 bool "ARC console support"
1027 depends on SGI_IP22 || SNI_RM200_PCI 1084 depends on SGI_IP22 || SNI_RM
1028 1085
1029config ARC_MEMORY 1086config ARC_MEMORY
1030 bool 1087 bool
1031 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP32 1088 depends on MACH_JAZZ || SNI_RM || SGI_IP32
1032 default y 1089 default y
1033 1090
1034config ARC_PROMLIB 1091config ARC_PROMLIB
1035 bool 1092 bool
1036 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 1093 depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32
1037 default y 1094 default y
1038 1095
1039config ARC64 1096config ARC64
@@ -1248,6 +1305,7 @@ config CPU_RM9000
1248 select CPU_SUPPORTS_32BIT_KERNEL 1305 select CPU_SUPPORTS_32BIT_KERNEL
1249 select CPU_SUPPORTS_64BIT_KERNEL 1306 select CPU_SUPPORTS_64BIT_KERNEL
1250 select CPU_SUPPORTS_HIGHMEM 1307 select CPU_SUPPORTS_HIGHMEM
1308 select WEAK_ORDERING
1251 1309
1252config CPU_SB1 1310config CPU_SB1
1253 bool "SB1" 1311 bool "SB1"
@@ -1256,6 +1314,7 @@ config CPU_SB1
1256 select CPU_SUPPORTS_32BIT_KERNEL 1314 select CPU_SUPPORTS_32BIT_KERNEL
1257 select CPU_SUPPORTS_64BIT_KERNEL 1315 select CPU_SUPPORTS_64BIT_KERNEL
1258 select CPU_SUPPORTS_HIGHMEM 1316 select CPU_SUPPORTS_HIGHMEM
1317 select WEAK_ORDERING
1259 1318
1260endchoice 1319endchoice
1261 1320
@@ -1316,6 +1375,8 @@ config SYS_HAS_CPU_RM9000
1316config SYS_HAS_CPU_SB1 1375config SYS_HAS_CPU_SB1
1317 bool 1376 bool
1318 1377
1378config WEAK_ORDERING
1379 bool
1319endmenu 1380endmenu
1320 1381
1321# 1382#
@@ -1835,13 +1896,11 @@ source "drivers/pci/Kconfig"
1835config ISA 1896config ISA
1836 bool 1897 bool
1837 1898
1838config NO_ISA
1839 bool
1840
1841config EISA 1899config EISA
1842 bool "EISA support" 1900 bool "EISA support"
1843 depends on HW_HAS_EISA 1901 depends on HW_HAS_EISA
1844 select ISA 1902 select ISA
1903 select GENERIC_ISA_DMA
1845 ---help--- 1904 ---help---
1846 The Extended Industry Standard Architecture (EISA) bus was 1905 The Extended Industry Standard Architecture (EISA) bus was
1847 developed as an open alternative to the IBM MicroChannel bus. 1906 developed as an open alternative to the IBM MicroChannel bus.
@@ -1922,6 +1981,11 @@ config COMPAT
1922 depends on MIPS32_COMPAT 1981 depends on MIPS32_COMPAT
1923 default y 1982 default y
1924 1983
1984config SYSVIPC_COMPAT
1985 bool
1986 depends on COMPAT && SYSVIPC
1987 default y
1988
1925config MIPS32_O32 1989config MIPS32_O32
1926 bool "Kernel support for o32 binaries" 1990 bool "Kernel support for o32 binaries"
1927 depends on MIPS32_COMPAT 1991 depends on MIPS32_COMPAT
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d580d46f967b..d1b026a0337d 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -63,9 +63,7 @@ cflags-y += -mabi=64
63ifdef CONFIG_BUILD_ELF64 63ifdef CONFIG_BUILD_ELF64
64cflags-y += $(call cc-option,-mno-explicit-relocs) 64cflags-y += $(call cc-option,-mno-explicit-relocs)
65else 65else
66# -msym32 can not be used for modules since they are loaded into XKSEG 66cflags-y += $(call cc-option,-msym32)
67CFLAGS_MODULE += $(call cc-option,-mno-explicit-relocs)
68CFLAGS_KERNEL += $(call cc-option,-msym32)
69endif 67endif
70endif 68endif
71 69
@@ -465,6 +463,11 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
465#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550 463#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
466load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000 464load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
467 465
466# Philips PNX8550 STB810 board
467#
468libs-$(CONFIG_PNX8550_STB810) += arch/mips/philips/pnx8550/stb810/
469load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
470
468# NEC EMMA2RH boards 471# NEC EMMA2RH boards
469# 472#
470core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/ 473core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
@@ -571,11 +574,11 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
571load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 574load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
572 575
573# 576#
574# SNI RM200 PCI 577# SNI RM
575# 578#
576core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/ 579core-$(CONFIG_SNI_RM) += arch/mips/sni/
577cflags-$(CONFIG_SNI_RM200_PCI) += -Iinclude/asm-mips/mach-rm200 580cflags-$(CONFIG_SNI_RM) += -Iinclude/asm-mips/mach-rm
578load-$(CONFIG_SNI_RM200_PCI) += 0xffffffff80600000 581load-$(CONFIG_SNI_RM) += 0xffffffff80600000
579 582
580# 583#
581# Toshiba JMR-TX3927 board 584# Toshiba JMR-TX3927 board
@@ -697,7 +700,7 @@ ifdef CONFIG_QEMU
697all: vmlinux.bin 700all: vmlinux.bin
698endif 701endif
699 702
700ifdef CONFIG_SNI_RM200_PCI 703ifdef CONFIG_SNI_RM
701all: vmlinux.ecoff 704all: vmlinux.ecoff
702endif 705endif
703 706
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq);
74static void end_irq(unsigned int irq_nr); 73static void end_irq(unsigned int irq_nr);
75static inline void mask_and_ack_level_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void);
84static DEFINE_SPINLOCK(irq_lock); 83static DEFINE_SPINLOCK(irq_lock);
85 84
86 85
87static unsigned int startup_irq(unsigned int irq_nr)
88{
89 local_enable_irq(irq_nr);
90 return 0;
91}
92
93
94static void shutdown_irq(unsigned int irq_nr)
95{
96 local_disable_irq(irq_nr);
97 return;
98}
99
100
101inline void local_enable_irq(unsigned int irq_nr) 86inline void local_enable_irq(unsigned int irq_nr)
102{ 87{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 88 if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
249 234
250static struct irq_chip rise_edge_irq_type = { 235static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge", 236 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq, 237 .ack = mask_and_ack_rise_edge_irq,
238 .mask = local_disable_irq,
239 .mask_ack = mask_and_ack_rise_edge_irq,
240 .unmask = local_enable_irq,
257 .end = end_irq, 241 .end = end_irq,
258}; 242};
259 243
260static struct irq_chip fall_edge_irq_type = { 244static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge", 245 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq, 246 .ack = mask_and_ack_fall_edge_irq,
247 .mask = local_disable_irq,
248 .mask_ack = mask_and_ack_fall_edge_irq,
249 .unmask = local_enable_irq,
267 .end = end_irq, 250 .end = end_irq,
268}; 251};
269 252
270static struct irq_chip either_edge_irq_type = { 253static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge", 254 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq, 255 .ack = mask_and_ack_either_edge_irq,
256 .mask = local_disable_irq,
257 .mask_ack = mask_and_ack_either_edge_irq,
258 .unmask = local_enable_irq,
277 .end = end_irq, 259 .end = end_irq,
278}; 260};
279 261
280static struct irq_chip level_irq_type = { 262static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level", 263 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq, 264 .ack = mask_and_ack_level_irq,
265 .mask = local_disable_irq,
266 .mask_ack = mask_and_ack_level_irq,
267 .unmask = local_enable_irq,
287 .end = end_irq, 268 .end = end_irq,
288}; 269};
289 270
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type; 312 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break; 313 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type; 318 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break; 319 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type; 324 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break; 325 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type; 330 set_irq_chip(irq_nr, &level_irq_type);
350 break; 331 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type; 336 set_irq_chip(irq_nr, &level_irq_type);
356 break; 337 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */ 338 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 361 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET); 363 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type; 364 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break; 365 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 367 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET); 368 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR); 369 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type; 370 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break; 371 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR); 373 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET); 374 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type; 376 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break; 377 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET); 379 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR); 380 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET); 381 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type; 382 set_irq_chip(irq_nr, &level_irq_type);
402 break; 383 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET); 385 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR); 387 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type; 388 set_irq_chip(irq_nr, &level_irq_type);
408 break; 389 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */ 390 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR); 391 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
index da591f674893..9f8ce08e173b 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/au1000/common/pci.c
@@ -39,15 +39,15 @@
39 39
40/* TBD */ 40/* TBD */
41static struct resource pci_io_resource = { 41static struct resource pci_io_resource = {
42 .start = PCI_IO_START, 42 .start = (resource_size_t)PCI_IO_START,
43 .end = PCI_IO_END, 43 .end = (resource_size_t)PCI_IO_END,
44 .name = "PCI IO space", 44 .name = "PCI IO space",
45 .flags = IORESOURCE_IO 45 .flags = IORESOURCE_IO
46}; 46};
47 47
48static struct resource pci_mem_resource = { 48static struct resource pci_mem_resource = {
49 .start = PCI_MEM_START, 49 .start = (resource_size_t)PCI_MEM_START,
50 .end = PCI_MEM_END, 50 .end = (resource_size_t)PCI_MEM_END,
51 .name = "PCI memory space", 51 .name = "PCI memory space",
52 .flags = IORESOURCE_MEM 52 .flags = IORESOURCE_MEM
53}; 53};
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index 8b953b9fc25c..043302b7fe58 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -55,7 +55,7 @@
55#endif 55#endif
56 56
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset (void)
61{ 61{
@@ -151,11 +151,7 @@ void __init board_setup(void)
151#endif 151#endif
152 152
153 /* Setup Pb1200 External Interrupt Controller */ 153 /* Setup Pb1200 External Interrupt Controller */
154 { 154 board_init_irq = _board_init_irq;
155 extern void (*board_init_irq)(void);
156 extern void _board_init_irq(void);
157 board_init_irq = _board_init_irq;
158 }
159} 155}
160 156
161int 157int
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 82e569d5b02c..4c46f0e73783 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -45,25 +45,22 @@ static inline void galileo_irq(void)
45{ 45{
46 unsigned int mask, pending, devfn; 46 unsigned int mask, pending, devfn;
47 47
48 mask = GALILEO_INL(GT_INTRMASK_OFS); 48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; 49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50 50
51 if (pending & GALILEO_INTR_T0EXP) { 51 if (pending & GT_INTR_T0EXP_MSK) {
52 52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
54 do_IRQ(COBALT_GALILEO_IRQ); 53 do_IRQ(COBALT_GALILEO_IRQ);
55 54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
56 } else if (pending & GALILEO_INTR_RETRY_CTR) { 55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
57 56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
58 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; 57 printk(KERN_WARNING
59 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); 58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
60 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", 59 PCI_SLOT(devfn), PCI_FUNC(devfn));
61 PCI_SLOT(devfn), PCI_FUNC(devfn));
62
63 } else { 60 } else {
64 61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
65 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); 62 printk(KERN_WARNING
66 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); 63 "Galileo: masking unexpected interrupt %08x\n", pending);
67 } 64 }
68} 65}
69 66
@@ -104,7 +101,7 @@ void __init arch_init_irq(void)
104 * Mask all Galileo interrupts. The Galileo 101 * Mask all Galileo interrupts. The Galileo
105 * handler is set in cobalt_timer_setup() 102 * handler is set in cobalt_timer_setup()
106 */ 103 */
107 GALILEO_OUTL(0, GT_INTRMASK_OFS); 104 GT_WRITE(GT_INTRMASK_OFS, 0);
108 105
109 init_i8259_irqs(); /* 0 ... 15 */ 106 init_i8259_irqs(); /* 0 ... 15 */
110 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 107 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index bf9dc72b9720..e8f0f20b852d 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -51,23 +51,23 @@ const char *get_system_type(void)
51void __init plat_timer_setup(struct irqaction *irq) 51void __init plat_timer_setup(struct irqaction *irq)
52{ 52{
53 /* Load timer value for HZ (TCLK is 50MHz) */ 53 /* Load timer value for HZ (TCLK is 50MHz) */
54 GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
55 55
56 /* Enable timer */ 56 /* Enable timer */
57 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
58 58
59 /* Register interrupt */ 59 /* Register interrupt */
60 setup_irq(COBALT_GALILEO_IRQ, irq); 60 setup_irq(COBALT_GALILEO_IRQ, irq);
61 61
62 /* Enable interrupt */ 62 /* Enable interrupt */
63 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
64} 64}
65 65
66extern struct pci_ops gt64111_pci_ops; 66extern struct pci_ops gt64111_pci_ops;
67 67
68static struct resource cobalt_mem_resource = { 68static struct resource cobalt_mem_resource = {
69 .start = GT64111_MEM_BASE, 69 .start = GT_DEF_PCI0_MEM0_BASE,
70 .end = GT64111_MEM_END, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
71 .name = "PCI memory", 71 .name = "PCI memory",
72 .flags = IORESOURCE_MEM 72 .flags = IORESOURCE_MEM
73}; 73};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
115 .mem_resource = &cobalt_mem_resource, 115 .mem_resource = &cobalt_mem_resource,
116 .mem_offset = 0, 116 .mem_offset = 0,
117 .io_resource = &cobalt_io_resource, 117 .io_resource = &cobalt_io_resource,
118 .io_offset = 0 - GT64111_IO_BASE 118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
119}; 119};
120 120
121void __init plat_mem_setup(void) 121void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
128 _machine_halt = cobalt_machine_halt; 128 _machine_halt = cobalt_machine_halt;
129 pm_power_off = cobalt_machine_power_off; 129 pm_power_off = cobalt_machine_power_off;
130 130
131 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
132 132
133 /* I/O port resource must include UART and LCD/buttons */ 133 /* I/O port resource must include UART and LCD/buttons */
134 ioport_resource.end = 0x0fffffff; 134 ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
139 139
140 /* Read the cobalt id register out of the PCI config space */ 140 /* Read the cobalt id register out of the PCI config space */
141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
142 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 142 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
145 145
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index 35931bedc3df..ac1891687520 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_ATLAS=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index ba3bf733d27d..9554257c6f3a 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -57,7 +57,7 @@ CONFIG_SIBYTE_BIGSUR=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index e5358121d2da..49590d443712 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index adf1e8c98c65..0607fc239087 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_COBALT=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 4fd29ffdfb8d..1a57b3375483 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_DB1000=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 025b960ba990..0055ec41f207 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_DB1100=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index 80c9dd98f897..c41823b81be0 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_DB1200=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index 6caa90b0e176..7d6d92187880 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_DB1500=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index c6cae86c6ab7..c681c91763aa 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_DB1550=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index 72f24001c99e..dd4bb0080211 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -59,7 +59,7 @@ CONFIG_DDB5477=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index fe1387eb83c9..8a31ce4be12c 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_DECSTATION=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 6133c28beb8c..6fa4f914f6e4 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig
index a484b7d396fc..4c9d0405a5df 100644
--- a/arch/mips/configs/emma2rh_defconfig
+++ b/arch/mips/configs/emma2rh_defconfig
@@ -59,7 +59,7 @@ CONFIG_MARKEINS=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index 21bfcdebf8f5..d5b49735683b 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_EV64120=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig
index 1a5b06cfb4d6..697140c6562f 100644
--- a/arch/mips/configs/excite_defconfig
+++ b/arch/mips/configs/excite_defconfig
@@ -60,7 +60,7 @@ CONFIG_BASLER_EXCITE=y
60# CONFIG_SIBYTE_LITTLESUR is not set 60# CONFIG_SIBYTE_LITTLESUR is not set
61# CONFIG_SIBYTE_CRHINE is not set 61# CONFIG_SIBYTE_CRHINE is not set
62# CONFIG_SIBYTE_CRHONE is not set 62# CONFIG_SIBYTE_CRHONE is not set
63# CONFIG_SNI_RM200_PCI is not set 63# CONFIG_SNI_RM is not set
64# CONFIG_TOSHIBA_JMR3927 is not set 64# CONFIG_TOSHIBA_JMR3927 is not set
65# CONFIG_TOSHIBA_RBTX4927 is not set 65# CONFIG_TOSHIBA_RBTX4927 is not set
66# CONFIG_TOSHIBA_RBTX4938 is not set 66# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 21d53e0c9ee8..f9812d1e4579 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -59,7 +59,7 @@ CONFIG_SGI_IP22=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index e3e94c7e5ee1..96090f28373b 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -59,7 +59,7 @@ CONFIG_SGI_IP27=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index b4ab2bea9723..61e069a0f1aa 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -59,7 +59,7 @@ CONFIG_SGI_IP32=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 9d4d17ace123..88966666f4c6 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -59,7 +59,7 @@ CONFIG_MOMENCO_JAGUAR_ATX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig
index 382083ebea0a..835764d834f7 100644
--- a/arch/mips/configs/jazz_defconfig
+++ b/arch/mips/configs/jazz_defconfig
@@ -57,7 +57,7 @@ CONFIG_MACH_JAZZ=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index d03746667a96..50fd9557e646 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63CONFIG_TOSHIBA_JMR3927=y 63CONFIG_TOSHIBA_JMR3927=y
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 1db8249b4c0f..05f539f84f58 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -59,7 +59,7 @@ CONFIG_LASAT=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 101e80347dce..96e941084c04 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -57,7 +57,7 @@ CONFIG_MIPS_MALTA=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
@@ -644,7 +644,85 @@ CONFIG_CONNECTOR=m
644# 644#
645# Memory Technology Devices (MTD) 645# Memory Technology Devices (MTD)
646# 646#
647# CONFIG_MTD is not set 647CONFIG_MTD=y
648# CONFIG_MTD_DEBUG is not set
649# CONFIG_MTD_CONCAT is not set
650CONFIG_MTD_PARTITIONS=y
651# CONFIG_MTD_REDBOOT_PARTS is not set
652# CONFIG_MTD_CMDLINE_PARTS is not set
653
654#
655# User Modules And Translation Layers
656#
657CONFIG_MTD_CHAR=y
658CONFIG_MTD_BLOCK=y
659# CONFIG_FTL is not set
660# CONFIG_NFTL is not set
661# CONFIG_INFTL is not set
662# CONFIG_RFD_FTL is not set
663# CONFIG_SSFDC is not set
664
665#
666# RAM/ROM/Flash chip drivers
667#
668CONFIG_MTD_CFI=y
669# CONFIG_MTD_JEDECPROBE is not set
670CONFIG_MTD_GEN_PROBE=y
671# CONFIG_MTD_CFI_ADV_OPTIONS is not set
672CONFIG_MTD_MAP_BANK_WIDTH_1=y
673CONFIG_MTD_MAP_BANK_WIDTH_2=y
674CONFIG_MTD_MAP_BANK_WIDTH_4=y
675# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
676# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
677# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
678CONFIG_MTD_CFI_I1=y
679CONFIG_MTD_CFI_I2=y
680# CONFIG_MTD_CFI_I4 is not set
681# CONFIG_MTD_CFI_I8 is not set
682CONFIG_MTD_CFI_INTELEXT=y
683CONFIG_MTD_CFI_AMDSTD=y
684CONFIG_MTD_CFI_STAA=y
685CONFIG_MTD_CFI_UTIL=y
686# CONFIG_MTD_RAM is not set
687# CONFIG_MTD_ROM is not set
688# CONFIG_MTD_ABSENT is not set
689# CONFIG_MTD_OBSOLETE_CHIPS is not set
690
691#
692# Mapping drivers for chip access
693#
694# CONFIG_MTD_COMPLEX_MAPPINGS is not set
695CONFIG_MTD_PHYSMAP=y
696CONFIG_MTD_PHYSMAP_START=0x0
697CONFIG_MTD_PHYSMAP_LEN=0x0
698CONFIG_MTD_PHYSMAP_BANKWIDTH=0
699# CONFIG_MTD_PLATRAM is not set
700
701#
702# Self-contained MTD device drivers
703#
704# CONFIG_MTD_PMC551 is not set
705# CONFIG_MTD_SLRAM is not set
706# CONFIG_MTD_PHRAM is not set
707# CONFIG_MTD_MTDRAM is not set
708# CONFIG_MTD_BLOCK2MTD is not set
709
710#
711# Disk-On-Chip Device Drivers
712#
713# CONFIG_MTD_DOC2000 is not set
714# CONFIG_MTD_DOC2001 is not set
715# CONFIG_MTD_DOC2001PLUS is not set
716
717#
718# NAND Flash Device Drivers
719#
720# CONFIG_MTD_NAND is not set
721
722#
723# OneNAND Flash Device Drivers
724#
725# CONFIG_MTD_ONENAND is not set
648 726
649# 727#
650# Parallel port support 728# Parallel port support
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index a3cbd23bf217..03efcfd0503b 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_SIM=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 6570b47426ce..e4221aafbc4c 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index 440d65f93a94..32b1afdd1c20 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_3=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index c2c7ae77da3e..ebe75c1c71af 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_C=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 67efe270e0cc..5a9603c12902 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index a10f34de5f7e..46a942c253cf 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -59,7 +59,7 @@ CONFIG_MOMENCO_OCELOT_G=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 9e672f63a0aa..7d3c688181d5 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_PB1100=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index d0c0f4af1bff..a77805af0819 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_PB1500=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 3db7427d1b55..8318d74d6adb 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_PB1550=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 280a8001eacf..fcb8fea3052c 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -57,7 +57,7 @@ CONFIG_PNX8550_JBS=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
new file mode 100644
index 000000000000..f38a2c123037
--- /dev/null
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -0,0 +1,1229 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19
4# Thu Dec 7 16:35:12 2006
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MIPS_MTX1 is not set
12# CONFIG_MIPS_BOSPORUS is not set
13# CONFIG_MIPS_PB1000 is not set
14# CONFIG_MIPS_PB1100 is not set
15# CONFIG_MIPS_PB1500 is not set
16# CONFIG_MIPS_PB1550 is not set
17# CONFIG_MIPS_PB1200 is not set
18# CONFIG_MIPS_DB1000 is not set
19# CONFIG_MIPS_DB1100 is not set
20# CONFIG_MIPS_DB1500 is not set
21# CONFIG_MIPS_DB1550 is not set
22# CONFIG_MIPS_DB1200 is not set
23# CONFIG_MIPS_MIRAGE is not set
24# CONFIG_BASLER_EXCITE is not set
25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MACH_JAZZ is not set
29# CONFIG_LASAT is not set
30# CONFIG_MIPS_ATLAS is not set
31# CONFIG_MIPS_MALTA is not set
32# CONFIG_MIPS_SEAD is not set
33# CONFIG_WR_PPMC is not set
34# CONFIG_MIPS_SIM is not set
35# CONFIG_MOMENCO_JAGUAR_ATX is not set
36# CONFIG_MOMENCO_OCELOT is not set
37# CONFIG_MOMENCO_OCELOT_3 is not set
38# CONFIG_MOMENCO_OCELOT_C is not set
39# CONFIG_MOMENCO_OCELOT_G is not set
40# CONFIG_MIPS_XXS1500 is not set
41# CONFIG_PNX8550_V2PCI is not set
42# CONFIG_PNX8550_JBS is not set
43CONFIG_PNX8550_STB810=y
44# CONFIG_DDB5477 is not set
45# CONFIG_MACH_VR41XX is not set
46# CONFIG_PMC_YOSEMITE is not set
47# CONFIG_QEMU is not set
48# CONFIG_MARKEINS is not set
49# CONFIG_SGI_IP22 is not set
50# CONFIG_SGI_IP27 is not set
51# CONFIG_SGI_IP32 is not set
52# CONFIG_SIBYTE_BIGSUR is not set
53# CONFIG_SIBYTE_SWARM is not set
54# CONFIG_SIBYTE_SENTOSA is not set
55# CONFIG_SIBYTE_RHONE is not set
56# CONFIG_SIBYTE_CARMEL is not set
57# CONFIG_SIBYTE_PTSWARM is not set
58# CONFIG_SIBYTE_LITTLESUR is not set
59# CONFIG_SIBYTE_CRHINE is not set
60# CONFIG_SIBYTE_CRHONE is not set
61# CONFIG_SNI_RM200_PCI is not set
62# CONFIG_TOSHIBA_JMR3927 is not set
63# CONFIG_TOSHIBA_RBTX4927 is not set
64# CONFIG_TOSHIBA_RBTX4938 is not set
65# CONFIG_KEXEC is not set
66CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y
70CONFIG_GENERIC_TIME=y
71CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
72CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y
74# CONFIG_CPU_BIG_ENDIAN is not set
75CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_PNX8550=y
78CONFIG_SOC_PNX8550=y
79CONFIG_MIPS_L1_CACHE_SHIFT=5
80
81#
82# CPU selection
83#
84CONFIG_CPU_MIPS32_R1=y
85# CONFIG_CPU_MIPS32_R2 is not set
86# CONFIG_CPU_MIPS64_R1 is not set
87# CONFIG_CPU_MIPS64_R2 is not set
88# CONFIG_CPU_R3000 is not set
89# CONFIG_CPU_TX39XX is not set
90# CONFIG_CPU_VR41XX is not set
91# CONFIG_CPU_R4300 is not set
92# CONFIG_CPU_R4X00 is not set
93# CONFIG_CPU_TX49XX is not set
94# CONFIG_CPU_R5000 is not set
95# CONFIG_CPU_R5432 is not set
96# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set
99# CONFIG_CPU_R10000 is not set
100# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set
103CONFIG_SYS_HAS_CPU_MIPS32_R1=y
104CONFIG_CPU_MIPS32=y
105CONFIG_CPU_MIPSR1=y
106CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
108
109#
110# Kernel type
111#
112CONFIG_32BIT=y
113# CONFIG_64BIT is not set
114CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set
118CONFIG_CPU_HAS_PREFETCH=y
119CONFIG_MIPS_MT_DISABLED=y
120# CONFIG_MIPS_MT_SMP is not set
121# CONFIG_MIPS_MT_SMTC is not set
122# CONFIG_MIPS_VPE_LOADER is not set
123# CONFIG_64BIT_PHYS_ADDR is not set
124CONFIG_CPU_HAS_LLSC=y
125CONFIG_CPU_HAS_SYNC=y
126CONFIG_GENERIC_HARDIRQS=y
127CONFIG_GENERIC_IRQ_PROBE=y
128CONFIG_CPU_SUPPORTS_HIGHMEM=y
129CONFIG_ARCH_FLATMEM_ENABLE=y
130CONFIG_SELECT_MEMORY_MODEL=y
131CONFIG_FLATMEM_MANUAL=y
132# CONFIG_DISCONTIGMEM_MANUAL is not set
133# CONFIG_SPARSEMEM_MANUAL is not set
134CONFIG_FLATMEM=y
135CONFIG_FLAT_NODE_MEM_MAP=y
136# CONFIG_SPARSEMEM_STATIC is not set
137CONFIG_SPLIT_PTLOCK_CPUS=4
138# CONFIG_RESOURCES_64BIT is not set
139# CONFIG_HZ_48 is not set
140# CONFIG_HZ_100 is not set
141# CONFIG_HZ_128 is not set
142CONFIG_HZ_250=y
143# CONFIG_HZ_256 is not set
144# CONFIG_HZ_1000 is not set
145# CONFIG_HZ_1024 is not set
146CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
147CONFIG_HZ=250
148CONFIG_PREEMPT_NONE=y
149# CONFIG_PREEMPT_VOLUNTARY is not set
150# CONFIG_PREEMPT is not set
151CONFIG_LOCKDEP_SUPPORT=y
152CONFIG_STACKTRACE_SUPPORT=y
153CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
154
155#
156# Code maturity level options
157#
158CONFIG_EXPERIMENTAL=y
159CONFIG_BROKEN_ON_SMP=y
160CONFIG_INIT_ENV_ARG_LIMIT=32
161
162#
163# General setup
164#
165CONFIG_LOCALVERSION=""
166CONFIG_LOCALVERSION_AUTO=y
167CONFIG_SWAP=y
168CONFIG_SYSVIPC=y
169# CONFIG_IPC_NS is not set
170# CONFIG_POSIX_MQUEUE is not set
171# CONFIG_BSD_PROCESS_ACCT is not set
172# CONFIG_TASKSTATS is not set
173# CONFIG_UTS_NS is not set
174# CONFIG_AUDIT is not set
175CONFIG_IKCONFIG=y
176CONFIG_IKCONFIG_PROC=y
177CONFIG_SYSFS_DEPRECATED=y
178# CONFIG_RELAY is not set
179CONFIG_INITRAMFS_SOURCE=""
180# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
181CONFIG_SYSCTL=y
182CONFIG_EMBEDDED=y
183# CONFIG_SYSCTL_SYSCALL is not set
184CONFIG_KALLSYMS=y
185# CONFIG_KALLSYMS_ALL is not set
186# CONFIG_KALLSYMS_EXTRA_PASS is not set
187# CONFIG_HOTPLUG is not set
188CONFIG_PRINTK=y
189CONFIG_BUG=y
190CONFIG_ELF_CORE=y
191CONFIG_BASE_FULL=y
192CONFIG_FUTEX=y
193CONFIG_EPOLL=y
194CONFIG_SHMEM=y
195CONFIG_SLAB=y
196CONFIG_VM_EVENT_COUNTERS=y
197CONFIG_RT_MUTEXES=y
198# CONFIG_TINY_SHMEM is not set
199CONFIG_BASE_SMALL=0
200# CONFIG_SLOB is not set
201
202#
203# Loadable module support
204#
205CONFIG_MODULES=y
206# CONFIG_MODULE_UNLOAD is not set
207# CONFIG_MODVERSIONS is not set
208# CONFIG_MODULE_SRCVERSION_ALL is not set
209CONFIG_KMOD=y
210
211#
212# Block layer
213#
214CONFIG_BLOCK=y
215# CONFIG_LBD is not set
216# CONFIG_BLK_DEV_IO_TRACE is not set
217# CONFIG_LSF is not set
218
219#
220# IO Schedulers
221#
222CONFIG_IOSCHED_NOOP=y
223CONFIG_IOSCHED_AS=y
224CONFIG_IOSCHED_DEADLINE=y
225CONFIG_IOSCHED_CFQ=y
226CONFIG_DEFAULT_AS=y
227# CONFIG_DEFAULT_DEADLINE is not set
228# CONFIG_DEFAULT_CFQ is not set
229# CONFIG_DEFAULT_NOOP is not set
230CONFIG_DEFAULT_IOSCHED="anticipatory"
231
232#
233# Bus options (PCI, PCMCIA, EISA, ISA, TC)
234#
235CONFIG_HW_HAS_PCI=y
236CONFIG_PCI=y
237# CONFIG_PCI_MULTITHREAD_PROBE is not set
238# CONFIG_PCI_DEBUG is not set
239CONFIG_MMU=y
240
241#
242# PCCARD (PCMCIA/CardBus) support
243#
244
245#
246# PCI Hotplug Support
247#
248
249#
250# Executable file formats
251#
252CONFIG_BINFMT_ELF=y
253# CONFIG_BINFMT_MISC is not set
254CONFIG_TRAD_SIGNALS=y
255
256#
257# Networking
258#
259CONFIG_NET=y
260
261#
262# Networking options
263#
264# CONFIG_NETDEBUG is not set
265CONFIG_PACKET=y
266# CONFIG_PACKET_MMAP is not set
267CONFIG_UNIX=y
268CONFIG_XFRM=y
269# CONFIG_XFRM_USER is not set
270# CONFIG_XFRM_SUB_POLICY is not set
271# CONFIG_NET_KEY is not set
272CONFIG_INET=y
273# CONFIG_IP_MULTICAST is not set
274# CONFIG_IP_ADVANCED_ROUTER is not set
275CONFIG_IP_FIB_HASH=y
276CONFIG_IP_PNP=y
277CONFIG_IP_PNP_DHCP=y
278CONFIG_IP_PNP_BOOTP=y
279# CONFIG_IP_PNP_RARP is not set
280# CONFIG_NET_IPIP is not set
281# CONFIG_NET_IPGRE is not set
282# CONFIG_ARPD is not set
283# CONFIG_SYN_COOKIES is not set
284# CONFIG_INET_AH is not set
285# CONFIG_INET_ESP is not set
286# CONFIG_INET_IPCOMP is not set
287# CONFIG_INET_XFRM_TUNNEL is not set
288# CONFIG_INET_TUNNEL is not set
289CONFIG_INET_XFRM_MODE_TRANSPORT=y
290CONFIG_INET_XFRM_MODE_TUNNEL=y
291CONFIG_INET_XFRM_MODE_BEET=y
292CONFIG_INET_DIAG=y
293CONFIG_INET_TCP_DIAG=y
294# CONFIG_TCP_CONG_ADVANCED is not set
295CONFIG_TCP_CONG_CUBIC=y
296CONFIG_DEFAULT_TCP_CONG="cubic"
297# CONFIG_TCP_MD5SIG is not set
298# CONFIG_IPV6 is not set
299# CONFIG_INET6_XFRM_TUNNEL is not set
300# CONFIG_INET6_TUNNEL is not set
301# CONFIG_NETWORK_SECMARK is not set
302# CONFIG_NETFILTER is not set
303
304#
305# DCCP Configuration (EXPERIMENTAL)
306#
307# CONFIG_IP_DCCP is not set
308
309#
310# SCTP Configuration (EXPERIMENTAL)
311#
312# CONFIG_IP_SCTP is not set
313
314#
315# TIPC Configuration (EXPERIMENTAL)
316#
317# CONFIG_TIPC is not set
318# CONFIG_ATM is not set
319# CONFIG_BRIDGE is not set
320# CONFIG_VLAN_8021Q is not set
321# CONFIG_DECNET is not set
322# CONFIG_LLC2 is not set
323# CONFIG_IPX is not set
324# CONFIG_ATALK is not set
325# CONFIG_X25 is not set
326# CONFIG_LAPB is not set
327# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set
329
330#
331# QoS and/or fair queueing
332#
333# CONFIG_NET_SCHED is not set
334
335#
336# Network testing
337#
338# CONFIG_NET_PKTGEN is not set
339# CONFIG_HAMRADIO is not set
340# CONFIG_IRDA is not set
341# CONFIG_BT is not set
342# CONFIG_IEEE80211 is not set
343
344#
345# Device Drivers
346#
347
348#
349# Generic Driver Options
350#
351CONFIG_STANDALONE=y
352CONFIG_PREVENT_FIRMWARE_BUILD=y
353# CONFIG_DEBUG_DRIVER is not set
354# CONFIG_SYS_HYPERVISOR is not set
355
356#
357# Connector - unified userspace <-> kernelspace linker
358#
359# CONFIG_CONNECTOR is not set
360
361#
362# Memory Technology Devices (MTD)
363#
364# CONFIG_MTD is not set
365
366#
367# Parallel port support
368#
369# CONFIG_PARPORT is not set
370
371#
372# Plug and Play support
373#
374
375#
376# Block devices
377#
378# CONFIG_BLK_CPQ_DA is not set
379# CONFIG_BLK_CPQ_CISS_DA is not set
380# CONFIG_BLK_DEV_DAC960 is not set
381# CONFIG_BLK_DEV_UMEM is not set
382# CONFIG_BLK_DEV_COW_COMMON is not set
383CONFIG_BLK_DEV_LOOP=y
384# CONFIG_BLK_DEV_CRYPTOLOOP is not set
385# CONFIG_BLK_DEV_NBD is not set
386# CONFIG_BLK_DEV_SX8 is not set
387# CONFIG_BLK_DEV_UB is not set
388CONFIG_BLK_DEV_RAM=y
389CONFIG_BLK_DEV_RAM_COUNT=16
390CONFIG_BLK_DEV_RAM_SIZE=8192
391CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
392CONFIG_BLK_DEV_INITRD=y
393# CONFIG_CDROM_PKTCDVD is not set
394# CONFIG_ATA_OVER_ETH is not set
395
396#
397# Misc devices
398#
399# CONFIG_SGI_IOC4 is not set
400# CONFIG_TIFM_CORE is not set
401
402#
403# ATA/ATAPI/MFM/RLL support
404#
405CONFIG_IDE=y
406CONFIG_IDE_MAX_HWIFS=4
407CONFIG_BLK_DEV_IDE=y
408
409#
410# Please see Documentation/ide.txt for help/info on IDE drives
411#
412# CONFIG_BLK_DEV_IDE_SATA is not set
413CONFIG_BLK_DEV_IDEDISK=y
414# CONFIG_IDEDISK_MULTI_MODE is not set
415CONFIG_BLK_DEV_IDECD=m
416# CONFIG_BLK_DEV_IDETAPE is not set
417# CONFIG_BLK_DEV_IDEFLOPPY is not set
418CONFIG_BLK_DEV_IDESCSI=y
419# CONFIG_IDE_TASK_IOCTL is not set
420
421#
422# IDE chipset support/bugfixes
423#
424CONFIG_IDE_GENERIC=y
425CONFIG_BLK_DEV_IDEPCI=y
426CONFIG_IDEPCI_SHARE_IRQ=y
427CONFIG_BLK_DEV_OFFBOARD=y
428CONFIG_BLK_DEV_GENERIC=y
429# CONFIG_BLK_DEV_OPTI621 is not set
430CONFIG_BLK_DEV_IDEDMA_PCI=y
431# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
432# CONFIG_IDEDMA_PCI_AUTO is not set
433# CONFIG_BLK_DEV_AEC62XX is not set
434# CONFIG_BLK_DEV_ALI15X3 is not set
435# CONFIG_BLK_DEV_AMD74XX is not set
436# CONFIG_BLK_DEV_CMD64X is not set
437# CONFIG_BLK_DEV_TRIFLEX is not set
438# CONFIG_BLK_DEV_CY82C693 is not set
439# CONFIG_BLK_DEV_CS5520 is not set
440# CONFIG_BLK_DEV_CS5530 is not set
441# CONFIG_BLK_DEV_HPT34X is not set
442CONFIG_BLK_DEV_HPT366=y
443# CONFIG_BLK_DEV_JMICRON is not set
444# CONFIG_BLK_DEV_SC1200 is not set
445# CONFIG_BLK_DEV_PIIX is not set
446# CONFIG_BLK_DEV_IT821X is not set
447# CONFIG_BLK_DEV_NS87415 is not set
448# CONFIG_BLK_DEV_PDC202XX_OLD is not set
449# CONFIG_BLK_DEV_PDC202XX_NEW is not set
450# CONFIG_BLK_DEV_SVWKS is not set
451# CONFIG_BLK_DEV_SIIMAGE is not set
452# CONFIG_BLK_DEV_SLC90E66 is not set
453# CONFIG_BLK_DEV_TRM290 is not set
454# CONFIG_BLK_DEV_VIA82CXXX is not set
455# CONFIG_IDE_ARM is not set
456CONFIG_BLK_DEV_IDEDMA=y
457# CONFIG_IDEDMA_IVB is not set
458# CONFIG_IDEDMA_AUTO is not set
459# CONFIG_BLK_DEV_HD is not set
460
461#
462# SCSI device support
463#
464# CONFIG_RAID_ATTRS is not set
465CONFIG_SCSI=y
466# CONFIG_SCSI_NETLINK is not set
467CONFIG_SCSI_PROC_FS=y
468
469#
470# SCSI support type (disk, tape, CD-ROM)
471#
472CONFIG_BLK_DEV_SD=y
473# CONFIG_CHR_DEV_ST is not set
474# CONFIG_CHR_DEV_OSST is not set
475# CONFIG_BLK_DEV_SR is not set
476# CONFIG_CHR_DEV_SG is not set
477# CONFIG_CHR_DEV_SCH is not set
478
479#
480# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
481#
482# CONFIG_SCSI_MULTI_LUN is not set
483CONFIG_SCSI_CONSTANTS=y
484# CONFIG_SCSI_LOGGING is not set
485
486#
487# SCSI Transports
488#
489# CONFIG_SCSI_SPI_ATTRS is not set
490# CONFIG_SCSI_FC_ATTRS is not set
491CONFIG_SCSI_ISCSI_ATTRS=m
492# CONFIG_SCSI_SAS_ATTRS is not set
493# CONFIG_SCSI_SAS_LIBSAS is not set
494
495#
496# SCSI low-level drivers
497#
498CONFIG_ISCSI_TCP=m
499# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
500# CONFIG_SCSI_3W_9XXX is not set
501# CONFIG_SCSI_ACARD is not set
502# CONFIG_SCSI_AACRAID is not set
503# CONFIG_SCSI_AIC7XXX is not set
504# CONFIG_SCSI_AIC7XXX_OLD is not set
505# CONFIG_SCSI_AIC79XX is not set
506# CONFIG_SCSI_AIC94XX is not set
507# CONFIG_SCSI_DPT_I2O is not set
508# CONFIG_SCSI_ARCMSR is not set
509# CONFIG_MEGARAID_NEWGEN is not set
510# CONFIG_MEGARAID_LEGACY is not set
511# CONFIG_MEGARAID_SAS is not set
512# CONFIG_SCSI_HPTIOP is not set
513# CONFIG_SCSI_DMX3191D is not set
514# CONFIG_SCSI_FUTURE_DOMAIN is not set
515# CONFIG_SCSI_IPS is not set
516# CONFIG_SCSI_INITIO is not set
517# CONFIG_SCSI_INIA100 is not set
518# CONFIG_SCSI_STEX is not set
519# CONFIG_SCSI_SYM53C8XX_2 is not set
520# CONFIG_SCSI_QLOGIC_1280 is not set
521# CONFIG_SCSI_QLA_FC is not set
522# CONFIG_SCSI_QLA_ISCSI is not set
523# CONFIG_SCSI_LPFC is not set
524# CONFIG_SCSI_DC395x is not set
525# CONFIG_SCSI_DC390T is not set
526# CONFIG_SCSI_NSP32 is not set
527# CONFIG_SCSI_DEBUG is not set
528
529#
530# Serial ATA (prod) and Parallel ATA (experimental) drivers
531#
532# CONFIG_ATA is not set
533
534#
535# Multi-device support (RAID and LVM)
536#
537# CONFIG_MD is not set
538
539#
540# Fusion MPT device support
541#
542# CONFIG_FUSION is not set
543# CONFIG_FUSION_SPI is not set
544# CONFIG_FUSION_FC is not set
545# CONFIG_FUSION_SAS is not set
546
547#
548# IEEE 1394 (FireWire) support
549#
550# CONFIG_IEEE1394 is not set
551
552#
553# I2O device support
554#
555# CONFIG_I2O is not set
556
557#
558# Network device support
559#
560CONFIG_NETDEVICES=y
561# CONFIG_DUMMY is not set
562# CONFIG_BONDING is not set
563# CONFIG_EQUALIZER is not set
564# CONFIG_TUN is not set
565
566#
567# ARCnet devices
568#
569# CONFIG_ARCNET is not set
570
571#
572# PHY device support
573#
574# CONFIG_PHYLIB is not set
575
576#
577# Ethernet (10 or 100Mbit)
578#
579CONFIG_NET_ETHERNET=y
580CONFIG_MII=y
581# CONFIG_HAPPYMEAL is not set
582# CONFIG_SUNGEM is not set
583# CONFIG_CASSINI is not set
584# CONFIG_NET_VENDOR_3COM is not set
585# CONFIG_DM9000 is not set
586
587#
588# Tulip family network device support
589#
590# CONFIG_NET_TULIP is not set
591# CONFIG_HP100 is not set
592CONFIG_NET_PCI=y
593# CONFIG_PCNET32 is not set
594# CONFIG_AMD8111_ETH is not set
595# CONFIG_ADAPTEC_STARFIRE is not set
596# CONFIG_B44 is not set
597# CONFIG_FORCEDETH is not set
598# CONFIG_DGRS is not set
599# CONFIG_EEPRO100 is not set
600# CONFIG_E100 is not set
601# CONFIG_FEALNX is not set
602CONFIG_NATSEMI=y
603# CONFIG_NE2K_PCI is not set
604# CONFIG_8139CP is not set
605# CONFIG_8139TOO is not set
606# CONFIG_SIS900 is not set
607# CONFIG_EPIC100 is not set
608# CONFIG_SUNDANCE is not set
609# CONFIG_TLAN is not set
610# CONFIG_VIA_RHINE is not set
611
612#
613# Ethernet (1000 Mbit)
614#
615# CONFIG_ACENIC is not set
616# CONFIG_DL2K is not set
617# CONFIG_E1000 is not set
618# CONFIG_NS83820 is not set
619# CONFIG_HAMACHI is not set
620# CONFIG_YELLOWFIN is not set
621# CONFIG_R8169 is not set
622# CONFIG_SIS190 is not set
623# CONFIG_SKGE is not set
624# CONFIG_SKY2 is not set
625# CONFIG_SK98LIN is not set
626# CONFIG_VIA_VELOCITY is not set
627# CONFIG_TIGON3 is not set
628# CONFIG_BNX2 is not set
629# CONFIG_QLA3XXX is not set
630
631#
632# Ethernet (10000 Mbit)
633#
634# CONFIG_CHELSIO_T1 is not set
635# CONFIG_IXGB is not set
636# CONFIG_S2IO is not set
637# CONFIG_MYRI10GE is not set
638# CONFIG_NETXEN_NIC is not set
639
640#
641# Token Ring devices
642#
643# CONFIG_TR is not set
644
645#
646# Wireless LAN (non-hamradio)
647#
648# CONFIG_NET_RADIO is not set
649
650#
651# Wan interfaces
652#
653# CONFIG_WAN is not set
654# CONFIG_FDDI is not set
655# CONFIG_HIPPI is not set
656# CONFIG_PPP is not set
657# CONFIG_SLIP is not set
658# CONFIG_NET_FC is not set
659# CONFIG_SHAPER is not set
660# CONFIG_NETCONSOLE is not set
661# CONFIG_NETPOLL is not set
662# CONFIG_NET_POLL_CONTROLLER is not set
663
664#
665# ISDN subsystem
666#
667# CONFIG_ISDN is not set
668
669#
670# Telephony Support
671#
672# CONFIG_PHONE is not set
673
674#
675# Input device support
676#
677CONFIG_INPUT=y
678# CONFIG_INPUT_FF_MEMLESS is not set
679
680#
681# Userland interfaces
682#
683# CONFIG_INPUT_MOUSEDEV is not set
684# CONFIG_INPUT_JOYDEV is not set
685# CONFIG_INPUT_TSDEV is not set
686# CONFIG_INPUT_EVDEV is not set
687# CONFIG_INPUT_EVBUG is not set
688
689#
690# Input Device Drivers
691#
692# CONFIG_INPUT_KEYBOARD is not set
693# CONFIG_INPUT_MOUSE is not set
694# CONFIG_INPUT_JOYSTICK is not set
695# CONFIG_INPUT_TOUCHSCREEN is not set
696# CONFIG_INPUT_MISC is not set
697
698#
699# Hardware I/O ports
700#
701CONFIG_SERIO=y
702# CONFIG_SERIO_I8042 is not set
703# CONFIG_SERIO_SERPORT is not set
704# CONFIG_SERIO_PCIPS2 is not set
705CONFIG_SERIO_LIBPS2=y
706# CONFIG_SERIO_RAW is not set
707# CONFIG_GAMEPORT is not set
708
709#
710# Character devices
711#
712CONFIG_VT=y
713CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y
715# CONFIG_VT_HW_CONSOLE_BINDING is not set
716# CONFIG_SERIAL_NONSTANDARD is not set
717
718#
719# Serial drivers
720#
721# CONFIG_SERIAL_8250 is not set
722
723#
724# Non-8250 serial port support
725#
726# CONFIG_SERIAL_PNX8XXX is not set
727# CONFIG_SERIAL_JSM is not set
728CONFIG_UNIX98_PTYS=y
729CONFIG_LEGACY_PTYS=y
730CONFIG_LEGACY_PTY_COUNT=256
731
732#
733# IPMI
734#
735# CONFIG_IPMI_HANDLER is not set
736
737#
738# Watchdog Cards
739#
740# CONFIG_WATCHDOG is not set
741CONFIG_HW_RANDOM=y
742# CONFIG_RTC is not set
743# CONFIG_GEN_RTC is not set
744# CONFIG_DTLK is not set
745# CONFIG_R3964 is not set
746# CONFIG_APPLICOM is not set
747# CONFIG_DRM is not set
748# CONFIG_RAW_DRIVER is not set
749
750#
751# TPM devices
752#
753# CONFIG_TCG_TPM is not set
754
755#
756# I2C support
757#
758# CONFIG_I2C is not set
759
760#
761# SPI support
762#
763# CONFIG_SPI is not set
764# CONFIG_SPI_MASTER is not set
765
766#
767# Dallas's 1-wire bus
768#
769# CONFIG_W1 is not set
770
771#
772# Hardware Monitoring support
773#
774CONFIG_HWMON=y
775# CONFIG_HWMON_VID is not set
776# CONFIG_SENSORS_ABITUGURU is not set
777# CONFIG_SENSORS_F71805F is not set
778# CONFIG_SENSORS_VT1211 is not set
779# CONFIG_HWMON_DEBUG_CHIP is not set
780
781#
782# Multimedia devices
783#
784# CONFIG_VIDEO_DEV is not set
785
786#
787# Digital Video Broadcasting Devices
788#
789# CONFIG_DVB is not set
790# CONFIG_USB_DABUSB is not set
791
792#
793# Graphics support
794#
795CONFIG_FIRMWARE_EDID=y
796# CONFIG_FB is not set
797
798#
799# Console display driver support
800#
801# CONFIG_VGA_CONSOLE is not set
802CONFIG_DUMMY_CONSOLE=y
803# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
804
805#
806# Sound
807#
808# CONFIG_SOUND is not set
809
810#
811# USB support
812#
813CONFIG_USB_ARCH_HAS_HCD=y
814CONFIG_USB_ARCH_HAS_OHCI=y
815CONFIG_USB_ARCH_HAS_EHCI=y
816CONFIG_USB=y
817# CONFIG_USB_DEBUG is not set
818
819#
820# Miscellaneous USB options
821#
822# CONFIG_USB_DEVICEFS is not set
823# CONFIG_USB_BANDWIDTH is not set
824# CONFIG_USB_DYNAMIC_MINORS is not set
825# CONFIG_USB_MULTITHREAD_PROBE is not set
826# CONFIG_USB_OTG is not set
827
828#
829# USB Host Controller Drivers
830#
831# CONFIG_USB_EHCI_HCD is not set
832# CONFIG_USB_ISP116X_HCD is not set
833CONFIG_USB_OHCI_HCD=y
834# CONFIG_USB_OHCI_BIG_ENDIAN is not set
835CONFIG_USB_OHCI_LITTLE_ENDIAN=y
836# CONFIG_USB_UHCI_HCD is not set
837# CONFIG_USB_SL811_HCD is not set
838
839#
840# USB Device Class drivers
841#
842# CONFIG_USB_ACM is not set
843# CONFIG_USB_PRINTER is not set
844
845#
846# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
847#
848
849#
850# may also be needed; see USB_STORAGE Help for more information
851#
852CONFIG_USB_STORAGE=y
853# CONFIG_USB_STORAGE_DEBUG is not set
854CONFIG_USB_STORAGE_DATAFAB=y
855CONFIG_USB_STORAGE_FREECOM=y
856CONFIG_USB_STORAGE_ISD200=y
857CONFIG_USB_STORAGE_DPCM=y
858CONFIG_USB_STORAGE_USBAT=y
859CONFIG_USB_STORAGE_SDDR09=y
860CONFIG_USB_STORAGE_SDDR55=y
861CONFIG_USB_STORAGE_JUMPSHOT=y
862# CONFIG_USB_STORAGE_ALAUDA is not set
863# CONFIG_USB_STORAGE_KARMA is not set
864# CONFIG_USB_LIBUSUAL is not set
865
866#
867# USB Input Devices
868#
869# CONFIG_USB_HID is not set
870
871#
872# USB HID Boot Protocol drivers
873#
874# CONFIG_USB_KBD is not set
875# CONFIG_USB_MOUSE is not set
876# CONFIG_USB_AIPTEK is not set
877# CONFIG_USB_WACOM is not set
878# CONFIG_USB_ACECAD is not set
879# CONFIG_USB_KBTAB is not set
880# CONFIG_USB_POWERMATE is not set
881# CONFIG_USB_TOUCHSCREEN is not set
882# CONFIG_USB_YEALINK is not set
883# CONFIG_USB_XPAD is not set
884# CONFIG_USB_ATI_REMOTE is not set
885# CONFIG_USB_ATI_REMOTE2 is not set
886# CONFIG_USB_KEYSPAN_REMOTE is not set
887# CONFIG_USB_APPLETOUCH is not set
888
889#
890# USB Imaging devices
891#
892# CONFIG_USB_MDC800 is not set
893# CONFIG_USB_MICROTEK is not set
894
895#
896# USB Network Adapters
897#
898# CONFIG_USB_CATC is not set
899# CONFIG_USB_KAWETH is not set
900# CONFIG_USB_PEGASUS is not set
901# CONFIG_USB_RTL8150 is not set
902# CONFIG_USB_USBNET_MII is not set
903# CONFIG_USB_USBNET is not set
904CONFIG_USB_MON=y
905
906#
907# USB port drivers
908#
909
910#
911# USB Serial Converter support
912#
913# CONFIG_USB_SERIAL is not set
914
915#
916# USB Miscellaneous drivers
917#
918# CONFIG_USB_EMI62 is not set
919# CONFIG_USB_EMI26 is not set
920# CONFIG_USB_ADUTUX is not set
921# CONFIG_USB_AUERSWALD is not set
922# CONFIG_USB_RIO500 is not set
923# CONFIG_USB_LEGOTOWER is not set
924# CONFIG_USB_LCD is not set
925# CONFIG_USB_LED is not set
926# CONFIG_USB_CYPRESS_CY7C63 is not set
927# CONFIG_USB_CYTHERM is not set
928# CONFIG_USB_PHIDGET is not set
929# CONFIG_USB_IDMOUSE is not set
930# CONFIG_USB_FTDI_ELAN is not set
931# CONFIG_USB_APPLEDISPLAY is not set
932# CONFIG_USB_LD is not set
933# CONFIG_USB_TRANCEVIBRATOR is not set
934
935#
936# USB DSL modem support
937#
938
939#
940# USB Gadget Support
941#
942# CONFIG_USB_GADGET is not set
943
944#
945# MMC/SD Card support
946#
947# CONFIG_MMC is not set
948
949#
950# LED devices
951#
952# CONFIG_NEW_LEDS is not set
953
954#
955# LED drivers
956#
957
958#
959# LED Triggers
960#
961
962#
963# InfiniBand support
964#
965# CONFIG_INFINIBAND is not set
966
967#
968# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
969#
970
971#
972# Real Time Clock
973#
974# CONFIG_RTC_CLASS is not set
975
976#
977# DMA Engine support
978#
979# CONFIG_DMA_ENGINE is not set
980
981#
982# DMA Clients
983#
984
985#
986# DMA Devices
987#
988
989#
990# File systems
991#
992CONFIG_EXT2_FS=y
993# CONFIG_EXT2_FS_XATTR is not set
994# CONFIG_EXT2_FS_XIP is not set
995# CONFIG_EXT3_FS is not set
996# CONFIG_EXT4DEV_FS is not set
997# CONFIG_REISERFS_FS is not set
998# CONFIG_JFS_FS is not set
999# CONFIG_FS_POSIX_ACL is not set
1000# CONFIG_XFS_FS is not set
1001# CONFIG_GFS2_FS is not set
1002# CONFIG_OCFS2_FS is not set
1003# CONFIG_MINIX_FS is not set
1004# CONFIG_ROMFS_FS is not set
1005CONFIG_INOTIFY=y
1006CONFIG_INOTIFY_USER=y
1007# CONFIG_QUOTA is not set
1008# CONFIG_DNOTIFY is not set
1009# CONFIG_AUTOFS_FS is not set
1010# CONFIG_AUTOFS4_FS is not set
1011# CONFIG_FUSE_FS is not set
1012
1013#
1014# CD-ROM/DVD Filesystems
1015#
1016# CONFIG_ISO9660_FS is not set
1017# CONFIG_UDF_FS is not set
1018
1019#
1020# DOS/FAT/NT Filesystems
1021#
1022CONFIG_FAT_FS=y
1023CONFIG_MSDOS_FS=y
1024CONFIG_VFAT_FS=y
1025CONFIG_FAT_DEFAULT_CODEPAGE=437
1026CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1027# CONFIG_NTFS_FS is not set
1028
1029#
1030# Pseudo filesystems
1031#
1032CONFIG_PROC_FS=y
1033# CONFIG_PROC_KCORE is not set
1034CONFIG_PROC_SYSCTL=y
1035CONFIG_SYSFS=y
1036CONFIG_TMPFS=y
1037# CONFIG_TMPFS_POSIX_ACL is not set
1038# CONFIG_HUGETLB_PAGE is not set
1039CONFIG_RAMFS=y
1040# CONFIG_CONFIGFS_FS is not set
1041
1042#
1043# Miscellaneous filesystems
1044#
1045# CONFIG_ADFS_FS is not set
1046# CONFIG_AFFS_FS is not set
1047# CONFIG_HFS_FS is not set
1048# CONFIG_HFSPLUS_FS is not set
1049# CONFIG_BEFS_FS is not set
1050# CONFIG_BFS_FS is not set
1051# CONFIG_EFS_FS is not set
1052# CONFIG_CRAMFS is not set
1053# CONFIG_VXFS_FS is not set
1054# CONFIG_HPFS_FS is not set
1055# CONFIG_QNX4FS_FS is not set
1056# CONFIG_SYSV_FS is not set
1057# CONFIG_UFS_FS is not set
1058
1059#
1060# Network File Systems
1061#
1062CONFIG_NFS_FS=y
1063CONFIG_NFS_V3=y
1064# CONFIG_NFS_V3_ACL is not set
1065# CONFIG_NFS_V4 is not set
1066# CONFIG_NFS_DIRECTIO is not set
1067CONFIG_NFSD=m
1068# CONFIG_NFSD_V3 is not set
1069# CONFIG_NFSD_TCP is not set
1070CONFIG_ROOT_NFS=y
1071CONFIG_LOCKD=y
1072CONFIG_LOCKD_V4=y
1073CONFIG_EXPORTFS=m
1074CONFIG_NFS_COMMON=y
1075CONFIG_SUNRPC=y
1076# CONFIG_RPCSEC_GSS_KRB5 is not set
1077# CONFIG_RPCSEC_GSS_SPKM3 is not set
1078# CONFIG_SMB_FS is not set
1079# CONFIG_CIFS is not set
1080# CONFIG_NCP_FS is not set
1081# CONFIG_CODA_FS is not set
1082# CONFIG_AFS_FS is not set
1083# CONFIG_9P_FS is not set
1084
1085#
1086# Partition Types
1087#
1088# CONFIG_PARTITION_ADVANCED is not set
1089CONFIG_MSDOS_PARTITION=y
1090
1091#
1092# Native Language Support
1093#
1094CONFIG_NLS=y
1095CONFIG_NLS_DEFAULT="iso8859-1"
1096# CONFIG_NLS_CODEPAGE_437 is not set
1097# CONFIG_NLS_CODEPAGE_737 is not set
1098# CONFIG_NLS_CODEPAGE_775 is not set
1099# CONFIG_NLS_CODEPAGE_850 is not set
1100# CONFIG_NLS_CODEPAGE_852 is not set
1101# CONFIG_NLS_CODEPAGE_855 is not set
1102# CONFIG_NLS_CODEPAGE_857 is not set
1103# CONFIG_NLS_CODEPAGE_860 is not set
1104# CONFIG_NLS_CODEPAGE_861 is not set
1105# CONFIG_NLS_CODEPAGE_862 is not set
1106# CONFIG_NLS_CODEPAGE_863 is not set
1107# CONFIG_NLS_CODEPAGE_864 is not set
1108# CONFIG_NLS_CODEPAGE_865 is not set
1109# CONFIG_NLS_CODEPAGE_866 is not set
1110# CONFIG_NLS_CODEPAGE_869 is not set
1111# CONFIG_NLS_CODEPAGE_936 is not set
1112# CONFIG_NLS_CODEPAGE_950 is not set
1113# CONFIG_NLS_CODEPAGE_932 is not set
1114# CONFIG_NLS_CODEPAGE_949 is not set
1115# CONFIG_NLS_CODEPAGE_874 is not set
1116# CONFIG_NLS_ISO8859_8 is not set
1117# CONFIG_NLS_CODEPAGE_1250 is not set
1118# CONFIG_NLS_CODEPAGE_1251 is not set
1119# CONFIG_NLS_ASCII is not set
1120# CONFIG_NLS_ISO8859_1 is not set
1121# CONFIG_NLS_ISO8859_2 is not set
1122# CONFIG_NLS_ISO8859_3 is not set
1123# CONFIG_NLS_ISO8859_4 is not set
1124# CONFIG_NLS_ISO8859_5 is not set
1125# CONFIG_NLS_ISO8859_6 is not set
1126# CONFIG_NLS_ISO8859_7 is not set
1127# CONFIG_NLS_ISO8859_9 is not set
1128# CONFIG_NLS_ISO8859_13 is not set
1129# CONFIG_NLS_ISO8859_14 is not set
1130# CONFIG_NLS_ISO8859_15 is not set
1131# CONFIG_NLS_KOI8_R is not set
1132# CONFIG_NLS_KOI8_U is not set
1133# CONFIG_NLS_UTF8 is not set
1134
1135#
1136# Profiling support
1137#
1138# CONFIG_PROFILING is not set
1139
1140#
1141# Kernel hacking
1142#
1143CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1144# CONFIG_PRINTK_TIME is not set
1145CONFIG_ENABLE_MUST_CHECK=y
1146CONFIG_MAGIC_SYSRQ=y
1147# CONFIG_UNUSED_SYMBOLS is not set
1148CONFIG_DEBUG_KERNEL=y
1149CONFIG_LOG_BUF_SHIFT=14
1150CONFIG_DETECT_SOFTLOCKUP=y
1151# CONFIG_SCHEDSTATS is not set
1152CONFIG_DEBUG_SLAB=y
1153# CONFIG_DEBUG_SLAB_LEAK is not set
1154# CONFIG_DEBUG_RT_MUTEXES is not set
1155# CONFIG_RT_MUTEX_TESTER is not set
1156# CONFIG_DEBUG_SPINLOCK is not set
1157# CONFIG_DEBUG_MUTEXES is not set
1158# CONFIG_DEBUG_RWSEMS is not set
1159# CONFIG_DEBUG_LOCK_ALLOC is not set
1160# CONFIG_PROVE_LOCKING is not set
1161# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1162# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1163# CONFIG_DEBUG_KOBJECT is not set
1164# CONFIG_DEBUG_INFO is not set
1165# CONFIG_DEBUG_FS is not set
1166# CONFIG_DEBUG_VM is not set
1167# CONFIG_DEBUG_LIST is not set
1168CONFIG_FORCED_INLINING=y
1169CONFIG_HEADERS_CHECK=y
1170# CONFIG_RCU_TORTURE_TEST is not set
1171CONFIG_CROSSCOMPILE=y
1172CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
1173# CONFIG_DEBUG_STACK_USAGE is not set
1174# CONFIG_KGDB is not set
1175# CONFIG_RUNTIME_DEBUG is not set
1176# CONFIG_MIPS_UNCACHED is not set
1177
1178#
1179# Security options
1180#
1181# CONFIG_KEYS is not set
1182# CONFIG_SECURITY is not set
1183
1184#
1185# Cryptographic options
1186#
1187CONFIG_CRYPTO=y
1188CONFIG_CRYPTO_ALGAPI=m
1189CONFIG_CRYPTO_BLKCIPHER=m
1190CONFIG_CRYPTO_MANAGER=m
1191# CONFIG_CRYPTO_HMAC is not set
1192# CONFIG_CRYPTO_NULL is not set
1193# CONFIG_CRYPTO_MD4 is not set
1194CONFIG_CRYPTO_MD5=m
1195# CONFIG_CRYPTO_SHA1 is not set
1196# CONFIG_CRYPTO_SHA256 is not set
1197# CONFIG_CRYPTO_SHA512 is not set
1198# CONFIG_CRYPTO_WP512 is not set
1199# CONFIG_CRYPTO_TGR192 is not set
1200CONFIG_CRYPTO_ECB=m
1201CONFIG_CRYPTO_CBC=m
1202# CONFIG_CRYPTO_DES is not set
1203# CONFIG_CRYPTO_BLOWFISH is not set
1204# CONFIG_CRYPTO_TWOFISH is not set
1205# CONFIG_CRYPTO_SERPENT is not set
1206# CONFIG_CRYPTO_AES is not set
1207# CONFIG_CRYPTO_CAST5 is not set
1208# CONFIG_CRYPTO_CAST6 is not set
1209# CONFIG_CRYPTO_TEA is not set
1210# CONFIG_CRYPTO_ARC4 is not set
1211# CONFIG_CRYPTO_KHAZAD is not set
1212# CONFIG_CRYPTO_ANUBIS is not set
1213# CONFIG_CRYPTO_DEFLATE is not set
1214# CONFIG_CRYPTO_MICHAEL_MIC is not set
1215CONFIG_CRYPTO_CRC32C=m
1216# CONFIG_CRYPTO_TEST is not set
1217
1218#
1219# Hardware crypto devices
1220#
1221
1222#
1223# Library routines
1224#
1225CONFIG_CRC_CCITT=m
1226# CONFIG_CRC16 is not set
1227CONFIG_CRC32=y
1228CONFIG_LIBCRC32C=m
1229CONFIG_PLIST=y
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index 64b9fbf44a64..5bc3248e50e4 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -57,7 +57,7 @@ CONFIG_PNX8550_V2PCI=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/qemu_defconfig b/arch/mips/configs/qemu_defconfig
index 9b0dab822bd0..aa61f0f030a5 100644
--- a/arch/mips/configs/qemu_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -59,7 +59,7 @@ CONFIG_QEMU=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/rbhma4500_defconfig b/arch/mips/configs/rbhma4500_defconfig
index dd0296036026..f9e8f41d17f2 100644
--- a/arch/mips/configs/rbhma4500_defconfig
+++ b/arch/mips/configs/rbhma4500_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65CONFIG_TOSHIBA_RBTX4938=y 65CONFIG_TOSHIBA_RBTX4938=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index d8a498d64d62..496aa67b9f82 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62CONFIG_SNI_RM200_PCI=y 62CONFIG_SNI_RM=y
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 805a4fe450f5..e33c17200b39 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -59,7 +59,7 @@ CONFIG_SIBYTE_SWARM=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 6fcb656d8d87..83fb932f9d4b 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -59,7 +59,7 @@ CONFIG_MIPS_SEAD=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index dc312f19ada7..e9d4eae45bfa 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index 85615d99b01a..c19597fb0c32 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index f7e8194809a1..97d94f96990f 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -57,7 +57,7 @@ CONFIG_MACH_VR41XX=y
57# CONFIG_SIBYTE_LITTLESUR is not set 57# CONFIG_SIBYTE_LITTLESUR is not set
58# CONFIG_SIBYTE_CRHINE is not set 58# CONFIG_SIBYTE_CRHINE is not set
59# CONFIG_SIBYTE_CRHONE is not set 59# CONFIG_SIBYTE_CRHONE is not set
60# CONFIG_SNI_RM200_PCI is not set 60# CONFIG_SNI_RM is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 61# CONFIG_TOSHIBA_JMR3927 is not set
62# CONFIG_TOSHIBA_RBTX4927 is not set 62# CONFIG_TOSHIBA_RBTX4927 is not set
63# CONFIG_TOSHIBA_RBTX4938 is not set 63# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 863f6a7cadfd..553734a47b62 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -59,7 +59,7 @@ CONFIG_MACH_VR41XX=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig
index c10267d61cc9..d3dfb702bb7c 100644
--- a/arch/mips/configs/wrppmc_defconfig
+++ b/arch/mips/configs/wrppmc_defconfig
@@ -59,7 +59,7 @@ CONFIG_WR_PPMC=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 4d3c1329f3cf..b9f74d6745ee 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -59,7 +59,7 @@ CONFIG_PMC_YOSEMITE=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index ba52705a2738..96249aa5df5d 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -53,14 +53,6 @@ vrc5477_irq_disable(unsigned int irq)
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base); 53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54} 54}
55 55
56static unsigned int vrc5477_irq_startup(unsigned int irq)
57{
58 vrc5477_irq_enable(irq);
59 return 0;
60}
61
62#define vrc5477_irq_shutdown vrc5477_irq_disable
63
64static void 56static void
65vrc5477_irq_ack(unsigned int irq) 57vrc5477_irq_ack(unsigned int irq)
66{ 58{
@@ -91,11 +83,10 @@ vrc5477_irq_end(unsigned int irq)
91 83
92struct irq_chip vrc5477_irq_controller = { 84struct irq_chip vrc5477_irq_controller = {
93 .typename = "vrc5477_irq", 85 .typename = "vrc5477_irq",
94 .startup = vrc5477_irq_startup,
95 .shutdown = vrc5477_irq_shutdown,
96 .enable = vrc5477_irq_enable,
97 .disable = vrc5477_irq_disable,
98 .ack = vrc5477_irq_ack, 86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
99 .end = vrc5477_irq_end 90 .end = vrc5477_irq_end
100}; 91};
101 92
@@ -103,12 +94,8 @@ void __init vrc5477_irq_init(u32 irq_base)
103{ 94{
104 u32 i; 95 u32 i;
105 96
106 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) { 97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
107 irq_desc[i].status = IRQ_DISABLED; 98 set_irq_chip(i, &vrc5477_irq_controller);
108 irq_desc[i].action = NULL;
109 irq_desc[i].depth = 1;
110 irq_desc[i].chip = &vrc5477_irq_controller;
111 }
112 99
113 vrc5477_irq_base = irq_base; 100 vrc5477_irq_base = irq_base;
114} 101}
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..6d55e8aab668 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/spinlock.h>
22#include <linux/types.h> 21#include <linux/types.h>
23 22
24#include <asm/addrspace.h> 23#include <asm/addrspace.h>
@@ -26,6 +25,7 @@
26#include <asm/cpu.h> 25#include <asm/cpu.h>
27#include <asm/irq_regs.h> 26#include <asm/irq_regs.h>
28#include <asm/processor.h> 27#include <asm/processor.h>
28#include <asm/ptrace.h>
29#include <asm/system.h> 29#include <asm/system.h>
30#include <asm/traps.h> 30#include <asm/traps.h>
31 31
@@ -231,13 +231,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
231static inline void dec_kn02_be_init(void) 231static inline void dec_kn02_be_init(void)
232{ 232{
233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
234 unsigned long flags;
235 234
236 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); 235 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
237 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); 236 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
238 237
239 spin_lock_irqsave(&kn02_lock, flags);
240
241 /* Preset write-only bits of the Control Register cache. */ 238 /* Preset write-only bits of the Control Register cache. */
242 cached_kn02_csr = *csr | KN02_CSR_LEDS; 239 cached_kn02_csr = *csr | KN02_CSR_LEDS;
243 240
@@ -247,8 +244,6 @@ static inline void dec_kn02_be_init(void)
247 cached_kn02_csr |= KN02_CSR_CORRECT; 244 cached_kn02_csr |= KN02_CSR_CORRECT;
248 *csr = cached_kn02_csr; 245 *csr = cached_kn02_csr;
249 iob(); 246 iob();
250
251 spin_unlock_irqrestore(&kn02_lock, flags);
252} 247}
253 248
254static inline void dec_kn03_be_init(void) 249static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 31dd47d1002d..b251ef864c33 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -267,7 +267,7 @@ handle_it:
267 LONG_L s0, TI_REGS($28) 267 LONG_L s0, TI_REGS($28)
268 LONG_S sp, TI_REGS($28) 268 LONG_S sp, TI_REGS($28)
269 PTR_LA ra, ret_from_irq 269 PTR_LA ra, ret_from_irq
270 j do_IRQ 270 j dec_irq_dispatch
271 nop 271 nop
272 272
273#ifdef CONFIG_32BIT 273#ifdef CONFIG_32BIT
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..4c7cb4048d35 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/spinlock.h>
17#include <linux/types.h> 16#include <linux/types.h>
18 17
19#include <asm/dec/ioasic.h> 18#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
21#include <asm/dec/ioasic_ints.h> 20#include <asm/dec/ioasic_ints.h>
22 21
23 22
24static DEFINE_SPINLOCK(ioasic_lock);
25
26static int ioasic_irq_base; 23static int ioasic_irq_base;
27 24
28 25
@@ -52,65 +49,30 @@ static inline void clear_ioasic_irq(unsigned int irq)
52 ioasic_write(IO_REG_SIR, sir); 49 ioasic_write(IO_REG_SIR, sir);
53} 50}
54 51
55static inline void enable_ioasic_irq(unsigned int irq)
56{
57 unsigned long flags;
58
59 spin_lock_irqsave(&ioasic_lock, flags);
60 unmask_ioasic_irq(irq);
61 spin_unlock_irqrestore(&ioasic_lock, flags);
62}
63
64static inline void disable_ioasic_irq(unsigned int irq)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&ioasic_lock, flags);
69 mask_ioasic_irq(irq);
70 spin_unlock_irqrestore(&ioasic_lock, flags);
71}
72
73
74static inline unsigned int startup_ioasic_irq(unsigned int irq)
75{
76 enable_ioasic_irq(irq);
77 return 0;
78}
79
80#define shutdown_ioasic_irq disable_ioasic_irq
81
82static inline void ack_ioasic_irq(unsigned int irq) 52static inline void ack_ioasic_irq(unsigned int irq)
83{ 53{
84 spin_lock(&ioasic_lock);
85 mask_ioasic_irq(irq); 54 mask_ioasic_irq(irq);
86 spin_unlock(&ioasic_lock);
87 fast_iob(); 55 fast_iob();
88} 56}
89 57
90static inline void end_ioasic_irq(unsigned int irq) 58static inline void end_ioasic_irq(unsigned int irq)
91{ 59{
92 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
93 enable_ioasic_irq(irq); 61 unmask_ioasic_irq(irq);
94} 62}
95 63
96static struct irq_chip ioasic_irq_type = { 64static struct irq_chip ioasic_irq_type = {
97 .typename = "IO-ASIC", 65 .typename = "IO-ASIC",
98 .startup = startup_ioasic_irq,
99 .shutdown = shutdown_ioasic_irq,
100 .enable = enable_ioasic_irq,
101 .disable = disable_ioasic_irq,
102 .ack = ack_ioasic_irq, 66 .ack = ack_ioasic_irq,
103 .end = end_ioasic_irq, 67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq,
104}; 70};
105 71
106 72
107#define startup_ioasic_dma_irq startup_ioasic_irq 73#define unmask_ioasic_dma_irq unmask_ioasic_irq
108
109#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
110
111#define enable_ioasic_dma_irq enable_ioasic_irq
112 74
113#define disable_ioasic_dma_irq disable_ioasic_irq 75#define mask_ioasic_dma_irq mask_ioasic_irq
114 76
115#define ack_ioasic_dma_irq ack_ioasic_irq 77#define ack_ioasic_dma_irq ack_ioasic_irq
116 78
@@ -123,11 +85,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
123 85
124static struct irq_chip ioasic_dma_irq_type = { 86static struct irq_chip ioasic_dma_irq_type = {
125 .typename = "IO-ASIC-DMA", 87 .typename = "IO-ASIC-DMA",
126 .startup = startup_ioasic_dma_irq,
127 .shutdown = shutdown_ioasic_dma_irq,
128 .enable = enable_ioasic_dma_irq,
129 .disable = disable_ioasic_dma_irq,
130 .ack = ack_ioasic_dma_irq, 88 .ack = ack_ioasic_dma_irq,
89 .mask = mask_ioasic_dma_irq,
90 .mask_ack = ack_ioasic_dma_irq,
91 .unmask = unmask_ioasic_dma_irq,
131 .end = end_ioasic_dma_irq, 92 .end = end_ioasic_dma_irq,
132}; 93};
133 94
@@ -140,18 +101,11 @@ void __init init_ioasic_irqs(int base)
140 ioasic_write(IO_REG_SIMR, 0); 101 ioasic_write(IO_REG_SIMR, 0);
141 fast_iob(); 102 fast_iob();
142 103
143 for (i = base; i < base + IO_INR_DMA; i++) { 104 for (i = base; i < base + IO_INR_DMA; i++)
144 irq_desc[i].status = IRQ_DISABLED; 105 set_irq_chip_and_handler(i, &ioasic_irq_type,
145 irq_desc[i].action = 0; 106 handle_level_irq);
146 irq_desc[i].depth = 1; 107 for (; i < base + IO_IRQ_LINES; i++)
147 irq_desc[i].chip = &ioasic_irq_type; 108 set_irq_chip(i, &ioasic_dma_irq_type);
148 }
149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1;
153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 }
155 109
156 ioasic_irq_base = base; 110 ioasic_irq_base = base;
157} 111}
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
index f19b4617a0a6..d3b8002bf1e7 100644
--- a/arch/mips/dec/kn01-berr.c
+++ b/arch/mips/dec/kn01-berr.c
@@ -20,8 +20,10 @@
20#include <linux/types.h> 20#include <linux/types.h>
21 21
22#include <asm/inst.h> 22#include <asm/inst.h>
23#include <asm/irq_regs.h>
23#include <asm/mipsregs.h> 24#include <asm/mipsregs.h>
24#include <asm/page.h> 25#include <asm/page.h>
26#include <asm/ptrace.h>
25#include <asm/system.h> 27#include <asm/system.h>
26#include <asm/traps.h> 28#include <asm/traps.h>
27#include <asm/uaccess.h> 29#include <asm/uaccess.h>
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..916e46b8ccd8 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <linux/types.h> 17#include <linux/types.h>
19 18
20#include <asm/dec/kn02.h> 19#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
29 * There is no default value -- it has to be initialized. 28 * There is no default value -- it has to be initialized.
30 */ 29 */
31u32 cached_kn02_csr; 30u32 cached_kn02_csr;
32DEFINE_SPINLOCK(kn02_lock);
33 31
34 32
35static int kn02_irq_base; 33static int kn02_irq_base;
@@ -53,55 +51,18 @@ static inline void mask_kn02_irq(unsigned int irq)
53 *csr = cached_kn02_csr; 51 *csr = cached_kn02_csr;
54} 52}
55 53
56static inline void enable_kn02_irq(unsigned int irq)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&kn02_lock, flags);
61 unmask_kn02_irq(irq);
62 spin_unlock_irqrestore(&kn02_lock, flags);
63}
64
65static inline void disable_kn02_irq(unsigned int irq)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&kn02_lock, flags);
70 mask_kn02_irq(irq);
71 spin_unlock_irqrestore(&kn02_lock, flags);
72}
73
74
75static unsigned int startup_kn02_irq(unsigned int irq)
76{
77 enable_kn02_irq(irq);
78 return 0;
79}
80
81#define shutdown_kn02_irq disable_kn02_irq
82
83static void ack_kn02_irq(unsigned int irq) 54static void ack_kn02_irq(unsigned int irq)
84{ 55{
85 spin_lock(&kn02_lock);
86 mask_kn02_irq(irq); 56 mask_kn02_irq(irq);
87 spin_unlock(&kn02_lock);
88 iob(); 57 iob();
89} 58}
90 59
91static void end_kn02_irq(unsigned int irq)
92{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 enable_kn02_irq(irq);
95}
96
97static struct irq_chip kn02_irq_type = { 60static struct irq_chip kn02_irq_type = {
98 .typename = "KN02-CSR", 61 .typename = "KN02-CSR",
99 .startup = startup_kn02_irq,
100 .shutdown = shutdown_kn02_irq,
101 .enable = enable_kn02_irq,
102 .disable = disable_kn02_irq,
103 .ack = ack_kn02_irq, 62 .ack = ack_kn02_irq,
104 .end = end_kn02_irq, 63 .mask = mask_kn02_irq,
64 .mask_ack = ack_kn02_irq,
65 .unmask = unmask_kn02_irq,
105}; 66};
106 67
107 68
@@ -109,22 +70,15 @@ void __init init_kn02_irqs(int base)
109{ 70{
110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 71 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR); 72 KN02_CSR);
112 unsigned long flags;
113 int i; 73 int i;
114 74
115 /* Mask interrupts. */ 75 /* Mask interrupts. */
116 spin_lock_irqsave(&kn02_lock, flags);
117 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 76 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
118 *csr = cached_kn02_csr; 77 *csr = cached_kn02_csr;
119 iob(); 78 iob();
120 spin_unlock_irqrestore(&kn02_lock, flags); 79
121 80 for (i = base; i < base + KN02_IRQ_LINES; i++)
122 for (i = base; i < base + KN02_IRQ_LINES; i++) { 81 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1;
126 irq_desc[i].chip = &kn02_irq_type;
127 }
128 82
129 kn02_irq_base = base; 83 kn02_irq_base = base;
130} 84}
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6b7481e97bec..d34032ac492a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -761,3 +761,9 @@ void __init arch_init_irq(void)
761 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 761 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
763} 763}
764
765asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
766{
767 do_IRQ(irq);
768 return 0;
769}
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 69e424e9ab6f..8b7e0c17ac35 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -151,7 +151,7 @@ static void dec_timer_ack(void)
151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */ 151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */
152} 152}
153 153
154static unsigned int dec_ioasic_hpt_read(void) 154static cycle_t dec_ioasic_hpt_read(void)
155{ 155{
156 /* 156 /*
157 * The free-running counter is 32-bit which is good for about 157 * The free-running counter is 32-bit which is good for about
@@ -171,7 +171,7 @@ void __init dec_time_init(void)
171 171
172 if (!cpu_has_counter && IOASIC) 172 if (!cpu_has_counter && IOASIC)
173 /* For pre-R4k systems we use the I/O ASIC's counter. */ 173 /* For pre-R4k systems we use the I/O ASIC's counter. */
174 mips_hpt_read = dec_ioasic_hpt_read; 174 clocksource_mips.read = dec_ioasic_hpt_read;
175 175
176 /* Set up the rate of periodic DS1287 interrupts. */ 176 /* Set up the rate of periodic DS1287 interrupts. */
177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); 177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index 21d53e0c9ee8..f9812d1e4579 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -59,7 +59,7 @@ CONFIG_SGI_IP22=y
59# CONFIG_SIBYTE_LITTLESUR is not set 59# CONFIG_SIBYTE_LITTLESUR is not set
60# CONFIG_SIBYTE_CRHINE is not set 60# CONFIG_SIBYTE_CRHINE is not set
61# CONFIG_SIBYTE_CRHONE is not set 61# CONFIG_SIBYTE_CRHONE is not set
62# CONFIG_SNI_RM200_PCI is not set 62# CONFIG_SNI_RM is not set
63# CONFIG_TOSHIBA_JMR3927 is not set 63# CONFIG_TOSHIBA_JMR3927 is not set
64# CONFIG_TOSHIBA_RBTX4927 is not set 64# CONFIG_TOSHIBA_RBTX4927 is not set
65# CONFIG_TOSHIBA_RBTX4938 is not set 65# CONFIG_TOSHIBA_RBTX4938 is not set
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index 197ed4c2ba04..8d880f0b06ec 100644
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -56,49 +56,21 @@ static void emma2rh_irq_disable(unsigned int irq)
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base); 56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57} 57}
58 58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq)
76{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
78 ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
79}
80
81struct irq_chip emma2rh_irq_controller = { 59struct irq_chip emma2rh_irq_controller = {
82 .typename = "emma2rh_irq", 60 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup, 61 .ack = emma2rh_irq_disable,
84 .shutdown = emma2rh_irq_shutdown, 62 .mask = emma2rh_irq_disable,
85 .enable = emma2rh_irq_enable, 63 .mask_ack = emma2rh_irq_disable,
86 .disable = emma2rh_irq_disable, 64 .unmask = emma2rh_irq_enable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90}; 65};
91 66
92void emma2rh_irq_init(u32 irq_base) 67void emma2rh_irq_init(u32 irq_base)
93{ 68{
94 u32 i; 69 u32 i;
95 70
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { 71 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
97 irq_desc[i].status = IRQ_DISABLED; 72 set_irq_chip_and_handler(i, &emma2rh_irq_controller,
98 irq_desc[i].action = NULL; 73 handle_level_irq);
99 irq_desc[i].depth = 1;
100 irq_desc[i].chip = &emma2rh_irq_controller;
101 }
102 74
103 emma2rh_irq_base = irq_base; 75 emma2rh_irq_base = irq_base;
104} 76}
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index 0b36eb001e62..2116d9be5fa9 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -48,46 +48,21 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); 48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49} 49}
50 50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq)
65{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
67 ll_emma2rh_sw_irq_enable(irq - emma2rh_sw_irq_base);
68}
69
70struct irq_chip emma2rh_sw_irq_controller = { 51struct irq_chip emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq", 52 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup, 53 .ack = emma2rh_sw_irq_disable,
73 .shutdown = emma2rh_sw_irq_shutdown, 54 .mask = emma2rh_sw_irq_disable,
74 .enable = emma2rh_sw_irq_enable, 55 .mask_ack = emma2rh_sw_irq_disable,
75 .disable = emma2rh_sw_irq_disable, 56 .unmask = emma2rh_sw_irq_enable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79}; 57};
80 58
81void emma2rh_sw_irq_init(u32 irq_base) 59void emma2rh_sw_irq_init(u32 irq_base)
82{ 60{
83 u32 i; 61 u32 i;
84 62
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { 63 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
86 irq_desc[i].status = IRQ_DISABLED; 64 set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
87 irq_desc[i].action = NULL; 65 handle_level_irq);
88 irq_desc[i].depth = 2;
89 irq_desc[i].chip = &emma2rh_sw_irq_controller;
90 }
91 66
92 emma2rh_sw_irq_base = irq_base; 67 emma2rh_sw_irq_base = irq_base;
93} 68}
@@ -126,14 +101,6 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); 101 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127} 102}
128 103
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq) 104static void emma2rh_gpio_irq_ack(unsigned int irq)
138{ 105{
139 irq -= emma2rh_gpio_irq_base; 106 irq -= emma2rh_gpio_irq_base;
@@ -149,25 +116,19 @@ static void emma2rh_gpio_irq_end(unsigned int irq)
149 116
150struct irq_chip emma2rh_gpio_irq_controller = { 117struct irq_chip emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq", 118 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack, 119 .ack = emma2rh_gpio_irq_ack,
120 .mask = emma2rh_gpio_irq_disable,
121 .mask_ack = emma2rh_gpio_irq_ack,
122 .unmask = emma2rh_gpio_irq_enable,
157 .end = emma2rh_gpio_irq_end, 123 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159}; 124};
160 125
161void emma2rh_gpio_irq_init(u32 irq_base) 126void emma2rh_gpio_irq_init(u32 irq_base)
162{ 127{
163 u32 i; 128 u32 i;
164 129
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { 130 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
166 irq_desc[i].status = IRQ_DISABLED; 131 set_irq_chip(i, &emma2rh_gpio_irq_controller);
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].chip = &emma2rh_gpio_irq_controller;
170 }
171 132
172 emma2rh_gpio_irq_base = irq_base; 133 emma2rh_gpio_irq_base = irq_base;
173} 134}
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index ed4d82b9a24a..b3e5796c81d7 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void)
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
68{ 68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10); 70 clear_c0_status(9 << 10);
74 } else { 71 } else {
75 clear_c0_status(1 << (irq_nr + 8)); 72 clear_c0_status(1 << (irq_nr + 8));
76 } 73 }
77 local_irq_restore(flags);
78} 74}
79 75
80static void enable_ev64120_irq(unsigned int irq_nr) 76static void enable_ev64120_irq(unsigned int irq_nr)
81{ 77{
82 unsigned long flags;
83
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10); 79 set_c0_status(9 << 10);
87 else 80 else
88 set_c0_status(1 << (irq_nr + 8)); 81 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
90}
91
92static unsigned int startup_ev64120_irq(unsigned int irq)
93{
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
96} 82}
97 83
98#define shutdown_ev64120_irq disable_ev64120_irq
99#define mask_and_ack_ev64120_irq disable_ev64120_irq
100
101static void end_ev64120_irq(unsigned int irq) 84static void end_ev64120_irq(unsigned int irq)
102{ 85{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq)
106 89
107static struct irq_chip ev64120_irq_type = { 90static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120", 91 .typename = "EV64120",
109 .startup = startup_ev64120_irq, 92 .ack = disable_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq, 93 .mask = disable_ev64120_irq,
111 .enable = enable_ev64120_irq, 94 .mask_ack = disable_ev64120_irq,
112 .disable = disable_ev64120_irq, 95 .unmask = enable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq, 96 .end = end_ev64120_irq,
115 .set_affinity = NULL
116}; 97};
117 98
118void gt64120_irq_setup(void) 99void gt64120_irq_setup(void)
@@ -122,8 +103,6 @@ void gt64120_irq_setup(void)
122 */ 103 */
123 clear_c0_status(ST0_IM); 104 clear_c0_status(ST0_IM);
124 105
125 local_irq_disable();
126
127 /* 106 /*
128 * Enable timer. Other interrupts will be enabled as they are 107 * Enable timer. Other interrupts will be enabled as they are
129 * registered. 108 * registered.
@@ -133,16 +112,5 @@ void gt64120_irq_setup(void)
133 112
134void __init arch_init_irq(void) 113void __init arch_init_irq(void)
135{ 114{
136 int i;
137
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
145 }
146
147 gt64120_irq_setup(); 115 gt64120_irq_setup();
148} 116}
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index d5bd6b3a0933..f8d417b5c2bb 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -28,14 +28,6 @@ static void enable_r4030_irq(unsigned int irq)
28 spin_unlock_irqrestore(&r4030_lock, flags); 28 spin_unlock_irqrestore(&r4030_lock, flags);
29} 29}
30 30
31static unsigned int startup_r4030_irq(unsigned int irq)
32{
33 enable_r4030_irq(irq);
34 return 0; /* never anything pending */
35}
36
37#define shutdown_r4030_irq disable_r4030_irq
38
39void disable_r4030_irq(unsigned int irq) 31void disable_r4030_irq(unsigned int irq)
40{ 32{
41 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ));
@@ -47,34 +39,20 @@ void disable_r4030_irq(unsigned int irq)
47 spin_unlock_irqrestore(&r4030_lock, flags); 39 spin_unlock_irqrestore(&r4030_lock, flags);
48} 40}
49 41
50#define mask_and_ack_r4030_irq disable_r4030_irq
51
52static void end_r4030_irq(unsigned int irq)
53{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
55 enable_r4030_irq(irq);
56}
57
58static struct irq_chip r4030_irq_type = { 42static struct irq_chip r4030_irq_type = {
59 .typename = "R4030", 43 .typename = "R4030",
60 .startup = startup_r4030_irq, 44 .ack = disable_r4030_irq,
61 .shutdown = shutdown_r4030_irq, 45 .mask = disable_r4030_irq,
62 .enable = enable_r4030_irq, 46 .mask_ack = disable_r4030_irq,
63 .disable = disable_r4030_irq, 47 .unmask = enable_r4030_irq,
64 .ack = mask_and_ack_r4030_irq,
65 .end = end_r4030_irq,
66}; 48};
67 49
68void __init init_r4030_ints(void) 50void __init init_r4030_ints(void)
69{ 51{
70 int i; 52 int i;
71 53
72 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) { 54 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
73 irq_desc[i].status = IRQ_DISABLED; 55 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
74 irq_desc[i].action = 0;
75 irq_desc[i].depth = 1;
76 irq_desc[i].chip = &r4030_irq_type;
77 }
78 56
79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 57 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
80 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ 58 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index de4a238c28be..3da49c5aaf49 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -90,17 +90,6 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
90static void jmr3927_irq_disable(unsigned int irq_nr); 90static void jmr3927_irq_disable(unsigned int irq_nr);
91static void jmr3927_irq_enable(unsigned int irq_nr); 91static void jmr3927_irq_enable(unsigned int irq_nr);
92 92
93static DEFINE_SPINLOCK(jmr3927_irq_lock);
94
95static unsigned int jmr3927_irq_startup(unsigned int irq)
96{
97 jmr3927_irq_enable(irq);
98
99 return 0;
100}
101
102#define jmr3927_irq_shutdown jmr3927_irq_disable
103
104static void jmr3927_irq_ack(unsigned int irq) 93static void jmr3927_irq_ack(unsigned int irq)
105{ 94{
106 if (irq == JMR3927_IRQ_IRC_TMR0) 95 if (irq == JMR3927_IRQ_IRC_TMR0)
@@ -118,9 +107,7 @@ static void jmr3927_irq_end(unsigned int irq)
118static void jmr3927_irq_disable(unsigned int irq_nr) 107static void jmr3927_irq_disable(unsigned int irq_nr)
119{ 108{
120 struct tb_irq_space* sp; 109 struct tb_irq_space* sp;
121 unsigned long flags;
122 110
123 spin_lock_irqsave(&jmr3927_irq_lock, flags);
124 for (sp = tb_irq_spaces; sp; sp = sp->next) { 111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
125 if (sp->start_irqno <= irq_nr && 112 if (sp->start_irqno <= irq_nr &&
126 irq_nr < sp->start_irqno + sp->nr_irqs) { 113 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -130,15 +117,12 @@ static void jmr3927_irq_disable(unsigned int irq_nr)
130 break; 117 break;
131 } 118 }
132 } 119 }
133 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
134} 120}
135 121
136static void jmr3927_irq_enable(unsigned int irq_nr) 122static void jmr3927_irq_enable(unsigned int irq_nr)
137{ 123{
138 struct tb_irq_space* sp; 124 struct tb_irq_space* sp;
139 unsigned long flags;
140 125
141 spin_lock_irqsave(&jmr3927_irq_lock, flags);
142 for (sp = tb_irq_spaces; sp; sp = sp->next) { 126 for (sp = tb_irq_spaces; sp; sp = sp->next) {
143 if (sp->start_irqno <= irq_nr && 127 if (sp->start_irqno <= irq_nr &&
144 irq_nr < sp->start_irqno + sp->nr_irqs) { 128 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -148,7 +132,6 @@ static void jmr3927_irq_enable(unsigned int irq_nr)
148 break; 132 break;
149 } 133 }
150 } 134 }
151 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
152} 135}
153 136
154/* 137/*
@@ -457,11 +440,10 @@ void __init arch_init_irq(void)
457 440
458static struct irq_chip jmr3927_irq_controller = { 441static struct irq_chip jmr3927_irq_controller = {
459 .typename = "jmr3927_irq", 442 .typename = "jmr3927_irq",
460 .startup = jmr3927_irq_startup,
461 .shutdown = jmr3927_irq_shutdown,
462 .enable = jmr3927_irq_enable,
463 .disable = jmr3927_irq_disable,
464 .ack = jmr3927_irq_ack, 443 .ack = jmr3927_irq_ack,
444 .mask = jmr3927_irq_disable,
445 .mask_ack = jmr3927_irq_ack,
446 .unmask = jmr3927_irq_enable,
465 .end = jmr3927_irq_end, 447 .end = jmr3927_irq_end,
466}; 448};
467 449
@@ -469,12 +451,8 @@ void jmr3927_irq_init(u32 irq_base)
469{ 451{
470 u32 i; 452 u32 i;
471 453
472 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { 454 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
473 irq_desc[i].status = IRQ_DISABLED; 455 set_irq_chip(i, &jmr3927_irq_controller);
474 irq_desc[i].action = NULL;
475 irq_desc[i].depth = 1;
476 irq_desc[i].chip = &jmr3927_irq_controller;
477 }
478 456
479 jmr3927_irq_base = irq_base; 457 jmr3927_irq_base = irq_base;
480} 458}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 16e5dfe7aa8a..138f25efe38a 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -170,7 +170,7 @@ static void jmr3927_machine_power_off(void)
170 while (1); 170 while (1);
171} 171}
172 172
173static unsigned int jmr3927_hpt_read(void) 173static cycle_t jmr3927_hpt_read(void)
174{ 174{
175 /* We assume this function is called xtime_lock held. */ 175 /* We assume this function is called xtime_lock held. */
176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
@@ -182,7 +182,7 @@ extern void rtc_ds1742_init(unsigned long base);
182#endif 182#endif
183static void __init jmr3927_time_init(void) 183static void __init jmr3927_time_init(void)
184{ 184{
185 mips_hpt_read = jmr3927_hpt_read; 185 clocksource_mips.read = jmr3927_hpt_read;
186 mips_hpt_frequency = JMR3927_TIMER_CLK; 186 mips_hpt_frequency = JMR3927_TIMER_CLK;
187#ifdef USE_RTC_DS1742 187#ifdef USE_RTC_DS1742
188 if (jmr3927_have_nvram()) { 188 if (jmr3927_have_nvram()) {
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 6bfbbed0897e..bbbb8d7cb89b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -45,7 +45,6 @@ obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
47 47
48obj-$(CONFIG_NO_ISA) += dma-no-isa.o
49obj-$(CONFIG_I8259) += i8259.o 48obj-$(CONFIG_I8259) += i8259.o
50obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 49obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
51obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
@@ -67,6 +66,8 @@ obj-$(CONFIG_64BIT) += cpu-bugs64.o
67 66
68obj-$(CONFIG_I8253) += i8253.o 67obj-$(CONFIG_I8253) += i8253.o
69 68
69obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
70
70CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 71CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
71 72
72EXTRA_AFLAGS := $(CFLAGS) 73EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c
index 528e731049c1..ba16d07588cb 100644
--- a/arch/mips/kernel/apm.c
+++ b/arch/mips/kernel/apm.c
@@ -356,7 +356,7 @@ static int apm_open(struct inode * inode, struct file * filp)
356{ 356{
357 struct apm_user *as; 357 struct apm_user *as;
358 358
359 as = (struct apm_user *)kzalloc(sizeof(*as), GFP_KERNEL); 359 as = kzalloc(sizeof(*as), GFP_KERNEL);
360 if (as) { 360 if (as) {
361 /* 361 /*
362 * XXX - this is a tiny bit broken, when we consider BSD 362 * XXX - this is a tiny bit broken, when we consider BSD
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index 4a9f1ecefaf2..9b34238d41c0 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -90,7 +90,6 @@ struct elf_prpsinfo32
90 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ 90 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
91}; 91};
92 92
93#define elf_addr_t u32
94#define elf_caddr_t u32 93#define elf_caddr_t u32
95#define init_elf_binfmt init_elfn32_binfmt 94#define init_elf_binfmt init_elfn32_binfmt
96 95
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index e31813779895..993f7ec70f35 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -92,7 +92,6 @@ struct elf_prpsinfo32
92 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */ 92 char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
93}; 93};
94 94
95#define elf_addr_t u32
96#define elf_caddr_t u32 95#define elf_caddr_t u32
97#define init_elf_binfmt init_elf32_binfmt 96#define init_elf_binfmt init_elf32_binfmt
98 97
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8485af340ee1..442839e9578c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -110,9 +110,8 @@ static inline void check_wait(void)
110{ 110{
111 struct cpuinfo_mips *c = &current_cpu_data; 111 struct cpuinfo_mips *c = &current_cpu_data;
112 112
113 printk("Checking for 'wait' instruction... ");
114 if (nowait) { 113 if (nowait) {
115 printk (" disabled.\n"); 114 printk("Wait instruction disabled.\n");
116 return; 115 return;
117 } 116 }
118 117
@@ -120,11 +119,9 @@ static inline void check_wait(void)
120 case CPU_R3081: 119 case CPU_R3081:
121 case CPU_R3081E: 120 case CPU_R3081E:
122 cpu_wait = r3081_wait; 121 cpu_wait = r3081_wait;
123 printk(" available.\n");
124 break; 122 break;
125 case CPU_TX3927: 123 case CPU_TX3927:
126 cpu_wait = r39xx_wait; 124 cpu_wait = r39xx_wait;
127 printk(" available.\n");
128 break; 125 break;
129 case CPU_R4200: 126 case CPU_R4200:
130/* case CPU_R4300: */ 127/* case CPU_R4300: */
@@ -146,33 +143,23 @@ static inline void check_wait(void)
146 case CPU_74K: 143 case CPU_74K:
147 case CPU_PR4450: 144 case CPU_PR4450:
148 cpu_wait = r4k_wait; 145 cpu_wait = r4k_wait;
149 printk(" available.\n");
150 break; 146 break;
151 case CPU_TX49XX: 147 case CPU_TX49XX:
152 cpu_wait = r4k_wait_irqoff; 148 cpu_wait = r4k_wait_irqoff;
153 printk(" available.\n");
154 break; 149 break;
155 case CPU_AU1000: 150 case CPU_AU1000:
156 case CPU_AU1100: 151 case CPU_AU1100:
157 case CPU_AU1500: 152 case CPU_AU1500:
158 case CPU_AU1550: 153 case CPU_AU1550:
159 case CPU_AU1200: 154 case CPU_AU1200:
160 if (allow_au1k_wait) { 155 if (allow_au1k_wait)
161 cpu_wait = au1k_wait; 156 cpu_wait = au1k_wait;
162 printk(" available.\n");
163 } else
164 printk(" unavailable.\n");
165 break; 157 break;
166 case CPU_RM9000: 158 case CPU_RM9000:
167 if ((c->processor_id & 0x00ff) >= 0x40) { 159 if ((c->processor_id & 0x00ff) >= 0x40)
168 cpu_wait = r4k_wait; 160 cpu_wait = r4k_wait;
169 printk(" available.\n");
170 } else {
171 printk(" unavailable.\n");
172 }
173 break; 161 break;
174 default: 162 default:
175 printk(" unavailable.\n");
176 break; 163 break;
177 } 164 }
178} 165}
diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c
deleted file mode 100644
index 6df8b07741e3..000000000000
--- a/arch/mips/kernel/dma-no-isa.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 *
8 * Dummy ISA DMA functions for systems that don't have ISA but share drivers
9 * with ISA such as legacy free PCI.
10 */
11#include <linux/errno.h>
12#include <linux/module.h>
13#include <linux/spinlock.h>
14
15DEFINE_SPINLOCK(dma_spin_lock);
16
17int request_dma(unsigned int dmanr, const char * device_id)
18{
19 return -EINVAL;
20}
21
22void free_dma(unsigned int dmanr)
23{
24}
25
26EXPORT_SYMBOL(dma_spin_lock);
27EXPORT_SYMBOL(request_dma);
28EXPORT_SYMBOL(free_dma);
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 5baca16993d0..aacd4a005c5f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -19,6 +19,7 @@
19#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
20#include <asm/stackframe.h> 20#include <asm/stackframe.h>
21#include <asm/war.h> 21#include <asm/war.h>
22#include <asm/page.h>
22 23
23#define PANIC_PIC(msg) \ 24#define PANIC_PIC(msg) \
24 .set push; \ 25 .set push; \
@@ -378,6 +379,68 @@ NESTED(nmi_handler, PT_SIZE, sp)
378 BUILD_HANDLER dsp dsp sti silent /* #26 */ 379 BUILD_HANDLER dsp dsp sti silent /* #26 */
379 BUILD_HANDLER reserved reserved sti verbose /* others */ 380 BUILD_HANDLER reserved reserved sti verbose /* others */
380 381
382 .align 5
383 LEAF(handle_ri_rdhwr_vivt)
384#ifdef CONFIG_MIPS_MT_SMTC
385 PANIC_PIC("handle_ri_rdhwr_vivt called")
386#else
387 .set push
388 .set noat
389 .set noreorder
390 /* check if TLB contains a entry for EPC */
391 MFC0 k1, CP0_ENTRYHI
392 andi k1, 0xff /* ASID_MASK */
393 MFC0 k0, CP0_EPC
394 PTR_SRL k0, PAGE_SHIFT + 1
395 PTR_SLL k0, PAGE_SHIFT + 1
396 or k1, k0
397 MTC0 k1, CP0_ENTRYHI
398 mtc0_tlbw_hazard
399 tlbp
400 tlb_probe_hazard
401 mfc0 k1, CP0_INDEX
402 .set pop
403 bltz k1, handle_ri /* slow path */
404 /* fall thru */
405#endif
406 END(handle_ri_rdhwr_vivt)
407
408 LEAF(handle_ri_rdhwr)
409 .set push
410 .set noat
411 .set noreorder
412 /* 0x7c03e83b: rdhwr v1,$29 */
413 MFC0 k1, CP0_EPC
414 lui k0, 0x7c03
415 lw k1, (k1)
416 ori k0, 0xe83b
417 .set reorder
418 bne k0, k1, handle_ri /* if not ours */
419 /* The insn is rdhwr. No need to check CAUSE.BD here. */
420 get_saved_sp /* k1 := current_thread_info */
421 .set noreorder
422 MFC0 k0, CP0_EPC
423#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
424 ori k1, _THREAD_MASK
425 xori k1, _THREAD_MASK
426 LONG_L v1, TI_TP_VALUE(k1)
427 LONG_ADDIU k0, 4
428 jr k0
429 rfe
430#else
431 LONG_ADDIU k0, 4 /* stall on $k0 */
432 MTC0 k0, CP0_EPC
433 /* I hope three instructions between MTC0 and ERET are enough... */
434 ori k1, _THREAD_MASK
435 xori k1, _THREAD_MASK
436 LONG_L v1, TI_TP_VALUE(k1)
437 .set mips3
438 eret
439 .set mips0
440#endif
441 .set pop
442 END(handle_ri_rdhwr)
443
381#ifdef CONFIG_64BIT 444#ifdef CONFIG_64BIT
382/* A temporary overflow handler used by check_daddi(). */ 445/* A temporary overflow handler used by check_daddi(). */
383 446
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index ddc1b71c9378..9a7811d13db2 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -138,7 +138,7 @@
138EXPORT(stext) # used for profiling 138EXPORT(stext) # used for profiling
139EXPORT(_stext) 139EXPORT(_stext)
140 140
141#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM) 141#ifdef CONFIG_MIPS_SIM
142 /* 142 /*
143 * Give us a fighting chance of running if execution beings at the 143 * Give us a fighting chance of running if execution beings at the
144 * kernel load address. This is needed because this platform does 144 * kernel load address. This is needed because this platform does
@@ -250,6 +250,9 @@ NESTED(smp_bootstrap, 16, sp)
250 */ 250 */
251 page swapper_pg_dir, _PGD_ORDER 251 page swapper_pg_dir, _PGD_ORDER
252#ifdef CONFIG_64BIT 252#ifdef CONFIG_64BIT
253#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64)
254 page module_pg_dir, _PGD_ORDER
255#endif
253 page invalid_pmd_table, _PMD_ORDER 256 page invalid_pmd_table, _PMD_ORDER
254#endif 257#endif
255 page invalid_pte_table, _PTE_ORDER 258 page invalid_pte_table, _PTE_ORDER
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 48e3418c217b..b59a676c6d0e 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -19,9 +19,6 @@
19#include <asm/i8259.h> 19#include <asm/i8259.h>
20#include <asm/io.h> 20#include <asm/io.h>
21 21
22void enable_8259A_irq(unsigned int irq);
23void disable_8259A_irq(unsigned int irq);
24
25/* 22/*
26 * This is the 'legacy' 8259A Programmable Interrupt Controller, 23 * This is the 'legacy' 8259A Programmable Interrupt Controller,
27 * present in the majority of PC/AT boxes. 24 * present in the majority of PC/AT boxes.
@@ -31,34 +28,16 @@ void disable_8259A_irq(unsigned int irq);
31 * moves to arch independent land 28 * moves to arch independent land
32 */ 29 */
33 30
31static int i8259A_auto_eoi;
34DEFINE_SPINLOCK(i8259A_lock); 32DEFINE_SPINLOCK(i8259A_lock);
35 33/* some platforms call this... */
36static void end_8259A_irq (unsigned int irq)
37{
38 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
39 irq_desc[irq].action)
40 enable_8259A_irq(irq);
41}
42
43#define shutdown_8259A_irq disable_8259A_irq
44
45void mask_and_ack_8259A(unsigned int); 34void mask_and_ack_8259A(unsigned int);
46 35
47static unsigned int startup_8259A_irq(unsigned int irq) 36static struct irq_chip i8259A_chip = {
48{ 37 .name = "XT-PIC",
49 enable_8259A_irq(irq); 38 .mask = disable_8259A_irq,
50 39 .unmask = enable_8259A_irq,
51 return 0; /* never anything pending */ 40 .mask_ack = mask_and_ack_8259A,
52}
53
54static struct irq_chip i8259A_irq_type = {
55 .typename = "XT-PIC",
56 .startup = startup_8259A_irq,
57 .shutdown = shutdown_8259A_irq,
58 .enable = enable_8259A_irq,
59 .disable = disable_8259A_irq,
60 .ack = mask_and_ack_8259A,
61 .end = end_8259A_irq,
62}; 41};
63 42
64/* 43/*
@@ -70,8 +49,8 @@ static struct irq_chip i8259A_irq_type = {
70 */ 49 */
71static unsigned int cached_irq_mask = 0xffff; 50static unsigned int cached_irq_mask = 0xffff;
72 51
73#define cached_21 (cached_irq_mask) 52#define cached_master_mask (cached_irq_mask)
74#define cached_A1 (cached_irq_mask >> 8) 53#define cached_slave_mask (cached_irq_mask >> 8)
75 54
76void disable_8259A_irq(unsigned int irq) 55void disable_8259A_irq(unsigned int irq)
77{ 56{
@@ -81,9 +60,9 @@ void disable_8259A_irq(unsigned int irq)
81 spin_lock_irqsave(&i8259A_lock, flags); 60 spin_lock_irqsave(&i8259A_lock, flags);
82 cached_irq_mask |= mask; 61 cached_irq_mask |= mask;
83 if (irq & 8) 62 if (irq & 8)
84 outb(cached_A1,0xA1); 63 outb(cached_slave_mask, PIC_SLAVE_IMR);
85 else 64 else
86 outb(cached_21,0x21); 65 outb(cached_master_mask, PIC_MASTER_IMR);
87 spin_unlock_irqrestore(&i8259A_lock, flags); 66 spin_unlock_irqrestore(&i8259A_lock, flags);
88} 67}
89 68
@@ -95,9 +74,9 @@ void enable_8259A_irq(unsigned int irq)
95 spin_lock_irqsave(&i8259A_lock, flags); 74 spin_lock_irqsave(&i8259A_lock, flags);
96 cached_irq_mask &= mask; 75 cached_irq_mask &= mask;
97 if (irq & 8) 76 if (irq & 8)
98 outb(cached_A1,0xA1); 77 outb(cached_slave_mask, PIC_SLAVE_IMR);
99 else 78 else
100 outb(cached_21,0x21); 79 outb(cached_master_mask, PIC_MASTER_IMR);
101 spin_unlock_irqrestore(&i8259A_lock, flags); 80 spin_unlock_irqrestore(&i8259A_lock, flags);
102} 81}
103 82
@@ -109,9 +88,9 @@ int i8259A_irq_pending(unsigned int irq)
109 88
110 spin_lock_irqsave(&i8259A_lock, flags); 89 spin_lock_irqsave(&i8259A_lock, flags);
111 if (irq < 8) 90 if (irq < 8)
112 ret = inb(0x20) & mask; 91 ret = inb(PIC_MASTER_CMD) & mask;
113 else 92 else
114 ret = inb(0xA0) & (mask >> 8); 93 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
115 spin_unlock_irqrestore(&i8259A_lock, flags); 94 spin_unlock_irqrestore(&i8259A_lock, flags);
116 95
117 return ret; 96 return ret;
@@ -120,7 +99,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 99void make_8259A_irq(unsigned int irq)
121{ 100{
122 disable_irq_nosync(irq); 101 disable_irq_nosync(irq);
123 irq_desc[irq].chip = &i8259A_irq_type; 102 set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
124 enable_irq(irq); 103 enable_irq(irq);
125} 104}
126 105
@@ -136,14 +115,14 @@ static inline int i8259A_irq_real(unsigned int irq)
136 int irqmask = 1 << irq; 115 int irqmask = 1 << irq;
137 116
138 if (irq < 8) { 117 if (irq < 8) {
139 outb(0x0B,0x20); /* ISR register */ 118 outb(0x0B,PIC_MASTER_CMD); /* ISR register */
140 value = inb(0x20) & irqmask; 119 value = inb(PIC_MASTER_CMD) & irqmask;
141 outb(0x0A,0x20); /* back to the IRR register */ 120 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
142 return value; 121 return value;
143 } 122 }
144 outb(0x0B,0xA0); /* ISR register */ 123 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
145 value = inb(0xA0) & (irqmask >> 8); 124 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
146 outb(0x0A,0xA0); /* back to the IRR register */ 125 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
147 return value; 126 return value;
148} 127}
149 128
@@ -160,17 +139,19 @@ void mask_and_ack_8259A(unsigned int irq)
160 139
161 spin_lock_irqsave(&i8259A_lock, flags); 140 spin_lock_irqsave(&i8259A_lock, flags);
162 /* 141 /*
163 * Lightweight spurious IRQ detection. We do not want to overdo 142 * Lightweight spurious IRQ detection. We do not want
164 * spurious IRQ handling - it's usually a sign of hardware problems, so 143 * to overdo spurious IRQ handling - it's usually a sign
165 * we only do the checks we can do without slowing down good hardware 144 * of hardware problems, so we only do the checks we can
166 * nnecesserily. 145 * do without slowing down good hardware unnecessarily.
167 * 146 *
168 * Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting 147 * Note that IRQ7 and IRQ15 (the two spurious IRQs
169 * rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A. 148 * usually resulting from the 8259A-1|2 PICs) occur
170 * Thus we can check spurious 8259A IRQs without doing the quite slow 149 * even if the IRQ is masked in the 8259A. Thus we
171 * i8259A_irq_real() call for every IRQ. This does not cover 100% of 150 * can check spurious 8259A IRQs without doing the
172 * spurious interrupts, but should be enough to warn the user that 151 * quite slow i8259A_irq_real() call for every IRQ.
173 * there is something bad going on ... 152 * This does not cover 100% of spurious interrupts,
153 * but should be enough to warn the user that there
154 * is something bad going on ...
174 */ 155 */
175 if (cached_irq_mask & irqmask) 156 if (cached_irq_mask & irqmask)
176 goto spurious_8259A_irq; 157 goto spurious_8259A_irq;
@@ -178,14 +159,14 @@ void mask_and_ack_8259A(unsigned int irq)
178 159
179handle_real_irq: 160handle_real_irq:
180 if (irq & 8) { 161 if (irq & 8) {
181 inb(0xA1); /* DUMMY - (do we need this?) */ 162 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
182 outb(cached_A1,0xA1); 163 outb(cached_slave_mask, PIC_SLAVE_IMR);
183 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ 164 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
184 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 165 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
185 } else { 166 } else {
186 inb(0x21); /* DUMMY - (do we need this?) */ 167 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
187 outb(cached_21,0x21); 168 outb(cached_master_mask, PIC_MASTER_IMR);
188 outb(0x60+irq,0x20); /* 'Specific EOI' to master */ 169 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
189 } 170 }
190#ifdef CONFIG_MIPS_MT_SMTC 171#ifdef CONFIG_MIPS_MT_SMTC
191 if (irq_hwmask[irq] & ST0_IM) 172 if (irq_hwmask[irq] & ST0_IM)
@@ -206,7 +187,7 @@ spurious_8259A_irq:
206 goto handle_real_irq; 187 goto handle_real_irq;
207 188
208 { 189 {
209 static int spurious_irq_mask = 0; 190 static int spurious_irq_mask;
210 /* 191 /*
211 * At this point we can be sure the IRQ is spurious, 192 * At this point we can be sure the IRQ is spurious,
212 * lets ACK and report it. [once per IRQ] 193 * lets ACK and report it. [once per IRQ]
@@ -227,13 +208,25 @@ spurious_8259A_irq:
227 208
228static int i8259A_resume(struct sys_device *dev) 209static int i8259A_resume(struct sys_device *dev)
229{ 210{
230 init_8259A(0); 211 init_8259A(i8259A_auto_eoi);
212 return 0;
213}
214
215static int i8259A_shutdown(struct sys_device *dev)
216{
217 /* Put the i8259A into a quiescent state that
218 * the kernel initialization code can get it
219 * out of.
220 */
221 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
222 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
231 return 0; 223 return 0;
232} 224}
233 225
234static struct sysdev_class i8259_sysdev_class = { 226static struct sysdev_class i8259_sysdev_class = {
235 set_kset_name("i8259"), 227 set_kset_name("i8259"),
236 .resume = i8259A_resume, 228 .resume = i8259A_resume,
229 .shutdown = i8259A_shutdown,
237}; 230};
238 231
239static struct sys_device device_i8259A = { 232static struct sys_device device_i8259A = {
@@ -255,41 +248,41 @@ void __init init_8259A(int auto_eoi)
255{ 248{
256 unsigned long flags; 249 unsigned long flags;
257 250
251 i8259A_auto_eoi = auto_eoi;
252
258 spin_lock_irqsave(&i8259A_lock, flags); 253 spin_lock_irqsave(&i8259A_lock, flags);
259 254
260 outb(0xff, 0x21); /* mask all of 8259A-1 */ 255 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
261 outb(0xff, 0xA1); /* mask all of 8259A-2 */ 256 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
262 257
263 /* 258 /*
264 * outb_p - this has to work on a wide range of PC hardware. 259 * outb_p - this has to work on a wide range of PC hardware.
265 */ 260 */
266 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ 261 outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
267 outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */ 262 outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
268 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ 263 outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
269 if (auto_eoi) 264 if (auto_eoi) /* master does Auto EOI */
270 outb_p(0x03, 0x21); /* master does Auto EOI */ 265 outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
271 else 266 else /* master expects normal EOI */
272 outb_p(0x01, 0x21); /* master expects normal EOI */ 267 outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
273 268
274 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ 269 outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
275 outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */ 270 outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
276 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ 271 outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
277 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode 272 outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
278 is to be investigated) */
279
280 if (auto_eoi) 273 if (auto_eoi)
281 /* 274 /*
282 * in AEOI mode we just have to mask the interrupt 275 * In AEOI mode we just have to mask the interrupt
283 * when acking. 276 * when acking.
284 */ 277 */
285 i8259A_irq_type.ack = disable_8259A_irq; 278 i8259A_chip.mask_ack = disable_8259A_irq;
286 else 279 else
287 i8259A_irq_type.ack = mask_and_ack_8259A; 280 i8259A_chip.mask_ack = mask_and_ack_8259A;
288 281
289 udelay(100); /* wait for 8259A to initialize */ 282 udelay(100); /* wait for 8259A to initialize */
290 283
291 outb(cached_21, 0x21); /* restore master IRQ mask */ 284 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
292 outb(cached_A1, 0xA1); /* restore slave IRQ mask */ 285 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
293 286
294 spin_unlock_irqrestore(&i8259A_lock, flags); 287 spin_unlock_irqrestore(&i8259A_lock, flags);
295} 288}
@@ -302,11 +295,17 @@ static struct irqaction irq2 = {
302}; 295};
303 296
304static struct resource pic1_io_resource = { 297static struct resource pic1_io_resource = {
305 .name = "pic1", .start = 0x20, .end = 0x21, .flags = IORESOURCE_BUSY 298 .name = "pic1",
299 .start = PIC_MASTER_CMD,
300 .end = PIC_MASTER_IMR,
301 .flags = IORESOURCE_BUSY
306}; 302};
307 303
308static struct resource pic2_io_resource = { 304static struct resource pic2_io_resource = {
309 .name = "pic2", .start = 0xa0, .end = 0xa1, .flags = IORESOURCE_BUSY 305 .name = "pic2",
306 .start = PIC_SLAVE_CMD,
307 .end = PIC_SLAVE_IMR,
308 .flags = IORESOURCE_BUSY
310}; 309};
311 310
312/* 311/*
@@ -323,12 +322,8 @@ void __init init_i8259_irqs (void)
323 322
324 init_8259A(0); 323 init_8259A(0);
325 324
326 for (i = 0; i < 16; i++) { 325 for (i = 0; i < 16; i++)
327 irq_desc[i].status = IRQ_DISABLED; 326 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1;
330 irq_desc[i].chip = &i8259A_irq_type;
331 }
332 327
333 setup_irq(2, &irq2); 328 setup_irq(PIC_CASCADE_IR, &irq2);
334} 329}
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index ab12c8f01518..37cad5de515c 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -52,10 +52,6 @@ static struct linux_binfmt irix_format = {
52 irix_core_dump, PAGE_SIZE 52 irix_core_dump, PAGE_SIZE
53}; 53};
54 54
55#ifndef elf_addr_t
56#define elf_addr_t unsigned long
57#endif
58
59#ifdef DEBUG 55#ifdef DEBUG
60/* Debugging routines. */ 56/* Debugging routines. */
61static char *get_elf_p_type(Elf32_Word p_type) 57static char *get_elf_p_type(Elf32_Word p_type)
@@ -1013,7 +1009,7 @@ static int notesize(struct memelfnote *en)
1013 int sz; 1009 int sz;
1014 1010
1015 sz = sizeof(struct elf_note); 1011 sz = sizeof(struct elf_note);
1016 sz += roundup(strlen(en->name), 4); 1012 sz += roundup(strlen(en->name) + 1, 4);
1017 sz += roundup(en->datasz, 4); 1013 sz += roundup(en->datasz, 4);
1018 1014
1019 return sz; 1015 return sz;
@@ -1032,7 +1028,7 @@ static int writenote(struct memelfnote *men, struct file *file)
1032{ 1028{
1033 struct elf_note en; 1029 struct elf_note en;
1034 1030
1035 en.n_namesz = strlen(men->name); 1031 en.n_namesz = strlen(men->name) + 1;
1036 en.n_descsz = men->datasz; 1032 en.n_descsz = men->datasz;
1037 en.n_type = men->type; 1033 en.n_type = men->type;
1038 1034
@@ -1149,7 +1145,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1149 psinfo.pr_pid = prstatus.pr_pid = current->pid; 1145 psinfo.pr_pid = prstatus.pr_pid = current->pid;
1150 psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid; 1146 psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid;
1151 psinfo.pr_pgrp = prstatus.pr_pgrp = process_group(current); 1147 psinfo.pr_pgrp = prstatus.pr_pgrp = process_group(current);
1152 psinfo.pr_sid = prstatus.pr_sid = current->signal->session; 1148 psinfo.pr_sid = prstatus.pr_sid = process_session(current);
1153 if (current->pid == current->tgid) { 1149 if (current->pid == current->tgid) {
1154 /* 1150 /*
1155 * This is the record for the group leader. Add in the 1151 * This is the record for the group leader. Add in the
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 650a80ca3741..bcaad6696082 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq)
45} 45}
46 46
47/* 47/*
48 * Enables the IRQ on SOC-it
49 */
50static void enable_msc_irq(unsigned int irq)
51{
52 unmask_msc_irq(irq);
53}
54
55/*
56 * Initialize the IRQ on SOC-it
57 */
58static unsigned int startup_msc_irq(unsigned int irq)
59{
60 unmask_msc_irq(irq);
61 return 0;
62}
63
64/*
65 * Disables the IRQ on SOC-it
66 */
67static void disable_msc_irq(unsigned int irq)
68{
69 mask_msc_irq(irq);
70}
71
72/*
73 * Masks and ACKs an IRQ 48 * Masks and ACKs an IRQ
74 */ 49 */
75static void level_mask_and_ack_msc_irq(unsigned int irq) 50static void level_mask_and_ack_msc_irq(unsigned int irq)
@@ -136,25 +111,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
137} 112}
138 113
139#define shutdown_msc_irq disable_msc_irq
140
141struct irq_chip msc_levelirq_type = { 114struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level", 115 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq, 116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
120 .eoi = unmask_msc_irq,
148 .end = end_msc_irq, 121 .end = end_msc_irq,
149}; 122};
150 123
151struct irq_chip msc_edgeirq_type = { 124struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge", 125 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq, 126 .ack = edge_mask_and_ack_msc_irq,
127 .mask = mask_msc_irq,
128 .mask_ack = edge_mask_and_ack_msc_irq,
129 .unmask = unmask_msc_irq,
130 .eoi = unmask_msc_irq,
158 .end = end_msc_irq, 131 .end = end_msc_irq,
159}; 132};
160 133
@@ -175,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
175 148
176 switch (imp->im_type) { 149 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE: 150 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type; 151 set_irq_chip(base+n, &msc_edgeirq_type);
179 if (cpu_has_veic) 152 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else 154 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break; 156 break;
184 case MSC01_IRQ_LEVEL: 157 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type; 158 set_irq_chip(base+n, &msc_levelirq_type);
186 if (cpu_has_veic) 159 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 160 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else 161 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 37d106202b83..efbd219845b5 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -67,48 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
67} 67}
68 68
69/* 69/*
70 * Enables the IRQ on Marvell Chip
71 */
72static void enable_mv64340_irq(unsigned int irq)
73{
74 unmask_mv64340_irq(irq);
75}
76
77/*
78 * Initialize the IRQ on Marvell Chip
79 */
80static unsigned int startup_mv64340_irq(unsigned int irq)
81{
82 unmask_mv64340_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ on Marvell Chip
88 */
89static void disable_mv64340_irq(unsigned int irq)
90{
91 mask_mv64340_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_mv64340_irq(unsigned int irq)
98{
99 mask_mv64340_irq(irq);
100}
101
102/*
103 * End IRQ processing
104 */
105static void end_mv64340_irq(unsigned int irq)
106{
107 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
108 unmask_mv64340_irq(irq);
109}
110
111/*
112 * Interrupt handler for interrupts coming from the Marvell chip. 70 * Interrupt handler for interrupts coming from the Marvell chip.
113 * It could be built in ethernet ports etc... 71 * It could be built in ethernet ports etc...
114 */ 72 */
@@ -133,29 +91,21 @@ void ll_mv64340_irq(void)
133 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); 91 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
134} 92}
135 93
136#define shutdown_mv64340_irq disable_mv64340_irq
137
138struct irq_chip mv64340_irq_type = { 94struct irq_chip mv64340_irq_type = {
139 .typename = "MV-64340", 95 .typename = "MV-64340",
140 .startup = startup_mv64340_irq, 96 .ack = mask_mv64340_irq,
141 .shutdown = shutdown_mv64340_irq, 97 .mask = mask_mv64340_irq,
142 .enable = enable_mv64340_irq, 98 .mask_ack = mask_mv64340_irq,
143 .disable = disable_mv64340_irq, 99 .unmask = unmask_mv64340_irq,
144 .ack = mask_and_ack_mv64340_irq,
145 .end = end_mv64340_irq,
146}; 100};
147 101
148void __init mv64340_irq_init(unsigned int base) 102void __init mv64340_irq_init(unsigned int base)
149{ 103{
150 int i; 104 int i;
151 105
152 /* Reset irq handlers pointers to NULL */ 106 for (i = base; i < base + 64; i++)
153 for (i = base; i < base + 64; i++) { 107 set_irq_chip_and_handler(i, &mv64340_irq_type,
154 irq_desc[i].status = IRQ_DISABLED; 108 handle_level_irq);
155 irq_desc[i].action = 0;
156 irq_desc[i].depth = 2;
157 irq_desc[i].chip = &mv64340_irq_type;
158 }
159 109
160 irq_base = base; 110 irq_base = base;
161} 111}
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6b54c7109e2e..123324ba8c14 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -29,56 +29,12 @@ static inline void mask_rm7k_irq(unsigned int irq)
29 clear_c0_intcontrol(0x100 << (irq - irq_base)); 29 clear_c0_intcontrol(0x100 << (irq - irq_base));
30} 30}
31 31
32static inline void rm7k_cpu_irq_enable(unsigned int irq)
33{
34 unsigned long flags;
35
36 local_irq_save(flags);
37 unmask_rm7k_irq(irq);
38 local_irq_restore(flags);
39}
40
41static void rm7k_cpu_irq_disable(unsigned int irq)
42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 mask_rm7k_irq(irq);
47 local_irq_restore(flags);
48}
49
50static unsigned int rm7k_cpu_irq_startup(unsigned int irq)
51{
52 rm7k_cpu_irq_enable(irq);
53
54 return 0;
55}
56
57#define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable
58
59/*
60 * While we ack the interrupt interrupts are disabled and thus we don't need
61 * to deal with concurrency issues. Same for rm7k_cpu_irq_end.
62 */
63static void rm7k_cpu_irq_ack(unsigned int irq)
64{
65 mask_rm7k_irq(irq);
66}
67
68static void rm7k_cpu_irq_end(unsigned int irq)
69{
70 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
71 unmask_rm7k_irq(irq);
72}
73
74static struct irq_chip rm7k_irq_controller = { 32static struct irq_chip rm7k_irq_controller = {
75 .typename = "RM7000", 33 .typename = "RM7000",
76 .startup = rm7k_cpu_irq_startup, 34 .ack = mask_rm7k_irq,
77 .shutdown = rm7k_cpu_irq_shutdown, 35 .mask = mask_rm7k_irq,
78 .enable = rm7k_cpu_irq_enable, 36 .mask_ack = mask_rm7k_irq,
79 .disable = rm7k_cpu_irq_disable, 37 .unmask = unmask_rm7k_irq,
80 .ack = rm7k_cpu_irq_ack,
81 .end = rm7k_cpu_irq_end,
82}; 38};
83 39
84void __init rm7k_cpu_irq_init(int base) 40void __init rm7k_cpu_irq_init(int base)
@@ -87,12 +43,9 @@ void __init rm7k_cpu_irq_init(int base)
87 43
88 clear_c0_intcontrol(0x00000f00); /* Mask all */ 44 clear_c0_intcontrol(0x00000f00); /* Mask all */
89 45
90 for (i = base; i < base + 4; i++) { 46 for (i = base; i < base + 4; i++)
91 irq_desc[i].status = IRQ_DISABLED; 47 set_irq_chip_and_handler(i, &rm7k_irq_controller,
92 irq_desc[i].action = NULL; 48 handle_level_irq);
93 irq_desc[i].depth = 1;
94 irq_desc[i].chip = &rm7k_irq_controller;
95 }
96 49
97 irq_base = base; 50 irq_base = base;
98} 51}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 62f011ba97a2..0e6f4c5349d2 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq)
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49} 49}
50 50
51static unsigned int rm9k_cpu_irq_startup(unsigned int irq)
52{
53 rm9k_cpu_irq_enable(irq);
54
55 return 0;
56}
57
58#define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable
59
60/* 51/*
61 * Performance counter interrupts are global on all processors. 52 * Performance counter interrupts are global on all processors.
62 */ 53 */
@@ -89,40 +80,22 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
89 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); 80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
90} 81}
91 82
92
93/*
94 * While we ack the interrupt interrupts are disabled and thus we don't need
95 * to deal with concurrency issues. Same for rm9k_cpu_irq_end.
96 */
97static void rm9k_cpu_irq_ack(unsigned int irq)
98{
99 mask_rm9k_irq(irq);
100}
101
102static void rm9k_cpu_irq_end(unsigned int irq)
103{
104 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
105 unmask_rm9k_irq(irq);
106}
107
108static struct irq_chip rm9k_irq_controller = { 83static struct irq_chip rm9k_irq_controller = {
109 .typename = "RM9000", 84 .typename = "RM9000",
110 .startup = rm9k_cpu_irq_startup, 85 .ack = mask_rm9k_irq,
111 .shutdown = rm9k_cpu_irq_shutdown, 86 .mask = mask_rm9k_irq,
112 .enable = rm9k_cpu_irq_enable, 87 .mask_ack = mask_rm9k_irq,
113 .disable = rm9k_cpu_irq_disable, 88 .unmask = unmask_rm9k_irq,
114 .ack = rm9k_cpu_irq_ack,
115 .end = rm9k_cpu_irq_end,
116}; 89};
117 90
118static struct irq_chip rm9k_perfcounter_irq = { 91static struct irq_chip rm9k_perfcounter_irq = {
119 .typename = "RM9000", 92 .typename = "RM9000",
120 .startup = rm9k_perfcounter_irq_startup, 93 .startup = rm9k_perfcounter_irq_startup,
121 .shutdown = rm9k_perfcounter_irq_shutdown, 94 .shutdown = rm9k_perfcounter_irq_shutdown,
122 .enable = rm9k_cpu_irq_enable, 95 .ack = mask_rm9k_irq,
123 .disable = rm9k_cpu_irq_disable, 96 .mask = mask_rm9k_irq,
124 .ack = rm9k_cpu_irq_ack, 97 .mask_ack = mask_rm9k_irq,
125 .end = rm9k_cpu_irq_end, 98 .unmask = unmask_rm9k_irq,
126}; 99};
127 100
128unsigned int rm9000_perfcount_irq; 101unsigned int rm9000_perfcount_irq;
@@ -135,15 +108,13 @@ void __init rm9k_cpu_irq_init(int base)
135 108
136 clear_c0_intcontrol(0x0000f000); /* Mask all */ 109 clear_c0_intcontrol(0x0000f000); /* Mask all */
137 110
138 for (i = base; i < base + 4; i++) { 111 for (i = base; i < base + 4; i++)
139 irq_desc[i].status = IRQ_DISABLED; 112 set_irq_chip_and_handler(i, &rm9k_irq_controller,
140 irq_desc[i].action = NULL; 113 handle_level_irq);
141 irq_desc[i].depth = 1;
142 irq_desc[i].chip = &rm9k_irq_controller;
143 }
144 114
145 rm9000_perfcount_irq = base + 1; 115 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; 116 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
117 handle_level_irq);
147 118
148 irq_base = base; 119 irq_base = base;
149} 120}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 9b0e49d63d7b..2fe4c868a801 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -88,25 +88,6 @@ atomic_t irq_err_count;
88unsigned long irq_hwmask[NR_IRQS]; 88unsigned long irq_hwmask[NR_IRQS];
89#endif /* CONFIG_MIPS_MT_SMTC */ 89#endif /* CONFIG_MIPS_MT_SMTC */
90 90
91#undef do_IRQ
92
93/*
94 * do_IRQ handles all normal device IRQ's (the special
95 * SMP cross-CPU interrupts have their own specific
96 * handlers).
97 */
98asmlinkage unsigned int do_IRQ(unsigned int irq)
99{
100 irq_enter();
101
102 __DO_IRQ_SMTC_HOOK();
103 __do_IRQ(irq);
104
105 irq_exit();
106
107 return 1;
108}
109
110/* 91/*
111 * Generic, controller-independent functions: 92 * Generic, controller-independent functions:
112 */ 93 */
@@ -136,7 +117,7 @@ int show_interrupts(struct seq_file *p, void *v)
136 for_each_online_cpu(j) 117 for_each_online_cpu(j)
137 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 118 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
138#endif 119#endif
139 seq_printf(p, " %14s", irq_desc[i].chip->typename); 120 seq_printf(p, " %14s", irq_desc[i].chip->name);
140 seq_printf(p, " %s", action->name); 121 seq_printf(p, " %s", action->name);
141 122
142 for (action=action->next; action; action = action->next) 123 for (action=action->next; action; action = action->next)
@@ -172,19 +153,6 @@ __setup("nokgdb", nokgdb);
172 153
173void __init init_IRQ(void) 154void __init init_IRQ(void)
174{ 155{
175 int i;
176
177 for (i = 0; i < NR_IRQS; i++) {
178 irq_desc[i].status = IRQ_DISABLED;
179 irq_desc[i].action = NULL;
180 irq_desc[i].depth = 1;
181 irq_desc[i].chip = &no_irq_chip;
182 spin_lock_init(&irq_desc[i].lock);
183#ifdef CONFIG_MIPS_MT_SMTC
184 irq_hwmask[i] = 0;
185#endif /* CONFIG_MIPS_MT_SMTC */
186 }
187
188 arch_init_irq(); 156 arch_init_irq();
189 157
190#ifdef CONFIG_KGDB 158#ifdef CONFIG_KGDB
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 9bb21c7f2149..fcc86b96ccf6 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,58 +50,13 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static inline void mips_cpu_irq_enable(unsigned int irq)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
60 local_irq_restore(flags);
61}
62
63static void mips_cpu_irq_disable(unsigned int irq)
64{
65 unsigned long flags;
66
67 local_irq_save(flags);
68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
70 local_irq_restore(flags);
71}
72
73static unsigned int mips_cpu_irq_startup(unsigned int irq)
74{
75 mips_cpu_irq_enable(irq);
76
77 return 0;
78}
79
80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
81
82/*
83 * While we ack the interrupt interrupts are disabled and thus we don't need
84 * to deal with concurrency issues. Same for mips_cpu_irq_end.
85 */
86static void mips_cpu_irq_ack(unsigned int irq)
87{
88 mask_mips_irq(irq);
89}
90
91static void mips_cpu_irq_end(unsigned int irq)
92{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 unmask_mips_irq(irq);
95}
96
97static struct irq_chip mips_cpu_irq_controller = { 53static struct irq_chip mips_cpu_irq_controller = {
98 .typename = "MIPS", 54 .typename = "MIPS",
99 .startup = mips_cpu_irq_startup, 55 .ack = mask_mips_irq,
100 .shutdown = mips_cpu_irq_shutdown, 56 .mask = mask_mips_irq,
101 .enable = mips_cpu_irq_enable, 57 .mask_ack = mask_mips_irq,
102 .disable = mips_cpu_irq_disable, 58 .unmask = unmask_mips_irq,
103 .ack = mips_cpu_irq_ack, 59 .eoi = unmask_mips_irq,
104 .end = mips_cpu_irq_end,
105}; 60};
106 61
107/* 62/*
@@ -110,8 +65,6 @@ static struct irq_chip mips_cpu_irq_controller = {
110 65
111#define unmask_mips_mt_irq unmask_mips_irq 66#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq 67#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115 68
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) 69static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{ 70{
@@ -119,13 +72,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
119 72
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 73 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags); 74 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq); 75 unmask_mips_mt_irq(irq);
123 76
124 return 0; 77 return 0;
125} 78}
126 79
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/* 80/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need 81 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end. 82 * to deal with concurrency issues. Same for mips_cpu_irq_end.
@@ -138,16 +89,14 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
138 mask_mips_mt_irq(irq); 89 mask_mips_mt_irq(irq);
139} 90}
140 91
141#define mips_mt_cpu_irq_end mips_cpu_irq_end
142
143static struct irq_chip mips_mt_cpu_irq_controller = { 92static struct irq_chip mips_mt_cpu_irq_controller = {
144 .typename = "MIPS", 93 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup, 94 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack, 95 .ack = mips_mt_cpu_irq_ack,
150 .end = mips_mt_cpu_irq_end, 96 .mask = mask_mips_mt_irq,
97 .mask_ack = mips_mt_cpu_irq_ack,
98 .unmask = unmask_mips_mt_irq,
99 .eoi = unmask_mips_mt_irq,
151}; 100};
152 101
153void __init mips_cpu_irq_init(int irq_base) 102void __init mips_cpu_irq_init(int irq_base)
@@ -163,19 +112,12 @@ void __init mips_cpu_irq_init(int irq_base)
163 * leave them uninitialized for other processors. 112 * leave them uninitialized for other processors.
164 */ 113 */
165 if (cpu_has_mipsmt) 114 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) { 115 for (i = irq_base; i < irq_base + 2; i++)
167 irq_desc[i].status = IRQ_DISABLED; 116 set_irq_chip(i, &mips_mt_cpu_irq_controller);
168 irq_desc[i].action = NULL; 117
169 irq_desc[i].depth = 1; 118 for (i = irq_base + 2; i < irq_base + 8; i++)
170 irq_desc[i].chip = &mips_mt_cpu_irq_controller; 119 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
171 } 120 handle_level_irq);
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1;
177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 }
179 121
180 mips_cpu_irq_base = irq_base; 122 mips_cpu_irq_base = irq_base;
181} 123}
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index f06a144c7881..5929f883e46b 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -301,7 +301,7 @@ static void sp_cleanup(void)
301 for (;;) { 301 for (;;) {
302 unsigned long set; 302 unsigned long set;
303 i = j * __NFDBITS; 303 i = j * __NFDBITS;
304 if (i >= fdt->max_fdset || i >= fdt->max_fds) 304 if (i >= fdt->max_fds)
305 break; 305 break;
306 set = fdt->open_fds->fds_bits[j++]; 306 set = fdt->open_fds->fds_bits[j++];
307 while (set) { 307 while (set) {
@@ -319,7 +319,7 @@ static void sp_cleanup(void)
319static int channel_open = 0; 319static int channel_open = 0;
320 320
321/* the work handler */ 321/* the work handler */
322static void sp_work(void *data) 322static void sp_work(struct work_struct *unused)
323{ 323{
324 if (!channel_open) { 324 if (!channel_open) {
325 if( rtlx_open(RTLX_CHANNEL_SYSIO, 1) != 0) { 325 if( rtlx_open(RTLX_CHANNEL_SYSIO, 1) != 0) {
@@ -354,7 +354,7 @@ static void startwork(int vpe)
354 return; 354 return;
355 } 355 }
356 356
357 INIT_WORK(&work, sp_work, NULL); 357 INIT_WORK(&work, sp_work);
358 queue_work(workqueue, &work); 358 queue_work(workqueue, &work);
359 } else 359 } else
360 queue_work(workqueue, &work); 360 queue_work(workqueue, &work);
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 7a3ebbeba1f3..de3fae260ff8 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -382,531 +382,6 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
382 return ret; 382 return ret;
383} 383}
384 384
385struct msgbuf32 { s32 mtype; char mtext[1]; };
386
387struct ipc_perm32
388{
389 key_t key;
390 __compat_uid_t uid;
391 __compat_gid_t gid;
392 __compat_uid_t cuid;
393 __compat_gid_t cgid;
394 compat_mode_t mode;
395 unsigned short seq;
396};
397
398struct ipc64_perm32 {
399 key_t key;
400 __compat_uid_t uid;
401 __compat_gid_t gid;
402 __compat_uid_t cuid;
403 __compat_gid_t cgid;
404 compat_mode_t mode;
405 unsigned short seq;
406 unsigned short __pad1;
407 unsigned int __unused1;
408 unsigned int __unused2;
409};
410
411struct semid_ds32 {
412 struct ipc_perm32 sem_perm; /* permissions .. see ipc.h */
413 compat_time_t sem_otime; /* last semop time */
414 compat_time_t sem_ctime; /* last change time */
415 u32 sem_base; /* ptr to first semaphore in array */
416 u32 sem_pending; /* pending operations to be processed */
417 u32 sem_pending_last; /* last pending operation */
418 u32 undo; /* undo requests on this array */
419 unsigned short sem_nsems; /* no. of semaphores in array */
420};
421
422struct semid64_ds32 {
423 struct ipc64_perm32 sem_perm;
424 compat_time_t sem_otime;
425 compat_time_t sem_ctime;
426 unsigned int sem_nsems;
427 unsigned int __unused1;
428 unsigned int __unused2;
429};
430
431struct msqid_ds32
432{
433 struct ipc_perm32 msg_perm;
434 u32 msg_first;
435 u32 msg_last;
436 compat_time_t msg_stime;
437 compat_time_t msg_rtime;
438 compat_time_t msg_ctime;
439 u32 wwait;
440 u32 rwait;
441 unsigned short msg_cbytes;
442 unsigned short msg_qnum;
443 unsigned short msg_qbytes;
444 compat_ipc_pid_t msg_lspid;
445 compat_ipc_pid_t msg_lrpid;
446};
447
448struct msqid64_ds32 {
449 struct ipc64_perm32 msg_perm;
450 compat_time_t msg_stime;
451 unsigned int __unused1;
452 compat_time_t msg_rtime;
453 unsigned int __unused2;
454 compat_time_t msg_ctime;
455 unsigned int __unused3;
456 unsigned int msg_cbytes;
457 unsigned int msg_qnum;
458 unsigned int msg_qbytes;
459 compat_pid_t msg_lspid;
460 compat_pid_t msg_lrpid;
461 unsigned int __unused4;
462 unsigned int __unused5;
463};
464
465struct shmid_ds32 {
466 struct ipc_perm32 shm_perm;
467 int shm_segsz;
468 compat_time_t shm_atime;
469 compat_time_t shm_dtime;
470 compat_time_t shm_ctime;
471 compat_ipc_pid_t shm_cpid;
472 compat_ipc_pid_t shm_lpid;
473 unsigned short shm_nattch;
474};
475
476struct shmid64_ds32 {
477 struct ipc64_perm32 shm_perm;
478 compat_size_t shm_segsz;
479 compat_time_t shm_atime;
480 compat_time_t shm_dtime;
481 compat_time_t shm_ctime;
482 compat_pid_t shm_cpid;
483 compat_pid_t shm_lpid;
484 unsigned int shm_nattch;
485 unsigned int __unused1;
486 unsigned int __unused2;
487};
488
489struct ipc_kludge32 {
490 u32 msgp;
491 s32 msgtyp;
492};
493
494static int
495do_sys32_semctl(int first, int second, int third, void __user *uptr)
496{
497 union semun fourth;
498 u32 pad;
499 int err, err2;
500 struct semid64_ds s;
501 mm_segment_t old_fs;
502
503 if (!uptr)
504 return -EINVAL;
505 err = -EFAULT;
506 if (get_user (pad, (u32 __user *)uptr))
507 return err;
508 if ((third & ~IPC_64) == SETVAL)
509 fourth.val = (int)pad;
510 else
511 fourth.__pad = (void __user *)A(pad);
512 switch (third & ~IPC_64) {
513 case IPC_INFO:
514 case IPC_RMID:
515 case IPC_SET:
516 case SEM_INFO:
517 case GETVAL:
518 case GETPID:
519 case GETNCNT:
520 case GETZCNT:
521 case GETALL:
522 case SETVAL:
523 case SETALL:
524 err = sys_semctl (first, second, third, fourth);
525 break;
526
527 case IPC_STAT:
528 case SEM_STAT:
529 fourth.__pad = (struct semid64_ds __user *)&s;
530 old_fs = get_fs();
531 set_fs(KERNEL_DS);
532 err = sys_semctl(first, second, third | IPC_64, fourth);
533 set_fs(old_fs);
534
535 if (third & IPC_64) {
536 struct semid64_ds32 __user *usp64 = (struct semid64_ds32 __user *) A(pad);
537
538 if (!access_ok(VERIFY_WRITE, usp64, sizeof(*usp64))) {
539 err = -EFAULT;
540 break;
541 }
542 err2 = __put_user(s.sem_perm.key, &usp64->sem_perm.key);
543 err2 |= __put_user(s.sem_perm.uid, &usp64->sem_perm.uid);
544 err2 |= __put_user(s.sem_perm.gid, &usp64->sem_perm.gid);
545 err2 |= __put_user(s.sem_perm.cuid, &usp64->sem_perm.cuid);
546 err2 |= __put_user(s.sem_perm.cgid, &usp64->sem_perm.cgid);
547 err2 |= __put_user(s.sem_perm.mode, &usp64->sem_perm.mode);
548 err2 |= __put_user(s.sem_perm.seq, &usp64->sem_perm.seq);
549 err2 |= __put_user(s.sem_otime, &usp64->sem_otime);
550 err2 |= __put_user(s.sem_ctime, &usp64->sem_ctime);
551 err2 |= __put_user(s.sem_nsems, &usp64->sem_nsems);
552 } else {
553 struct semid_ds32 __user *usp32 = (struct semid_ds32 __user *) A(pad);
554
555 if (!access_ok(VERIFY_WRITE, usp32, sizeof(*usp32))) {
556 err = -EFAULT;
557 break;
558 }
559 err2 = __put_user(s.sem_perm.key, &usp32->sem_perm.key);
560 err2 |= __put_user(s.sem_perm.uid, &usp32->sem_perm.uid);
561 err2 |= __put_user(s.sem_perm.gid, &usp32->sem_perm.gid);
562 err2 |= __put_user(s.sem_perm.cuid, &usp32->sem_perm.cuid);
563 err2 |= __put_user(s.sem_perm.cgid, &usp32->sem_perm.cgid);
564 err2 |= __put_user(s.sem_perm.mode, &usp32->sem_perm.mode);
565 err2 |= __put_user(s.sem_perm.seq, &usp32->sem_perm.seq);
566 err2 |= __put_user(s.sem_otime, &usp32->sem_otime);
567 err2 |= __put_user(s.sem_ctime, &usp32->sem_ctime);
568 err2 |= __put_user(s.sem_nsems, &usp32->sem_nsems);
569 }
570 if (err2)
571 err = -EFAULT;
572 break;
573
574 default:
575 err = - EINVAL;
576 break;
577 }
578
579 return err;
580}
581
582static int
583do_sys32_msgsnd (int first, int second, int third, void __user *uptr)
584{
585 struct msgbuf32 __user *up = (struct msgbuf32 __user *)uptr;
586 struct msgbuf *p;
587 mm_segment_t old_fs;
588 int err;
589
590 if (second < 0)
591 return -EINVAL;
592 p = kmalloc (second + sizeof (struct msgbuf)
593 + 4, GFP_USER);
594 if (!p)
595 return -ENOMEM;
596 err = get_user (p->mtype, &up->mtype);
597 if (err)
598 goto out;
599 err |= __copy_from_user (p->mtext, &up->mtext, second);
600 if (err)
601 goto out;
602 old_fs = get_fs ();
603 set_fs (KERNEL_DS);
604 err = sys_msgsnd (first, (struct msgbuf __user *)p, second, third);
605 set_fs (old_fs);
606out:
607 kfree (p);
608
609 return err;
610}
611
612static int
613do_sys32_msgrcv (int first, int second, int msgtyp, int third,
614 int version, void __user *uptr)
615{
616 struct msgbuf32 __user *up;
617 struct msgbuf *p;
618 mm_segment_t old_fs;
619 int err;
620
621 if (!version) {
622 struct ipc_kludge32 __user *uipck = (struct ipc_kludge32 __user *)uptr;
623 struct ipc_kludge32 ipck;
624
625 err = -EINVAL;
626 if (!uptr)
627 goto out;
628 err = -EFAULT;
629 if (copy_from_user (&ipck, uipck, sizeof (struct ipc_kludge32)))
630 goto out;
631 uptr = (void __user *)AA(ipck.msgp);
632 msgtyp = ipck.msgtyp;
633 }
634
635 if (second < 0)
636 return -EINVAL;
637 err = -ENOMEM;
638 p = kmalloc (second + sizeof (struct msgbuf) + 4, GFP_USER);
639 if (!p)
640 goto out;
641 old_fs = get_fs ();
642 set_fs (KERNEL_DS);
643 err = sys_msgrcv (first, (struct msgbuf __user *)p, second + 4, msgtyp, third);
644 set_fs (old_fs);
645 if (err < 0)
646 goto free_then_out;
647 up = (struct msgbuf32 __user *)uptr;
648 if (put_user (p->mtype, &up->mtype) ||
649 __copy_to_user (&up->mtext, p->mtext, err))
650 err = -EFAULT;
651free_then_out:
652 kfree (p);
653out:
654 return err;
655}
656
657static int
658do_sys32_msgctl (int first, int second, void __user *uptr)
659{
660 int err = -EINVAL, err2;
661 struct msqid64_ds m;
662 struct msqid_ds32 __user *up32 = (struct msqid_ds32 __user *)uptr;
663 struct msqid64_ds32 __user *up64 = (struct msqid64_ds32 __user *)uptr;
664 mm_segment_t old_fs;
665
666 switch (second & ~IPC_64) {
667 case IPC_INFO:
668 case IPC_RMID:
669 case MSG_INFO:
670 err = sys_msgctl (first, second, (struct msqid_ds __user *)uptr);
671 break;
672
673 case IPC_SET:
674 if (second & IPC_64) {
675 if (!access_ok(VERIFY_READ, up64, sizeof(*up64))) {
676 err = -EFAULT;
677 break;
678 }
679 err = __get_user(m.msg_perm.uid, &up64->msg_perm.uid);
680 err |= __get_user(m.msg_perm.gid, &up64->msg_perm.gid);
681 err |= __get_user(m.msg_perm.mode, &up64->msg_perm.mode);
682 err |= __get_user(m.msg_qbytes, &up64->msg_qbytes);
683 } else {
684 if (!access_ok(VERIFY_READ, up32, sizeof(*up32))) {
685 err = -EFAULT;
686 break;
687 }
688 err = __get_user(m.msg_perm.uid, &up32->msg_perm.uid);
689 err |= __get_user(m.msg_perm.gid, &up32->msg_perm.gid);
690 err |= __get_user(m.msg_perm.mode, &up32->msg_perm.mode);
691 err |= __get_user(m.msg_qbytes, &up32->msg_qbytes);
692 }
693 if (err)
694 break;
695 old_fs = get_fs();
696 set_fs(KERNEL_DS);
697 err = sys_msgctl(first, second | IPC_64, (struct msqid_ds __user *)&m);
698 set_fs(old_fs);
699 break;
700
701 case IPC_STAT:
702 case MSG_STAT:
703 old_fs = get_fs();
704 set_fs(KERNEL_DS);
705 err = sys_msgctl(first, second | IPC_64, (struct msqid_ds __user *)&m);
706 set_fs(old_fs);
707 if (second & IPC_64) {
708 if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) {
709 err = -EFAULT;
710 break;
711 }
712 err2 = __put_user(m.msg_perm.key, &up64->msg_perm.key);
713 err2 |= __put_user(m.msg_perm.uid, &up64->msg_perm.uid);
714 err2 |= __put_user(m.msg_perm.gid, &up64->msg_perm.gid);
715 err2 |= __put_user(m.msg_perm.cuid, &up64->msg_perm.cuid);
716 err2 |= __put_user(m.msg_perm.cgid, &up64->msg_perm.cgid);
717 err2 |= __put_user(m.msg_perm.mode, &up64->msg_perm.mode);
718 err2 |= __put_user(m.msg_perm.seq, &up64->msg_perm.seq);
719 err2 |= __put_user(m.msg_stime, &up64->msg_stime);
720 err2 |= __put_user(m.msg_rtime, &up64->msg_rtime);
721 err2 |= __put_user(m.msg_ctime, &up64->msg_ctime);
722 err2 |= __put_user(m.msg_cbytes, &up64->msg_cbytes);
723 err2 |= __put_user(m.msg_qnum, &up64->msg_qnum);
724 err2 |= __put_user(m.msg_qbytes, &up64->msg_qbytes);
725 err2 |= __put_user(m.msg_lspid, &up64->msg_lspid);
726 err2 |= __put_user(m.msg_lrpid, &up64->msg_lrpid);
727 if (err2)
728 err = -EFAULT;
729 } else {
730 if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) {
731 err = -EFAULT;
732 break;
733 }
734 err2 = __put_user(m.msg_perm.key, &up32->msg_perm.key);
735 err2 |= __put_user(m.msg_perm.uid, &up32->msg_perm.uid);
736 err2 |= __put_user(m.msg_perm.gid, &up32->msg_perm.gid);
737 err2 |= __put_user(m.msg_perm.cuid, &up32->msg_perm.cuid);
738 err2 |= __put_user(m.msg_perm.cgid, &up32->msg_perm.cgid);
739 err2 |= __put_user(m.msg_perm.mode, &up32->msg_perm.mode);
740 err2 |= __put_user(m.msg_perm.seq, &up32->msg_perm.seq);
741 err2 |= __put_user(m.msg_stime, &up32->msg_stime);
742 err2 |= __put_user(m.msg_rtime, &up32->msg_rtime);
743 err2 |= __put_user(m.msg_ctime, &up32->msg_ctime);
744 err2 |= __put_user(m.msg_cbytes, &up32->msg_cbytes);
745 err2 |= __put_user(m.msg_qnum, &up32->msg_qnum);
746 err2 |= __put_user(m.msg_qbytes, &up32->msg_qbytes);
747 err2 |= __put_user(m.msg_lspid, &up32->msg_lspid);
748 err2 |= __put_user(m.msg_lrpid, &up32->msg_lrpid);
749 if (err2)
750 err = -EFAULT;
751 }
752 break;
753 }
754
755 return err;
756}
757
758static int
759do_sys32_shmat (int first, int second, int third, int version, void __user *uptr)
760{
761 unsigned long raddr;
762 u32 __user *uaddr = (u32 __user *)A((u32)third);
763 int err = -EINVAL;
764
765 if (version == 1)
766 return err;
767 err = do_shmat (first, uptr, second, &raddr);
768 if (err)
769 return err;
770 err = put_user (raddr, uaddr);
771 return err;
772}
773
774struct shm_info32 {
775 int used_ids;
776 u32 shm_tot, shm_rss, shm_swp;
777 u32 swap_attempts, swap_successes;
778};
779
780static int
781do_sys32_shmctl (int first, int second, void __user *uptr)
782{
783 struct shmid64_ds32 __user *up64 = (struct shmid64_ds32 __user *)uptr;
784 struct shmid_ds32 __user *up32 = (struct shmid_ds32 __user *)uptr;
785 struct shm_info32 __user *uip = (struct shm_info32 __user *)uptr;
786 int err = -EFAULT, err2;
787 struct shmid64_ds s64;
788 mm_segment_t old_fs;
789 struct shm_info si;
790 struct shmid_ds s;
791
792 switch (second & ~IPC_64) {
793 case IPC_INFO:
794 second = IPC_INFO; /* So that we don't have to translate it */
795 case IPC_RMID:
796 case SHM_LOCK:
797 case SHM_UNLOCK:
798 err = sys_shmctl(first, second, (struct shmid_ds __user *)uptr);
799 break;
800 case IPC_SET:
801 if (second & IPC_64) {
802 err = get_user(s.shm_perm.uid, &up64->shm_perm.uid);
803 err |= get_user(s.shm_perm.gid, &up64->shm_perm.gid);
804 err |= get_user(s.shm_perm.mode, &up64->shm_perm.mode);
805 } else {
806 err = get_user(s.shm_perm.uid, &up32->shm_perm.uid);
807 err |= get_user(s.shm_perm.gid, &up32->shm_perm.gid);
808 err |= get_user(s.shm_perm.mode, &up32->shm_perm.mode);
809 }
810 if (err)
811 break;
812 old_fs = get_fs();
813 set_fs(KERNEL_DS);
814 err = sys_shmctl(first, second & ~IPC_64, (struct shmid_ds __user *)&s);
815 set_fs(old_fs);
816 break;
817
818 case IPC_STAT:
819 case SHM_STAT:
820 old_fs = get_fs();
821 set_fs(KERNEL_DS);
822 err = sys_shmctl(first, second | IPC_64, (void __user *) &s64);
823 set_fs(old_fs);
824 if (err < 0)
825 break;
826 if (second & IPC_64) {
827 if (!access_ok(VERIFY_WRITE, up64, sizeof(*up64))) {
828 err = -EFAULT;
829 break;
830 }
831 err2 = __put_user(s64.shm_perm.key, &up64->shm_perm.key);
832 err2 |= __put_user(s64.shm_perm.uid, &up64->shm_perm.uid);
833 err2 |= __put_user(s64.shm_perm.gid, &up64->shm_perm.gid);
834 err2 |= __put_user(s64.shm_perm.cuid, &up64->shm_perm.cuid);
835 err2 |= __put_user(s64.shm_perm.cgid, &up64->shm_perm.cgid);
836 err2 |= __put_user(s64.shm_perm.mode, &up64->shm_perm.mode);
837 err2 |= __put_user(s64.shm_perm.seq, &up64->shm_perm.seq);
838 err2 |= __put_user(s64.shm_atime, &up64->shm_atime);
839 err2 |= __put_user(s64.shm_dtime, &up64->shm_dtime);
840 err2 |= __put_user(s64.shm_ctime, &up64->shm_ctime);
841 err2 |= __put_user(s64.shm_segsz, &up64->shm_segsz);
842 err2 |= __put_user(s64.shm_nattch, &up64->shm_nattch);
843 err2 |= __put_user(s64.shm_cpid, &up64->shm_cpid);
844 err2 |= __put_user(s64.shm_lpid, &up64->shm_lpid);
845 } else {
846 if (!access_ok(VERIFY_WRITE, up32, sizeof(*up32))) {
847 err = -EFAULT;
848 break;
849 }
850 err2 = __put_user(s64.shm_perm.key, &up32->shm_perm.key);
851 err2 |= __put_user(s64.shm_perm.uid, &up32->shm_perm.uid);
852 err2 |= __put_user(s64.shm_perm.gid, &up32->shm_perm.gid);
853 err2 |= __put_user(s64.shm_perm.cuid, &up32->shm_perm.cuid);
854 err2 |= __put_user(s64.shm_perm.cgid, &up32->shm_perm.cgid);
855 err2 |= __put_user(s64.shm_perm.mode, &up32->shm_perm.mode);
856 err2 |= __put_user(s64.shm_perm.seq, &up32->shm_perm.seq);
857 err2 |= __put_user(s64.shm_atime, &up32->shm_atime);
858 err2 |= __put_user(s64.shm_dtime, &up32->shm_dtime);
859 err2 |= __put_user(s64.shm_ctime, &up32->shm_ctime);
860 err2 |= __put_user(s64.shm_segsz, &up32->shm_segsz);
861 err2 |= __put_user(s64.shm_nattch, &up32->shm_nattch);
862 err2 |= __put_user(s64.shm_cpid, &up32->shm_cpid);
863 err2 |= __put_user(s64.shm_lpid, &up32->shm_lpid);
864 }
865 if (err2)
866 err = -EFAULT;
867 break;
868
869 case SHM_INFO:
870 old_fs = get_fs();
871 set_fs(KERNEL_DS);
872 err = sys_shmctl(first, second, (void __user *)&si);
873 set_fs(old_fs);
874 if (err < 0)
875 break;
876 err2 = put_user(si.used_ids, &uip->used_ids);
877 err2 |= __put_user(si.shm_tot, &uip->shm_tot);
878 err2 |= __put_user(si.shm_rss, &uip->shm_rss);
879 err2 |= __put_user(si.shm_swp, &uip->shm_swp);
880 err2 |= __put_user(si.swap_attempts, &uip->swap_attempts);
881 err2 |= __put_user (si.swap_successes, &uip->swap_successes);
882 if (err2)
883 err = -EFAULT;
884 break;
885
886 default:
887 err = -EINVAL;
888 break;
889 }
890
891 return err;
892}
893
894static int sys32_semtimedop(int semid, struct sembuf __user *tsems, int nsems,
895 const struct compat_timespec __user *timeout32)
896{
897 struct compat_timespec t32;
898 struct timespec __user *t64 = compat_alloc_user_space(sizeof(*t64));
899
900 if (copy_from_user(&t32, timeout32, sizeof(t32)))
901 return -EFAULT;
902
903 if (put_user(t32.tv_sec, &t64->tv_sec) ||
904 put_user(t32.tv_nsec, &t64->tv_nsec))
905 return -EFAULT;
906
907 return sys_semtimedop(semid, tsems, nsems, t64);
908}
909
910asmlinkage long 385asmlinkage long
911sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 386sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
912{ 387{
@@ -918,48 +393,43 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
918 switch (call) { 393 switch (call) {
919 case SEMOP: 394 case SEMOP:
920 /* struct sembuf is the same on 32 and 64bit :)) */ 395 /* struct sembuf is the same on 32 and 64bit :)) */
921 err = sys_semtimedop (first, (struct sembuf __user *)AA(ptr), second, 396 err = sys_semtimedop(first, compat_ptr(ptr), second, NULL);
922 NULL);
923 break; 397 break;
924 case SEMTIMEDOP: 398 case SEMTIMEDOP:
925 err = sys32_semtimedop (first, (struct sembuf __user *)AA(ptr), second, 399 err = compat_sys_semtimedop(first, compat_ptr(ptr), second,
926 (const struct compat_timespec __user *)AA(fifth)); 400 compat_ptr(fifth));
927 break; 401 break;
928 case SEMGET: 402 case SEMGET:
929 err = sys_semget (first, second, third); 403 err = sys_semget(first, second, third);
930 break; 404 break;
931 case SEMCTL: 405 case SEMCTL:
932 err = do_sys32_semctl (first, second, third, 406 err = compat_sys_semctl(first, second, third, compat_ptr(ptr));
933 (void __user *)AA(ptr));
934 break; 407 break;
935
936 case MSGSND: 408 case MSGSND:
937 err = do_sys32_msgsnd (first, second, third, 409 err = compat_sys_msgsnd(first, second, third, compat_ptr(ptr));
938 (void __user *)AA(ptr));
939 break; 410 break;
940 case MSGRCV: 411 case MSGRCV:
941 err = do_sys32_msgrcv (first, second, fifth, third, 412 err = compat_sys_msgrcv(first, second, fifth, third,
942 version, (void __user *)AA(ptr)); 413 version, compat_ptr(ptr));
943 break; 414 break;
944 case MSGGET: 415 case MSGGET:
945 err = sys_msgget ((key_t) first, second); 416 err = sys_msgget((key_t) first, second);
946 break; 417 break;
947 case MSGCTL: 418 case MSGCTL:
948 err = do_sys32_msgctl (first, second, (void __user *)AA(ptr)); 419 err = compat_sys_msgctl(first, second, compat_ptr(ptr));
949 break; 420 break;
950
951 case SHMAT: 421 case SHMAT:
952 err = do_sys32_shmat (first, second, third, 422 err = compat_sys_shmat(first, second, third, version,
953 version, (void __user *)AA(ptr)); 423 compat_ptr(ptr));
954 break; 424 break;
955 case SHMDT: 425 case SHMDT:
956 err = sys_shmdt ((char __user *)A(ptr)); 426 err = sys_shmdt(compat_ptr(ptr));
957 break; 427 break;
958 case SHMGET: 428 case SHMGET:
959 err = sys_shmget (first, (unsigned)second, third); 429 err = sys_shmget(first, (unsigned)second, third);
960 break; 430 break;
961 case SHMCTL: 431 case SHMCTL:
962 err = do_sys32_shmctl (first, second, (void __user *)AA(ptr)); 432 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
963 break; 433 break;
964 default: 434 default:
965 err = -EINVAL; 435 err = -EINVAL;
@@ -969,18 +439,28 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
969 return err; 439 return err;
970} 440}
971 441
972asmlinkage long sys32_shmat(int shmid, char __user *shmaddr, 442#ifdef CONFIG_MIPS32_N32
973 int shmflg, int32_t __user *addr) 443asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, u32 arg)
974{ 444{
975 unsigned long raddr; 445 /* compat_sys_semctl expects a pointer to union semun */
976 int err; 446 u32 __user *uptr = compat_alloc_user_space(sizeof(u32));
447 if (put_user(arg, uptr))
448 return -EFAULT;
449 return compat_sys_semctl(semid, semnum, cmd, uptr);
450}
977 451
978 err = do_shmat(shmid, shmaddr, shmflg, &raddr); 452asmlinkage long sysn32_msgsnd(int msqid, u32 msgp, unsigned msgsz, int msgflg)
979 if (err) 453{
980 return err; 454 return compat_sys_msgsnd(msqid, msgsz, msgflg, compat_ptr(msgp));
455}
981 456
982 return put_user(raddr, addr); 457asmlinkage long sysn32_msgrcv(int msqid, u32 msgp, size_t msgsz, int msgtyp,
458 int msgflg)
459{
460 return compat_sys_msgrcv(msqid, msgsz, msgtyp, msgflg, IPC_64,
461 compat_ptr(msgp));
983} 462}
463#endif
984 464
985struct sysctl_args32 465struct sysctl_args32
986{ 466{
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
new file mode 100644
index 000000000000..e0ad754c7edd
--- /dev/null
+++ b/arch/mips/kernel/machine_kexec.c
@@ -0,0 +1,85 @@
1/*
2 * machine_kexec.c for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 15:15:06 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <linux/kexec.h>
10#include <linux/mm.h>
11#include <linux/delay.h>
12
13#include <asm/cacheflush.h>
14#include <asm/page.h>
15
16const extern unsigned char relocate_new_kernel[];
17const extern unsigned int relocate_new_kernel_size;
18
19extern unsigned long kexec_start_address;
20extern unsigned long kexec_indirection_page;
21
22int
23machine_kexec_prepare(struct kimage *kimage)
24{
25 return 0;
26}
27
28void
29machine_kexec_cleanup(struct kimage *kimage)
30{
31}
32
33void
34machine_shutdown(void)
35{
36}
37
38void
39machine_crash_shutdown(struct pt_regs *regs)
40{
41}
42
43void
44machine_kexec(struct kimage *image)
45{
46 unsigned long reboot_code_buffer;
47 unsigned long entry;
48 unsigned long *ptr;
49
50 reboot_code_buffer =
51 (unsigned long)page_address(image->control_code_page);
52
53 kexec_start_address = image->start;
54 kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK);
55
56 memcpy((void*)reboot_code_buffer, relocate_new_kernel,
57 relocate_new_kernel_size);
58
59 /*
60 * The generic kexec code builds a page list with physical
61 * addresses. they are directly accessible through KSEG0 (or
62 * CKSEG0 or XPHYS if on 64bit system), hence the
63 * pys_to_virt() call.
64 */
65 for (ptr = &image->head; (entry = *ptr) && !(entry &IND_DONE);
66 ptr = (entry & IND_INDIRECTION) ?
67 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
68 if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
69 *ptr & IND_DESTINATION)
70 *ptr = phys_to_virt(*ptr);
71 }
72
73 /*
74 * we do not want to be bothered.
75 */
76 local_irq_disable();
77
78 flush_icache_range(reboot_code_buffer,
79 reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
80
81 printk("Will call new kernel at %08x\n", image->start);
82 printk("Bye ...\n");
83 flush_cache_all();
84 ((void (*)(void))reboot_code_buffer)();
85}
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index f44a01357ada..2ef857c3ee53 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -46,5 +46,7 @@ EXPORT_SYMBOL(__strnlen_user_nocheck_asm);
46EXPORT_SYMBOL(__strnlen_user_asm); 46EXPORT_SYMBOL(__strnlen_user_asm);
47 47
48EXPORT_SYMBOL(csum_partial); 48EXPORT_SYMBOL(csum_partial);
49EXPORT_SYMBOL(csum_partial_copy_nocheck);
50EXPORT_SYMBOL(__csum_partial_copy_user);
49 51
50EXPORT_SYMBOL(invalid_pte_table); 52EXPORT_SYMBOL(invalid_pte_table);
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index d7bf0215bc1d..cb0801437b66 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -29,6 +29,7 @@
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32#include <asm/pgtable.h> /* MODULE_START */
32 33
33struct mips_hi16 { 34struct mips_hi16 {
34 struct mips_hi16 *next; 35 struct mips_hi16 *next;
@@ -43,9 +44,23 @@ static DEFINE_SPINLOCK(dbe_lock);
43 44
44void *module_alloc(unsigned long size) 45void *module_alloc(unsigned long size)
45{ 46{
47#ifdef MODULE_START
48 struct vm_struct *area;
49
50 size = PAGE_ALIGN(size);
51 if (!size)
52 return NULL;
53
54 area = __get_vm_area(size, VM_ALLOC, MODULE_START, MODULE_END);
55 if (!area)
56 return NULL;
57
58 return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
59#else
46 if (size == 0) 60 if (size == 0)
47 return NULL; 61 return NULL;
48 return vmalloc(size); 62 return vmalloc(size);
63#endif
49} 64}
50 65
51/* Free memory returned from module_alloc */ 66/* Free memory returned from module_alloc */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
new file mode 100644
index 000000000000..a3f0d00c1334
--- /dev/null
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -0,0 +1,80 @@
1/*
2 * relocate_kernel.S for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 17:49:57 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <asm/asm.h>
10#include <asm/asmmacro.h>
11#include <asm/regdef.h>
12#include <asm/page.h>
13#include <asm/mipsregs.h>
14#include <asm/stackframe.h>
15#include <asm/addrspace.h>
16
17 .globl relocate_new_kernel
18relocate_new_kernel:
19
20 PTR_L s0, kexec_indirection_page
21 PTR_L s1, kexec_start_address
22
23process_entry:
24 PTR_L s2, (s0)
25 PTR_ADD s0, s0, SZREG
26
27 /* destination page */
28 and s3, s2, 0x1
29 beq s3, zero, 1f
30 and s4, s2, ~0x1 /* store destination addr in s4 */
31 move a0, s4
32 b process_entry
33
341:
35 /* indirection page, update s0 */
36 and s3, s2, 0x2
37 beq s3, zero, 1f
38 and s0, s2, ~0x2
39 b process_entry
40
411:
42 /* done page */
43 and s3, s2, 0x4
44 beq s3, zero, 1f
45 b done
461:
47 /* source page */
48 and s3, s2, 0x8
49 beq s3, zero, process_entry
50 and s2, s2, ~0x8
51 li s6, (1 << PAGE_SHIFT) / SZREG
52
53copy_word:
54 /* copy page word by word */
55 REG_L s5, (s2)
56 REG_S s5, (s4)
57 INT_ADD s4, s4, SZREG
58 INT_ADD s2, s2, SZREG
59 INT_SUB s6, s6, 1
60 beq s6, zero, process_entry
61 b copy_word
62 b process_entry
63
64done:
65 /* jump to kexec_start_address */
66 j s1
67
68 .globl kexec_start_address
69kexec_start_address:
70 .long 0x0
71
72 .globl kexec_indirection_page
73kexec_indirection_page:
74 .long 0x0
75
76relocate_new_kernel_end:
77
78 .globl relocate_new_kernel_size
79relocate_new_kernel_size:
80 .long relocate_new_kernel_end - relocate_new_kernel
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 621037db2290..060563a712b6 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -23,6 +23,8 @@ void (*_machine_restart)(char *command);
23void (*_machine_halt)(void); 23void (*_machine_halt)(void);
24void (*pm_power_off)(void); 24void (*pm_power_off)(void);
25 25
26EXPORT_SYMBOL(pm_power_off);
27
26void machine_restart(char *command) 28void machine_restart(char *command)
27{ 29{
28 if (_machine_restart) 30 if (_machine_restart)
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 8c8c8324f775..5a99e3e0c96d 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -415,7 +415,7 @@ static unsigned int file_poll(struct file *file, poll_table * wait)
415 int minor; 415 int minor;
416 unsigned int mask = 0; 416 unsigned int mask = 0;
417 417
418 minor = iminor(file->f_dentry->d_inode); 418 minor = iminor(file->f_path.dentry->d_inode);
419 419
420 poll_wait(file, &channel_wqs[minor].rt_queue, wait); 420 poll_wait(file, &channel_wqs[minor].rt_queue, wait);
421 poll_wait(file, &channel_wqs[minor].lx_queue, wait); 421 poll_wait(file, &channel_wqs[minor].lx_queue, wait);
@@ -437,7 +437,7 @@ static unsigned int file_poll(struct file *file, poll_table * wait)
437static ssize_t file_read(struct file *file, char __user * buffer, size_t count, 437static ssize_t file_read(struct file *file, char __user * buffer, size_t count,
438 loff_t * ppos) 438 loff_t * ppos)
439{ 439{
440 int minor = iminor(file->f_dentry->d_inode); 440 int minor = iminor(file->f_path.dentry->d_inode);
441 441
442 /* data available? */ 442 /* data available? */
443 if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { 443 if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) {
@@ -454,7 +454,7 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
454 struct rtlx_channel *rt; 454 struct rtlx_channel *rt;
455 DECLARE_WAITQUEUE(wait, current); 455 DECLARE_WAITQUEUE(wait, current);
456 456
457 minor = iminor(file->f_dentry->d_inode); 457 minor = iminor(file->f_path.dentry->d_inode);
458 rt = &rtlx->channel[minor]; 458 rt = &rtlx->channel[minor];
459 459
460 /* any space left... */ 460 /* any space left... */
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index a95f37de080e..7c0b3936ba44 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -653,7 +653,7 @@ einval: li v0, -EINVAL
653 sys sys_move_pages 6 653 sys sys_move_pages 6
654 sys sys_set_robust_list 2 654 sys sys_set_robust_list 2
655 sys sys_get_robust_list 3 /* 4310 */ 655 sys sys_get_robust_list 3 /* 4310 */
656 sys sys_ni_syscall 0 656 sys sys_kexec_load 4
657 sys sys_getcpu 3 657 sys sys_getcpu 3
658 sys sys_epoll_pwait 6 658 sys sys_epoll_pwait 6
659 .endm 659 .endm
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 8fb0f60f657b..e569b846e9a3 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -468,6 +468,6 @@ sys_call_table:
468 PTR sys_move_pages 468 PTR sys_move_pages
469 PTR sys_set_robust_list 469 PTR sys_set_robust_list
470 PTR sys_get_robust_list 470 PTR sys_get_robust_list
471 PTR sys_ni_syscall /* 5270 */ 471 PTR sys_kexec_load /* 5270 */
472 PTR sys_getcpu 472 PTR sys_getcpu
473 PTR sys_epoll_pwait 473 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 0da5ca2040ff..a7bff2a54723 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -149,8 +149,8 @@ EXPORT(sysn32_call_table)
149 PTR sys_mincore 149 PTR sys_mincore
150 PTR sys_madvise 150 PTR sys_madvise
151 PTR sys_shmget 151 PTR sys_shmget
152 PTR sys32_shmat 152 PTR sys_shmat
153 PTR sys_shmctl /* 6030 */ 153 PTR compat_sys_shmctl /* 6030 */
154 PTR sys_dup 154 PTR sys_dup
155 PTR sys_dup2 155 PTR sys_dup2
156 PTR sys_pause 156 PTR sys_pause
@@ -184,12 +184,12 @@ EXPORT(sysn32_call_table)
184 PTR sys32_newuname 184 PTR sys32_newuname
185 PTR sys_semget 185 PTR sys_semget
186 PTR sys_semop 186 PTR sys_semop
187 PTR sys_semctl 187 PTR sysn32_semctl
188 PTR sys_shmdt /* 6065 */ 188 PTR sys_shmdt /* 6065 */
189 PTR sys_msgget 189 PTR sys_msgget
190 PTR sys_msgsnd 190 PTR sysn32_msgsnd
191 PTR sys_msgrcv 191 PTR sysn32_msgrcv
192 PTR sys_msgctl 192 PTR compat_sys_msgctl
193 PTR compat_sys_fcntl /* 6070 */ 193 PTR compat_sys_fcntl /* 6070 */
194 PTR sys_flock 194 PTR sys_flock
195 PTR sys_fsync 195 PTR sys_fsync
@@ -335,7 +335,7 @@ EXPORT(sysn32_call_table)
335 PTR compat_sys_fcntl64 335 PTR compat_sys_fcntl64
336 PTR sys_set_tid_address 336 PTR sys_set_tid_address
337 PTR sys_restart_syscall 337 PTR sys_restart_syscall
338 PTR sys_semtimedop /* 6215 */ 338 PTR compat_sys_semtimedop /* 6215 */
339 PTR sys_fadvise64_64 339 PTR sys_fadvise64_64
340 PTR compat_sys_statfs64 340 PTR compat_sys_statfs64
341 PTR compat_sys_fstatfs64 341 PTR compat_sys_fstatfs64
@@ -394,6 +394,6 @@ EXPORT(sysn32_call_table)
394 PTR sys_move_pages 394 PTR sys_move_pages
395 PTR compat_sys_set_robust_list 395 PTR compat_sys_set_robust_list
396 PTR compat_sys_get_robust_list 396 PTR compat_sys_get_robust_list
397 PTR sys_ni_syscall 397 PTR compat_sys_kexec_load
398 PTR sys_getcpu 398 PTR sys_getcpu
399 PTR sys_epoll_pwait 399 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index b9d00cae8b5f..e91379c1be1d 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -516,7 +516,7 @@ sys_call_table:
516 PTR compat_sys_move_pages 516 PTR compat_sys_move_pages
517 PTR compat_sys_set_robust_list 517 PTR compat_sys_set_robust_list
518 PTR compat_sys_get_robust_list /* 4310 */ 518 PTR compat_sys_get_robust_list /* 4310 */
519 PTR sys_ni_syscall 519 PTR compat_sys_kexec_load
520 PTR sys_getcpu 520 PTR sys_getcpu
521 PTR sys_epoll_pwait 521 PTR sys_epoll_pwait
522 .size sys_call_table,.-sys_call_table 522 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8f6e89697ccf..89440a0d8528 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -145,13 +145,12 @@ static int __init rd_start_early(char *p)
145 unsigned long start = memparse(p, &p); 145 unsigned long start = memparse(p, &p);
146 146
147#ifdef CONFIG_64BIT 147#ifdef CONFIG_64BIT
148 /* HACK: Guess if the sign extension was forgotten */ 148 /* Guess if the sign extension was forgotten by bootloader */
149 if (start > 0x0000000080000000 && start < 0x00000000ffffffff) 149 if (start < XKPHYS)
150 start |= 0xffffffff00000000UL; 150 start = (int)start;
151#endif 151#endif
152 initrd_start = start; 152 initrd_start = start;
153 initrd_end += start; 153 initrd_end += start;
154
155 return 0; 154 return 0;
156} 155}
157early_param("rd_start", rd_start_early); 156early_param("rd_start", rd_start_early);
@@ -159,41 +158,64 @@ early_param("rd_start", rd_start_early);
159static int __init rd_size_early(char *p) 158static int __init rd_size_early(char *p)
160{ 159{
161 initrd_end += memparse(p, &p); 160 initrd_end += memparse(p, &p);
162
163 return 0; 161 return 0;
164} 162}
165early_param("rd_size", rd_size_early); 163early_param("rd_size", rd_size_early);
166 164
165/* it returns the next free pfn after initrd */
167static unsigned long __init init_initrd(void) 166static unsigned long __init init_initrd(void)
168{ 167{
169 unsigned long tmp, end, size; 168 unsigned long end;
170 u32 *initrd_header; 169 u32 *initrd_header;
171 170
172 ROOT_DEV = Root_RAM0;
173
174 /* 171 /*
175 * Board specific code or command line parser should have 172 * Board specific code or command line parser should have
176 * already set up initrd_start and initrd_end. In these cases 173 * already set up initrd_start and initrd_end. In these cases
177 * perfom sanity checks and use them if all looks good. 174 * perfom sanity checks and use them if all looks good.
178 */ 175 */
179 size = initrd_end - initrd_start; 176 if (initrd_start && initrd_end > initrd_start)
180 if (initrd_end == 0 || size == 0) { 177 goto sanitize;
181 initrd_start = 0; 178
182 initrd_end = 0; 179 /*
183 } else 180 * See if initrd has been added to the kernel image by
184 return initrd_end; 181 * arch/mips/boot/addinitrd.c. In that case a header is
185 182 * prepended to initrd and is made up by 8 bytes. The fisrt
186 end = (unsigned long)&_end; 183 * word is a magic number and the second one is the size of
187 tmp = PAGE_ALIGN(end) - sizeof(u32) * 2; 184 * initrd. Initrd start must be page aligned in any cases.
188 if (tmp < end) 185 */
189 tmp += PAGE_SIZE; 186 initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
190 187 if (initrd_header[0] != 0x494E5244)
191 initrd_header = (u32 *)tmp; 188 goto disable;
192 if (initrd_header[0] == 0x494E5244) { 189 initrd_start = (unsigned long)(initrd_header + 2);
193 initrd_start = (unsigned long)&initrd_header[2]; 190 initrd_end = initrd_start + initrd_header[1];
194 initrd_end = initrd_start + initrd_header[1]; 191
192sanitize:
193 if (initrd_start & ~PAGE_MASK) {
194 printk(KERN_ERR "initrd start must be page aligned\n");
195 goto disable;
195 } 196 }
196 return initrd_end; 197 if (initrd_start < PAGE_OFFSET) {
198 printk(KERN_ERR "initrd start < PAGE_OFFSET\n");
199 goto disable;
200 }
201
202 /*
203 * Sanitize initrd addresses. For example firmware
204 * can't guess if they need to pass them through
205 * 64-bits values if the kernel has been built in pure
206 * 32-bit. We need also to switch from KSEG0 to XKPHYS
207 * addresses now, so the code can now safely use __pa().
208 */
209 end = __pa(initrd_end);
210 initrd_end = (unsigned long)__va(end);
211 initrd_start = (unsigned long)__va(__pa(initrd_start));
212
213 ROOT_DEV = Root_RAM0;
214 return PFN_UP(end);
215disable:
216 initrd_start = 0;
217 initrd_end = 0;
218 return 0;
197} 219}
198 220
199static void __init finalize_initrd(void) 221static void __init finalize_initrd(void)
@@ -204,12 +226,12 @@ static void __init finalize_initrd(void)
204 printk(KERN_INFO "Initrd not found or empty"); 226 printk(KERN_INFO "Initrd not found or empty");
205 goto disable; 227 goto disable;
206 } 228 }
207 if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { 229 if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
208 printk("Initrd extends beyond end of memory"); 230 printk("Initrd extends beyond end of memory");
209 goto disable; 231 goto disable;
210 } 232 }
211 233
212 reserve_bootmem(CPHYSADDR(initrd_start), size); 234 reserve_bootmem(__pa(initrd_start), size);
213 initrd_below_start_ok = 1; 235 initrd_below_start_ok = 1;
214 236
215 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 237 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
@@ -259,8 +281,7 @@ static void __init bootmem_init(void)
259 * not selected. Once that done we can determine the low bound 281 * not selected. Once that done we can determine the low bound
260 * of usable memory. 282 * of usable memory.
261 */ 283 */
262 reserved_end = init_initrd(); 284 reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
263 reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end)));
264 285
265 /* 286 /*
266 * Find the highest page frame number we have available. 287 * Find the highest page frame number we have available.
@@ -432,10 +453,10 @@ static void __init resource_init(void)
432 if (UNCAC_BASE != IO_BASE) 453 if (UNCAC_BASE != IO_BASE)
433 return; 454 return;
434 455
435 code_resource.start = virt_to_phys(&_text); 456 code_resource.start = __pa_symbol(&_text);
436 code_resource.end = virt_to_phys(&_etext) - 1; 457 code_resource.end = __pa_symbol(&_etext) - 1;
437 data_resource.start = virt_to_phys(&_etext); 458 data_resource.start = __pa_symbol(&_etext);
438 data_resource.end = virt_to_phys(&_edata) - 1; 459 data_resource.end = __pa_symbol(&_edata) - 1;
439 460
440 /* 461 /*
441 * Request address space for all standard RAM. 462 * Request address space for all standard RAM.
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 477c5334ec1b..a67c18555ed3 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -17,7 +17,6 @@
17 */ 17 */
18#include <linux/cache.h> 18#include <linux/cache.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/sched.h>
21#include <linux/mm.h> 20#include <linux/mm.h>
22#include <linux/smp.h> 21#include <linux/smp.h>
23#include <linux/smp_lock.h> 22#include <linux/smp_lock.h>
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2ac19a6cbf68..1ee689c0e0c9 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
278 278
279 /* need to mark IPI's as IRQ_PER_CPU */ 279 /* need to mark IPI's as IRQ_PER_CPU */
280 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; 280 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
281 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
281 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; 282 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
283 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
282} 284}
283 285
284/* 286/*
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 49db516789e0..0555fc554f65 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -172,7 +172,7 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
172 172
173 spin_lock(&smp_call_lock); 173 spin_lock(&smp_call_lock);
174 call_data = &data; 174 call_data = &data;
175 mb(); 175 smp_mb();
176 176
177 /* Send a message to all other CPUs and wait for them to respond */ 177 /* Send a message to all other CPUs and wait for them to respond */
178 for_each_online_cpu(i) 178 for_each_online_cpu(i)
@@ -204,7 +204,7 @@ void smp_call_function_interrupt(void)
204 * Notify initiating CPU that I've grabbed the data and am 204 * Notify initiating CPU that I've grabbed the data and am
205 * about to execute the function. 205 * about to execute the function.
206 */ 206 */
207 mb(); 207 smp_mb();
208 atomic_inc(&call_data->started); 208 atomic_inc(&call_data->started);
209 209
210 /* 210 /*
@@ -215,7 +215,7 @@ void smp_call_function_interrupt(void)
215 irq_exit(); 215 irq_exit();
216 216
217 if (wait) { 217 if (wait) {
218 mb(); 218 smp_mb();
219 atomic_inc(&call_data->finished); 219 atomic_inc(&call_data->finished);
220 } 220 }
221} 221}
@@ -271,7 +271,7 @@ void __devinit smp_prepare_boot_cpu(void)
271 * and keep control until "cpu_online(cpu)" is set. Note: cpu is 271 * and keep control until "cpu_online(cpu)" is set. Note: cpu is
272 * physical, not logical. 272 * physical, not logical.
273 */ 273 */
274int __devinit __cpu_up(unsigned int cpu) 274int __cpuinit __cpu_up(unsigned int cpu)
275{ 275{
276 struct task_struct *idle; 276 struct task_struct *idle;
277 277
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 3b78caf112f5..802febed7df5 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void)
1009 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1009 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1010 1010
1011 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; 1011 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
1012 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1012} 1013}
1013 1014
1014/* 1015/*
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index 93c74fefff76..6c2406a93f2b 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -732,7 +732,7 @@ asmlinkage int irix_fstatfs(unsigned int fd, struct irix_statfs __user *buf)
732 goto out; 732 goto out;
733 } 733 }
734 734
735 error = vfs_statfs(file->f_dentry, &kbuf); 735 error = vfs_statfs(file->f_path.dentry, &kbuf);
736 if (error) 736 if (error)
737 goto out_f; 737 goto out_f;
738 738
@@ -1041,7 +1041,7 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot,
1041 unsigned long old_pos; 1041 unsigned long old_pos;
1042 long max_size = offset + len; 1042 long max_size = offset + len;
1043 1043
1044 if (max_size > file->f_dentry->d_inode->i_size) { 1044 if (max_size > file->f_path.dentry->d_inode->i_size) {
1045 old_pos = sys_lseek (fd, max_size - 1, 0); 1045 old_pos = sys_lseek (fd, max_size - 1, 0);
1046 sys_write (fd, (void __user *) "", 1); 1046 sys_write (fd, (void __user *) "", 1);
1047 sys_lseek (fd, old_pos, 0); 1047 sys_lseek (fd, old_pos, 0);
@@ -1406,7 +1406,7 @@ asmlinkage int irix_fstatvfs(int fd, struct irix_statvfs __user *buf)
1406 error = -EBADF; 1406 error = -EBADF;
1407 goto out; 1407 goto out;
1408 } 1408 }
1409 error = vfs_statfs(file->f_dentry, &kbuf); 1409 error = vfs_statfs(file->f_path.dentry, &kbuf);
1410 if (error) 1410 if (error)
1411 goto out_f; 1411 goto out_f;
1412 1412
@@ -1526,7 +1526,7 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1526 unsigned long old_pos; 1526 unsigned long old_pos;
1527 long max_size = off2 + len; 1527 long max_size = off2 + len;
1528 1528
1529 if (max_size > file->f_dentry->d_inode->i_size) { 1529 if (max_size > file->f_path.dentry->d_inode->i_size) {
1530 old_pos = sys_lseek (fd, max_size - 1, 0); 1530 old_pos = sys_lseek (fd, max_size - 1, 0);
1531 sys_write (fd, (void __user *) "", 1); 1531 sys_write (fd, (void __user *) "", 1);
1532 sys_lseek (fd, old_pos, 0); 1532 sys_lseek (fd, old_pos, 0);
@@ -1658,7 +1658,7 @@ asmlinkage int irix_fstatvfs64(int fd, struct irix_statvfs __user *buf)
1658 error = -EBADF; 1658 error = -EBADF;
1659 goto out; 1659 goto out;
1660 } 1660 }
1661 error = vfs_statfs(file->f_dentry, &kbuf); 1661 error = vfs_statfs(file->f_path.dentry, &kbuf);
1662 if (error) 1662 if (error)
1663 goto out_f; 1663 goto out_f;
1664 1664
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index e535f86efa2f..8aa544f73a5e 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,7 +11,6 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/clocksource.h>
15#include <linux/types.h> 14#include <linux/types.h>
16#include <linux/kernel.h> 15#include <linux/kernel.h>
17#include <linux/init.h> 16#include <linux/init.h>
@@ -83,17 +82,11 @@ static void null_timer_ack(void) { /* nothing */ }
83/* 82/*
84 * Null high precision timer functions for systems lacking one. 83 * Null high precision timer functions for systems lacking one.
85 */ 84 */
86static unsigned int null_hpt_read(void) 85static cycle_t null_hpt_read(void)
87{ 86{
88 return 0; 87 return 0;
89} 88}
90 89
91static void __init null_hpt_init(void)
92{
93 /* nothing */
94}
95
96
97/* 90/*
98 * Timer ack for an R4k-compatible timer of a known frequency. 91 * Timer ack for an R4k-compatible timer of a known frequency.
99 */ 92 */
@@ -101,10 +94,8 @@ static void c0_timer_ack(void)
101{ 94{
102 unsigned int count; 95 unsigned int count;
103 96
104#ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */
105 /* Ack this timer interrupt and set the next one. */ 97 /* Ack this timer interrupt and set the next one. */
106 expirelo += cycles_per_jiffy; 98 expirelo += cycles_per_jiffy;
107#endif
108 write_c0_compare(expirelo); 99 write_c0_compare(expirelo);
109 100
110 /* Check to see if we have missed any timer interrupts. */ 101 /* Check to see if we have missed any timer interrupts. */
@@ -118,7 +109,7 @@ static void c0_timer_ack(void)
118/* 109/*
119 * High precision timer functions for a R4k-compatible timer. 110 * High precision timer functions for a R4k-compatible timer.
120 */ 111 */
121static unsigned int c0_hpt_read(void) 112static cycle_t c0_hpt_read(void)
122{ 113{
123 return read_c0_count(); 114 return read_c0_count();
124} 115}
@@ -132,9 +123,6 @@ static void __init c0_hpt_timer_init(void)
132 123
133int (*mips_timer_state)(void); 124int (*mips_timer_state)(void);
134void (*mips_timer_ack)(void); 125void (*mips_timer_ack)(void);
135unsigned int (*mips_hpt_read)(void);
136void (*mips_hpt_init)(void) __initdata = null_hpt_init;
137unsigned int mips_hpt_mask = 0xffffffff;
138 126
139/* last time when xtime and rtc are sync'ed up */ 127/* last time when xtime and rtc are sync'ed up */
140static long last_rtc_update; 128static long last_rtc_update;
@@ -276,8 +264,7 @@ static struct irqaction timer_irqaction = {
276 264
277static unsigned int __init calibrate_hpt(void) 265static unsigned int __init calibrate_hpt(void)
278{ 266{
279 u64 frequency; 267 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
280 u32 hpt_start, hpt_end, hpt_count, hz;
281 268
282 const int loops = HZ / 10; 269 const int loops = HZ / 10;
283 int log_2_loops = 0; 270 int log_2_loops = 0;
@@ -303,28 +290,23 @@ static unsigned int __init calibrate_hpt(void)
303 * during the calculated number of periods between timer 290 * during the calculated number of periods between timer
304 * interrupts. 291 * interrupts.
305 */ 292 */
306 hpt_start = mips_hpt_read(); 293 hpt_start = clocksource_mips.read();
307 do { 294 do {
308 while (mips_timer_state()); 295 while (mips_timer_state());
309 while (!mips_timer_state()); 296 while (!mips_timer_state());
310 } while (--i); 297 } while (--i);
311 hpt_end = mips_hpt_read(); 298 hpt_end = clocksource_mips.read();
312 299
313 hpt_count = (hpt_end - hpt_start) & mips_hpt_mask; 300 hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
314 hz = HZ; 301 hz = HZ;
315 frequency = (u64)hpt_count * (u64)hz; 302 frequency = hpt_count * hz;
316 303
317 return frequency >> log_2_loops; 304 return frequency >> log_2_loops;
318} 305}
319 306
320static cycle_t read_mips_hpt(void) 307struct clocksource clocksource_mips = {
321{
322 return (cycle_t)mips_hpt_read();
323}
324
325static struct clocksource clocksource_mips = {
326 .name = "MIPS", 308 .name = "MIPS",
327 .read = read_mips_hpt, 309 .mask = 0xffffffff,
328 .is_continuous = 1, 310 .is_continuous = 1,
329}; 311};
330 312
@@ -333,7 +315,7 @@ static void __init init_mips_clocksource(void)
333 u64 temp; 315 u64 temp;
334 u32 shift; 316 u32 shift;
335 317
336 if (!mips_hpt_frequency || mips_hpt_read == null_hpt_read) 318 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
337 return; 319 return;
338 320
339 /* Calclate a somewhat reasonable rating value */ 321 /* Calclate a somewhat reasonable rating value */
@@ -347,7 +329,6 @@ static void __init init_mips_clocksource(void)
347 } 329 }
348 clocksource_mips.shift = shift; 330 clocksource_mips.shift = shift;
349 clocksource_mips.mult = (u32)temp; 331 clocksource_mips.mult = (u32)temp;
350 clocksource_mips.mask = mips_hpt_mask;
351 332
352 clocksource_register(&clocksource_mips); 333 clocksource_register(&clocksource_mips);
353} 334}
@@ -367,32 +348,36 @@ void __init time_init(void)
367 -xtime.tv_sec, -xtime.tv_nsec); 348 -xtime.tv_sec, -xtime.tv_nsec);
368 349
369 /* Choose appropriate high precision timer routines. */ 350 /* Choose appropriate high precision timer routines. */
370 if (!cpu_has_counter && !mips_hpt_read) 351 if (!cpu_has_counter && !clocksource_mips.read)
371 /* No high precision timer -- sorry. */ 352 /* No high precision timer -- sorry. */
372 mips_hpt_read = null_hpt_read; 353 clocksource_mips.read = null_hpt_read;
373 else if (!mips_hpt_frequency && !mips_timer_state) { 354 else if (!mips_hpt_frequency && !mips_timer_state) {
374 /* A high precision timer of unknown frequency. */ 355 /* A high precision timer of unknown frequency. */
375 if (!mips_hpt_read) 356 if (!clocksource_mips.read)
376 /* No external high precision timer -- use R4k. */ 357 /* No external high precision timer -- use R4k. */
377 mips_hpt_read = c0_hpt_read; 358 clocksource_mips.read = c0_hpt_read;
378 } else { 359 } else {
379 /* We know counter frequency. Or we can get it. */ 360 /* We know counter frequency. Or we can get it. */
380 if (!mips_hpt_read) { 361 if (!clocksource_mips.read) {
381 /* No external high precision timer -- use R4k. */ 362 /* No external high precision timer -- use R4k. */
382 mips_hpt_read = c0_hpt_read; 363 clocksource_mips.read = c0_hpt_read;
383 364
384 if (!mips_timer_state) { 365 if (!mips_timer_state) {
385 /* No external timer interrupt -- use R4k. */ 366 /* No external timer interrupt -- use R4k. */
386 mips_hpt_init = c0_hpt_timer_init;
387 mips_timer_ack = c0_timer_ack; 367 mips_timer_ack = c0_timer_ack;
368 /* Calculate cache parameters. */
369 cycles_per_jiffy =
370 (mips_hpt_frequency + HZ / 2) / HZ;
371 /*
372 * This sets up the high precision
373 * timer for the first interrupt.
374 */
375 c0_hpt_timer_init();
388 } 376 }
389 } 377 }
390 if (!mips_hpt_frequency) 378 if (!mips_hpt_frequency)
391 mips_hpt_frequency = calibrate_hpt(); 379 mips_hpt_frequency = calibrate_hpt();
392 380
393 /* Calculate cache parameters. */
394 cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
395
396 /* Report the high precision timer rate for a reference. */ 381 /* Report the high precision timer rate for a reference. */
397 printk("Using %u.%03u MHz high precision timer.\n", 382 printk("Using %u.%03u MHz high precision timer.\n",
398 ((mips_hpt_frequency + 500) / 1000) / 1000, 383 ((mips_hpt_frequency + 500) / 1000) / 1000,
@@ -403,9 +388,6 @@ void __init time_init(void)
403 /* No timer interrupt ack (e.g. i8254). */ 388 /* No timer interrupt ack (e.g. i8254). */
404 mips_timer_ack = null_timer_ack; 389 mips_timer_ack = null_timer_ack;
405 390
406 /* This sets up the high precision timer for the first interrupt. */
407 mips_hpt_init();
408
409 /* 391 /*
410 * Call board specific timer interrupt setup. 392 * Call board specific timer interrupt setup.
411 * 393 *
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9fda1b8be3a7..2a932cada244 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -54,6 +54,8 @@ extern asmlinkage void handle_dbe(void);
54extern asmlinkage void handle_sys(void); 54extern asmlinkage void handle_sys(void);
55extern asmlinkage void handle_bp(void); 55extern asmlinkage void handle_bp(void);
56extern asmlinkage void handle_ri(void); 56extern asmlinkage void handle_ri(void);
57extern asmlinkage void handle_ri_rdhwr_vivt(void);
58extern asmlinkage void handle_ri_rdhwr(void);
57extern asmlinkage void handle_cpu(void); 59extern asmlinkage void handle_cpu(void);
58extern asmlinkage void handle_ov(void); 60extern asmlinkage void handle_ov(void);
59extern asmlinkage void handle_tr(void); 61extern asmlinkage void handle_tr(void);
@@ -397,19 +399,6 @@ asmlinkage void do_be(struct pt_regs *regs)
397 force_sig(SIGBUS, current); 399 force_sig(SIGBUS, current);
398} 400}
399 401
400static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
401{
402 unsigned int __user *epc;
403
404 epc = (unsigned int __user *) regs->cp0_epc +
405 ((regs->cp0_cause & CAUSEF_BD) != 0);
406 if (!get_user(*opcode, epc))
407 return 0;
408
409 force_sig(SIGSEGV, current);
410 return 1;
411}
412
413/* 402/*
414 * ll/sc emulation 403 * ll/sc emulation
415 */ 404 */
@@ -544,8 +533,8 @@ static inline int simulate_llsc(struct pt_regs *regs)
544{ 533{
545 unsigned int opcode; 534 unsigned int opcode;
546 535
547 if (unlikely(get_insn_opcode(regs, &opcode))) 536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
548 return -EFAULT; 537 goto out_sigsegv;
549 538
550 if ((opcode & OPCODE) == LL) { 539 if ((opcode & OPCODE) == LL) {
551 simulate_ll(regs, opcode); 540 simulate_ll(regs, opcode);
@@ -557,6 +546,10 @@ static inline int simulate_llsc(struct pt_regs *regs)
557 } 546 }
558 547
559 return -EFAULT; /* Strange things going on ... */ 548 return -EFAULT; /* Strange things going on ... */
549
550out_sigsegv:
551 force_sig(SIGSEGV, current);
552 return -EFAULT;
560} 553}
561 554
562/* 555/*
@@ -569,8 +562,8 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
569 struct thread_info *ti = task_thread_info(current); 562 struct thread_info *ti = task_thread_info(current);
570 unsigned int opcode; 563 unsigned int opcode;
571 564
572 if (unlikely(get_insn_opcode(regs, &opcode))) 565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
573 return -EFAULT; 566 goto out_sigsegv;
574 567
575 if (unlikely(compute_return_epc(regs))) 568 if (unlikely(compute_return_epc(regs)))
576 return -EFAULT; 569 return -EFAULT;
@@ -589,6 +582,10 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
589 582
590 /* Not ours. */ 583 /* Not ours. */
591 return -EFAULT; 584 return -EFAULT;
585
586out_sigsegv:
587 force_sig(SIGSEGV, current);
588 return -EFAULT;
592} 589}
593 590
594asmlinkage void do_ov(struct pt_regs *regs) 591asmlinkage void do_ov(struct pt_regs *regs)
@@ -672,10 +669,8 @@ asmlinkage void do_bp(struct pt_regs *regs)
672 unsigned int opcode, bcode; 669 unsigned int opcode, bcode;
673 siginfo_t info; 670 siginfo_t info;
674 671
675 die_if_kernel("Break instruction in kernel code", regs); 672 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
676 673 goto out_sigsegv;
677 if (get_insn_opcode(regs, &opcode))
678 return;
679 674
680 /* 675 /*
681 * There is the ancient bug in the MIPS assemblers that the break 676 * There is the ancient bug in the MIPS assemblers that the break
@@ -696,6 +691,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
696 switch (bcode) { 691 switch (bcode) {
697 case BRK_OVERFLOW << 10: 692 case BRK_OVERFLOW << 10:
698 case BRK_DIVZERO << 10: 693 case BRK_DIVZERO << 10:
694 die_if_kernel("Break instruction in kernel code", regs);
699 if (bcode == (BRK_DIVZERO << 10)) 695 if (bcode == (BRK_DIVZERO << 10))
700 info.si_code = FPE_INTDIV; 696 info.si_code = FPE_INTDIV;
701 else 697 else
@@ -705,9 +701,16 @@ asmlinkage void do_bp(struct pt_regs *regs)
705 info.si_addr = (void __user *) regs->cp0_epc; 701 info.si_addr = (void __user *) regs->cp0_epc;
706 force_sig_info(SIGFPE, &info, current); 702 force_sig_info(SIGFPE, &info, current);
707 break; 703 break;
704 case BRK_BUG:
705 die("Kernel bug detected", regs);
706 break;
708 default: 707 default:
708 die_if_kernel("Break instruction in kernel code", regs);
709 force_sig(SIGTRAP, current); 709 force_sig(SIGTRAP, current);
710 } 710 }
711
712out_sigsegv:
713 force_sig(SIGSEGV, current);
711} 714}
712 715
713asmlinkage void do_tr(struct pt_regs *regs) 716asmlinkage void do_tr(struct pt_regs *regs)
@@ -715,10 +718,8 @@ asmlinkage void do_tr(struct pt_regs *regs)
715 unsigned int opcode, tcode = 0; 718 unsigned int opcode, tcode = 0;
716 siginfo_t info; 719 siginfo_t info;
717 720
718 die_if_kernel("Trap instruction in kernel code", regs); 721 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
719 722 goto out_sigsegv;
720 if (get_insn_opcode(regs, &opcode))
721 return;
722 723
723 /* Immediate versions don't provide a code. */ 724 /* Immediate versions don't provide a code. */
724 if (!(opcode & OPCODE)) 725 if (!(opcode & OPCODE))
@@ -733,6 +734,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
733 switch (tcode) { 734 switch (tcode) {
734 case BRK_OVERFLOW: 735 case BRK_OVERFLOW:
735 case BRK_DIVZERO: 736 case BRK_DIVZERO:
737 die_if_kernel("Trap instruction in kernel code", regs);
736 if (tcode == BRK_DIVZERO) 738 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV; 739 info.si_code = FPE_INTDIV;
738 else 740 else
@@ -742,9 +744,16 @@ asmlinkage void do_tr(struct pt_regs *regs)
742 info.si_addr = (void __user *) regs->cp0_epc; 744 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current); 745 force_sig_info(SIGFPE, &info, current);
744 break; 746 break;
747 case BRK_BUG:
748 die("Kernel bug detected", regs);
749 break;
745 default: 750 default:
751 die_if_kernel("Trap instruction in kernel code", regs);
746 force_sig(SIGTRAP, current); 752 force_sig(SIGTRAP, current);
747 } 753 }
754
755out_sigsegv:
756 force_sig(SIGSEGV, current);
748} 757}
749 758
750asmlinkage void do_ri(struct pt_regs *regs) 759asmlinkage void do_ri(struct pt_regs *regs)
@@ -1423,6 +1432,15 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
1423 memcpy((void *)(uncached_ebase + offset), addr, size); 1432 memcpy((void *)(uncached_ebase + offset), addr, size);
1424} 1433}
1425 1434
1435static int __initdata rdhwr_noopt;
1436static int __init set_rdhwr_noopt(char *str)
1437{
1438 rdhwr_noopt = 1;
1439 return 1;
1440}
1441
1442__setup("rdhwr_noopt", set_rdhwr_noopt);
1443
1426void __init trap_init(void) 1444void __init trap_init(void)
1427{ 1445{
1428 extern char except_vec3_generic, except_vec3_r4000; 1446 extern char except_vec3_generic, except_vec3_r4000;
@@ -1502,7 +1520,9 @@ void __init trap_init(void)
1502 1520
1503 set_except_vector(8, handle_sys); 1521 set_except_vector(8, handle_sys);
1504 set_except_vector(9, handle_bp); 1522 set_except_vector(9, handle_bp);
1505 set_except_vector(10, handle_ri); 1523 set_except_vector(10, rdhwr_noopt ? handle_ri :
1524 (cpu_has_vtag_icache ?
1525 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1506 set_except_vector(11, handle_cpu); 1526 set_except_vector(11, handle_cpu);
1507 set_except_vector(12, handle_ov); 1527 set_except_vector(12, handle_ov);
1508 set_except_vector(13, handle_tr); 1528 set_except_vector(13, handle_tr);
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 79f0317d84ac..cecff24cc972 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -112,6 +112,7 @@ SECTIONS
112 /* .exit.text is discarded at runtime, not link time, to deal with 112 /* .exit.text is discarded at runtime, not link time, to deal with
113 references from .rodata */ 113 references from .rodata */
114 .exit.text : { *(.exit.text) } 114 .exit.text : { *(.exit.text) }
115 .exit.data : { *(.exit.data) }
115 . = ALIGN(_PAGE_SIZE); 116 . = ALIGN(_PAGE_SIZE);
116 __initramfs_start = .; 117 __initramfs_start = .;
117 .init.ramfs : { *(.init.ramfs) } 118 .init.ramfs : { *(.init.ramfs) }
@@ -139,7 +140,6 @@ SECTIONS
139 140
140 /* Sections to be discarded */ 141 /* Sections to be discarded */
141 /DISCARD/ : { 142 /DISCARD/ : {
142 *(.exit.data)
143 *(.exitcall.exit) 143 *(.exitcall.exit)
144 144
145 /* ABI crap starts here */ 145 /* ABI crap starts here */
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 51ddd2166898..666bef484dcb 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1179,7 +1179,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
1179 size_t ret = count; 1179 size_t ret = count;
1180 struct vpe *v; 1180 struct vpe *v;
1181 1181
1182 minor = iminor(file->f_dentry->d_inode); 1182 minor = iminor(file->f_path.dentry->d_inode);
1183 if ((v = get_vpe(minor)) == NULL) 1183 if ((v = get_vpe(minor)) == NULL)
1184 return -ENODEV; 1184 return -ENODEV;
1185 1185
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index a144a002dcc4..2affa5ff171c 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -36,47 +36,20 @@ static volatile int lasat_int_mask_shift;
36 36
37void disable_lasat_irq(unsigned int irq_nr) 37void disable_lasat_irq(unsigned int irq_nr)
38{ 38{
39 unsigned long flags;
40
41 local_irq_save(flags);
42 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; 39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
43 local_irq_restore(flags);
44} 40}
45 41
46void enable_lasat_irq(unsigned int irq_nr) 42void enable_lasat_irq(unsigned int irq_nr)
47{ 43{
48 unsigned long flags;
49
50 local_irq_save(flags);
51 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
52 local_irq_restore(flags);
53}
54
55static unsigned int startup_lasat_irq(unsigned int irq)
56{
57 enable_lasat_irq(irq);
58
59 return 0; /* never anything pending */
60}
61
62#define shutdown_lasat_irq disable_lasat_irq
63
64#define mask_and_ack_lasat_irq disable_lasat_irq
65
66static void end_lasat_irq(unsigned int irq)
67{
68 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
69 enable_lasat_irq(irq);
70} 45}
71 46
72static struct irq_chip lasat_irq_type = { 47static struct irq_chip lasat_irq_type = {
73 .typename = "Lasat", 48 .typename = "Lasat",
74 .startup = startup_lasat_irq, 49 .ack = disable_lasat_irq,
75 .shutdown = shutdown_lasat_irq, 50 .mask = disable_lasat_irq,
76 .enable = enable_lasat_irq, 51 .mask_ack = disable_lasat_irq,
77 .disable = disable_lasat_irq, 52 .unmask = enable_lasat_irq,
78 .ack = mask_and_ack_lasat_irq,
79 .end = end_lasat_irq,
80}; 53};
81 54
82static inline int ls1bit32(unsigned int x) 55static inline int ls1bit32(unsigned int x)
@@ -152,10 +125,6 @@ void __init arch_init_irq(void)
152 panic("arch_init_irq: mips_machtype incorrect"); 125 panic("arch_init_irq: mips_machtype incorrect");
153 } 126 }
154 127
155 for (i = 0; i <= LASATINT_END; i++) { 128 for (i = 0; i <= LASATINT_END; i++)
156 irq_desc[i].status = IRQ_DISABLED; 129 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
157 irq_desc[i].action = 0;
158 irq_desc[i].depth = 1;
159 irq_desc[i].chip = &lasat_irq_type;
160 }
161} 130}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 6dd7ae1b7c25..12878359f2c8 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -40,12 +40,12 @@ static DEFINE_MUTEX(lasat_info_mutex);
40/* Strategy function to write EEPROM after changing string entry */ 40/* Strategy function to write EEPROM after changing string entry */
41int sysctl_lasatstring(ctl_table *table, int *name, int nlen, 41int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
42 void *oldval, size_t *oldlenp, 42 void *oldval, size_t *oldlenp,
43 void *newval, size_t newlen, void **context) 43 void *newval, size_t newlen)
44{ 44{
45 int r; 45 int r;
46 mutex_lock(&lasat_info_mutex); 46 mutex_lock(&lasat_info_mutex);
47 r = sysctl_string(table, name, 47 r = sysctl_string(table, name,
48 nlen, oldval, oldlenp, newval, newlen, context); 48 nlen, oldval, oldlenp, newval, newlen);
49 if (r < 0) { 49 if (r < 0) {
50 mutex_unlock(&lasat_info_mutex); 50 mutex_unlock(&lasat_info_mutex);
51 return r; 51 return r;
@@ -119,11 +119,11 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
119/* Sysctl for setting the IP addresses */ 119/* Sysctl for setting the IP addresses */
120int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen, 120int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen,
121 void *oldval, size_t *oldlenp, 121 void *oldval, size_t *oldlenp,
122 void *newval, size_t newlen, void **context) 122 void *newval, size_t newlen)
123{ 123{
124 int r; 124 int r;
125 mutex_lock(&lasat_info_mutex); 125 mutex_lock(&lasat_info_mutex);
126 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); 126 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
127 if (r < 0) { 127 if (r < 0) {
128 mutex_unlock(&lasat_info_mutex); 128 mutex_unlock(&lasat_info_mutex);
129 return r; 129 return r;
@@ -139,14 +139,14 @@ int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen,
139/* Same for RTC */ 139/* Same for RTC */
140int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, 140int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen,
141 void *oldval, size_t *oldlenp, 141 void *oldval, size_t *oldlenp,
142 void *newval, size_t newlen, void **context) 142 void *newval, size_t newlen)
143{ 143{
144 int r; 144 int r;
145 mutex_lock(&lasat_info_mutex); 145 mutex_lock(&lasat_info_mutex);
146 rtctmp = ds1603_read(); 146 rtctmp = ds1603_read();
147 if (rtctmp < 0) 147 if (rtctmp < 0)
148 rtctmp = 0; 148 rtctmp = 0;
149 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); 149 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
150 if (r < 0) { 150 if (r < 0) {
151 mutex_unlock(&lasat_info_mutex); 151 mutex_unlock(&lasat_info_mutex);
152 return r; 152 return r;
@@ -251,13 +251,12 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
251 251
252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, 252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
253 void *oldval, size_t *oldlenp, 253 void *oldval, size_t *oldlenp,
254 void *newval, size_t newlen, 254 void *newval, size_t newlen)
255 void **context)
256{ 255{
257 int r; 256 int r;
258 257
259 mutex_lock(&lasat_info_mutex); 258 mutex_lock(&lasat_info_mutex);
260 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen, context); 259 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
261 if (r < 0) { 260 if (r < 0) {
262 mutex_unlock(&lasat_info_mutex); 261 mutex_unlock(&lasat_info_mutex);
263 return r; 262 return r;
@@ -286,11 +285,11 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
286 mutex_unlock(&lasat_info_mutex); 285 mutex_unlock(&lasat_info_mutex);
287 return r; 286 return r;
288 } 287 }
289 if (filp && filp->f_dentry) 288 if (filp && filp->f_path.dentry)
290 { 289 {
291 if (!strcmp(filp->f_dentry->d_name.name, "prid")) 290 if (!strcmp(filp->f_path.dentry->d_name.name, "prid"))
292 lasat_board_info.li_eeprom_info.prid = lasat_board_info.li_prid; 291 lasat_board_info.li_eeprom_info.prid = lasat_board_info.li_prid;
293 if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) 292 if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess"))
294 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; 293 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess;
295 } 294 }
296 lasat_write_eeprom_info(); 295 lasat_write_eeprom_info();
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
index ad285786e74b..dcd4d2ed2ac4 100644
--- a/arch/mips/lib-32/Makefile
+++ b/arch/mips/lib-32/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib-32/csum_partial.S b/arch/mips/lib-32/csum_partial.S
deleted file mode 100644
index ea257dbdcc40..000000000000
--- a/arch/mips/lib-32/csum_partial.S
+++ /dev/null
@@ -1,240 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998 Ralf Baechle
7 */
8#include <asm/asm.h>
9#include <asm/regdef.h>
10
11#define ADDC(sum,reg) \
12 addu sum, reg; \
13 sltu v1, sum, reg; \
14 addu sum, v1
15
16#define CSUM_BIGCHUNK(src, offset, sum, t0, t1, t2, t3) \
17 lw t0, (offset + 0x00)(src); \
18 lw t1, (offset + 0x04)(src); \
19 lw t2, (offset + 0x08)(src); \
20 lw t3, (offset + 0x0c)(src); \
21 ADDC(sum, t0); \
22 ADDC(sum, t1); \
23 ADDC(sum, t2); \
24 ADDC(sum, t3); \
25 lw t0, (offset + 0x10)(src); \
26 lw t1, (offset + 0x14)(src); \
27 lw t2, (offset + 0x18)(src); \
28 lw t3, (offset + 0x1c)(src); \
29 ADDC(sum, t0); \
30 ADDC(sum, t1); \
31 ADDC(sum, t2); \
32 ADDC(sum, t3); \
33
34/*
35 * a0: source address
36 * a1: length of the area to checksum
37 * a2: partial checksum
38 */
39
40#define src a0
41#define dest a1
42#define sum v0
43
44 .text
45 .set noreorder
46
47/* unknown src alignment and < 8 bytes to go */
48small_csumcpy:
49 move a1, t2
50
51 andi t0, a1, 4
52 beqz t0, 1f
53 andi t0, a1, 2
54
55 /* Still a full word to go */
56 ulw t1, (src)
57 addiu src, 4
58 ADDC(sum, t1)
59
601: move t1, zero
61 beqz t0, 1f
62 andi t0, a1, 1
63
64 /* Still a halfword to go */
65 ulhu t1, (src)
66 addiu src, 2
67
681: beqz t0, 1f
69 sll t1, t1, 16
70
71 lbu t2, (src)
72 nop
73
74#ifdef __MIPSEB__
75 sll t2, t2, 8
76#endif
77 or t1, t2
78
791: ADDC(sum, t1)
80
81 /* fold checksum */
82 sll v1, sum, 16
83 addu sum, v1
84 sltu v1, sum, v1
85 srl sum, sum, 16
86 addu sum, v1
87
88 /* odd buffer alignment? */
89 beqz t7, 1f
90 nop
91 sll v1, sum, 8
92 srl sum, sum, 8
93 or sum, v1
94 andi sum, 0xffff
951:
96 .set reorder
97 /* Add the passed partial csum. */
98 ADDC(sum, a2)
99 jr ra
100 .set noreorder
101
102/* ------------------------------------------------------------------------- */
103
104 .align 5
105LEAF(csum_partial)
106 move sum, zero
107 move t7, zero
108
109 sltiu t8, a1, 0x8
110 bnez t8, small_csumcpy /* < 8 bytes to copy */
111 move t2, a1
112
113 beqz a1, out
114 andi t7, src, 0x1 /* odd buffer? */
115
116hword_align:
117 beqz t7, word_align
118 andi t8, src, 0x2
119
120 lbu t0, (src)
121 subu a1, a1, 0x1
122#ifdef __MIPSEL__
123 sll t0, t0, 8
124#endif
125 ADDC(sum, t0)
126 addu src, src, 0x1
127 andi t8, src, 0x2
128
129word_align:
130 beqz t8, dword_align
131 sltiu t8, a1, 56
132
133 lhu t0, (src)
134 subu a1, a1, 0x2
135 ADDC(sum, t0)
136 sltiu t8, a1, 56
137 addu src, src, 0x2
138
139dword_align:
140 bnez t8, do_end_words
141 move t8, a1
142
143 andi t8, src, 0x4
144 beqz t8, qword_align
145 andi t8, src, 0x8
146
147 lw t0, 0x00(src)
148 subu a1, a1, 0x4
149 ADDC(sum, t0)
150 addu src, src, 0x4
151 andi t8, src, 0x8
152
153qword_align:
154 beqz t8, oword_align
155 andi t8, src, 0x10
156
157 lw t0, 0x00(src)
158 lw t1, 0x04(src)
159 subu a1, a1, 0x8
160 ADDC(sum, t0)
161 ADDC(sum, t1)
162 addu src, src, 0x8
163 andi t8, src, 0x10
164
165oword_align:
166 beqz t8, begin_movement
167 srl t8, a1, 0x7
168
169 lw t3, 0x08(src)
170 lw t4, 0x0c(src)
171 lw t0, 0x00(src)
172 lw t1, 0x04(src)
173 ADDC(sum, t3)
174 ADDC(sum, t4)
175 ADDC(sum, t0)
176 ADDC(sum, t1)
177 subu a1, a1, 0x10
178 addu src, src, 0x10
179 srl t8, a1, 0x7
180
181begin_movement:
182 beqz t8, 1f
183 andi t2, a1, 0x40
184
185move_128bytes:
186 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
187 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
188 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
189 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
190 subu t8, t8, 0x01
191 bnez t8, move_128bytes
192 addu src, src, 0x80
193
1941:
195 beqz t2, 1f
196 andi t2, a1, 0x20
197
198move_64bytes:
199 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
200 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
201 addu src, src, 0x40
202
2031:
204 beqz t2, do_end_words
205 andi t8, a1, 0x1c
206
207move_32bytes:
208 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
209 andi t8, a1, 0x1c
210 addu src, src, 0x20
211
212do_end_words:
213 beqz t8, maybe_end_cruft
214 srl t8, t8, 0x2
215
216end_words:
217 lw t0, (src)
218 subu t8, t8, 0x1
219 ADDC(sum, t0)
220 bnez t8, end_words
221 addu src, src, 0x4
222
223maybe_end_cruft:
224 andi t2, a1, 0x3
225
226small_memcpy:
227 j small_csumcpy; move a1, t2
228 beqz t2, out
229 move a1, t2
230
231end_bytes:
232 lb t0, (src)
233 subu a1, a1, 0x1
234 bnez a2, end_bytes
235 addu src, src, 0x1
236
237out:
238 jr ra
239 move v0, sum
240 END(csum_partial)
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
index ad285786e74b..dcd4d2ed2ac4 100644
--- a/arch/mips/lib-64/Makefile
+++ b/arch/mips/lib-64/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib-64/csum_partial.S b/arch/mips/lib-64/csum_partial.S
deleted file mode 100644
index 25aba660cc9c..000000000000
--- a/arch/mips/lib-64/csum_partial.S
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Quick'n'dirty IP checksum ...
7 *
8 * Copyright (C) 1998, 1999 Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#include <asm/asm.h>
12#include <asm/regdef.h>
13
14#define ADDC(sum,reg) \
15 addu sum, reg; \
16 sltu v1, sum, reg; \
17 addu sum, v1
18
19#define CSUM_BIGCHUNK(src, offset, sum, t0, t1, t2, t3) \
20 lw t0, (offset + 0x00)(src); \
21 lw t1, (offset + 0x04)(src); \
22 lw t2, (offset + 0x08)(src); \
23 lw t3, (offset + 0x0c)(src); \
24 ADDC(sum, t0); \
25 ADDC(sum, t1); \
26 ADDC(sum, t2); \
27 ADDC(sum, t3); \
28 lw t0, (offset + 0x10)(src); \
29 lw t1, (offset + 0x14)(src); \
30 lw t2, (offset + 0x18)(src); \
31 lw t3, (offset + 0x1c)(src); \
32 ADDC(sum, t0); \
33 ADDC(sum, t1); \
34 ADDC(sum, t2); \
35 ADDC(sum, t3); \
36
37/*
38 * a0: source address
39 * a1: length of the area to checksum
40 * a2: partial checksum
41 */
42
43#define src a0
44#define sum v0
45
46 .text
47 .set noreorder
48
49/* unknown src alignment and < 8 bytes to go */
50small_csumcpy:
51 move a1, ta2
52
53 andi ta0, a1, 4
54 beqz ta0, 1f
55 andi ta0, a1, 2
56
57 /* Still a full word to go */
58 ulw ta1, (src)
59 daddiu src, 4
60 ADDC(sum, ta1)
61
621: move ta1, zero
63 beqz ta0, 1f
64 andi ta0, a1, 1
65
66 /* Still a halfword to go */
67 ulhu ta1, (src)
68 daddiu src, 2
69
701: beqz ta0, 1f
71 sll ta1, ta1, 16
72
73 lbu ta2, (src)
74 nop
75
76#ifdef __MIPSEB__
77 sll ta2, ta2, 8
78#endif
79 or ta1, ta2
80
811: ADDC(sum, ta1)
82
83 /* fold checksum */
84 sll v1, sum, 16
85 addu sum, v1
86 sltu v1, sum, v1
87 srl sum, sum, 16
88 addu sum, v1
89
90 /* odd buffer alignment? */
91 beqz t3, 1f
92 nop
93 sll v1, sum, 8
94 srl sum, sum, 8
95 or sum, v1
96 andi sum, 0xffff
971:
98 .set reorder
99 /* Add the passed partial csum. */
100 ADDC(sum, a2)
101 jr ra
102 .set noreorder
103
104/* ------------------------------------------------------------------------- */
105
106 .align 5
107LEAF(csum_partial)
108 move sum, zero
109 move t3, zero
110
111 sltiu t8, a1, 0x8
112 bnez t8, small_csumcpy /* < 8 bytes to copy */
113 move ta2, a1
114
115 beqz a1, out
116 andi t3, src, 0x1 /* odd buffer? */
117
118hword_align:
119 beqz t3, word_align
120 andi t8, src, 0x2
121
122 lbu ta0, (src)
123 dsubu a1, a1, 0x1
124#ifdef __MIPSEL__
125 sll ta0, ta0, 8
126#endif
127 ADDC(sum, ta0)
128 daddu src, src, 0x1
129 andi t8, src, 0x2
130
131word_align:
132 beqz t8, dword_align
133 sltiu t8, a1, 56
134
135 lhu ta0, (src)
136 dsubu a1, a1, 0x2
137 ADDC(sum, ta0)
138 sltiu t8, a1, 56
139 daddu src, src, 0x2
140
141dword_align:
142 bnez t8, do_end_words
143 move t8, a1
144
145 andi t8, src, 0x4
146 beqz t8, qword_align
147 andi t8, src, 0x8
148
149 lw ta0, 0x00(src)
150 dsubu a1, a1, 0x4
151 ADDC(sum, ta0)
152 daddu src, src, 0x4
153 andi t8, src, 0x8
154
155qword_align:
156 beqz t8, oword_align
157 andi t8, src, 0x10
158
159 lw ta0, 0x00(src)
160 lw ta1, 0x04(src)
161 dsubu a1, a1, 0x8
162 ADDC(sum, ta0)
163 ADDC(sum, ta1)
164 daddu src, src, 0x8
165 andi t8, src, 0x10
166
167oword_align:
168 beqz t8, begin_movement
169 dsrl t8, a1, 0x7
170
171 lw ta3, 0x08(src)
172 lw t0, 0x0c(src)
173 lw ta0, 0x00(src)
174 lw ta1, 0x04(src)
175 ADDC(sum, ta3)
176 ADDC(sum, t0)
177 ADDC(sum, ta0)
178 ADDC(sum, ta1)
179 dsubu a1, a1, 0x10
180 daddu src, src, 0x10
181 dsrl t8, a1, 0x7
182
183begin_movement:
184 beqz t8, 1f
185 andi ta2, a1, 0x40
186
187move_128bytes:
188 CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0)
189 CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0)
190 CSUM_BIGCHUNK(src, 0x40, sum, ta0, ta1, ta3, t0)
191 CSUM_BIGCHUNK(src, 0x60, sum, ta0, ta1, ta3, t0)
192 dsubu t8, t8, 0x01
193 bnez t8, move_128bytes
194 daddu src, src, 0x80
195
1961:
197 beqz ta2, 1f
198 andi ta2, a1, 0x20
199
200move_64bytes:
201 CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0)
202 CSUM_BIGCHUNK(src, 0x20, sum, ta0, ta1, ta3, t0)
203 daddu src, src, 0x40
204
2051:
206 beqz ta2, do_end_words
207 andi t8, a1, 0x1c
208
209move_32bytes:
210 CSUM_BIGCHUNK(src, 0x00, sum, ta0, ta1, ta3, t0)
211 andi t8, a1, 0x1c
212 daddu src, src, 0x20
213
214do_end_words:
215 beqz t8, maybe_end_cruft
216 dsrl t8, t8, 0x2
217
218end_words:
219 lw ta0, (src)
220 dsubu t8, t8, 0x1
221 ADDC(sum, ta0)
222 bnez t8, end_words
223 daddu src, src, 0x4
224
225maybe_end_cruft:
226 andi ta2, a1, 0x3
227
228small_memcpy:
229 j small_csumcpy; move a1, ta2 /* XXX ??? */
230 beqz t2, out
231 move a1, ta2
232
233end_bytes:
234 lb ta0, (src)
235 dsubu a1, a1, 0x1
236 bnez a2, end_bytes
237 daddu src, src, 0x1
238
239out:
240 jr ra
241 move v0, sum
242 END(csum_partial)
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b225543f5302..989c900b8b14 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,8 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial_copy.o memcpy.o promlib.o strlen_user.o strncpy_user.o \ 5lib-y += csum_partial.o memcpy.o promlib.o \
6 strnlen_user.o uncached.o 6 strlen_user.o strncpy_user.o strnlen_user.o uncached.o
7 7
8obj-y += iomap.o 8obj-y += iomap.o
9 9
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
new file mode 100644
index 000000000000..c0a77fe038be
--- /dev/null
+++ b/arch/mips/lib/csum_partial.S
@@ -0,0 +1,715 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Quick'n'dirty IP checksum ...
7 *
8 * Copyright (C) 1998, 1999 Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 */
11#include <linux/errno.h>
12#include <asm/asm.h>
13#include <asm/asm-offsets.h>
14#include <asm/regdef.h>
15
16#ifdef CONFIG_64BIT
17/*
18 * As we are sharing code base with the mips32 tree (which use the o32 ABI
19 * register definitions). We need to redefine the register definitions from
20 * the n64 ABI register naming to the o32 ABI register naming.
21 */
22#undef t0
23#undef t1
24#undef t2
25#undef t3
26#define t0 $8
27#define t1 $9
28#define t2 $10
29#define t3 $11
30#define t4 $12
31#define t5 $13
32#define t6 $14
33#define t7 $15
34
35#define USE_DOUBLE
36#endif
37
38#ifdef USE_DOUBLE
39
40#define LOAD ld
41#define ADD daddu
42#define NBYTES 8
43
44#else
45
46#define LOAD lw
47#define ADD addu
48#define NBYTES 4
49
50#endif /* USE_DOUBLE */
51
52#define UNIT(unit) ((unit)*NBYTES)
53
54#define ADDC(sum,reg) \
55 ADD sum, reg; \
56 sltu v1, sum, reg; \
57 ADD sum, v1
58
59#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
60 LOAD _t0, (offset + UNIT(0))(src); \
61 LOAD _t1, (offset + UNIT(1))(src); \
62 LOAD _t2, (offset + UNIT(2))(src); \
63 LOAD _t3, (offset + UNIT(3))(src); \
64 ADDC(sum, _t0); \
65 ADDC(sum, _t1); \
66 ADDC(sum, _t2); \
67 ADDC(sum, _t3)
68
69#ifdef USE_DOUBLE
70#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \
71 CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)
72#else
73#define CSUM_BIGCHUNK(src, offset, sum, _t0, _t1, _t2, _t3) \
74 CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3); \
75 CSUM_BIGCHUNK1(src, offset + 0x10, sum, _t0, _t1, _t2, _t3)
76#endif
77
78/*
79 * a0: source address
80 * a1: length of the area to checksum
81 * a2: partial checksum
82 */
83
84#define src a0
85#define sum v0
86
87 .text
88 .set noreorder
89 .align 5
90LEAF(csum_partial)
91 move sum, zero
92 move t7, zero
93
94 sltiu t8, a1, 0x8
95 bnez t8, small_csumcpy /* < 8 bytes to copy */
96 move t2, a1
97
98 andi t7, src, 0x1 /* odd buffer? */
99
100hword_align:
101 beqz t7, word_align
102 andi t8, src, 0x2
103
104 lbu t0, (src)
105 LONG_SUBU a1, a1, 0x1
106#ifdef __MIPSEL__
107 sll t0, t0, 8
108#endif
109 ADDC(sum, t0)
110 PTR_ADDU src, src, 0x1
111 andi t8, src, 0x2
112
113word_align:
114 beqz t8, dword_align
115 sltiu t8, a1, 56
116
117 lhu t0, (src)
118 LONG_SUBU a1, a1, 0x2
119 ADDC(sum, t0)
120 sltiu t8, a1, 56
121 PTR_ADDU src, src, 0x2
122
123dword_align:
124 bnez t8, do_end_words
125 move t8, a1
126
127 andi t8, src, 0x4
128 beqz t8, qword_align
129 andi t8, src, 0x8
130
131 lw t0, 0x00(src)
132 LONG_SUBU a1, a1, 0x4
133 ADDC(sum, t0)
134 PTR_ADDU src, src, 0x4
135 andi t8, src, 0x8
136
137qword_align:
138 beqz t8, oword_align
139 andi t8, src, 0x10
140
141#ifdef USE_DOUBLE
142 ld t0, 0x00(src)
143 LONG_SUBU a1, a1, 0x8
144 ADDC(sum, t0)
145#else
146 lw t0, 0x00(src)
147 lw t1, 0x04(src)
148 LONG_SUBU a1, a1, 0x8
149 ADDC(sum, t0)
150 ADDC(sum, t1)
151#endif
152 PTR_ADDU src, src, 0x8
153 andi t8, src, 0x10
154
155oword_align:
156 beqz t8, begin_movement
157 LONG_SRL t8, a1, 0x7
158
159#ifdef USE_DOUBLE
160 ld t0, 0x00(src)
161 ld t1, 0x08(src)
162 ADDC(sum, t0)
163 ADDC(sum, t1)
164#else
165 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
166#endif
167 LONG_SUBU a1, a1, 0x10
168 PTR_ADDU src, src, 0x10
169 LONG_SRL t8, a1, 0x7
170
171begin_movement:
172 beqz t8, 1f
173 andi t2, a1, 0x40
174
175move_128bytes:
176 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
177 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
178 CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4)
179 CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4)
180 LONG_SUBU t8, t8, 0x01
181 bnez t8, move_128bytes
182 PTR_ADDU src, src, 0x80
183
1841:
185 beqz t2, 1f
186 andi t2, a1, 0x20
187
188move_64bytes:
189 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
190 CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4)
191 PTR_ADDU src, src, 0x40
192
1931:
194 beqz t2, do_end_words
195 andi t8, a1, 0x1c
196
197move_32bytes:
198 CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4)
199 andi t8, a1, 0x1c
200 PTR_ADDU src, src, 0x20
201
202do_end_words:
203 beqz t8, small_csumcpy
204 andi t2, a1, 0x3
205 LONG_SRL t8, t8, 0x2
206
207end_words:
208 lw t0, (src)
209 LONG_SUBU t8, t8, 0x1
210 ADDC(sum, t0)
211 bnez t8, end_words
212 PTR_ADDU src, src, 0x4
213
214/* unknown src alignment and < 8 bytes to go */
215small_csumcpy:
216 move a1, t2
217
218 andi t0, a1, 4
219 beqz t0, 1f
220 andi t0, a1, 2
221
222 /* Still a full word to go */
223 ulw t1, (src)
224 PTR_ADDIU src, 4
225 ADDC(sum, t1)
226
2271: move t1, zero
228 beqz t0, 1f
229 andi t0, a1, 1
230
231 /* Still a halfword to go */
232 ulhu t1, (src)
233 PTR_ADDIU src, 2
234
2351: beqz t0, 1f
236 sll t1, t1, 16
237
238 lbu t2, (src)
239 nop
240
241#ifdef __MIPSEB__
242 sll t2, t2, 8
243#endif
244 or t1, t2
245
2461: ADDC(sum, t1)
247
248 /* fold checksum */
249#ifdef USE_DOUBLE
250 dsll32 v1, sum, 0
251 daddu sum, v1
252 sltu v1, sum, v1
253 dsra32 sum, sum, 0
254 addu sum, v1
255#endif
256 sll v1, sum, 16
257 addu sum, v1
258 sltu v1, sum, v1
259 srl sum, sum, 16
260 addu sum, v1
261
262 /* odd buffer alignment? */
263 beqz t7, 1f
264 nop
265 sll v1, sum, 8
266 srl sum, sum, 8
267 or sum, v1
268 andi sum, 0xffff
2691:
270 .set reorder
271 /* Add the passed partial csum. */
272 ADDC(sum, a2)
273 jr ra
274 .set noreorder
275 END(csum_partial)
276
277
278/*
279 * checksum and copy routines based on memcpy.S
280 *
281 * csum_partial_copy_nocheck(src, dst, len, sum)
282 * __csum_partial_copy_user(src, dst, len, sum, errp)
283 *
284 * See "Spec" in memcpy.S for details. Unlike __copy_user, all
285 * function in this file use the standard calling convention.
286 */
287
288#define src a0
289#define dst a1
290#define len a2
291#define psum a3
292#define sum v0
293#define odd t8
294#define errptr t9
295
296/*
297 * The exception handler for loads requires that:
298 * 1- AT contain the address of the byte just past the end of the source
299 * of the copy,
300 * 2- src_entry <= src < AT, and
301 * 3- (dst - src) == (dst_entry - src_entry),
302 * The _entry suffix denotes values when __copy_user was called.
303 *
304 * (1) is set up up by __csum_partial_copy_from_user and maintained by
305 * not writing AT in __csum_partial_copy
306 * (2) is met by incrementing src by the number of bytes copied
307 * (3) is met by not doing loads between a pair of increments of dst and src
308 *
309 * The exception handlers for stores stores -EFAULT to errptr and return.
310 * These handlers do not need to overwrite any data.
311 */
312
313#define EXC(inst_reg,addr,handler) \
3149: inst_reg, addr; \
315 .section __ex_table,"a"; \
316 PTR 9b, handler; \
317 .previous
318
319#ifdef USE_DOUBLE
320
321#define LOAD ld
322#define LOADL ldl
323#define LOADR ldr
324#define STOREL sdl
325#define STORER sdr
326#define STORE sd
327#define ADD daddu
328#define SUB dsubu
329#define SRL dsrl
330#define SLL dsll
331#define SLLV dsllv
332#define SRLV dsrlv
333#define NBYTES 8
334#define LOG_NBYTES 3
335
336#else
337
338#define LOAD lw
339#define LOADL lwl
340#define LOADR lwr
341#define STOREL swl
342#define STORER swr
343#define STORE sw
344#define ADD addu
345#define SUB subu
346#define SRL srl
347#define SLL sll
348#define SLLV sllv
349#define SRLV srlv
350#define NBYTES 4
351#define LOG_NBYTES 2
352
353#endif /* USE_DOUBLE */
354
355#ifdef CONFIG_CPU_LITTLE_ENDIAN
356#define LDFIRST LOADR
357#define LDREST LOADL
358#define STFIRST STORER
359#define STREST STOREL
360#define SHIFT_DISCARD SLLV
361#define SHIFT_DISCARD_REVERT SRLV
362#else
363#define LDFIRST LOADL
364#define LDREST LOADR
365#define STFIRST STOREL
366#define STREST STORER
367#define SHIFT_DISCARD SRLV
368#define SHIFT_DISCARD_REVERT SLLV
369#endif
370
371#define FIRST(unit) ((unit)*NBYTES)
372#define REST(unit) (FIRST(unit)+NBYTES-1)
373
374#define ADDRMASK (NBYTES-1)
375
376 .set noat
377
378LEAF(__csum_partial_copy_user)
379 PTR_ADDU AT, src, len /* See (1) above. */
380#ifdef CONFIG_64BIT
381 move errptr, a4
382#else
383 lw errptr, 16(sp)
384#endif
385FEXPORT(csum_partial_copy_nocheck)
386 move sum, zero
387 move odd, zero
388 /*
389 * Note: dst & src may be unaligned, len may be 0
390 * Temps
391 */
392 /*
393 * The "issue break"s below are very approximate.
394 * Issue delays for dcache fills will perturb the schedule, as will
395 * load queue full replay traps, etc.
396 *
397 * If len < NBYTES use byte operations.
398 */
399 sltu t2, len, NBYTES
400 and t1, dst, ADDRMASK
401 bnez t2, copy_bytes_checklen
402 and t0, src, ADDRMASK
403 andi odd, dst, 0x1 /* odd buffer? */
404 bnez t1, dst_unaligned
405 nop
406 bnez t0, src_unaligned_dst_aligned
407 /*
408 * use delay slot for fall-through
409 * src and dst are aligned; need to compute rem
410 */
411both_aligned:
412 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
413 beqz t0, cleanup_both_aligned # len < 8*NBYTES
414 nop
415 SUB len, 8*NBYTES # subtract here for bgez loop
416 .align 4
4171:
418EXC( LOAD t0, UNIT(0)(src), l_exc)
419EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
420EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
421EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
422EXC( LOAD t4, UNIT(4)(src), l_exc_copy)
423EXC( LOAD t5, UNIT(5)(src), l_exc_copy)
424EXC( LOAD t6, UNIT(6)(src), l_exc_copy)
425EXC( LOAD t7, UNIT(7)(src), l_exc_copy)
426 SUB len, len, 8*NBYTES
427 ADD src, src, 8*NBYTES
428EXC( STORE t0, UNIT(0)(dst), s_exc)
429 ADDC(sum, t0)
430EXC( STORE t1, UNIT(1)(dst), s_exc)
431 ADDC(sum, t1)
432EXC( STORE t2, UNIT(2)(dst), s_exc)
433 ADDC(sum, t2)
434EXC( STORE t3, UNIT(3)(dst), s_exc)
435 ADDC(sum, t3)
436EXC( STORE t4, UNIT(4)(dst), s_exc)
437 ADDC(sum, t4)
438EXC( STORE t5, UNIT(5)(dst), s_exc)
439 ADDC(sum, t5)
440EXC( STORE t6, UNIT(6)(dst), s_exc)
441 ADDC(sum, t6)
442EXC( STORE t7, UNIT(7)(dst), s_exc)
443 ADDC(sum, t7)
444 bgez len, 1b
445 ADD dst, dst, 8*NBYTES
446 ADD len, 8*NBYTES # revert len (see above)
447
448 /*
449 * len == the number of bytes left to copy < 8*NBYTES
450 */
451cleanup_both_aligned:
452#define rem t7
453 beqz len, done
454 sltu t0, len, 4*NBYTES
455 bnez t0, less_than_4units
456 and rem, len, (NBYTES-1) # rem = len % NBYTES
457 /*
458 * len >= 4*NBYTES
459 */
460EXC( LOAD t0, UNIT(0)(src), l_exc)
461EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
462EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
463EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
464 SUB len, len, 4*NBYTES
465 ADD src, src, 4*NBYTES
466EXC( STORE t0, UNIT(0)(dst), s_exc)
467 ADDC(sum, t0)
468EXC( STORE t1, UNIT(1)(dst), s_exc)
469 ADDC(sum, t1)
470EXC( STORE t2, UNIT(2)(dst), s_exc)
471 ADDC(sum, t2)
472EXC( STORE t3, UNIT(3)(dst), s_exc)
473 ADDC(sum, t3)
474 beqz len, done
475 ADD dst, dst, 4*NBYTES
476less_than_4units:
477 /*
478 * rem = len % NBYTES
479 */
480 beq rem, len, copy_bytes
481 nop
4821:
483EXC( LOAD t0, 0(src), l_exc)
484 ADD src, src, NBYTES
485 SUB len, len, NBYTES
486EXC( STORE t0, 0(dst), s_exc)
487 ADDC(sum, t0)
488 bne rem, len, 1b
489 ADD dst, dst, NBYTES
490
491 /*
492 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
493 * A loop would do only a byte at a time with possible branch
494 * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE
495 * because can't assume read-access to dst. Instead, use
496 * STREST dst, which doesn't require read access to dst.
497 *
498 * This code should perform better than a simple loop on modern,
499 * wide-issue mips processors because the code has fewer branches and
500 * more instruction-level parallelism.
501 */
502#define bits t2
503 beqz len, done
504 ADD t1, dst, len # t1 is just past last byte of dst
505 li bits, 8*NBYTES
506 SLL rem, len, 3 # rem = number of bits to keep
507EXC( LOAD t0, 0(src), l_exc)
508 SUB bits, bits, rem # bits = number of bits to discard
509 SHIFT_DISCARD t0, t0, bits
510EXC( STREST t0, -1(t1), s_exc)
511 SHIFT_DISCARD_REVERT t0, t0, bits
512 .set reorder
513 ADDC(sum, t0)
514 b done
515 .set noreorder
516dst_unaligned:
517 /*
518 * dst is unaligned
519 * t0 = src & ADDRMASK
520 * t1 = dst & ADDRMASK; T1 > 0
521 * len >= NBYTES
522 *
523 * Copy enough bytes to align dst
524 * Set match = (src and dst have same alignment)
525 */
526#define match rem
527EXC( LDFIRST t3, FIRST(0)(src), l_exc)
528 ADD t2, zero, NBYTES
529EXC( LDREST t3, REST(0)(src), l_exc_copy)
530 SUB t2, t2, t1 # t2 = number of bytes copied
531 xor match, t0, t1
532EXC( STFIRST t3, FIRST(0)(dst), s_exc)
533 SLL t4, t1, 3 # t4 = number of bits to discard
534 SHIFT_DISCARD t3, t3, t4
535 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */
536 ADDC(sum, t3)
537 beq len, t2, done
538 SUB len, len, t2
539 ADD dst, dst, t2
540 beqz match, both_aligned
541 ADD src, src, t2
542
543src_unaligned_dst_aligned:
544 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
545 beqz t0, cleanup_src_unaligned
546 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
5471:
548/*
549 * Avoid consecutive LD*'s to the same register since some mips
550 * implementations can't issue them in the same cycle.
551 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
552 * are to the same unit (unless src is aligned, but it's not).
553 */
554EXC( LDFIRST t0, FIRST(0)(src), l_exc)
555EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
556 SUB len, len, 4*NBYTES
557EXC( LDREST t0, REST(0)(src), l_exc_copy)
558EXC( LDREST t1, REST(1)(src), l_exc_copy)
559EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
560EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
561EXC( LDREST t2, REST(2)(src), l_exc_copy)
562EXC( LDREST t3, REST(3)(src), l_exc_copy)
563 ADD src, src, 4*NBYTES
564#ifdef CONFIG_CPU_SB1
565 nop # improves slotting
566#endif
567EXC( STORE t0, UNIT(0)(dst), s_exc)
568 ADDC(sum, t0)
569EXC( STORE t1, UNIT(1)(dst), s_exc)
570 ADDC(sum, t1)
571EXC( STORE t2, UNIT(2)(dst), s_exc)
572 ADDC(sum, t2)
573EXC( STORE t3, UNIT(3)(dst), s_exc)
574 ADDC(sum, t3)
575 bne len, rem, 1b
576 ADD dst, dst, 4*NBYTES
577
578cleanup_src_unaligned:
579 beqz len, done
580 and rem, len, NBYTES-1 # rem = len % NBYTES
581 beq rem, len, copy_bytes
582 nop
5831:
584EXC( LDFIRST t0, FIRST(0)(src), l_exc)
585EXC( LDREST t0, REST(0)(src), l_exc_copy)
586 ADD src, src, NBYTES
587 SUB len, len, NBYTES
588EXC( STORE t0, 0(dst), s_exc)
589 ADDC(sum, t0)
590 bne len, rem, 1b
591 ADD dst, dst, NBYTES
592
593copy_bytes_checklen:
594 beqz len, done
595 nop
596copy_bytes:
597 /* 0 < len < NBYTES */
598#ifdef CONFIG_CPU_LITTLE_ENDIAN
599#define SHIFT_START 0
600#define SHIFT_INC 8
601#else
602#define SHIFT_START 8*(NBYTES-1)
603#define SHIFT_INC -8
604#endif
605 move t2, zero # partial word
606 li t3, SHIFT_START # shift
607/* use l_exc_copy here to return correct sum on fault */
608#define COPY_BYTE(N) \
609EXC( lbu t0, N(src), l_exc_copy); \
610 SUB len, len, 1; \
611EXC( sb t0, N(dst), s_exc); \
612 SLLV t0, t0, t3; \
613 addu t3, SHIFT_INC; \
614 beqz len, copy_bytes_done; \
615 or t2, t0
616
617 COPY_BYTE(0)
618 COPY_BYTE(1)
619#ifdef USE_DOUBLE
620 COPY_BYTE(2)
621 COPY_BYTE(3)
622 COPY_BYTE(4)
623 COPY_BYTE(5)
624#endif
625EXC( lbu t0, NBYTES-2(src), l_exc_copy)
626 SUB len, len, 1
627EXC( sb t0, NBYTES-2(dst), s_exc)
628 SLLV t0, t0, t3
629 or t2, t0
630copy_bytes_done:
631 ADDC(sum, t2)
632done:
633 /* fold checksum */
634#ifdef USE_DOUBLE
635 dsll32 v1, sum, 0
636 daddu sum, v1
637 sltu v1, sum, v1
638 dsra32 sum, sum, 0
639 addu sum, v1
640#endif
641 sll v1, sum, 16
642 addu sum, v1
643 sltu v1, sum, v1
644 srl sum, sum, 16
645 addu sum, v1
646
647 /* odd buffer alignment? */
648 beqz odd, 1f
649 nop
650 sll v1, sum, 8
651 srl sum, sum, 8
652 or sum, v1
653 andi sum, 0xffff
6541:
655 .set reorder
656 ADDC(sum, psum)
657 jr ra
658 .set noreorder
659
660l_exc_copy:
661 /*
662 * Copy bytes from src until faulting load address (or until a
663 * lb faults)
664 *
665 * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
666 * may be more than a byte beyond the last address.
667 * Hence, the lb below may get an exception.
668 *
669 * Assumes src < THREAD_BUADDR($28)
670 */
671 LOAD t0, TI_TASK($28)
672 li t2, SHIFT_START
673 LOAD t0, THREAD_BUADDR(t0)
6741:
675EXC( lbu t1, 0(src), l_exc)
676 ADD src, src, 1
677 sb t1, 0(dst) # can't fault -- we're copy_from_user
678 SLLV t1, t1, t2
679 addu t2, SHIFT_INC
680 ADDC(sum, t1)
681 bne src, t0, 1b
682 ADD dst, dst, 1
683l_exc:
684 LOAD t0, TI_TASK($28)
685 nop
686 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
687 nop
688 SUB len, AT, t0 # len number of uncopied bytes
689 /*
690 * Here's where we rely on src and dst being incremented in tandem,
691 * See (3) above.
692 * dst += (fault addr - src) to put dst at first byte to clear
693 */
694 ADD dst, t0 # compute start address in a1
695 SUB dst, src
696 /*
697 * Clear len bytes starting at dst. Can't call __bzero because it
698 * might modify len. An inefficient loop for these rare times...
699 */
700 beqz len, done
701 SUB src, len, 1
7021: sb zero, 0(dst)
703 ADD dst, dst, 1
704 bnez src, 1b
705 SUB src, src, 1
706 li v1, -EFAULT
707 b done
708 sw v1, (errptr)
709
710s_exc:
711 li v0, -1 /* invalid checksum */
712 li v1, -EFAULT
713 jr ra
714 sw v1, (errptr)
715 END(__csum_partial_copy_user)
diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c
deleted file mode 100644
index 6e9f366f961d..000000000000
--- a/arch/mips/lib/csum_partial_copy.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics GmbH
7 * Copyright (C) 1998, 1999 Ralf Baechle
8 */
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <asm/byteorder.h>
12#include <asm/string.h>
13#include <asm/uaccess.h>
14#include <net/checksum.h>
15
16/*
17 * copy while checksumming, otherwise like csum_partial
18 */
19unsigned int csum_partial_copy_nocheck(const unsigned char *src,
20 unsigned char *dst, int len, unsigned int sum)
21{
22 /*
23 * It's 2:30 am and I don't feel like doing it real ...
24 * This is lots slower than the real thing (tm)
25 */
26 sum = csum_partial(src, len, sum);
27 memcpy(dst, src, len);
28
29 return sum;
30}
31
32/*
33 * Copy from userspace and compute checksum. If we catch an exception
34 * then zero the rest of the buffer.
35 */
36unsigned int csum_partial_copy_from_user (const unsigned char __user *src,
37 unsigned char *dst, int len, unsigned int sum, int *err_ptr)
38{
39 int missing;
40
41 might_sleep();
42 missing = copy_from_user(dst, src, len);
43 if (missing) {
44 memset(dst + len - missing, 0, missing);
45 *err_ptr = -EFAULT;
46 }
47
48 return csum_partial(dst, len, sum);
49}
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index be624b8c3b0e..43dba6ce6603 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr)
62 iob(); 62 iob();
63} 63}
64 64
65static unsigned int startup_atlas_irq(unsigned int irq)
66{
67 enable_atlas_irq(irq);
68 return 0; /* never anything pending */
69}
70
71#define shutdown_atlas_irq disable_atlas_irq
72
73#define mask_and_ack_atlas_irq disable_atlas_irq
74
75static void end_atlas_irq(unsigned int irq) 65static void end_atlas_irq(unsigned int irq)
76{ 66{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -80,11 +70,11 @@ static void end_atlas_irq(unsigned int irq)
80 70
81static struct irq_chip atlas_irq_type = { 71static struct irq_chip atlas_irq_type = {
82 .typename = "Atlas", 72 .typename = "Atlas",
83 .startup = startup_atlas_irq, 73 .ack = disable_atlas_irq,
84 .shutdown = shutdown_atlas_irq, 74 .mask = disable_atlas_irq,
85 .enable = enable_atlas_irq, 75 .mask_ack = disable_atlas_irq,
86 .disable = disable_atlas_irq, 76 .unmask = enable_atlas_irq,
87 .ack = mask_and_ack_atlas_irq, 77 .eoi = enable_atlas_irq,
88 .end = end_atlas_irq, 78 .end = end_atlas_irq,
89}; 79};
90 80
@@ -217,13 +207,8 @@ static inline void init_atlas_irqs (int base)
217 */ 207 */
218 atlas_hw0_icregs->intrsten = 0xffffffff; 208 atlas_hw0_icregs->intrsten = 0xffffffff;
219 209
220 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) { 210 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
221 irq_desc[i].status = IRQ_DISABLED; 211 set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
222 irq_desc[i].action = 0;
223 irq_desc[i].depth = 1;
224 irq_desc[i].chip = &atlas_irq_type;
225 spin_lock_init(&irq_desc[i].lock);
226 }
227} 212}
228 213
229static struct irqaction atlasirq = { 214static struct irqaction atlasirq = {
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d817c60c5ca5..a3c3a1d462b2 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -47,6 +47,9 @@
47#ifdef CONFIG_MIPS_MALTA 47#ifdef CONFIG_MIPS_MALTA
48#include <asm/mips-boards/maltaint.h> 48#include <asm/mips-boards/maltaint.h>
49#endif 49#endif
50#ifdef CONFIG_MIPS_SEAD
51#include <asm/mips-boards/seadint.h>
52#endif
50 53
51unsigned long cpu_khz; 54unsigned long cpu_khz;
52 55
@@ -263,11 +266,13 @@ void __init mips_time_init(void)
263 266
264void __init plat_timer_setup(struct irqaction *irq) 267void __init plat_timer_setup(struct irqaction *irq)
265{ 268{
269#ifdef MSC01E_INT_BASE
266 if (cpu_has_veic) { 270 if (cpu_has_veic) {
267 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); 271 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
268 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 272 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
269 } 273 } else
270 else { 274#endif
275 {
271 if (cpu_has_vint) 276 if (cpu_has_vint)
272 set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch); 277 set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
273 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR; 278 mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
@@ -288,6 +293,7 @@ void __init plat_timer_setup(struct irqaction *irq)
288 The effect is that the int remains disabled on the second cpu. 293 The effect is that the int remains disabled on the second cpu.
289 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 294 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
290 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 295 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
296 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
291#endif 297#endif
292 298
293 /* to generate the first timer interrupt */ 299 /* to generate the first timer interrupt */
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
index 77ee5c6d33c1..b662c75fb28e 100644
--- a/arch/mips/mips-boards/malta/Makefile
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -19,5 +19,5 @@
19# under Linux. 19# under Linux.
20# 20#
21 21
22obj-y := malta_int.o malta_setup.o 22obj-y := malta_int.o malta_mtd.o malta_setup.o
23obj-$(CONFIG_SMP) += malta_smp.o 23obj-$(CONFIG_SMP) += malta_smp.o
diff --git a/arch/mips/mips-boards/malta/malta_mtd.c b/arch/mips/mips-boards/malta/malta_mtd.c
new file mode 100644
index 000000000000..8ad9bdf25dce
--- /dev/null
+++ b/arch/mips/mips-boards/malta/malta_mtd.c
@@ -0,0 +1,63 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 MIPS Technologies, Inc.
7 * written by Ralf Baechle <ralf@linux-mips.org>
8 */
9
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <mtd/mtd-abi.h>
15
16static struct mtd_partition malta_mtd_partitions[] = {
17 {
18 .name = "YAMON",
19 .offset = 0x0,
20 .size = 0x100000,
21 .mask_flags = MTD_WRITEABLE
22 }, {
23 .name = "User FS",
24 .offset = 0x100000,
25 .size = 0x2e0000
26 }, {
27 .name = "Board Config",
28 .offset = 0x3e0000,
29 .size = 0x020000,
30 .mask_flags = MTD_WRITEABLE
31 }
32};
33
34static struct physmap_flash_data malta_flash_data = {
35 .width = 4,
36 .nr_parts = ARRAY_SIZE(malta_mtd_partitions),
37 .parts = malta_mtd_partitions
38};
39
40static struct resource malta_flash_resource = {
41 .start = 0x1e000000,
42 .end = 0x1e3fffff,
43 .flags = IORESOURCE_MEM
44};
45
46static struct platform_device malta_flash = {
47 .name = "physmap-flash",
48 .id = 0,
49 .dev = {
50 .platform_data = &malta_flash_data,
51 },
52 .num_resources = 1,
53 .resource = &malta_flash_resource,
54};
55
56static int __init malta_mtd_init(void)
57{
58 platform_device_register(&malta_flash);
59
60 return 0;
61}
62
63module_init(malta_mtd_init)
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 282f3e52eea3..56ea76679cd4 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -21,13 +21,6 @@
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <linux/screen_info.h> 22#include <linux/screen_info.h>
23 23
24#ifdef CONFIG_MTD
25#include <linux/mtd/partitions.h>
26#include <linux/mtd/physmap.h>
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/map.h>
29#endif
30
31#include <asm/cpu.h> 24#include <asm/cpu.h>
32#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
33#include <asm/irq.h> 26#include <asm/irq.h>
@@ -58,30 +51,6 @@ struct resource standard_io_resources[] = {
58 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, 51 { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
59}; 52};
60 53
61#ifdef CONFIG_MTD
62static struct mtd_partition malta_mtd_partitions[] = {
63 {
64 .name = "YAMON",
65 .offset = 0x0,
66 .size = 0x100000,
67 .mask_flags = MTD_WRITEABLE
68 },
69 {
70 .name = "User FS",
71 .offset = 0x100000,
72 .size = 0x2e0000
73 },
74 {
75 .name = "Board Config",
76 .offset = 0x3e0000,
77 .size = 0x020000,
78 .mask_flags = MTD_WRITEABLE
79 }
80};
81
82#define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
83#endif
84
85const char *get_system_type(void) 54const char *get_system_type(void)
86{ 55{
87 return "MIPS Malta"; 56 return "MIPS Malta";
@@ -211,14 +180,6 @@ void __init plat_mem_setup(void)
211#endif 180#endif
212#endif 181#endif
213 182
214#ifdef CONFIG_MTD
215 /*
216 * Support for MTD on Malta. Use the generic physmap driver
217 */
218 physmap_configure(0x1e000000, 0x400000, 4, NULL);
219 physmap_set_partitions(malta_mtd_partitions, number_partitions);
220#endif
221
222 mips_reboot_setup(); 183 mips_reboot_setup();
223 184
224 board_time_init = mips_time_init; 185 board_time_init = mips_time_init;
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index f445fcddfdfd..874ccb0066b8 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -21,7 +21,7 @@
21 * Sead board. 21 * Sead board.
22 */ 22 */
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/irq.h> 24#include <linux/interrupt.h>
25 25
26#include <asm/irq_cpu.h> 26#include <asm/irq_cpu.h>
27#include <asm/mipsregs.h> 27#include <asm/mipsregs.h>
@@ -108,7 +108,7 @@ asmlinkage void plat_irq_dispatch(void)
108 if (irq >= 0) 108 if (irq >= 0)
109 do_IRQ(MIPSCPU_INT_BASE + irq); 109 do_IRQ(MIPSCPU_INT_BASE + irq);
110 else 110 else
111 spurious_interrupt(regs); 111 spurious_interrupt();
112} 112}
113 113
114void __init arch_init_irq(void) 114void __init arch_init_irq(void)
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 24a4ed00cc0a..30711d016fed 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -3,31 +3,24 @@
3#include <linux/kernel_stat.h> 3#include <linux/kernel_stat.h>
4#include <linux/sched.h> 4#include <linux/sched.h>
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6
7#include <asm/mipsregs.h>
8#include <asm/ptrace.h>
9#include <asm/hardirq.h>
10#include <asm/div64.h>
11#include <asm/cpu.h>
12#include <asm/time.h>
13
14#include <linux/interrupt.h> 6#include <linux/interrupt.h>
15#include <linux/mc146818rtc.h> 7#include <linux/mc146818rtc.h>
16#include <linux/timex.h> 8#include <linux/timex.h>
9
17#include <asm/mipsregs.h> 10#include <asm/mipsregs.h>
11#include <asm/ptrace.h>
18#include <asm/hardirq.h> 12#include <asm/hardirq.h>
19#include <asm/irq.h>
20#include <asm/div64.h> 13#include <asm/div64.h>
21#include <asm/cpu.h> 14#include <asm/cpu.h>
22#include <asm/time.h> 15#include <asm/time.h>
16#include <asm/irq.h>
23#include <asm/mc146818-time.h> 17#include <asm/mc146818-time.h>
24#include <asm/msc01_ic.h> 18#include <asm/msc01_ic.h>
19#include <asm/smp.h>
25 20
26#include <asm/mips-boards/generic.h> 21#include <asm/mips-boards/generic.h>
27#include <asm/mips-boards/prom.h> 22#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/simint.h> 23#include <asm/mips-boards/simint.h>
29#include <asm/mc146818-time.h>
30#include <asm/smp.h>
31 24
32 25
33unsigned long cpu_khz; 26unsigned long cpu_khz;
@@ -203,7 +196,8 @@ void __init plat_timer_setup(struct irqaction *irq)
203 on seperate cpu's the first one tries to handle the second interrupt. 196 on seperate cpu's the first one tries to handle the second interrupt.
204 The effect is that the int remains disabled on the second cpu. 197 The effect is that the int remains disabled on the second cpu.
205 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 198 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
206 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
207#endif 201#endif
208 202
209 /* to generate the first timer interrupt */ 203 /* to generate the first timer interrupt */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cc895dad71d2..df04a315d830 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -323,7 +323,6 @@ static void __init r4k_blast_scache_setup(void)
323static inline void local_r4k_flush_cache_all(void * args) 323static inline void local_r4k_flush_cache_all(void * args)
324{ 324{
325 r4k_blast_dcache(); 325 r4k_blast_dcache();
326 r4k_blast_icache();
327} 326}
328 327
329static void r4k_flush_cache_all(void) 328static void r4k_flush_cache_all(void)
@@ -359,21 +358,19 @@ static void r4k___flush_cache_all(void)
359static inline void local_r4k_flush_cache_range(void * args) 358static inline void local_r4k_flush_cache_range(void * args)
360{ 359{
361 struct vm_area_struct *vma = args; 360 struct vm_area_struct *vma = args;
362 int exec;
363 361
364 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) 362 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
365 return; 363 return;
366 364
367 exec = vma->vm_flags & VM_EXEC; 365 r4k_blast_dcache();
368 if (cpu_has_dc_aliases || exec)
369 r4k_blast_dcache();
370 if (exec)
371 r4k_blast_icache();
372} 366}
373 367
374static void r4k_flush_cache_range(struct vm_area_struct *vma, 368static void r4k_flush_cache_range(struct vm_area_struct *vma,
375 unsigned long start, unsigned long end) 369 unsigned long start, unsigned long end)
376{ 370{
371 if (!cpu_has_dc_aliases)
372 return;
373
377 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 374 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
378} 375}
379 376
@@ -384,18 +381,21 @@ static inline void local_r4k_flush_cache_mm(void * args)
384 if (!cpu_context(smp_processor_id(), mm)) 381 if (!cpu_context(smp_processor_id(), mm))
385 return; 382 return;
386 383
387 r4k_blast_dcache();
388 r4k_blast_icache();
389
390 /* 384 /*
391 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 385 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
392 * only flush the primary caches but R10000 and R12000 behave sane ... 386 * only flush the primary caches but R10000 and R12000 behave sane ...
387 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
388 * caches, so we can bail out early.
393 */ 389 */
394 if (current_cpu_data.cputype == CPU_R4000SC || 390 if (current_cpu_data.cputype == CPU_R4000SC ||
395 current_cpu_data.cputype == CPU_R4000MC || 391 current_cpu_data.cputype == CPU_R4000MC ||
396 current_cpu_data.cputype == CPU_R4400SC || 392 current_cpu_data.cputype == CPU_R4400SC ||
397 current_cpu_data.cputype == CPU_R4400MC) 393 current_cpu_data.cputype == CPU_R4400MC) {
398 r4k_blast_scache(); 394 r4k_blast_scache();
395 return;
396 }
397
398 r4k_blast_dcache();
399} 399}
400 400
401static void r4k_flush_cache_mm(struct mm_struct *mm) 401static void r4k_flush_cache_mm(struct mm_struct *mm)
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index caf807ded514..1f954a238a63 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -32,6 +32,7 @@ void (*local_flush_data_cache_page)(void * addr);
32void (*flush_data_cache_page)(unsigned long addr); 32void (*flush_data_cache_page)(unsigned long addr);
33void (*flush_icache_all)(void); 33void (*flush_icache_all)(void);
34 34
35EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
35EXPORT_SYMBOL(flush_data_cache_page); 36EXPORT_SYMBOL(flush_data_cache_page);
36 37
37#ifdef CONFIG_DMA_NONCOHERENT 38#ifdef CONFIG_DMA_NONCOHERENT
diff --git a/arch/mips/mm/dma-coherent.c b/arch/mips/mm/dma-coherent.c
index 7fa5fd16e46b..5697c6e250a3 100644
--- a/arch/mips/mm/dma-coherent.c
+++ b/arch/mips/mm/dma-coherent.c
@@ -190,14 +190,14 @@ int dma_supported(struct device *dev, u64 mask)
190 190
191EXPORT_SYMBOL(dma_supported); 191EXPORT_SYMBOL(dma_supported);
192 192
193int dma_is_consistent(dma_addr_t dma_addr) 193int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
194{ 194{
195 return 1; 195 return 1;
196} 196}
197 197
198EXPORT_SYMBOL(dma_is_consistent); 198EXPORT_SYMBOL(dma_is_consistent);
199 199
200void dma_cache_sync(void *vaddr, size_t size, 200void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
201 enum dma_data_direction direction) 201 enum dma_data_direction direction)
202{ 202{
203 BUG_ON(direction == DMA_NONE); 203 BUG_ON(direction == DMA_NONE);
diff --git a/arch/mips/mm/dma-ip27.c b/arch/mips/mm/dma-ip27.c
index 8da19fd22ac6..f088344db465 100644
--- a/arch/mips/mm/dma-ip27.c
+++ b/arch/mips/mm/dma-ip27.c
@@ -197,14 +197,14 @@ int dma_supported(struct device *dev, u64 mask)
197 197
198EXPORT_SYMBOL(dma_supported); 198EXPORT_SYMBOL(dma_supported);
199 199
200int dma_is_consistent(dma_addr_t dma_addr) 200int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
201{ 201{
202 return 1; 202 return 1;
203} 203}
204 204
205EXPORT_SYMBOL(dma_is_consistent); 205EXPORT_SYMBOL(dma_is_consistent);
206 206
207void dma_cache_sync(void *vaddr, size_t size, 207void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
208 enum dma_data_direction direction) 208 enum dma_data_direction direction)
209{ 209{
210 BUG_ON(direction == DMA_NONE); 210 BUG_ON(direction == DMA_NONE);
diff --git a/arch/mips/mm/dma-ip32.c b/arch/mips/mm/dma-ip32.c
index ec54ed0d26ff..b42b6f7456e6 100644
--- a/arch/mips/mm/dma-ip32.c
+++ b/arch/mips/mm/dma-ip32.c
@@ -363,14 +363,15 @@ int dma_supported(struct device *dev, u64 mask)
363 363
364EXPORT_SYMBOL(dma_supported); 364EXPORT_SYMBOL(dma_supported);
365 365
366int dma_is_consistent(dma_addr_t dma_addr) 366int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
367{ 367{
368 return 1; 368 return 1;
369} 369}
370 370
371EXPORT_SYMBOL(dma_is_consistent); 371EXPORT_SYMBOL(dma_is_consistent);
372 372
373void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) 373void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
374 enum dma_data_direction direction)
374{ 375{
375 if (direction == DMA_NONE) 376 if (direction == DMA_NONE)
376 return; 377 return;
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 2eeffe5c2a3a..8cecef0957c3 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -299,14 +299,15 @@ int dma_supported(struct device *dev, u64 mask)
299 299
300EXPORT_SYMBOL(dma_supported); 300EXPORT_SYMBOL(dma_supported);
301 301
302int dma_is_consistent(dma_addr_t dma_addr) 302int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
303{ 303{
304 return 1; 304 return 1;
305} 305}
306 306
307EXPORT_SYMBOL(dma_is_consistent); 307EXPORT_SYMBOL(dma_is_consistent);
308 308
309void dma_cache_sync(void *vaddr, size_t size, enum dma_data_direction direction) 309void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
310 enum dma_data_direction direction)
310{ 311{
311 if (direction == DMA_NONE) 312 if (direction == DMA_NONE)
312 return; 313 return;
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 8423d8590779..6f90e7ef66ac 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -60,6 +60,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
60 */ 60 */
61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) 61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
62 goto vmalloc_fault; 62 goto vmalloc_fault;
63#ifdef MODULE_START
64 if (unlikely(address >= MODULE_START && address < MODULE_END))
65 goto vmalloc_fault;
66#endif
63 67
64 /* 68 /*
65 * If we're in an interrupt or have no user 69 * If we're in an interrupt or have no user
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 99ebf3ccc222..675502ada5a2 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -39,7 +39,7 @@ void *__kmap_atomic(struct page *page, enum km_type type)
39 unsigned long vaddr; 39 unsigned long vaddr;
40 40
41 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */ 41 /* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
42 inc_preempt_count(); 42 pagefault_disable();
43 if (!PageHighMem(page)) 43 if (!PageHighMem(page))
44 return page_address(page); 44 return page_address(page);
45 45
@@ -62,8 +62,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
62 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id(); 62 enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
63 63
64 if (vaddr < FIXADDR_START) { // FIXME 64 if (vaddr < FIXADDR_START) { // FIXME
65 dec_preempt_count(); 65 pagefault_enable();
66 preempt_check_resched();
67 return; 66 return;
68 } 67 }
69 68
@@ -78,8 +77,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
78 local_flush_tlb_one(vaddr); 77 local_flush_tlb_one(vaddr);
79#endif 78#endif
80 79
81 dec_preempt_count(); 80 pagefault_enable();
82 preempt_check_resched();
83} 81}
84 82
85#ifndef CONFIG_LIMITED_DMA 83#ifndef CONFIG_LIMITED_DMA
@@ -92,7 +90,7 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
92 enum fixed_addresses idx; 90 enum fixed_addresses idx;
93 unsigned long vaddr; 91 unsigned long vaddr;
94 92
95 inc_preempt_count(); 93 pagefault_disable();
96 94
97 idx = type + KM_TYPE_NR*smp_processor_id(); 95 idx = type + KM_TYPE_NR*smp_processor_id();
98 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 96 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 2de4d3c367a2..30245c09d025 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -90,9 +90,9 @@ unsigned long setup_zero_pages(void)
90 if (!empty_zero_page) 90 if (!empty_zero_page)
91 panic("Oh boy, that early out of memory?"); 91 panic("Oh boy, that early out of memory?");
92 92
93 page = virt_to_page(empty_zero_page); 93 page = virt_to_page((void *)empty_zero_page);
94 split_page(page, order); 94 split_page(page, order);
95 while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) { 95 while (page < virt_to_page((void *)(empty_zero_page + (PAGE_SIZE << order)))) {
96 SetPageReserved(page); 96 SetPageReserved(page);
97 page++; 97 page++;
98 } 98 }
@@ -203,6 +203,31 @@ static inline void kunmap_coherent(struct page *page)
203 preempt_check_resched(); 203 preempt_check_resched();
204} 204}
205 205
206void copy_user_highpage(struct page *to, struct page *from,
207 unsigned long vaddr, struct vm_area_struct *vma)
208{
209 void *vfrom, *vto;
210
211 vto = kmap_atomic(to, KM_USER1);
212 if (cpu_has_dc_aliases) {
213 vfrom = kmap_coherent(from, vaddr);
214 copy_page(vto, vfrom);
215 kunmap_coherent(from);
216 } else {
217 vfrom = kmap_atomic(from, KM_USER0);
218 copy_page(vto, vfrom);
219 kunmap_atomic(vfrom, KM_USER0);
220 }
221 if (((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc) ||
222 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
223 flush_data_cache_page((unsigned long)vto);
224 kunmap_atomic(vto, KM_USER1);
225 /* Make sure this page is cleared on other CPU's too before using it */
226 smp_wmb();
227}
228
229EXPORT_SYMBOL(copy_user_highpage);
230
206void copy_to_user_page(struct vm_area_struct *vma, 231void copy_to_user_page(struct vm_area_struct *vma,
207 struct page *page, unsigned long vaddr, void *dst, const void *src, 232 struct page *page, unsigned long vaddr, void *dst, const void *src,
208 unsigned long len) 233 unsigned long len)
@@ -316,7 +341,7 @@ static int __init page_is_ram(unsigned long pagenr)
316void __init paging_init(void) 341void __init paging_init(void)
317{ 342{
318 unsigned long zones_size[MAX_NR_ZONES] = { 0, }; 343 unsigned long zones_size[MAX_NR_ZONES] = { 0, };
319 unsigned long max_dma, high, low; 344 unsigned long max_dma, low;
320#ifndef CONFIG_FLATMEM 345#ifndef CONFIG_FLATMEM
321 unsigned long zholes_size[MAX_NR_ZONES] = { 0, }; 346 unsigned long zholes_size[MAX_NR_ZONES] = { 0, };
322 unsigned long i, j, pfn; 347 unsigned long i, j, pfn;
@@ -331,7 +356,6 @@ void __init paging_init(void)
331 356
332 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; 357 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
333 low = max_low_pfn; 358 low = max_low_pfn;
334 high = highend_pfn;
335 359
336#ifdef CONFIG_ISA 360#ifdef CONFIG_ISA
337 if (low < max_dma) 361 if (low < max_dma)
@@ -344,13 +368,13 @@ void __init paging_init(void)
344 zones_size[ZONE_DMA] = low; 368 zones_size[ZONE_DMA] = low;
345#endif 369#endif
346#ifdef CONFIG_HIGHMEM 370#ifdef CONFIG_HIGHMEM
347 if (cpu_has_dc_aliases) { 371 zones_size[ZONE_HIGHMEM] = highend_pfn - highstart_pfn;
348 printk(KERN_WARNING "This processor doesn't support highmem."); 372
349 if (high - low) 373 if (cpu_has_dc_aliases && zones_size[ZONE_HIGHMEM]) {
350 printk(" %ldk highmem ignored", high - low); 374 printk(KERN_WARNING "This processor doesn't support highmem."
351 printk("\n"); 375 " %ldk highmem ignored\n", zones_size[ZONE_HIGHMEM]);
352 } else 376 zones_size[ZONE_HIGHMEM] = 0;
353 zones_size[ZONE_HIGHMEM] = high - low; 377 }
354#endif 378#endif
355 379
356#ifdef CONFIG_FLATMEM 380#ifdef CONFIG_FLATMEM
@@ -443,15 +467,18 @@ void __init mem_init(void)
443} 467}
444#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 468#endif /* !CONFIG_NEED_MULTIPLE_NODES */
445 469
446void free_init_pages(char *what, unsigned long begin, unsigned long end) 470static void free_init_pages(char *what, unsigned long begin, unsigned long end)
447{ 471{
448 unsigned long addr; 472 unsigned long pfn;
473
474 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
475 struct page *page = pfn_to_page(pfn);
476 void *addr = phys_to_virt(PFN_PHYS(pfn));
449 477
450 for (addr = begin; addr < end; addr += PAGE_SIZE) { 478 ClearPageReserved(page);
451 ClearPageReserved(virt_to_page(addr)); 479 init_page_count(page);
452 init_page_count(virt_to_page(addr)); 480 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
453 memset((void *)addr, 0xcc, PAGE_SIZE); 481 __free_page(page);
454 free_page(addr);
455 totalram_pages++; 482 totalram_pages++;
456 } 483 }
457 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); 484 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
@@ -460,12 +487,9 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
460#ifdef CONFIG_BLK_DEV_INITRD 487#ifdef CONFIG_BLK_DEV_INITRD
461void free_initrd_mem(unsigned long start, unsigned long end) 488void free_initrd_mem(unsigned long start, unsigned long end)
462{ 489{
463#ifdef CONFIG_64BIT 490 free_init_pages("initrd memory",
464 /* Switch from KSEG0 to XKPHYS addresses */ 491 virt_to_phys((void *)start),
465 start = (unsigned long)phys_to_virt(CPHYSADDR(start)); 492 virt_to_phys((void *)end));
466 end = (unsigned long)phys_to_virt(CPHYSADDR(end));
467#endif
468 free_init_pages("initrd memory", start, end);
469} 493}
470#endif 494#endif
471 495
@@ -473,17 +497,13 @@ extern unsigned long prom_free_prom_memory(void);
473 497
474void free_initmem(void) 498void free_initmem(void)
475{ 499{
476 unsigned long start, end, freed; 500 unsigned long freed;
477 501
478 freed = prom_free_prom_memory(); 502 freed = prom_free_prom_memory();
479 if (freed) 503 if (freed)
480 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed); 504 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed);
481 505
482 start = (unsigned long)(&__init_begin); 506 free_init_pages("unused kernel memory",
483 end = (unsigned long)(&__init_end); 507 __pa_symbol(&__init_begin),
484#ifdef CONFIG_64BIT 508 __pa_symbol(&__init_end));
485 start = PAGE_OFFSET | CPHYSADDR(start);
486 end = PAGE_OFFSET | CPHYSADDR(end);
487#endif
488 free_init_pages("unused kernel memory", start, end);
489} 509}
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index cea7d0ea36e4..fc2c96f0a1fd 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -6,98 +6,13 @@
6 * (C) Copyright 1995 1996 Linus Torvalds 6 * (C) Copyright 1995 1996 Linus Torvalds
7 * (C) Copyright 2001, 2002 Ralf Baechle 7 * (C) Copyright 2001, 2002 Ralf Baechle
8 */ 8 */
9#include <linux/mm.h>
9#include <linux/module.h> 10#include <linux/module.h>
10#include <asm/addrspace.h> 11#include <asm/addrspace.h>
11#include <asm/byteorder.h> 12#include <asm/byteorder.h>
12 13
13#include <linux/vmalloc.h> 14#include <linux/vmalloc.h>
14#include <asm/cacheflush.h> 15#include <linux/io.h>
15#include <asm/io.h>
16#include <asm/tlbflush.h>
17
18static inline void remap_area_pte(pte_t * pte, unsigned long address,
19 phys_t size, phys_t phys_addr, unsigned long flags)
20{
21 phys_t end;
22 unsigned long pfn;
23 pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE
24 | __WRITEABLE | flags);
25
26 address &= ~PMD_MASK;
27 end = address + size;
28 if (end > PMD_SIZE)
29 end = PMD_SIZE;
30 if (address >= end)
31 BUG();
32 pfn = phys_addr >> PAGE_SHIFT;
33 do {
34 if (!pte_none(*pte)) {
35 printk("remap_area_pte: page already exists\n");
36 BUG();
37 }
38 set_pte(pte, pfn_pte(pfn, pgprot));
39 address += PAGE_SIZE;
40 pfn++;
41 pte++;
42 } while (address && (address < end));
43}
44
45static inline int remap_area_pmd(pmd_t * pmd, unsigned long address,
46 phys_t size, phys_t phys_addr, unsigned long flags)
47{
48 phys_t end;
49
50 address &= ~PGDIR_MASK;
51 end = address + size;
52 if (end > PGDIR_SIZE)
53 end = PGDIR_SIZE;
54 phys_addr -= address;
55 if (address >= end)
56 BUG();
57 do {
58 pte_t * pte = pte_alloc_kernel(pmd, address);
59 if (!pte)
60 return -ENOMEM;
61 remap_area_pte(pte, address, end - address, address + phys_addr, flags);
62 address = (address + PMD_SIZE) & PMD_MASK;
63 pmd++;
64 } while (address && (address < end));
65 return 0;
66}
67
68static int remap_area_pages(unsigned long address, phys_t phys_addr,
69 phys_t size, unsigned long flags)
70{
71 int error;
72 pgd_t * dir;
73 unsigned long end = address + size;
74
75 phys_addr -= address;
76 dir = pgd_offset(&init_mm, address);
77 flush_cache_all();
78 if (address >= end)
79 BUG();
80 do {
81 pud_t *pud;
82 pmd_t *pmd;
83
84 error = -ENOMEM;
85 pud = pud_alloc(&init_mm, dir, address);
86 if (!pud)
87 break;
88 pmd = pmd_alloc(&init_mm, pud, address);
89 if (!pmd)
90 break;
91 if (remap_area_pmd(pmd, address, end - address,
92 phys_addr + address, flags))
93 break;
94 error = 0;
95 address = (address + PGDIR_SIZE) & PGDIR_MASK;
96 dir++;
97 } while (address && (address < end));
98 flush_tlb_all();
99 return error;
100}
101 16
102/* 17/*
103 * Generic mapping function (not visible outside): 18 * Generic mapping function (not visible outside):
@@ -121,6 +36,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
121 unsigned long offset; 36 unsigned long offset;
122 phys_t last_addr; 37 phys_t last_addr;
123 void * addr; 38 void * addr;
39 pgprot_t pgprot;
124 40
125 phys_addr = fixup_bigphys_addr(phys_addr, size); 41 phys_addr = fixup_bigphys_addr(phys_addr, size);
126 42
@@ -152,6 +68,9 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
152 return NULL; 68 return NULL;
153 } 69 }
154 70
71 pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE
72 | __WRITEABLE | flags);
73
155 /* 74 /*
156 * Mappings have to be page-aligned 75 * Mappings have to be page-aligned
157 */ 76 */
@@ -166,7 +85,8 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
166 if (!area) 85 if (!area)
167 return NULL; 86 return NULL;
168 addr = area->addr; 87 addr = area->addr;
169 if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { 88 if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
89 phys_addr, pgprot)) {
170 vunmap(addr); 90 vunmap(addr);
171 return NULL; 91 return NULL;
172 } 92 }
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index d41fc5885e87..dc795be62807 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -243,11 +243,10 @@ static void __init __build_store_reg(int reg)
243 243
244static inline void build_store_reg(int reg) 244static inline void build_store_reg(int reg)
245{ 245{
246 if (cpu_has_prefetch) 246 int pref_off = cpu_has_prefetch ?
247 if (reg) 247 (reg ? pref_offset_copy : pref_offset_clear) : 0;
248 build_dst_pref(pref_offset_copy); 248 if (pref_off)
249 else 249 build_dst_pref(pref_off);
250 build_dst_pref(pref_offset_clear);
251 else if (cpu_has_cache_cdex_s) 250 else if (cpu_has_cache_cdex_s)
252 build_cdex_s(); 251 build_cdex_s();
253 else if (cpu_has_cache_cdex_p) 252 else if (cpu_has_cache_cdex_p)
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 8d600d307d5d..c46eb651bf09 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -58,6 +58,9 @@ void __init pagetable_init(void)
58 58
59 /* Initialize the entire pgd. */ 59 /* Initialize the entire pgd. */
60 pgd_init((unsigned long)swapper_pg_dir); 60 pgd_init((unsigned long)swapper_pg_dir);
61#ifdef MODULE_START
62 pgd_init((unsigned long)module_pg_dir);
63#endif
61 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 64 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
62 65
63 pgd_base = swapper_pg_dir; 66 pgd_base = swapper_pg_dir;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index fec318a1c8c5..492c518e7ba5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -423,6 +423,9 @@ enum label_id {
423 label_invalid, 423 label_invalid,
424 label_second_part, 424 label_second_part,
425 label_leave, 425 label_leave,
426#ifdef MODULE_START
427 label_module_alloc,
428#endif
426 label_vmalloc, 429 label_vmalloc,
427 label_vmalloc_done, 430 label_vmalloc_done,
428 label_tlbw_hazard, 431 label_tlbw_hazard,
@@ -455,6 +458,9 @@ static __init void build_label(struct label **lab, u32 *addr,
455 458
456L_LA(_second_part) 459L_LA(_second_part)
457L_LA(_leave) 460L_LA(_leave)
461#ifdef MODULE_START
462L_LA(_module_alloc)
463#endif
458L_LA(_vmalloc) 464L_LA(_vmalloc)
459L_LA(_vmalloc_done) 465L_LA(_vmalloc_done)
460L_LA(_tlbw_hazard) 466L_LA(_tlbw_hazard)
@@ -686,6 +692,13 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
686 i_bgezl(p, reg, 0); 692 i_bgezl(p, reg, 0);
687} 693}
688 694
695static void __init __attribute__((unused))
696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
697{
698 r_mips_pc16(r, *p, l);
699 i_bgez(p, reg, 0);
700}
701
689/* The only general purpose registers allowed in TLB handlers. */ 702/* The only general purpose registers allowed in TLB handlers. */
690#define K0 26 703#define K0 26
691#define K1 27 704#define K1 27
@@ -970,7 +983,11 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
970 * The vmalloc handling is not in the hotpath. 983 * The vmalloc handling is not in the hotpath.
971 */ 984 */
972 i_dmfc0(p, tmp, C0_BADVADDR); 985 i_dmfc0(p, tmp, C0_BADVADDR);
986#ifdef MODULE_START
987 il_bltz(p, r, tmp, label_module_alloc);
988#else
973 il_bltz(p, r, tmp, label_vmalloc); 989 il_bltz(p, r, tmp, label_vmalloc);
990#endif
974 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 991 /* No i_nop needed here, since the next insn doesn't touch TMP. */
975 992
976#ifdef CONFIG_SMP 993#ifdef CONFIG_SMP
@@ -1023,8 +1040,46 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1023{ 1040{
1024 long swpd = (long)swapper_pg_dir; 1041 long swpd = (long)swapper_pg_dir;
1025 1042
1043#ifdef MODULE_START
1044 long modd = (long)module_pg_dir;
1045
1046 l_module_alloc(l, *p);
1047 /*
1048 * Assumption:
1049 * VMALLOC_START >= 0xc000000000000000UL
1050 * MODULE_START >= 0xe000000000000000UL
1051 */
1052 i_SLL(p, ptr, bvaddr, 2);
1053 il_bgez(p, r, ptr, label_vmalloc);
1054
1055 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) {
1056 i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */
1057 } else {
1058 /* unlikely configuration */
1059 i_nop(p); /* delay slot */
1060 i_LA(p, ptr, MODULE_START);
1061 }
1062 i_dsubu(p, bvaddr, bvaddr, ptr);
1063
1064 if (in_compat_space_p(modd) && !rel_lo(modd)) {
1065 il_b(p, r, label_vmalloc_done);
1066 i_lui(p, ptr, rel_hi(modd));
1067 } else {
1068 i_LA_mostly(p, ptr, modd);
1069 il_b(p, r, label_vmalloc_done);
1070 i_daddiu(p, ptr, ptr, rel_lo(modd));
1071 }
1072
1073 l_vmalloc(l, *p);
1074 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) &&
1075 MODULE_START << 32 == VMALLOC_START)
1076 i_dsll32(p, ptr, ptr, 0); /* typical case */
1077 else
1078 i_LA(p, ptr, VMALLOC_START);
1079#else
1026 l_vmalloc(l, *p); 1080 l_vmalloc(l, *p);
1027 i_LA(p, ptr, VMALLOC_START); 1081 i_LA(p, ptr, VMALLOC_START);
1082#endif
1028 i_dsubu(p, bvaddr, bvaddr, ptr); 1083 i_dsubu(p, bvaddr, bvaddr, ptr);
1029 1084
1030 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1085 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..bb11fef08472 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,48 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing
103 */
104static void end_cpci_irq(unsigned int irq)
105{
106 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
107 unmask_cpci_irq(irq);
108}
109
110/*
111 * Interrupt handler for interrupts coming from the FPGA chip. 69 * Interrupt handler for interrupts coming from the FPGA chip.
112 * It could be built in ethernet ports etc... 70 * It could be built in ethernet ports etc...
113 */ 71 */
@@ -125,27 +83,18 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 83 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 84}
127 85
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 86struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 87 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 88 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 89 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 90 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 91 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq,
138}; 92};
139 93
140void cpci_irq_init(void) 94void cpci_irq_init(void)
141{ 95{
142 int i; 96 int i;
143 97
144 /* Reset irq handlers pointers to NULL */ 98 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 99 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 100}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..a7a80c0da569 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,48 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing
97 */
98static void end_uart_irq(unsigned int irq)
99{
100 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
101 unmask_uart_irq(irq);
102}
103
104/*
105 * Interrupt handler for interrupts coming from the FPGA chip. 63 * Interrupt handler for interrupts coming from the FPGA chip.
106 */ 64 */
107void ll_uart_irq(void) 65void ll_uart_irq(void)
@@ -118,28 +76,16 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 76 do_IRQ(ls1bit8(irq_src) + 74);
119} 77}
120 78
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 79struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 80 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 81 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 82 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 83 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 84 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq,
131}; 85};
132 86
133void uart_irq_init(void) 87void uart_irq_init(void)
134{ 88{
135 /* Reset irq handlers pointers to NULL */ 89 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
136 irq_desc[80].status = IRQ_DISABLED; 90 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 91}
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 0a50aad5bbe4..bf3be6fcf7ff 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -12,5 +12,6 @@ oprofile-y := $(DRIVER_OBJS) common.o
12 12
13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o 13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o 14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o 16oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
16oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o 17oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 65eb55400d77..4e0a90b3916b 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -83,6 +83,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
83 case CPU_74K: 83 case CPU_74K:
84 case CPU_SB1: 84 case CPU_SB1:
85 case CPU_SB1A: 85 case CPU_SB1A:
86 case CPU_R10000:
87 case CPU_R12000:
88 case CPU_R14000:
86 lmodel = &op_model_mipsxx_ops; 89 lmodel = &op_model_mipsxx_ops;
87 break; 90 break;
88 91
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1fb240c57bac..455d76ad06d8 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -18,7 +18,7 @@
18#define M_PERFCTL_SUPERVISOR (1UL << 2) 18#define M_PERFCTL_SUPERVISOR (1UL << 2)
19#define M_PERFCTL_USER (1UL << 3) 19#define M_PERFCTL_USER (1UL << 3)
20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) 20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
21#define M_PERFCTL_EVENT(event) ((event) << 5) 21#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
23#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 23#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
@@ -218,13 +218,23 @@ static inline int __n_counters(void)
218 218
219static inline int n_counters(void) 219static inline int n_counters(void)
220{ 220{
221 int counters = __n_counters(); 221 int counters;
222
223 switch (current_cpu_data.cputype) {
224 case CPU_R10000:
225 counters = 2;
226
227 case CPU_R12000:
228 case CPU_R14000:
229 counters = 4;
230
231 default:
232 counters = __n_counters();
233 }
222 234
223#ifdef CONFIG_MIPS_MT_SMP 235#ifdef CONFIG_MIPS_MT_SMP
224 if (current_cpu_data.cputype == CPU_34K) 236 counters >> 1;
225 return counters >> 1;
226#endif 237#endif
227
228 return counters; 238 return counters;
229} 239}
230 240
@@ -284,6 +294,18 @@ static int __init mipsxx_init(void)
284 op_model_mipsxx_ops.cpu_type = "mips/5K"; 294 op_model_mipsxx_ops.cpu_type = "mips/5K";
285 break; 295 break;
286 296
297 case CPU_R10000:
298 if ((current_cpu_data.processor_id & 0xff) == 0x20)
299 op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
300 else
301 op_model_mipsxx_ops.cpu_type = "mips/r10000";
302 break;
303
304 case CPU_R12000:
305 case CPU_R14000:
306 op_model_mipsxx_ops.cpu_type = "mips/r12000";
307 break;
308
287 case CPU_SB1: 309 case CPU_SB1:
288 case CPU_SB1A: 310 case CPU_SB1A:
289 op_model_mipsxx_ops.cpu_type = "mips/sb1"; 311 op_model_mipsxx_ops.cpu_type = "mips/sb1";
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 70cb55b89df6..82b20c28bef8 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_SGI_IP32) += fixup-ip32.o ops-mace.o pci-ip32.o
43obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o 43obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o
44obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o 44obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o
45obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o 45obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o
46obj-$(CONFIG_SNI_RM200_PCI) += fixup-sni.o ops-sni.o 46obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
47obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 47obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
48obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 48obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
49obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 49obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 75a01e764898..7d5f6bbf7a9d 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -94,22 +94,21 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
94#if 0 94#if 0
95 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
96 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
98 } else if (galileo_id == 0x1 || galileo_id == 0x2) 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif 99#endif
100 { 100 {
101 signed int timeo; 101 signed int timeo;
102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GT_READ(GT_PCI0_TOR_OFS);
104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
105 GALILEO_OUTL( 105 GT_WRITE(GT_PCI0_TOR_OFS,
106 (0xff << 16) | /* retry count */ 106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */ 107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */ 108 0xff); /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110 109
111 /* enable PCI retry exceeded interrupt */ 110 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 111 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
113 } 112 }
114} 113}
115 114
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
index 4256b3b30b77..50546dab6689 100644
--- a/arch/mips/pci/fixup-pnx8550.c
+++ b/arch/mips/pci/fixup-pnx8550.c
@@ -33,7 +33,7 @@
33#define DBG(x...) 33#define DBG(x...)
34#endif 34#endif
35 35
36extern char irq_tab_jbs[][5]; 36extern char pnx8550_irq_tab[][5];
37 37
38void __init pcibios_fixup_resources(struct pci_dev *dev) 38void __init pcibios_fixup_resources(struct pci_dev *dev)
39{ 39{
@@ -47,7 +47,7 @@ void __init pcibios_fixup(void)
47 47
48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 48int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
49{ 49{
50 return irq_tab_jbs[slot][pin]; 50 return pnx8550_irq_tab[slot][pin];
51} 51}
52 52
53/* Do platform specific device initialization at pci_enable_device() time */ 53/* Do platform specific device initialization at pci_enable_device() time */
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
index 13de45940b19..ecd3991bd0e4 100644
--- a/arch/mips/pci/ops-gt64111.c
+++ b/arch/mips/pci/ops-gt64111.c
@@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
38 switch (size) { 38 switch (size) {
39 case 4: 39 case 4:
40 PCI_CFG_SET(devfn, where); 40 PCI_CFG_SET(devfn, where);
41 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 41 *val = GT_READ(GT_PCI0_CFGDATA_OFS);
42 return PCIBIOS_SUCCESSFUL; 42 return PCIBIOS_SUCCESSFUL;
43 43
44 case 2: 44 case 2:
45 PCI_CFG_SET(devfn, (where & ~0x3)); 45 PCI_CFG_SET(devfn, (where & ~0x3));
46 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 46 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
47 >> ((where & 3) * 8); 47 >> ((where & 3) * 8);
48 return PCIBIOS_SUCCESSFUL; 48 return PCIBIOS_SUCCESSFUL;
49 49
50 case 1: 50 case 1:
51 PCI_CFG_SET(devfn, (where & ~0x3)); 51 PCI_CFG_SET(devfn, (where & ~0x3));
52 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 52 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
53 >> ((where & 3) * 8); 53 >> ((where & 3) * 8);
54 return PCIBIOS_SUCCESSFUL; 54 return PCIBIOS_SUCCESSFUL;
55 } 55 }
@@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
68 switch (size) { 68 switch (size) {
69 case 4: 69 case 4:
70 PCI_CFG_SET(devfn, where); 70 PCI_CFG_SET(devfn, where);
71 GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS); 71 GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
72 72
73 return PCIBIOS_SUCCESSFUL; 73 return PCIBIOS_SUCCESSFUL;
74 74
75 case 2: 75 case 2:
76 PCI_CFG_SET(devfn, (where & ~0x3)); 76 PCI_CFG_SET(devfn, (where & ~0x3));
77 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 77 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
78 tmp &= ~(0xffff << ((where & 0x3) * 8)); 78 tmp &= ~(0xffff << ((where & 0x3) * 8));
79 tmp |= (val << ((where & 0x3) * 8)); 79 tmp |= (val << ((where & 0x3) * 8));
80 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 80 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
81 81
82 return PCIBIOS_SUCCESSFUL; 82 return PCIBIOS_SUCCESSFUL;
83 83
84 case 1: 84 case 1:
85 PCI_CFG_SET(devfn, (where & ~0x3)); 85 PCI_CFG_SET(devfn, (where & ~0x3));
86 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 86 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
87 tmp &= ~(0xff << ((where & 0x3) * 8)); 87 tmp &= ~(0xff << ((where & 0x3) * 8));
88 tmp |= (val << ((where & 0x3) * 8)); 88 tmp |= (val << ((where & 0x3) * 8));
89 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 89 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
90 90
91 return PCIBIOS_SUCCESSFUL; 91 return PCIBIOS_SUCCESSFUL;
92 } 92 }
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
index 454b65cc3354..f556b7a8dccd 100644
--- a/arch/mips/pci/ops-pnx8550.c
+++ b/arch/mips/pci/ops-pnx8550.c
@@ -202,7 +202,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
202 break; 202 break;
203 } 203 }
204 204
205 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); 205 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(1 << (where & 3)), &data);
206 206
207 return err; 207 return err;
208} 208}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca2..2c36c108c4d6 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41static DEFINE_SPINLOCK(irq_lock);
42
43/* default prio for interrupts */ 41/* default prio for interrupts */
44/* first one is a no-no so therefore always prio 0 (disabled) */ 42/* first one is a no-no so therefore always prio 0 (disabled) */
45static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
149 } 147 }
150} 148}
151 149
152#define pnx8550_disable pnx8550_ack
153static void pnx8550_ack(unsigned int irq)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&irq_lock, flags);
158 mask_irq(irq);
159 spin_unlock_irqrestore(&irq_lock, flags);
160}
161
162#define pnx8550_enable pnx8550_unmask
163static void pnx8550_unmask(unsigned int irq)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&irq_lock, flags);
168 unmask_irq(irq);
169 spin_unlock_irqrestore(&irq_lock, flags);
170}
171
172static unsigned int startup_irq(unsigned int irq_nr)
173{
174 pnx8550_unmask(irq_nr);
175 return 0;
176}
177
178static void shutdown_irq(unsigned int irq_nr)
179{
180 pnx8550_ack(irq_nr);
181 return;
182}
183
184int pnx8550_set_gic_priority(int irq, int priority) 150int pnx8550_set_gic_priority(int irq, int priority)
185{ 151{
186 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,27 +158,12 @@ int pnx8550_set_gic_priority(int irq, int priority)
192 return prev_priority; 158 return prev_priority;
193} 159}
194 160
195static inline void mask_and_ack_level_irq(unsigned int irq)
196{
197 pnx8550_disable(irq);
198 return;
199}
200
201static void end_irq(unsigned int irq)
202{
203 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
204 pnx8550_enable(irq);
205 }
206}
207
208static struct irq_chip level_irq_type = { 161static struct irq_chip level_irq_type = {
209 .typename = "PNX Level IRQ", 162 .typename = "PNX Level IRQ",
210 .startup = startup_irq, 163 .ack = mask_irq,
211 .shutdown = shutdown_irq, 164 .mask = mask_irq,
212 .enable = pnx8550_enable, 165 .mask_ack = mask_irq,
213 .disable = pnx8550_disable, 166 .unmask = unmask_irq,
214 .ack = mask_and_ack_level_irq,
215 .end = end_irq,
216}; 167};
217 168
218static struct irqaction gic_action = { 169static struct irqaction gic_action = {
@@ -233,8 +184,8 @@ void __init arch_init_irq(void)
233 int configPR; 184 int configPR;
234 185
235 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 186 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
236 irq_desc[i].chip = &level_irq_type; 187 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
237 pnx8550_ack(i); /* mask the irq just in case */ 188 mask_irq(i); /* mask the irq just in case */
238 } 189 }
239 190
240 /* init of GIC/IPC interrupts */ 191 /* init of GIC/IPC interrupts */
@@ -270,7 +221,7 @@ void __init arch_init_irq(void)
270 /* mask/priority is still 0 so we will not get any 221 /* mask/priority is still 0 so we will not get any
271 * interrupts until it is unmasked */ 222 * interrupts until it is unmasked */
272 223
273 irq_desc[i].chip = &level_irq_type; 224 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
274 } 225 }
275 226
276 /* Priority level 0 */ 227 /* Priority level 0 */
@@ -279,20 +230,21 @@ void __init arch_init_irq(void)
279 /* Set int vector table address */ 230 /* Set int vector table address */
280 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 231 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
281 232
282 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; 233 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
234 handle_level_irq);
283 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 235 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
284 236
285 /* init of Timer interrupts */ 237 /* init of Timer interrupts */
286 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 238 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
287 irq_desc[i].chip = &level_irq_type; 239 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
288 }
289 240
290 /* Stop Timer 1-3 */ 241 /* Stop Timer 1-3 */
291 configPR = read_c0_config7(); 242 configPR = read_c0_config7();
292 configPR |= 0x00000038; 243 configPR |= 0x00000038;
293 write_c0_config7(configPR); 244 write_c0_config7(configPR);
294 245
295 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; 246 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
247 handle_level_irq);
296 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 248 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
297} 249}
298 250
diff --git a/arch/mips/philips/pnx8550/common/prom.c b/arch/mips/philips/pnx8550/common/prom.c
index f8952c1359cd..eb6ec11fef07 100644
--- a/arch/mips/philips/pnx8550/common/prom.c
+++ b/arch/mips/philips/pnx8550/common/prom.c
@@ -35,23 +35,15 @@ char * prom_getcmdline(void)
35 return &(arcs_cmdline[0]); 35 return &(arcs_cmdline[0]);
36} 36}
37 37
38void prom_init_cmdline(void) 38void __init prom_init_cmdline(void)
39{ 39{
40 char *cp; 40 int i;
41 int actr;
42
43 actr = 1; /* Always ignore argv[0] */
44 41
45 cp = &(arcs_cmdline[0]); 42 arcs_cmdline[0] = '\0';
46 while(actr < prom_argc) { 43 for (i = 0; i < prom_argc; i++) {
47 strcpy(cp, prom_argv[actr]); 44 strcat(arcs_cmdline, prom_argv[i]);
48 cp += strlen(prom_argv[actr]); 45 strcat(arcs_cmdline, " ");
49 *cp++ = ' ';
50 actr++;
51 } 46 }
52 if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
53 --cp;
54 *cp = '\0';
55} 47}
56 48
57char *prom_getenv(char *envname) 49char *prom_getenv(char *envname)
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 65c440e8480b..68def3880a1c 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -33,7 +33,17 @@
33#include <int.h> 33#include <int.h>
34#include <cm.h> 34#include <cm.h>
35 35
36extern unsigned int mips_hpt_frequency; 36static unsigned long cpj;
37
38static cycle_t hpt_read(void)
39{
40 return read_c0_count2();
41}
42
43static void timer_ack(void)
44{
45 write_c0_compare(cpj);
46}
37 47
38/* 48/*
39 * pnx8550_time_init() - it does the following things: 49 * pnx8550_time_init() - it does the following things:
@@ -68,27 +78,48 @@ void pnx8550_time_init(void)
68 * HZ timer interrupts per second. 78 * HZ timer interrupts per second.
69 */ 79 */
70 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); 80 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
81 cpj = (mips_hpt_frequency + HZ / 2) / HZ;
82 write_c0_count(0);
83 timer_ack();
84
85 /* Setup Timer 2 */
86 write_c0_count2(0);
87 write_c0_compare2(0xffffffff);
88
89 clocksource_mips.read = hpt_read;
90 mips_timer_ack = timer_ack;
91}
92
93static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
94{
95 /* Timer 2 clear interrupt */
96 write_c0_compare2(-1);
97 return IRQ_HANDLED;
71} 98}
72 99
100static struct irqaction monotonic_irqaction = {
101 .handler = monotonic_interrupt,
102 .flags = IRQF_DISABLED,
103 .name = "Monotonic timer",
104};
105
73void __init plat_timer_setup(struct irqaction *irq) 106void __init plat_timer_setup(struct irqaction *irq)
74{ 107{
75 int configPR; 108 int configPR;
76 109
77 setup_irq(PNX8550_INT_TIMER1, irq); 110 setup_irq(PNX8550_INT_TIMER1, irq);
111 setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
78 112
79 /* Start timer1 */ 113 /* Timer 1 start */
80 configPR = read_c0_config7(); 114 configPR = read_c0_config7();
81 configPR &= ~0x00000008; 115 configPR &= ~0x00000008;
82 write_c0_config7(configPR); 116 write_c0_config7(configPR);
83 117
84 /* Timer 2 stop */ 118 /* Timer 2 start */
85 configPR = read_c0_config7(); 119 configPR = read_c0_config7();
86 configPR |= 0x00000010; 120 configPR &= ~0x00000010;
87 write_c0_config7(configPR); 121 write_c0_config7(configPR);
88 122
89 write_c0_count2(0);
90 write_c0_compare2(0xffffffff);
91
92 /* Timer 3 stop */ 123 /* Timer 3 stop */
93 configPR = read_c0_config7(); 124 configPR = read_c0_config7();
94 configPR |= 0x00000020; 125 configPR |= 0x00000020;
diff --git a/arch/mips/philips/pnx8550/jbs/irqmap.c b/arch/mips/philips/pnx8550/jbs/irqmap.c
index f78e0423dc98..98c3429e6e50 100644
--- a/arch/mips/philips/pnx8550/jbs/irqmap.c
+++ b/arch/mips/philips/pnx8550/jbs/irqmap.c
@@ -28,9 +28,9 @@
28#include <linux/init.h> 28#include <linux/init.h>
29#include <int.h> 29#include <int.h>
30 30
31char irq_tab_jbs[][5] __initdata = { 31char pnx8550_irq_tab[][5] __initdata = {
32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, 32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, 33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff}, 34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
35}; 35};
36 36
diff --git a/arch/mips/philips/pnx8550/stb810/Makefile b/arch/mips/philips/pnx8550/stb810/Makefile
new file mode 100644
index 000000000000..f14b592af398
--- /dev/null
+++ b/arch/mips/philips/pnx8550/stb810/Makefile
@@ -0,0 +1,4 @@
1
2# Makefile for the Philips STB810 Board.
3
4lib-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/philips/pnx8550/stb810/board_setup.c b/arch/mips/philips/pnx8550/stb810/board_setup.c
new file mode 100644
index 000000000000..345d71e53cf2
--- /dev/null
+++ b/arch/mips/philips/pnx8550/stb810/board_setup.c
@@ -0,0 +1,49 @@
1/*
2 * STB810 specific board startup routines.
3 *
4 * Based on the arch/mips/philips/pnx8550/jbs/board_setup.c
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/sched.h>
19#include <linux/ioport.h>
20#include <linux/mm.h>
21#include <linux/console.h>
22#include <linux/mc146818rtc.h>
23#include <linux/delay.h>
24
25#include <asm/cpu.h>
26#include <asm/bootinfo.h>
27#include <asm/irq.h>
28#include <asm/mipsregs.h>
29#include <asm/reboot.h>
30#include <asm/pgtable.h>
31
32#include <glb.h>
33
34void __init board_setup(void)
35{
36 unsigned long config0, configpr;
37
38 config0 = read_c0_config();
39
40 /* clear all three cache coherency fields */
41 config0 &= ~(0x7 | (7<<25) | (7<<28));
42 config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
43 (CONF_CM_DEFAULT<<28));
44 write_c0_config(config0);
45
46 configpr = read_c0_config7();
47 configpr |= (1<<19); /* enable tlb */
48 write_c0_config7(configpr);
49}
diff --git a/arch/mips/philips/pnx8550/stb810/irqmap.c b/arch/mips/philips/pnx8550/stb810/irqmap.c
new file mode 100644
index 000000000000..5ee11e19975e
--- /dev/null
+++ b/arch/mips/philips/pnx8550/stb810/irqmap.c
@@ -0,0 +1,23 @@
1/*
2 * Philips STB810 board irqmap.
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <int.h>
17
18char pnx8550_irq_tab[][5] __initdata = {
19 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
20 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
21 [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
22};
23
diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c
new file mode 100644
index 000000000000..ea5b4e0fb47d
--- /dev/null
+++ b/arch/mips/philips/pnx8550/stb810/prom_init.c
@@ -0,0 +1,49 @@
1/*
2 * STB810 specific prom routines
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19#include <asm/addrspace.h>
20#include <asm/bootinfo.h>
21#include <linux/string.h>
22#include <linux/kernel.h>
23
24int prom_argc;
25char **prom_argv, **prom_envp;
26extern void __init prom_init_cmdline(void);
27extern char *prom_getenv(char *envname);
28
29const char *get_system_type(void)
30{
31 return "Philips PNX8550/STB810";
32}
33
34void __init prom_init(void)
35{
36 unsigned long memsize;
37
38 prom_argc = (int) fw_arg0;
39 prom_argv = (char **) fw_arg1;
40 prom_envp = (char **) fw_arg2;
41
42 prom_init_cmdline();
43
44 mips_machgroup = MACH_GROUP_PHILIPS;
45 mips_machtype = MACH_PHILIPS_STB810;
46
47 memsize = 0x08000000; /* Trimedia uses memory above */
48 add_memory_region(0, memsize, BOOT_MEM_RAM);
49}
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 3cc0436db6cf..305491e74dbe 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -99,8 +99,6 @@ void prom_cpus_done(void)
99 */ 99 */
100void prom_init_secondary(void) 100void prom_init_secondary(void)
101{ 101{
102 mips_hpt_init();
103
104 set_c0_status(ST0_CO | ST0_IE | ST0_IM); 102 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
105} 103}
106 104
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0d18ed47c47a..a1a9af6da7bf 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -95,16 +95,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
95 95
96static void enable_eisa1_irq(unsigned int irq) 96static void enable_eisa1_irq(unsigned int irq)
97{ 97{
98 unsigned long flags;
99 u8 mask; 98 u8 mask;
100 99
101 local_irq_save(flags);
102
103 mask = inb(EISA_INT1_MASK); 100 mask = inb(EISA_INT1_MASK);
104 mask &= ~((u8) (1 << irq)); 101 mask &= ~((u8) (1 << irq));
105 outb(mask, EISA_INT1_MASK); 102 outb(mask, EISA_INT1_MASK);
106
107 local_irq_restore(flags);
108} 103}
109 104
110static unsigned int startup_eisa1_irq(unsigned int irq) 105static unsigned int startup_eisa1_irq(unsigned int irq)
@@ -130,8 +125,6 @@ static void disable_eisa1_irq(unsigned int irq)
130 outb(mask, EISA_INT1_MASK); 125 outb(mask, EISA_INT1_MASK);
131} 126}
132 127
133#define shutdown_eisa1_irq disable_eisa1_irq
134
135static void mask_and_ack_eisa1_irq(unsigned int irq) 128static void mask_and_ack_eisa1_irq(unsigned int irq)
136{ 129{
137 disable_eisa1_irq(irq); 130 disable_eisa1_irq(irq);
@@ -148,25 +141,20 @@ static void end_eisa1_irq(unsigned int irq)
148static struct irq_chip ip22_eisa1_irq_type = { 141static struct irq_chip ip22_eisa1_irq_type = {
149 .typename = "IP22 EISA", 142 .typename = "IP22 EISA",
150 .startup = startup_eisa1_irq, 143 .startup = startup_eisa1_irq,
151 .shutdown = shutdown_eisa1_irq,
152 .enable = enable_eisa1_irq,
153 .disable = disable_eisa1_irq,
154 .ack = mask_and_ack_eisa1_irq, 144 .ack = mask_and_ack_eisa1_irq,
145 .mask = disable_eisa1_irq,
146 .mask_ack = mask_and_ack_eisa1_irq,
147 .unmask = enable_eisa1_irq,
155 .end = end_eisa1_irq, 148 .end = end_eisa1_irq,
156}; 149};
157 150
158static void enable_eisa2_irq(unsigned int irq) 151static void enable_eisa2_irq(unsigned int irq)
159{ 152{
160 unsigned long flags;
161 u8 mask; 153 u8 mask;
162 154
163 local_irq_save(flags);
164
165 mask = inb(EISA_INT2_MASK); 155 mask = inb(EISA_INT2_MASK);
166 mask &= ~((u8) (1 << (irq - 8))); 156 mask &= ~((u8) (1 << (irq - 8)));
167 outb(mask, EISA_INT2_MASK); 157 outb(mask, EISA_INT2_MASK);
168
169 local_irq_restore(flags);
170} 158}
171 159
172static unsigned int startup_eisa2_irq(unsigned int irq) 160static unsigned int startup_eisa2_irq(unsigned int irq)
@@ -192,8 +180,6 @@ static void disable_eisa2_irq(unsigned int irq)
192 outb(mask, EISA_INT2_MASK); 180 outb(mask, EISA_INT2_MASK);
193} 181}
194 182
195#define shutdown_eisa2_irq disable_eisa2_irq
196
197static void mask_and_ack_eisa2_irq(unsigned int irq) 183static void mask_and_ack_eisa2_irq(unsigned int irq)
198{ 184{
199 disable_eisa2_irq(irq); 185 disable_eisa2_irq(irq);
@@ -210,10 +196,10 @@ static void end_eisa2_irq(unsigned int irq)
210static struct irq_chip ip22_eisa2_irq_type = { 196static struct irq_chip ip22_eisa2_irq_type = {
211 .typename = "IP22 EISA", 197 .typename = "IP22 EISA",
212 .startup = startup_eisa2_irq, 198 .startup = startup_eisa2_irq,
213 .shutdown = shutdown_eisa2_irq,
214 .enable = enable_eisa2_irq,
215 .disable = disable_eisa2_irq,
216 .ack = mask_and_ack_eisa2_irq, 199 .ack = mask_and_ack_eisa2_irq,
200 .mask = disable_eisa2_irq,
201 .mask_ack = mask_and_ack_eisa2_irq,
202 .unmask = enable_eisa2_irq,
217 .end = end_eisa2_irq, 203 .end = end_eisa2_irq,
218}; 204};
219 205
@@ -275,13 +261,10 @@ int __init ip22_eisa_init(void)
275 outb(0, EISA_DMA2_WRITE_SINGLE); 261 outb(0, EISA_DMA2_WRITE_SINGLE);
276 262
277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 263 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
278 irq_desc[i].status = IRQ_DISABLED;
279 irq_desc[i].action = 0;
280 irq_desc[i].depth = 1;
281 if (i < (SGINT_EISA + 8)) 264 if (i < (SGINT_EISA + 8))
282 irq_desc[i].chip = &ip22_eisa1_irq_type; 265 set_irq_chip(i, &ip22_eisa1_irq_type);
283 else 266 else
284 irq_desc[i].chip = &ip22_eisa2_irq_type; 267 set_irq_chip(i, &ip22_eisa2_irq_type);
285 } 268 }
286 269
287 /* Cannot use request_irq because of kmalloc not being ready at such 270 /* Cannot use request_irq because of kmalloc not being ready at such
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index af518898eaa1..c44f8be0644f 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -40,186 +40,86 @@ extern int ip22_eisa_init(void);
40 40
41static void enable_local0_irq(unsigned int irq) 41static void enable_local0_irq(unsigned int irq)
42{ 42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 /* don't allow mappable interrupt to be enabled from setup_irq, 43 /* don't allow mappable interrupt to be enabled from setup_irq,
47 * we have our own way to do so */ 44 * we have our own way to do so */
48 if (irq != SGI_MAP_0_IRQ) 45 if (irq != SGI_MAP_0_IRQ)
49 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); 46 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
50 local_irq_restore(flags);
51}
52
53static unsigned int startup_local0_irq(unsigned int irq)
54{
55 enable_local0_irq(irq);
56 return 0; /* Never anything pending */
57} 47}
58 48
59static void disable_local0_irq(unsigned int irq) 49static void disable_local0_irq(unsigned int irq)
60{ 50{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
65 local_irq_restore(flags);
66}
67
68#define shutdown_local0_irq disable_local0_irq
69#define mask_and_ack_local0_irq disable_local0_irq
70
71static void end_local0_irq (unsigned int irq)
72{
73 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
74 enable_local0_irq(irq);
75} 52}
76 53
77static struct irq_chip ip22_local0_irq_type = { 54static struct irq_chip ip22_local0_irq_type = {
78 .typename = "IP22 local 0", 55 .typename = "IP22 local 0",
79 .startup = startup_local0_irq, 56 .ack = disable_local0_irq,
80 .shutdown = shutdown_local0_irq, 57 .mask = disable_local0_irq,
81 .enable = enable_local0_irq, 58 .mask_ack = disable_local0_irq,
82 .disable = disable_local0_irq, 59 .unmask = enable_local0_irq,
83 .ack = mask_and_ack_local0_irq,
84 .end = end_local0_irq,
85}; 60};
86 61
87static void enable_local1_irq(unsigned int irq) 62static void enable_local1_irq(unsigned int irq)
88{ 63{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /* don't allow mappable interrupt to be enabled from setup_irq, 64 /* don't allow mappable interrupt to be enabled from setup_irq,
93 * we have our own way to do so */ 65 * we have our own way to do so */
94 if (irq != SGI_MAP_1_IRQ) 66 if (irq != SGI_MAP_1_IRQ)
95 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 67 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
96 local_irq_restore(flags);
97}
98
99static unsigned int startup_local1_irq(unsigned int irq)
100{
101 enable_local1_irq(irq);
102 return 0; /* Never anything pending */
103} 68}
104 69
105void disable_local1_irq(unsigned int irq) 70void disable_local1_irq(unsigned int irq)
106{ 71{
107 unsigned long flags;
108
109 local_irq_save(flags);
110 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 72 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
111 local_irq_restore(flags);
112}
113
114#define shutdown_local1_irq disable_local1_irq
115#define mask_and_ack_local1_irq disable_local1_irq
116
117static void end_local1_irq (unsigned int irq)
118{
119 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
120 enable_local1_irq(irq);
121} 73}
122 74
123static struct irq_chip ip22_local1_irq_type = { 75static struct irq_chip ip22_local1_irq_type = {
124 .typename = "IP22 local 1", 76 .typename = "IP22 local 1",
125 .startup = startup_local1_irq, 77 .ack = disable_local1_irq,
126 .shutdown = shutdown_local1_irq, 78 .mask = disable_local1_irq,
127 .enable = enable_local1_irq, 79 .mask_ack = disable_local1_irq,
128 .disable = disable_local1_irq, 80 .unmask = enable_local1_irq,
129 .ack = mask_and_ack_local1_irq,
130 .end = end_local1_irq,
131}; 81};
132 82
133static void enable_local2_irq(unsigned int irq) 83static void enable_local2_irq(unsigned int irq)
134{ 84{
135 unsigned long flags;
136
137 local_irq_save(flags);
138 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 85 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
139 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 86 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
140 local_irq_restore(flags);
141}
142
143static unsigned int startup_local2_irq(unsigned int irq)
144{
145 enable_local2_irq(irq);
146 return 0; /* Never anything pending */
147} 87}
148 88
149void disable_local2_irq(unsigned int irq) 89void disable_local2_irq(unsigned int irq)
150{ 90{
151 unsigned long flags;
152
153 local_irq_save(flags);
154 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 91 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
155 if (!sgint->cmeimask0) 92 if (!sgint->cmeimask0)
156 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 93 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
157 local_irq_restore(flags);
158}
159
160#define shutdown_local2_irq disable_local2_irq
161#define mask_and_ack_local2_irq disable_local2_irq
162
163static void end_local2_irq (unsigned int irq)
164{
165 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
166 enable_local2_irq(irq);
167} 94}
168 95
169static struct irq_chip ip22_local2_irq_type = { 96static struct irq_chip ip22_local2_irq_type = {
170 .typename = "IP22 local 2", 97 .typename = "IP22 local 2",
171 .startup = startup_local2_irq, 98 .ack = disable_local2_irq,
172 .shutdown = shutdown_local2_irq, 99 .mask = disable_local2_irq,
173 .enable = enable_local2_irq, 100 .mask_ack = disable_local2_irq,
174 .disable = disable_local2_irq, 101 .unmask = enable_local2_irq,
175 .ack = mask_and_ack_local2_irq,
176 .end = end_local2_irq,
177}; 102};
178 103
179static void enable_local3_irq(unsigned int irq) 104static void enable_local3_irq(unsigned int irq)
180{ 105{
181 unsigned long flags;
182
183 local_irq_save(flags);
184 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 106 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
185 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 107 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
186 local_irq_restore(flags);
187}
188
189static unsigned int startup_local3_irq(unsigned int irq)
190{
191 enable_local3_irq(irq);
192 return 0; /* Never anything pending */
193} 108}
194 109
195void disable_local3_irq(unsigned int irq) 110void disable_local3_irq(unsigned int irq)
196{ 111{
197 unsigned long flags;
198
199 local_irq_save(flags);
200 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 112 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
201 if (!sgint->cmeimask1) 113 if (!sgint->cmeimask1)
202 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 114 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
203 local_irq_restore(flags);
204}
205
206#define shutdown_local3_irq disable_local3_irq
207#define mask_and_ack_local3_irq disable_local3_irq
208
209static void end_local3_irq (unsigned int irq)
210{
211 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
212 enable_local3_irq(irq);
213} 115}
214 116
215static struct irq_chip ip22_local3_irq_type = { 117static struct irq_chip ip22_local3_irq_type = {
216 .typename = "IP22 local 3", 118 .typename = "IP22 local 3",
217 .startup = startup_local3_irq, 119 .ack = disable_local3_irq,
218 .shutdown = shutdown_local3_irq, 120 .mask = disable_local3_irq,
219 .enable = enable_local3_irq, 121 .mask_ack = disable_local3_irq,
220 .disable = disable_local3_irq, 122 .unmask = enable_local3_irq,
221 .ack = mask_and_ack_local3_irq,
222 .end = end_local3_irq,
223}; 123};
224 124
225static void indy_local0_irqdispatch(void) 125static void indy_local0_irqdispatch(void)
@@ -430,10 +330,7 @@ void __init arch_init_irq(void)
430 else 330 else
431 handler = &ip22_local3_irq_type; 331 handler = &ip22_local3_irq_type;
432 332
433 irq_desc[i].status = IRQ_DISABLED; 333 set_irq_chip_and_handler(i, handler, handle_level_irq);
434 irq_desc[i].action = 0;
435 irq_desc[i].depth = 1;
436 irq_desc[i].chip = handler;
437 } 334 }
438 335
439 /* vector handler. this register the IRQ as non-sharable */ 336 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 270ecd3e6b4a..319f8803ef6f 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -332,34 +332,19 @@ static inline void disable_bridge_irq(unsigned int irq)
332 intr_disconnect_level(cpu, swlevel); 332 intr_disconnect_level(cpu, swlevel);
333} 333}
334 334
335static void mask_and_ack_bridge_irq(unsigned int irq)
336{
337 disable_bridge_irq(irq);
338}
339
340static void end_bridge_irq(unsigned int irq)
341{
342 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
343 irq_desc[irq].action)
344 enable_bridge_irq(irq);
345}
346
347static struct irq_chip bridge_irq_type = { 335static struct irq_chip bridge_irq_type = {
348 .typename = "bridge", 336 .typename = "bridge",
349 .startup = startup_bridge_irq, 337 .startup = startup_bridge_irq,
350 .shutdown = shutdown_bridge_irq, 338 .shutdown = shutdown_bridge_irq,
351 .enable = enable_bridge_irq, 339 .ack = disable_bridge_irq,
352 .disable = disable_bridge_irq, 340 .mask = disable_bridge_irq,
353 .ack = mask_and_ack_bridge_irq, 341 .mask_ack = disable_bridge_irq,
354 .end = end_bridge_irq, 342 .unmask = enable_bridge_irq,
355}; 343};
356 344
357void __devinit register_bridge_irq(unsigned int irq) 345void __devinit register_bridge_irq(unsigned int irq)
358{ 346{
359 irq_desc[irq].status = IRQ_DISABLED; 347 set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
360 irq_desc[irq].action = 0;
361 irq_desc[irq].depth = 1;
362 irq_desc[irq].chip = &bridge_irq_type;
363} 348}
364 349
365int __devinit request_bridge_irq(struct bridge_controller *bc) 350int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 5e82a268e3c9..c20e9899b34b 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -172,15 +172,6 @@ static __init unsigned long get_m48t35_time(void)
172 return mktime(year, month, date, hour, min, sec); 172 return mktime(year, month, date, hour, min, sec);
173} 173}
174 174
175static unsigned int startup_rt_irq(unsigned int irq)
176{
177 return 0;
178}
179
180static void shutdown_rt_irq(unsigned int irq)
181{
182}
183
184static void enable_rt_irq(unsigned int irq) 175static void enable_rt_irq(unsigned int irq)
185{ 176{
186} 177}
@@ -189,22 +180,13 @@ static void disable_rt_irq(unsigned int irq)
189{ 180{
190} 181}
191 182
192static void mask_and_ack_rt(unsigned int irq)
193{
194}
195
196static void end_rt_irq(unsigned int irq)
197{
198}
199
200static struct irq_chip rt_irq_type = { 183static struct irq_chip rt_irq_type = {
201 .typename = "SN HUB RT timer", 184 .typename = "SN HUB RT timer",
202 .startup = startup_rt_irq, 185 .ack = disable_rt_irq,
203 .shutdown = shutdown_rt_irq, 186 .mask = disable_rt_irq,
204 .enable = enable_rt_irq, 187 .mask_ack = disable_rt_irq,
205 .disable = disable_rt_irq, 188 .unmask = enable_rt_irq,
206 .ack = mask_and_ack_rt, 189 .eoi = enable_rt_irq,
207 .end = end_rt_irq,
208}; 190};
209 191
210static struct irqaction rt_irqaction = { 192static struct irqaction rt_irqaction = {
@@ -221,10 +203,7 @@ void __init plat_timer_setup(struct irqaction *irq)
221 if (irqno < 0) 203 if (irqno < 0)
222 panic("Can't allocate interrupt number for timer interrupt"); 204 panic("Can't allocate interrupt number for timer interrupt");
223 205
224 irq_desc[irqno].status = IRQ_DISABLED; 206 set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq);
225 irq_desc[irqno].action = NULL;
226 irq_desc[irqno].depth = 1;
227 irq_desc[irqno].chip = &rt_irq_type;
228 207
229 /* over-write the handler, we use our own way */ 208 /* over-write the handler, we use our own way */
230 irq->handler = no_action; 209 irq->handler = no_action;
@@ -239,14 +218,14 @@ void __init plat_timer_setup(struct irqaction *irq)
239 setup_irq(irqno, &rt_irqaction); 218 setup_irq(irqno, &rt_irqaction);
240} 219}
241 220
242static unsigned int ip27_hpt_read(void) 221static cycle_t ip27_hpt_read(void)
243{ 222{
244 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); 223 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
245} 224}
246 225
247void __init ip27_time_init(void) 226void __init ip27_time_init(void)
248{ 227{
249 mips_hpt_read = ip27_hpt_read; 228 clocksource_mips.read = ip27_hpt_read;
250 mips_hpt_frequency = CYCLES_PER_SEC; 229 mips_hpt_frequency = CYCLES_PER_SEC;
251 xtime.tv_sec = get_m48t35_time(); 230 xtime.tv_sec = get_m48t35_time();
252 xtime.tv_nsec = 0; 231 xtime.tv_nsec = 0;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c9acadd0846b..ae063864c026 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,12 +113,6 @@ static void inline flush_mace_bus(void)
113 * is quite different anyway. 113 * is quite different anyway.
114 */ 114 */
115 115
116/*
117 * IRQ spinlock - Ralf says not to disable CPU interrupts,
118 * and I think he knows better.
119 */
120static DEFINE_SPINLOCK(ip32_irq_lock);
121
122/* Some initial interrupts to set up */ 116/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
@@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq)
138 set_c0_status(STATUSF_IP7); 132 set_c0_status(STATUSF_IP7);
139} 133}
140 134
141static unsigned int startup_cpu_irq(unsigned int irq)
142{
143 enable_cpu_irq(irq);
144 return 0;
145}
146
147static void disable_cpu_irq(unsigned int irq) 135static void disable_cpu_irq(unsigned int irq)
148{ 136{
149 clear_c0_status(STATUSF_IP7); 137 clear_c0_status(STATUSF_IP7);
@@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq)
155 enable_cpu_irq (irq); 143 enable_cpu_irq (irq);
156} 144}
157 145
158#define shutdown_cpu_irq disable_cpu_irq
159#define mask_and_ack_cpu_irq disable_cpu_irq
160
161static struct irq_chip ip32_cpu_interrupt = { 146static struct irq_chip ip32_cpu_interrupt = {
162 .typename = "IP32 CPU", 147 .typename = "IP32 CPU",
163 .startup = startup_cpu_irq, 148 .ack = disable_cpu_irq,
164 .shutdown = shutdown_cpu_irq, 149 .mask = disable_cpu_irq,
165 .enable = enable_cpu_irq, 150 .mask_ack = disable_cpu_irq,
166 .disable = disable_cpu_irq, 151 .unmask = enable_cpu_irq,
167 .ack = mask_and_ack_cpu_irq,
168 .end = end_cpu_irq, 152 .end = end_cpu_irq,
169}; 153};
170 154
@@ -177,45 +161,27 @@ static uint64_t crime_mask;
177 161
178static void enable_crime_irq(unsigned int irq) 162static void enable_crime_irq(unsigned int irq)
179{ 163{
180 unsigned long flags;
181
182 spin_lock_irqsave(&ip32_irq_lock, flags);
183 crime_mask |= 1 << (irq - 1); 164 crime_mask |= 1 << (irq - 1);
184 crime->imask = crime_mask; 165 crime->imask = crime_mask;
185 spin_unlock_irqrestore(&ip32_irq_lock, flags);
186}
187
188static unsigned int startup_crime_irq(unsigned int irq)
189{
190 enable_crime_irq(irq);
191 return 0; /* This is probably not right; we could have pending irqs */
192} 166}
193 167
194static void disable_crime_irq(unsigned int irq) 168static void disable_crime_irq(unsigned int irq)
195{ 169{
196 unsigned long flags;
197
198 spin_lock_irqsave(&ip32_irq_lock, flags);
199 crime_mask &= ~(1 << (irq - 1)); 170 crime_mask &= ~(1 << (irq - 1));
200 crime->imask = crime_mask; 171 crime->imask = crime_mask;
201 flush_crime_bus(); 172 flush_crime_bus();
202 spin_unlock_irqrestore(&ip32_irq_lock, flags);
203} 173}
204 174
205static void mask_and_ack_crime_irq(unsigned int irq) 175static void mask_and_ack_crime_irq(unsigned int irq)
206{ 176{
207 unsigned long flags;
208
209 /* Edge triggered interrupts must be cleared. */ 177 /* Edge triggered interrupts must be cleared. */
210 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 178 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
211 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 179 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
212 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 180 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
213 uint64_t crime_int; 181 uint64_t crime_int;
214 spin_lock_irqsave(&ip32_irq_lock, flags);
215 crime_int = crime->hard_int; 182 crime_int = crime->hard_int;
216 crime_int &= ~(1 << (irq - 1)); 183 crime_int &= ~(1 << (irq - 1));
217 crime->hard_int = crime_int; 184 crime->hard_int = crime_int;
218 spin_unlock_irqrestore(&ip32_irq_lock, flags);
219 } 185 }
220 disable_crime_irq(irq); 186 disable_crime_irq(irq);
221} 187}
@@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq)
226 enable_crime_irq(irq); 192 enable_crime_irq(irq);
227} 193}
228 194
229#define shutdown_crime_irq disable_crime_irq
230
231static struct irq_chip ip32_crime_interrupt = { 195static struct irq_chip ip32_crime_interrupt = {
232 .typename = "IP32 CRIME", 196 .typename = "IP32 CRIME",
233 .startup = startup_crime_irq,
234 .shutdown = shutdown_crime_irq,
235 .enable = enable_crime_irq,
236 .disable = disable_crime_irq,
237 .ack = mask_and_ack_crime_irq, 197 .ack = mask_and_ack_crime_irq,
198 .mask = disable_crime_irq,
199 .mask_ack = mask_and_ack_crime_irq,
200 .unmask = enable_crime_irq,
238 .end = end_crime_irq, 201 .end = end_crime_irq,
239}; 202};
240 203
@@ -248,34 +211,20 @@ static unsigned long macepci_mask;
248 211
249static void enable_macepci_irq(unsigned int irq) 212static void enable_macepci_irq(unsigned int irq)
250{ 213{
251 unsigned long flags;
252
253 spin_lock_irqsave(&ip32_irq_lock, flags);
254 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 214 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
255 mace->pci.control = macepci_mask; 215 mace->pci.control = macepci_mask;
256 crime_mask |= 1 << (irq - 1); 216 crime_mask |= 1 << (irq - 1);
257 crime->imask = crime_mask; 217 crime->imask = crime_mask;
258 spin_unlock_irqrestore(&ip32_irq_lock, flags);
259}
260
261static unsigned int startup_macepci_irq(unsigned int irq)
262{
263 enable_macepci_irq (irq);
264 return 0;
265} 218}
266 219
267static void disable_macepci_irq(unsigned int irq) 220static void disable_macepci_irq(unsigned int irq)
268{ 221{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ip32_irq_lock, flags);
272 crime_mask &= ~(1 << (irq - 1)); 222 crime_mask &= ~(1 << (irq - 1));
273 crime->imask = crime_mask; 223 crime->imask = crime_mask;
274 flush_crime_bus(); 224 flush_crime_bus();
275 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 225 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
276 mace->pci.control = macepci_mask; 226 mace->pci.control = macepci_mask;
277 flush_mace_bus(); 227 flush_mace_bus();
278 spin_unlock_irqrestore(&ip32_irq_lock, flags);
279} 228}
280 229
281static void end_macepci_irq(unsigned int irq) 230static void end_macepci_irq(unsigned int irq)
@@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq)
284 enable_macepci_irq(irq); 233 enable_macepci_irq(irq);
285} 234}
286 235
287#define shutdown_macepci_irq disable_macepci_irq
288#define mask_and_ack_macepci_irq disable_macepci_irq
289
290static struct irq_chip ip32_macepci_interrupt = { 236static struct irq_chip ip32_macepci_interrupt = {
291 .typename = "IP32 MACE PCI", 237 .typename = "IP32 MACE PCI",
292 .startup = startup_macepci_irq, 238 .ack = disable_macepci_irq,
293 .shutdown = shutdown_macepci_irq, 239 .mask = disable_macepci_irq,
294 .enable = enable_macepci_irq, 240 .mask_ack = disable_macepci_irq,
295 .disable = disable_macepci_irq, 241 .unmask = enable_macepci_irq,
296 .ack = mask_and_ack_macepci_irq,
297 .end = end_macepci_irq, 242 .end = end_macepci_irq,
298}; 243};
299 244
@@ -339,7 +284,6 @@ static unsigned long maceisa_mask;
339static void enable_maceisa_irq (unsigned int irq) 284static void enable_maceisa_irq (unsigned int irq)
340{ 285{
341 unsigned int crime_int = 0; 286 unsigned int crime_int = 0;
342 unsigned long flags;
343 287
344 DBG ("maceisa enable: %u\n", irq); 288 DBG ("maceisa enable: %u\n", irq);
345 289
@@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq)
355 break; 299 break;
356 } 300 }
357 DBG ("crime_int %08x enabled\n", crime_int); 301 DBG ("crime_int %08x enabled\n", crime_int);
358 spin_lock_irqsave(&ip32_irq_lock, flags);
359 crime_mask |= crime_int; 302 crime_mask |= crime_int;
360 crime->imask = crime_mask; 303 crime->imask = crime_mask;
361 maceisa_mask |= 1 << (irq - 33); 304 maceisa_mask |= 1 << (irq - 33);
362 mace->perif.ctrl.imask = maceisa_mask; 305 mace->perif.ctrl.imask = maceisa_mask;
363 spin_unlock_irqrestore(&ip32_irq_lock, flags);
364}
365
366static unsigned int startup_maceisa_irq(unsigned int irq)
367{
368 enable_maceisa_irq(irq);
369 return 0;
370} 306}
371 307
372static void disable_maceisa_irq(unsigned int irq) 308static void disable_maceisa_irq(unsigned int irq)
373{ 309{
374 unsigned int crime_int = 0; 310 unsigned int crime_int = 0;
375 unsigned long flags;
376 311
377 spin_lock_irqsave(&ip32_irq_lock, flags);
378 maceisa_mask &= ~(1 << (irq - 33)); 312 maceisa_mask &= ~(1 << (irq - 33));
379 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 313 if(!(maceisa_mask & MACEISA_AUDIO_INT))
380 crime_int |= MACE_AUDIO_INT; 314 crime_int |= MACE_AUDIO_INT;
@@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq)
387 flush_crime_bus(); 321 flush_crime_bus();
388 mace->perif.ctrl.imask = maceisa_mask; 322 mace->perif.ctrl.imask = maceisa_mask;
389 flush_mace_bus(); 323 flush_mace_bus();
390 spin_unlock_irqrestore(&ip32_irq_lock, flags);
391} 324}
392 325
393static void mask_and_ack_maceisa_irq(unsigned int irq) 326static void mask_and_ack_maceisa_irq(unsigned int irq)
394{ 327{
395 unsigned long mace_int, flags; 328 unsigned long mace_int;
396 329
397 switch (irq) { 330 switch (irq) {
398 case MACEISA_PARALLEL_IRQ: 331 case MACEISA_PARALLEL_IRQ:
399 case MACEISA_SERIAL1_TDMAPR_IRQ: 332 case MACEISA_SERIAL1_TDMAPR_IRQ:
400 case MACEISA_SERIAL2_TDMAPR_IRQ: 333 case MACEISA_SERIAL2_TDMAPR_IRQ:
401 /* edge triggered */ 334 /* edge triggered */
402 spin_lock_irqsave(&ip32_irq_lock, flags);
403 mace_int = mace->perif.ctrl.istat; 335 mace_int = mace->perif.ctrl.istat;
404 mace_int &= ~(1 << (irq - 33)); 336 mace_int &= ~(1 << (irq - 33));
405 mace->perif.ctrl.istat = mace_int; 337 mace->perif.ctrl.istat = mace_int;
406 spin_unlock_irqrestore(&ip32_irq_lock, flags);
407 break; 338 break;
408 } 339 }
409 disable_maceisa_irq(irq); 340 disable_maceisa_irq(irq);
@@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq)
415 enable_maceisa_irq(irq); 346 enable_maceisa_irq(irq);
416} 347}
417 348
418#define shutdown_maceisa_irq disable_maceisa_irq
419
420static struct irq_chip ip32_maceisa_interrupt = { 349static struct irq_chip ip32_maceisa_interrupt = {
421 .typename = "IP32 MACE ISA", 350 .typename = "IP32 MACE ISA",
422 .startup = startup_maceisa_irq,
423 .shutdown = shutdown_maceisa_irq,
424 .enable = enable_maceisa_irq,
425 .disable = disable_maceisa_irq,
426 .ack = mask_and_ack_maceisa_irq, 351 .ack = mask_and_ack_maceisa_irq,
352 .mask = disable_maceisa_irq,
353 .mask_ack = mask_and_ack_maceisa_irq,
354 .unmask = enable_maceisa_irq,
427 .end = end_maceisa_irq, 355 .end = end_maceisa_irq,
428}; 356};
429 357
@@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = {
433 361
434static void enable_mace_irq(unsigned int irq) 362static void enable_mace_irq(unsigned int irq)
435{ 363{
436 unsigned long flags;
437
438 spin_lock_irqsave(&ip32_irq_lock, flags);
439 crime_mask |= 1 << (irq - 1); 364 crime_mask |= 1 << (irq - 1);
440 crime->imask = crime_mask; 365 crime->imask = crime_mask;
441 spin_unlock_irqrestore(&ip32_irq_lock, flags);
442}
443
444static unsigned int startup_mace_irq(unsigned int irq)
445{
446 enable_mace_irq(irq);
447 return 0;
448} 366}
449 367
450static void disable_mace_irq(unsigned int irq) 368static void disable_mace_irq(unsigned int irq)
451{ 369{
452 unsigned long flags;
453
454 spin_lock_irqsave(&ip32_irq_lock, flags);
455 crime_mask &= ~(1 << (irq - 1)); 370 crime_mask &= ~(1 << (irq - 1));
456 crime->imask = crime_mask; 371 crime->imask = crime_mask;
457 flush_crime_bus(); 372 flush_crime_bus();
458 spin_unlock_irqrestore(&ip32_irq_lock, flags);
459} 373}
460 374
461static void end_mace_irq(unsigned int irq) 375static void end_mace_irq(unsigned int irq)
@@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq)
464 enable_mace_irq(irq); 378 enable_mace_irq(irq);
465} 379}
466 380
467#define shutdown_mace_irq disable_mace_irq
468#define mask_and_ack_mace_irq disable_mace_irq
469
470static struct irq_chip ip32_mace_interrupt = { 381static struct irq_chip ip32_mace_interrupt = {
471 .typename = "IP32 MACE", 382 .typename = "IP32 MACE",
472 .startup = startup_mace_irq, 383 .ack = disable_mace_irq,
473 .shutdown = shutdown_mace_irq, 384 .mask = disable_mace_irq,
474 .enable = enable_mace_irq, 385 .mask_ack = disable_mace_irq,
475 .disable = disable_mace_irq, 386 .unmask = enable_mace_irq,
476 .ack = mask_and_ack_mace_irq,
477 .end = end_mace_irq, 387 .end = end_mace_irq,
478}; 388};
479 389
@@ -586,10 +496,7 @@ void __init arch_init_irq(void)
586 else 496 else
587 controller = &ip32_maceisa_interrupt; 497 controller = &ip32_maceisa_interrupt;
588 498
589 irq_desc[irq].status = IRQ_DISABLED; 499 set_irq_chip(irq, controller);
590 irq_desc[irq].action = 0;
591 irq_desc[irq].depth = 0;
592 irq_desc[irq].chip = controller;
593 } 500 }
594 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 501 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
595 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 502 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 8b1f41484923..2e8f6b2e2420 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -45,11 +45,9 @@
45 */ 45 */
46 46
47 47
48#define shutdown_bcm1480_irq disable_bcm1480_irq
49static void end_bcm1480_irq(unsigned int irq); 48static void end_bcm1480_irq(unsigned int irq);
50static void enable_bcm1480_irq(unsigned int irq); 49static void enable_bcm1480_irq(unsigned int irq);
51static void disable_bcm1480_irq(unsigned int irq); 50static void disable_bcm1480_irq(unsigned int irq);
52static unsigned int startup_bcm1480_irq(unsigned int irq);
53static void ack_bcm1480_irq(unsigned int irq); 51static void ack_bcm1480_irq(unsigned int irq);
54#ifdef CONFIG_SMP 52#ifdef CONFIG_SMP
55static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); 53static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
@@ -85,11 +83,10 @@ extern char sb1250_duart_present[];
85 83
86static struct irq_chip bcm1480_irq_type = { 84static struct irq_chip bcm1480_irq_type = {
87 .typename = "BCM1480-IMR", 85 .typename = "BCM1480-IMR",
88 .startup = startup_bcm1480_irq,
89 .shutdown = shutdown_bcm1480_irq,
90 .enable = enable_bcm1480_irq,
91 .disable = disable_bcm1480_irq,
92 .ack = ack_bcm1480_irq, 86 .ack = ack_bcm1480_irq,
87 .mask = disable_bcm1480_irq,
88 .mask_ack = ack_bcm1480_irq,
89 .unmask = enable_bcm1480_irq,
93 .end = end_bcm1480_irq, 90 .end = end_bcm1480_irq,
94#ifdef CONFIG_SMP 91#ifdef CONFIG_SMP
95 .set_affinity = bcm1480_set_affinity 92 .set_affinity = bcm1480_set_affinity
@@ -188,14 +185,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
188 185
189/*****************************************************************************/ 186/*****************************************************************************/
190 187
191static unsigned int startup_bcm1480_irq(unsigned int irq)
192{
193 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
194
195 return 0; /* never anything pending */
196}
197
198
199static void disable_bcm1480_irq(unsigned int irq) 188static void disable_bcm1480_irq(unsigned int irq)
200{ 189{
201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 190 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
@@ -270,16 +259,9 @@ void __init init_bcm1480_irqs(void)
270{ 259{
271 int i; 260 int i;
272 261
273 for (i = 0; i < NR_IRQS; i++) { 262 for (i = 0; i < BCM1480_NR_IRQS; i++) {
274 irq_desc[i].status = IRQ_DISABLED; 263 set_irq_chip(i, &bcm1480_irq_type);
275 irq_desc[i].action = 0; 264 bcm1480_irq_owner[i] = 0;
276 irq_desc[i].depth = 1;
277 if (i < BCM1480_NR_IRQS) {
278 irq_desc[i].chip = &bcm1480_irq_type;
279 bcm1480_irq_owner[i] = 0;
280 } else {
281 irq_desc[i].chip = &no_irq_chip;
282 }
283 } 265 }
284} 266}
285 267
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index e136bde5248e..6f3f71bf4244 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -94,8 +94,6 @@ void bcm1480_time_init(void)
94 */ 94 */
95} 95}
96 96
97#include <asm/sibyte/sb1250.h>
98
99void bcm1480_timer_interrupt(void) 97void bcm1480_timer_interrupt(void)
100{ 98{
101 int cpu = smp_processor_id(); 99 int cpu = smp_processor_id();
@@ -119,7 +117,7 @@ void bcm1480_timer_interrupt(void)
119 } 117 }
120} 118}
121 119
122static unsigned int bcm1480_hpt_read(void) 120static cycle_t bcm1480_hpt_read(void)
123{ 121{
124 /* We assume this function is called xtime_lock held. */ 122 /* We assume this function is called xtime_lock held. */
125 unsigned long count = 123 unsigned long count =
@@ -129,6 +127,6 @@ static unsigned int bcm1480_hpt_read(void)
129 127
130void __init bcm1480_hpt_setup(void) 128void __init bcm1480_hpt_setup(void)
131{ 129{
132 mips_hpt_read = bcm1480_hpt_read; 130 clocksource_mips.read = bcm1480_hpt_read;
133 mips_hpt_frequency = BCM1480_HPT_VALUE; 131 mips_hpt_frequency = BCM1480_HPT_VALUE;
134} 132}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index d5d26770daf6..82ce7533053f 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -44,11 +44,9 @@
44 */ 44 */
45 45
46 46
47#define shutdown_sb1250_irq disable_sb1250_irq
48static void end_sb1250_irq(unsigned int irq); 47static void end_sb1250_irq(unsigned int irq);
49static void enable_sb1250_irq(unsigned int irq); 48static void enable_sb1250_irq(unsigned int irq);
50static void disable_sb1250_irq(unsigned int irq); 49static void disable_sb1250_irq(unsigned int irq);
51static unsigned int startup_sb1250_irq(unsigned int irq);
52static void ack_sb1250_irq(unsigned int irq); 50static void ack_sb1250_irq(unsigned int irq);
53#ifdef CONFIG_SMP 51#ifdef CONFIG_SMP
54static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); 52static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
@@ -70,11 +68,10 @@ extern char sb1250_duart_present[];
70 68
71static struct irq_chip sb1250_irq_type = { 69static struct irq_chip sb1250_irq_type = {
72 .typename = "SB1250-IMR", 70 .typename = "SB1250-IMR",
73 .startup = startup_sb1250_irq,
74 .shutdown = shutdown_sb1250_irq,
75 .enable = enable_sb1250_irq,
76 .disable = disable_sb1250_irq,
77 .ack = ack_sb1250_irq, 71 .ack = ack_sb1250_irq,
72 .mask = disable_sb1250_irq,
73 .mask_ack = ack_sb1250_irq,
74 .unmask = enable_sb1250_irq,
78 .end = end_sb1250_irq, 75 .end = end_sb1250_irq,
79#ifdef CONFIG_SMP 76#ifdef CONFIG_SMP
80 .set_affinity = sb1250_set_affinity 77 .set_affinity = sb1250_set_affinity
@@ -163,14 +160,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
163 160
164/*****************************************************************************/ 161/*****************************************************************************/
165 162
166static unsigned int startup_sb1250_irq(unsigned int irq)
167{
168 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
169
170 return 0; /* never anything pending */
171}
172
173
174static void disable_sb1250_irq(unsigned int irq) 163static void disable_sb1250_irq(unsigned int irq)
175{ 164{
176 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 165 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
@@ -239,16 +228,9 @@ void __init init_sb1250_irqs(void)
239{ 228{
240 int i; 229 int i;
241 230
242 for (i = 0; i < NR_IRQS; i++) { 231 for (i = 0; i < SB1250_NR_IRQS; i++) {
243 irq_desc[i].status = IRQ_DISABLED; 232 set_irq_chip(i, &sb1250_irq_type);
244 irq_desc[i].action = 0; 233 sb1250_irq_owner[i] = 0;
245 irq_desc[i].depth = 1;
246 if (i < SB1250_NR_IRQS) {
247 irq_desc[i].chip = &sb1250_irq_type;
248 sb1250_irq_owner[i] = 0;
249 } else {
250 irq_desc[i].chip = &no_irq_chip;
251 }
252 } 234 }
253} 235}
254 236
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index bcb74f2c1948..2efffe15ff23 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -51,7 +51,7 @@
51 51
52extern int sb1250_steal_irq(int irq); 52extern int sb1250_steal_irq(int irq);
53 53
54static unsigned int sb1250_hpt_read(void); 54static cycle_t sb1250_hpt_read(void);
55 55
56void __init sb1250_hpt_setup(void) 56void __init sb1250_hpt_setup(void)
57{ 57{
@@ -66,8 +66,8 @@ void __init sb1250_hpt_setup(void)
66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
67 67
68 mips_hpt_frequency = V_SCD_TIMER_FREQ; 68 mips_hpt_frequency = V_SCD_TIMER_FREQ;
69 mips_hpt_read = sb1250_hpt_read; 69 clocksource_mips.read = sb1250_hpt_read;
70 mips_hpt_mask = M_SCD_TIMER_INIT; 70 clocksource_mips.mask = M_SCD_TIMER_INIT;
71 } 71 }
72} 72}
73 73
@@ -143,7 +143,7 @@ void sb1250_timer_interrupt(void)
143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
144 * again. 144 * again.
145 */ 145 */
146static unsigned int sb1250_hpt_read(void) 146static cycle_t sb1250_hpt_read(void)
147{ 147{
148 unsigned int count; 148 unsigned int count;
149 149
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index ac342f5643c9..defa1f1452ad 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -43,7 +43,7 @@
43#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 43#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
44#include <asm/sibyte/sb1250_regs.h> 44#include <asm/sibyte/sb1250_regs.h>
45#else 45#else
46#error invalid SiByte board configuation 46#error invalid SiByte board configuration
47#endif 47#endif
48#include <asm/sibyte/sb1250_genbus.h> 48#include <asm/sibyte/sb1250_genbus.h>
49#include <asm/sibyte/board.h> 49#include <asm/sibyte/board.h>
@@ -53,7 +53,7 @@ extern void bcm1480_setup(void);
53#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 53#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
54extern void sb1250_setup(void); 54extern void sb1250_setup(void);
55#else 55#else
56#error invalid SiByte board configuation 56#error invalid SiByte board configuration
57#endif 57#endif
58 58
59extern int xicor_probe(void); 59extern int xicor_probe(void);
@@ -90,7 +90,7 @@ void __init plat_timer_setup(struct irqaction *irq)
90#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 90#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
91 sb1250_time_init(); 91 sb1250_time_init();
92#else 92#else
93#error invalid SiByte board configuation 93#error invalid SiByte board configuration
94#endif 94#endif
95} 95}
96 96
@@ -111,7 +111,7 @@ void __init plat_mem_setup(void)
111#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 111#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
112 sb1250_setup(); 112 sb1250_setup();
113#else 113#else
114#error invalid SiByte board configuation 114#error invalid SiByte board configuration
115#endif 115#endif
116 116
117 panic_timeout = 5; /* For debug. */ 117 panic_timeout = 5; /* For debug. */
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 48fb74a7aaec..8511bcc6d99d 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -11,44 +11,25 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15 14
16#include <asm/i8259.h> 15#include <asm/i8259.h>
17#include <asm/io.h> 16#include <asm/io.h>
18#include <asm/sni.h> 17#include <asm/sni.h>
19 18
20DEFINE_SPINLOCK(pciasic_lock);
21
22static void enable_pciasic_irq(unsigned int irq) 19static void enable_pciasic_irq(unsigned int irq)
23{ 20{
24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 21 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
25 unsigned long flags;
26 22
27 spin_lock_irqsave(&pciasic_lock, flags);
28 *(volatile u8 *) PCIMT_IRQSEL |= mask; 23 *(volatile u8 *) PCIMT_IRQSEL |= mask;
29 spin_unlock_irqrestore(&pciasic_lock, flags);
30}
31
32static unsigned int startup_pciasic_irq(unsigned int irq)
33{
34 enable_pciasic_irq(irq);
35 return 0; /* never anything pending */
36} 24}
37 25
38#define shutdown_pciasic_irq disable_pciasic_irq
39
40void disable_pciasic_irq(unsigned int irq) 26void disable_pciasic_irq(unsigned int irq)
41{ 27{
42 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 28 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
43 unsigned long flags;
44 29
45 spin_lock_irqsave(&pciasic_lock, flags);
46 *(volatile u8 *) PCIMT_IRQSEL &= mask; 30 *(volatile u8 *) PCIMT_IRQSEL &= mask;
47 spin_unlock_irqrestore(&pciasic_lock, flags);
48} 31}
49 32
50#define mask_and_ack_pciasic_irq disable_pciasic_irq
51
52static void end_pciasic_irq(unsigned int irq) 33static void end_pciasic_irq(unsigned int irq)
53{ 34{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 35 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +38,10 @@ static void end_pciasic_irq(unsigned int irq)
57 38
58static struct irq_chip pciasic_irq_type = { 39static struct irq_chip pciasic_irq_type = {
59 .typename = "ASIC-PCI", 40 .typename = "ASIC-PCI",
60 .startup = startup_pciasic_irq, 41 .ack = disable_pciasic_irq,
61 .shutdown = shutdown_pciasic_irq, 42 .mask = disable_pciasic_irq,
62 .enable = enable_pciasic_irq, 43 .mask_ack = disable_pciasic_irq,
63 .disable = disable_pciasic_irq, 44 .unmask = enable_pciasic_irq,
64 .ack = mask_and_ack_pciasic_irq,
65 .end = end_pciasic_irq, 45 .end = end_pciasic_irq,
66}; 46};
67 47
@@ -178,12 +158,8 @@ asmlinkage void plat_irq_dispatch(void)
178 158
179void __init init_pciasic(void) 159void __init init_pciasic(void)
180{ 160{
181 unsigned long flags;
182
183 spin_lock_irqsave(&pciasic_lock, flags);
184 * (volatile u8 *) PCIMT_IRQSEL = 161 * (volatile u8 *) PCIMT_IRQSEL =
185 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 162 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
186 spin_unlock_irqrestore(&pciasic_lock, flags);
187} 163}
188 164
189/* 165/*
@@ -199,12 +175,8 @@ void __init arch_init_irq(void)
199 init_pciasic(); 175 init_pciasic();
200 176
201 /* Actually we've got more interrupts to handle ... */ 177 /* Actually we've got more interrupts to handle ... */
202 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { 178 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
203 irq_desc[i].status = IRQ_DISABLED; 179 set_irq_chip(i, &pciasic_irq_type);
204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1;
206 irq_desc[i].chip = &pciasic_irq_type;
207 }
208 180
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 181 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
210} 182}
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 8266a88a3f88..ed4a19adf361 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -64,20 +64,12 @@
64#define TX4927_IRQ_NEST4 ( 1 << 9 ) 64#define TX4927_IRQ_NEST4 ( 1 << 9 )
65 65
66#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) 66#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
67#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
68#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
69#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) 67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
70#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) 68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
71#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
72#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
73 69
74#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) 70#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
75#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
76#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
77#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) 71#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
78#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) 72#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
79#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
80#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
81 73
82#define TX4927_IRQ_ALL 0xffffffff 74#define TX4927_IRQ_ALL 0xffffffff
83#endif 75#endif
@@ -87,19 +79,11 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
87 | TX4927_IRQ_INFO 79 | TX4927_IRQ_INFO
88 | TX4927_IRQ_WARN | TX4927_IRQ_EROR 80 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
89// | TX4927_IRQ_CP0_INIT 81// | TX4927_IRQ_CP0_INIT
90// | TX4927_IRQ_CP0_STARTUP
91// | TX4927_IRQ_CP0_SHUTDOWN
92// | TX4927_IRQ_CP0_ENABLE 82// | TX4927_IRQ_CP0_ENABLE
93// | TX4927_IRQ_CP0_DISABLE
94// | TX4927_IRQ_CP0_MASK
95// | TX4927_IRQ_CP0_ENDIRQ 83// | TX4927_IRQ_CP0_ENDIRQ
96// | TX4927_IRQ_PIC_INIT 84// | TX4927_IRQ_PIC_INIT
97// | TX4927_IRQ_PIC_STARTUP
98// | TX4927_IRQ_PIC_SHUTDOWN
99// | TX4927_IRQ_PIC_ENABLE 85// | TX4927_IRQ_PIC_ENABLE
100// | TX4927_IRQ_PIC_DISABLE 86// | TX4927_IRQ_PIC_DISABLE
101// | TX4927_IRQ_PIC_MASK
102// | TX4927_IRQ_PIC_ENDIRQ
103// | TX4927_IRQ_INIT 87// | TX4927_IRQ_INIT
104// | TX4927_IRQ_NEST1 88// | TX4927_IRQ_NEST1
105// | TX4927_IRQ_NEST2 89// | TX4927_IRQ_NEST2
@@ -124,49 +108,32 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
124 * Forwad definitions for all pic's 108 * Forwad definitions for all pic's
125 */ 109 */
126 110
127static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
128static void tx4927_irq_cp0_shutdown(unsigned int irq);
129static void tx4927_irq_cp0_enable(unsigned int irq); 111static void tx4927_irq_cp0_enable(unsigned int irq);
130static void tx4927_irq_cp0_disable(unsigned int irq); 112static void tx4927_irq_cp0_disable(unsigned int irq);
131static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
132static void tx4927_irq_cp0_end(unsigned int irq);
133 113
134static unsigned int tx4927_irq_pic_startup(unsigned int irq);
135static void tx4927_irq_pic_shutdown(unsigned int irq);
136static void tx4927_irq_pic_enable(unsigned int irq); 114static void tx4927_irq_pic_enable(unsigned int irq);
137static void tx4927_irq_pic_disable(unsigned int irq); 115static void tx4927_irq_pic_disable(unsigned int irq);
138static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
139static void tx4927_irq_pic_end(unsigned int irq);
140 116
141/* 117/*
142 * Kernel structs for all pic's 118 * Kernel structs for all pic's
143 */ 119 */
144 120
145static DEFINE_SPINLOCK(tx4927_cp0_lock);
146static DEFINE_SPINLOCK(tx4927_pic_lock);
147
148#define TX4927_CP0_NAME "TX4927-CP0" 121#define TX4927_CP0_NAME "TX4927-CP0"
149static struct irq_chip tx4927_irq_cp0_type = { 122static struct irq_chip tx4927_irq_cp0_type = {
150 .typename = TX4927_CP0_NAME, 123 .typename = TX4927_CP0_NAME,
151 .startup = tx4927_irq_cp0_startup, 124 .ack = tx4927_irq_cp0_disable,
152 .shutdown = tx4927_irq_cp0_shutdown, 125 .mask = tx4927_irq_cp0_disable,
153 .enable = tx4927_irq_cp0_enable, 126 .mask_ack = tx4927_irq_cp0_disable,
154 .disable = tx4927_irq_cp0_disable, 127 .unmask = tx4927_irq_cp0_enable,
155 .ack = tx4927_irq_cp0_mask_and_ack,
156 .end = tx4927_irq_cp0_end,
157 .set_affinity = NULL
158}; 128};
159 129
160#define TX4927_PIC_NAME "TX4927-PIC" 130#define TX4927_PIC_NAME "TX4927-PIC"
161static struct irq_chip tx4927_irq_pic_type = { 131static struct irq_chip tx4927_irq_pic_type = {
162 .typename = TX4927_PIC_NAME, 132 .typename = TX4927_PIC_NAME,
163 .startup = tx4927_irq_pic_startup, 133 .ack = tx4927_irq_pic_disable,
164 .shutdown = tx4927_irq_pic_shutdown, 134 .mask = tx4927_irq_pic_disable,
165 .enable = tx4927_irq_pic_enable, 135 .mask_ack = tx4927_irq_pic_disable,
166 .disable = tx4927_irq_pic_disable, 136 .unmask = tx4927_irq_pic_enable,
167 .ack = tx4927_irq_pic_mask_and_ack,
168 .end = tx4927_irq_pic_end,
169 .set_affinity = NULL
170}; 137};
171 138
172#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 139#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
@@ -211,8 +178,6 @@ tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
211 break; 178 break;
212 } 179 }
213 } 180 }
214
215 return;
216} 181}
217 182
218static void __init tx4927_irq_cp0_init(void) 183static void __init tx4927_irq_cp0_init(void)
@@ -222,82 +187,23 @@ static void __init tx4927_irq_cp0_init(void)
222 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", 187 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
223 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); 188 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
224 189
225 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { 190 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
226 irq_desc[i].status = IRQ_DISABLED; 191 set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
227 irq_desc[i].action = 0; 192 handle_level_irq);
228 irq_desc[i].depth = 1;
229 irq_desc[i].chip = &tx4927_irq_cp0_type;
230 }
231
232 return;
233}
234
235static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
236{
237 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
238
239 tx4927_irq_cp0_enable(irq);
240
241 return (0);
242}
243
244static void tx4927_irq_cp0_shutdown(unsigned int irq)
245{
246 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
247
248 tx4927_irq_cp0_disable(irq);
249
250 return;
251} 193}
252 194
253static void tx4927_irq_cp0_enable(unsigned int irq) 195static void tx4927_irq_cp0_enable(unsigned int irq)
254{ 196{
255 unsigned long flags;
256
257 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); 197 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
258 198
259 spin_lock_irqsave(&tx4927_cp0_lock, flags);
260
261 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); 199 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
262
263 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
264
265 return;
266} 200}
267 201
268static void tx4927_irq_cp0_disable(unsigned int irq) 202static void tx4927_irq_cp0_disable(unsigned int irq)
269{ 203{
270 unsigned long flags;
271
272 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); 204 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
273 205
274 spin_lock_irqsave(&tx4927_cp0_lock, flags);
275
276 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); 206 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
277
278 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
279
280 return;
281}
282
283static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
284{
285 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
286
287 tx4927_irq_cp0_disable(irq);
288
289 return;
290}
291
292static void tx4927_irq_cp0_end(unsigned int irq)
293{
294 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENDIRQ, "irq=%d \n", irq);
295
296 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
297 tx4927_irq_cp0_enable(irq);
298 }
299
300 return;
301} 207}
302 208
303/* 209/*
@@ -418,105 +324,39 @@ static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
418 val &= (~clr_bits); 324 val &= (~clr_bits);
419 val |= (set_bits); 325 val |= (set_bits);
420 TX4927_WR(pic_reg, val); 326 TX4927_WR(pic_reg, val);
421
422 return;
423} 327}
424 328
425static void __init tx4927_irq_pic_init(void) 329static void __init tx4927_irq_pic_init(void)
426{ 330{
427 unsigned long flags;
428 int i; 331 int i;
429 332
430 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", 333 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
431 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); 334 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
432 335
433 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { 336 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
434 irq_desc[i].status = IRQ_DISABLED; 337 set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
435 irq_desc[i].action = 0; 338 handle_level_irq);
436 irq_desc[i].depth = 2;
437 irq_desc[i].chip = &tx4927_irq_pic_type;
438 }
439 339
440 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); 340 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
441 341
442 spin_lock_irqsave(&tx4927_pic_lock, flags);
443
444 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 342 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
445 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ 343 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
446
447 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
448
449 return;
450}
451
452static unsigned int tx4927_irq_pic_startup(unsigned int irq)
453{
454 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
455
456 tx4927_irq_pic_enable(irq);
457
458 return (0);
459}
460
461static void tx4927_irq_pic_shutdown(unsigned int irq)
462{
463 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
464
465 tx4927_irq_pic_disable(irq);
466
467 return;
468} 344}
469 345
470static void tx4927_irq_pic_enable(unsigned int irq) 346static void tx4927_irq_pic_enable(unsigned int irq)
471{ 347{
472 unsigned long flags;
473
474 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); 348 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
475 349
476 spin_lock_irqsave(&tx4927_pic_lock, flags);
477
478 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, 350 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
479 tx4927_irq_pic_mask(irq)); 351 tx4927_irq_pic_mask(irq));
480
481 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
482
483 return;
484} 352}
485 353
486static void tx4927_irq_pic_disable(unsigned int irq) 354static void tx4927_irq_pic_disable(unsigned int irq)
487{ 355{
488 unsigned long flags;
489
490 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); 356 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
491 357
492 spin_lock_irqsave(&tx4927_pic_lock, flags);
493
494 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 358 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
495 tx4927_irq_pic_mask(irq), 0); 359 tx4927_irq_pic_mask(irq), 0);
496
497 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
498
499 return;
500}
501
502static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
503{
504 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
505
506 tx4927_irq_pic_disable(irq);
507
508 return;
509}
510
511static void tx4927_irq_pic_end(unsigned int irq)
512{
513 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENDIRQ, "irq=%d\n", irq);
514
515 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
516 tx4927_irq_pic_enable(irq);
517 }
518
519 return;
520} 360}
521 361
522/* 362/*
@@ -533,8 +373,6 @@ void __init tx4927_irq_init(void)
533 tx4927_irq_pic_init(); 373 tx4927_irq_pic_init();
534 374
535 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); 375 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
536
537 return;
538} 376}
539 377
540static int tx4927_irq_nested(void) 378static int tx4927_irq_nested(void)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 0c3c3f668230..b54b529a29f9 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -151,20 +151,13 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) 151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
152 152
153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
157#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
158#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
159#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
160 156
161#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 157#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
162#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
163#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
164#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 158#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
165#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) 159#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
166#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) 160#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
167#define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ ( 1 << 26 )
168 161
169#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff 162#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
170#endif 163#endif
@@ -175,19 +168,12 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
175 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 168 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
176 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 169 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
177// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 170// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
178// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
179// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
180// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 171// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
181// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 172// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
183// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
184// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 173// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
185// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
186// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
187// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 174// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
188// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 175// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 176// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
190// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
191 ); 177 );
192#endif 178#endif
193 179
@@ -231,35 +217,22 @@ extern void disable_8259A_irq(unsigned int irq);
231extern void mask_and_ack_8259A(unsigned int irq); 217extern void mask_and_ack_8259A(unsigned int irq);
232#endif 218#endif
233 219
234static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
235static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
236static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 220static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
237static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 221static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
238static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
239static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
240 222
241#ifdef CONFIG_TOSHIBA_FPCIB0 223#ifdef CONFIG_TOSHIBA_FPCIB0
242static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
243static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
244static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 224static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
245static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); 225static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
246static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); 226static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
247static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
248#endif 227#endif
249 228
250static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
251
252
253#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 229#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
254static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 230static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
255 .typename = TOSHIBA_RBTX4927_IOC_NAME, 231 .typename = TOSHIBA_RBTX4927_IOC_NAME,
256 .startup = toshiba_rbtx4927_irq_ioc_startup, 232 .ack = toshiba_rbtx4927_irq_ioc_disable,
257 .shutdown = toshiba_rbtx4927_irq_ioc_shutdown, 233 .mask = toshiba_rbtx4927_irq_ioc_disable,
258 .enable = toshiba_rbtx4927_irq_ioc_enable, 234 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
259 .disable = toshiba_rbtx4927_irq_ioc_disable, 235 .unmask = toshiba_rbtx4927_irq_ioc_enable,
260 .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
261 .end = toshiba_rbtx4927_irq_ioc_end,
262 .set_affinity = NULL
263}; 236};
264#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 237#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
265#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 238#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
@@ -269,13 +242,10 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
269#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" 242#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
270static struct irq_chip toshiba_rbtx4927_irq_isa_type = { 243static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
271 .typename = TOSHIBA_RBTX4927_ISA_NAME, 244 .typename = TOSHIBA_RBTX4927_ISA_NAME,
272 .startup = toshiba_rbtx4927_irq_isa_startup,
273 .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
274 .enable = toshiba_rbtx4927_irq_isa_enable,
275 .disable = toshiba_rbtx4927_irq_isa_disable,
276 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 245 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
277 .end = toshiba_rbtx4927_irq_isa_end, 246 .mask = toshiba_rbtx4927_irq_isa_disable,
278 .set_affinity = NULL 247 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
248 .unmask = toshiba_rbtx4927_irq_isa_enable,
279}; 249};
280#endif 250#endif
281 251
@@ -363,58 +333,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
363 TOSHIBA_RBTX4927_IRQ_IOC_END); 333 TOSHIBA_RBTX4927_IRQ_IOC_END);
364 334
365 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 335 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
366 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { 336 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
367 irq_desc[i].status = IRQ_DISABLED; 337 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
368 irq_desc[i].action = 0; 338 handle_level_irq);
369 irq_desc[i].depth = 3;
370 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
371 }
372 339
373 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 340 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
374 &toshiba_rbtx4927_irq_ioc_action); 341 &toshiba_rbtx4927_irq_ioc_action);
375
376 return;
377}
378
379static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
380{
381 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
382 "irq=%d\n", irq);
383
384 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
385 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
386 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
387 "bad irq=%d\n", irq);
388 panic("\n");
389 }
390
391 toshiba_rbtx4927_irq_ioc_enable(irq);
392
393 return (0);
394}
395
396
397static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
398{
399 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
400 "irq=%d\n", irq);
401
402 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
403 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
404 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
405 "bad irq=%d\n", irq);
406 panic("\n");
407 }
408
409 toshiba_rbtx4927_irq_ioc_disable(irq);
410
411 return;
412} 342}
413 343
414
415static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 344static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
416{ 345{
417 unsigned long flags;
418 volatile unsigned char v; 346 volatile unsigned char v;
419 347
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, 348 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
@@ -427,21 +355,14 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
427 panic("\n"); 355 panic("\n");
428 } 356 }
429 357
430 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
431
432 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 358 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
433 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 359 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
434 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 360 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
435
436 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
437
438 return;
439} 361}
440 362
441 363
442static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 364static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
443{ 365{
444 unsigned long flags;
445 volatile unsigned char v; 366 volatile unsigned char v;
446 367
447 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, 368 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
@@ -454,53 +375,9 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
454 panic("\n"); 375 panic("\n");
455 } 376 }
456 377
457 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
458
459 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 378 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
460 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 379 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
461 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 380 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
462
463 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
464
465 return;
466}
467
468
469static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
470{
471 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
472 "irq=%d\n", irq);
473
474 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
475 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
477 "bad irq=%d\n", irq);
478 panic("\n");
479 }
480
481 toshiba_rbtx4927_irq_ioc_disable(irq);
482
483 return;
484}
485
486
487static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
488{
489 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
490 "irq=%d\n", irq);
491
492 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
493 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
494 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
495 "bad irq=%d\n", irq);
496 panic("\n");
497 }
498
499 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
500 toshiba_rbtx4927_irq_ioc_enable(irq);
501 }
502
503 return;
504} 381}
505 382
506 383
@@ -520,13 +397,9 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
520 TOSHIBA_RBTX4927_IRQ_ISA_END); 397 TOSHIBA_RBTX4927_IRQ_ISA_END);
521 398
522 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; 399 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
523 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { 400 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
524 irq_desc[i].status = IRQ_DISABLED; 401 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_isa_type,
525 irq_desc[i].action = 0; 402 handle_level_irq);
526 irq_desc[i].depth =
527 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
528 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
529 }
530 403
531 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 404 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
532 &toshiba_rbtx4927_irq_isa_master); 405 &toshiba_rbtx4927_irq_isa_master);
@@ -536,48 +409,6 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
536 /* make sure we are looking at IRR (not ISR) */ 409 /* make sure we are looking at IRR (not ISR) */
537 outb(0x0A, 0x20); 410 outb(0x0A, 0x20);
538 outb(0x0A, 0xA0); 411 outb(0x0A, 0xA0);
539
540 return;
541}
542#endif
543
544
545#ifdef CONFIG_TOSHIBA_FPCIB0
546static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
547{
548 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
549 "irq=%d\n", irq);
550
551 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
552 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
553 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
554 "bad irq=%d\n", irq);
555 panic("\n");
556 }
557
558 toshiba_rbtx4927_irq_isa_enable(irq);
559
560 return (0);
561}
562#endif
563
564
565#ifdef CONFIG_TOSHIBA_FPCIB0
566static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
567{
568 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
569 "irq=%d\n", irq);
570
571 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
572 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
574 "bad irq=%d\n", irq);
575 panic("\n");
576 }
577
578 toshiba_rbtx4927_irq_isa_disable(irq);
579
580 return;
581} 412}
582#endif 413#endif
583 414
@@ -596,8 +427,6 @@ static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
596 } 427 }
597 428
598 enable_8259A_irq(irq); 429 enable_8259A_irq(irq);
599
600 return;
601} 430}
602#endif 431#endif
603 432
@@ -616,8 +445,6 @@ static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
616 } 445 }
617 446
618 disable_8259A_irq(irq); 447 disable_8259A_irq(irq);
619
620 return;
621} 448}
622#endif 449#endif
623 450
@@ -636,30 +463,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
636 } 463 }
637 464
638 mask_and_ack_8259A(irq); 465 mask_and_ack_8259A(irq);
639
640 return;
641}
642#endif
643
644
645#ifdef CONFIG_TOSHIBA_FPCIB0
646static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
647{
648 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
649 "irq=%d\n", irq);
650
651 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
652 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
653 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
654 "bad irq=%d\n", irq);
655 panic("\n");
656 }
657
658 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
659 toshiba_rbtx4927_irq_isa_enable(irq);
660 }
661
662 return;
663} 466}
664#endif 467#endif
665 468
@@ -668,8 +471,6 @@ void __init arch_init_irq(void)
668{ 471{
669 extern void tx4927_irq_init(void); 472 extern void tx4927_irq_init(void);
670 473
671 local_irq_disable();
672
673 tx4927_irq_init(); 474 tx4927_irq_init();
674 toshiba_rbtx4927_irq_ioc_init(); 475 toshiba_rbtx4927_irq_ioc_init();
675#ifdef CONFIG_TOSHIBA_FPCIB0 476#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -681,8 +482,6 @@ void __init arch_init_irq(void)
681#endif 482#endif
682 483
683 wbflush(); 484 wbflush();
684
685 return;
686} 485}
687 486
688void toshiba_rbtx4927_irq_dump(char *key) 487void toshiba_rbtx4927_irq_dump(char *key)
@@ -715,7 +514,6 @@ void toshiba_rbtx4927_irq_dump(char *key)
715 } 514 }
716 } 515 }
717#endif 516#endif
718 return;
719} 517}
720 518
721void toshiba_rbtx4927_irq_dump_pics(char *s) 519void toshiba_rbtx4927_irq_dump_pics(char *s)
@@ -780,6 +578,4 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
780 level5_s); 578 level5_s);
781 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", 579 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
782 s); 580 s);
783
784 return;
785} 581}
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 77fe2454f5b9..a347b424d91c 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -37,48 +37,32 @@
37/* Forwad definitions for all pic's */ 37/* Forwad definitions for all pic's */
38/**********************************************************************************/ 38/**********************************************************************************/
39 39
40static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
41static void tx4938_irq_cp0_shutdown(unsigned int irq);
42static void tx4938_irq_cp0_enable(unsigned int irq); 40static void tx4938_irq_cp0_enable(unsigned int irq);
43static void tx4938_irq_cp0_disable(unsigned int irq); 41static void tx4938_irq_cp0_disable(unsigned int irq);
44static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
45static void tx4938_irq_cp0_end(unsigned int irq);
46 42
47static unsigned int tx4938_irq_pic_startup(unsigned int irq);
48static void tx4938_irq_pic_shutdown(unsigned int irq);
49static void tx4938_irq_pic_enable(unsigned int irq); 43static void tx4938_irq_pic_enable(unsigned int irq);
50static void tx4938_irq_pic_disable(unsigned int irq); 44static void tx4938_irq_pic_disable(unsigned int irq);
51static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
52static void tx4938_irq_pic_end(unsigned int irq);
53 45
54/**********************************************************************************/ 46/**********************************************************************************/
55/* Kernel structs for all pic's */ 47/* Kernel structs for all pic's */
56/**********************************************************************************/ 48/**********************************************************************************/
57DEFINE_SPINLOCK(tx4938_cp0_lock);
58DEFINE_SPINLOCK(tx4938_pic_lock);
59 49
60#define TX4938_CP0_NAME "TX4938-CP0" 50#define TX4938_CP0_NAME "TX4938-CP0"
61static struct irq_chip tx4938_irq_cp0_type = { 51static struct irq_chip tx4938_irq_cp0_type = {
62 .typename = TX4938_CP0_NAME, 52 .typename = TX4938_CP0_NAME,
63 .startup = tx4938_irq_cp0_startup, 53 .ack = tx4938_irq_cp0_disable,
64 .shutdown = tx4938_irq_cp0_shutdown, 54 .mask = tx4938_irq_cp0_disable,
65 .enable = tx4938_irq_cp0_enable, 55 .mask_ack = tx4938_irq_cp0_disable,
66 .disable = tx4938_irq_cp0_disable, 56 .unmask = tx4938_irq_cp0_enable,
67 .ack = tx4938_irq_cp0_mask_and_ack,
68 .end = tx4938_irq_cp0_end,
69 .set_affinity = NULL
70}; 57};
71 58
72#define TX4938_PIC_NAME "TX4938-PIC" 59#define TX4938_PIC_NAME "TX4938-PIC"
73static struct irq_chip tx4938_irq_pic_type = { 60static struct irq_chip tx4938_irq_pic_type = {
74 .typename = TX4938_PIC_NAME, 61 .typename = TX4938_PIC_NAME,
75 .startup = tx4938_irq_pic_startup, 62 .ack = tx4938_irq_pic_disable,
76 .shutdown = tx4938_irq_pic_shutdown, 63 .mask = tx4938_irq_pic_disable,
77 .enable = tx4938_irq_pic_enable, 64 .mask_ack = tx4938_irq_pic_disable,
78 .disable = tx4938_irq_pic_disable, 65 .unmask = tx4938_irq_pic_enable,
79 .ack = tx4938_irq_pic_mask_and_ack,
80 .end = tx4938_irq_pic_end,
81 .set_affinity = NULL
82}; 66};
83 67
84static struct irqaction tx4938_irq_pic_action = { 68static struct irqaction tx4938_irq_pic_action = {
@@ -99,64 +83,21 @@ tx4938_irq_cp0_init(void)
99{ 83{
100 int i; 84 int i;
101 85
102 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { 86 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
103 irq_desc[i].status = IRQ_DISABLED; 87 set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
104 irq_desc[i].action = 0; 88 handle_level_irq);
105 irq_desc[i].depth = 1;
106 irq_desc[i].chip = &tx4938_irq_cp0_type;
107 }
108}
109
110static unsigned int
111tx4938_irq_cp0_startup(unsigned int irq)
112{
113 tx4938_irq_cp0_enable(irq);
114
115 return 0;
116}
117
118static void
119tx4938_irq_cp0_shutdown(unsigned int irq)
120{
121 tx4938_irq_cp0_disable(irq);
122} 89}
123 90
124static void 91static void
125tx4938_irq_cp0_enable(unsigned int irq) 92tx4938_irq_cp0_enable(unsigned int irq)
126{ 93{
127 unsigned long flags;
128
129 spin_lock_irqsave(&tx4938_cp0_lock, flags);
130
131 set_c0_status(tx4938_irq_cp0_mask(irq)); 94 set_c0_status(tx4938_irq_cp0_mask(irq));
132
133 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
134} 95}
135 96
136static void 97static void
137tx4938_irq_cp0_disable(unsigned int irq) 98tx4938_irq_cp0_disable(unsigned int irq)
138{ 99{
139 unsigned long flags;
140
141 spin_lock_irqsave(&tx4938_cp0_lock, flags);
142
143 clear_c0_status(tx4938_irq_cp0_mask(irq)); 100 clear_c0_status(tx4938_irq_cp0_mask(irq));
144
145 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
146}
147
148static void
149tx4938_irq_cp0_mask_and_ack(unsigned int irq)
150{
151 tx4938_irq_cp0_disable(irq);
152}
153
154static void
155tx4938_irq_cp0_end(unsigned int irq)
156{
157 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
158 tx4938_irq_cp0_enable(irq);
159 }
160} 101}
161 102
162/**********************************************************************************/ 103/**********************************************************************************/
@@ -290,78 +231,30 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
290static void __init 231static void __init
291tx4938_irq_pic_init(void) 232tx4938_irq_pic_init(void)
292{ 233{
293 unsigned long flags;
294 int i; 234 int i;
295 235
296 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { 236 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
297 irq_desc[i].status = IRQ_DISABLED; 237 set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
298 irq_desc[i].action = 0; 238 handle_level_irq);
299 irq_desc[i].depth = 2;
300 irq_desc[i].chip = &tx4938_irq_pic_type;
301 }
302 239
303 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); 240 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
304 241
305 spin_lock_irqsave(&tx4938_pic_lock, flags);
306
307 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 242 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
308 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ 243 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
309
310 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
311}
312
313static unsigned int
314tx4938_irq_pic_startup(unsigned int irq)
315{
316 tx4938_irq_pic_enable(irq);
317
318 return 0;
319}
320
321static void
322tx4938_irq_pic_shutdown(unsigned int irq)
323{
324 tx4938_irq_pic_disable(irq);
325} 244}
326 245
327static void 246static void
328tx4938_irq_pic_enable(unsigned int irq) 247tx4938_irq_pic_enable(unsigned int irq)
329{ 248{
330 unsigned long flags;
331
332 spin_lock_irqsave(&tx4938_pic_lock, flags);
333
334 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, 249 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
335 tx4938_irq_pic_mask(irq)); 250 tx4938_irq_pic_mask(irq));
336
337 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
338} 251}
339 252
340static void 253static void
341tx4938_irq_pic_disable(unsigned int irq) 254tx4938_irq_pic_disable(unsigned int irq)
342{ 255{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 256 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
348 tx4938_irq_pic_mask(irq), 0); 257 tx4938_irq_pic_mask(irq), 0);
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351}
352
353static void
354tx4938_irq_pic_mask_and_ack(unsigned int irq)
355{
356 tx4938_irq_pic_disable(irq);
357}
358
359static void
360tx4938_irq_pic_end(unsigned int irq)
361{
362 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
363 tx4938_irq_pic_enable(irq);
364 }
365} 258}
366 259
367/**********************************************************************************/ 260/**********************************************************************************/
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index f415a1f18fba..dc87d92bb08d 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -31,7 +31,6 @@
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/system.h> 32#include <asm/system.h>
33#include <asm/time.h> 33#include <asm/time.h>
34#include <asm/time.h>
35#include <asm/tx4938/rbtx4938.h> 34#include <asm/tx4938/rbtx4938.h>
36 35
37extern void toshiba_rbtx4938_setup(void); 36extern void toshiba_rbtx4938_setup(void);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 102e473c10a2..b6f363d08011 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -87,25 +87,16 @@ IRQ Device
87#include <linux/bootmem.h> 87#include <linux/bootmem.h>
88#include <asm/tx4938/rbtx4938.h> 88#include <asm/tx4938/rbtx4938.h>
89 89
90static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
91static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); 91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
96
97DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
98 92
99#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" 93#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
100static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { 94static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
101 .typename = TOSHIBA_RBTX4938_IOC_NAME, 95 .typename = TOSHIBA_RBTX4938_IOC_NAME,
102 .startup = toshiba_rbtx4938_irq_ioc_startup, 96 .ack = toshiba_rbtx4938_irq_ioc_disable,
103 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, 97 .mask = toshiba_rbtx4938_irq_ioc_disable,
104 .enable = toshiba_rbtx4938_irq_ioc_enable, 98 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
105 .disable = toshiba_rbtx4938_irq_ioc_disable, 99 .unmask = toshiba_rbtx4938_irq_ioc_enable,
106 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
107 .end = toshiba_rbtx4938_irq_ioc_end,
108 .set_affinity = NULL
109}; 100};
110 101
111#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 102#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
@@ -142,77 +133,36 @@ toshiba_rbtx4938_irq_ioc_init(void)
142 int i; 133 int i;
143 134
144 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; 135 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
145 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { 136 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
146 irq_desc[i].status = IRQ_DISABLED; 137 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
147 irq_desc[i].action = 0; 138 handle_level_irq);
148 irq_desc[i].depth = 3;
149 irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
150 }
151 139
152 setup_irq(RBTX4938_IRQ_IOCINT, 140 setup_irq(RBTX4938_IRQ_IOCINT,
153 &toshiba_rbtx4938_irq_ioc_action); 141 &toshiba_rbtx4938_irq_ioc_action);
154} 142}
155 143
156static unsigned int
157toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
158{
159 toshiba_rbtx4938_irq_ioc_enable(irq);
160
161 return 0;
162}
163
164static void
165toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
166{
167 toshiba_rbtx4938_irq_ioc_disable(irq);
168}
169
170static void 144static void
171toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) 145toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
172{ 146{
173 unsigned long flags;
174 volatile unsigned char v; 147 volatile unsigned char v;
175 148
176 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
177
178 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 149 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
179 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 150 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
180 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 151 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
181 mmiowb(); 152 mmiowb();
182 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 153 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
183
184 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
185} 154}
186 155
187static void 156static void
188toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) 157toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
189{ 158{
190 unsigned long flags;
191 volatile unsigned char v; 159 volatile unsigned char v;
192 160
193 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
194
195 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 161 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
196 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 162 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
197 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 163 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
198 mmiowb(); 164 mmiowb();
199 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
200
201 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
202}
203
204static void
205toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
206{
207 toshiba_rbtx4938_irq_ioc_disable(irq);
208}
209
210static void
211toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
212{
213 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
214 toshiba_rbtx4938_irq_ioc_enable(irq);
215 }
216} 166}
217 167
218extern void __init txx9_spi_irqinit(int irc_irq); 168extern void __init txx9_spi_irqinit(int irc_irq);
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index c215c0d39fae..c075261976c5 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -417,14 +417,7 @@ void vr41xx_disable_bcuint(void)
417 417
418EXPORT_SYMBOL(vr41xx_disable_bcuint); 418EXPORT_SYMBOL(vr41xx_disable_bcuint);
419 419
420static unsigned int startup_sysint1_irq(unsigned int irq) 420static void disable_sysint1_irq(unsigned int irq)
421{
422 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
423
424 return 0; /* never anything pending */
425}
426
427static void shutdown_sysint1_irq(unsigned int irq)
428{ 421{
429 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 422 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
430} 423}
@@ -434,33 +427,15 @@ static void enable_sysint1_irq(unsigned int irq)
434 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435} 428}
436 429
437#define disable_sysint1_irq shutdown_sysint1_irq
438#define ack_sysint1_irq shutdown_sysint1_irq
439
440static void end_sysint1_irq(unsigned int irq)
441{
442 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
443 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
444}
445
446static struct irq_chip sysint1_irq_type = { 430static struct irq_chip sysint1_irq_type = {
447 .typename = "SYSINT1", 431 .typename = "SYSINT1",
448 .startup = startup_sysint1_irq, 432 .ack = disable_sysint1_irq,
449 .shutdown = shutdown_sysint1_irq, 433 .mask = disable_sysint1_irq,
450 .enable = enable_sysint1_irq, 434 .mask_ack = disable_sysint1_irq,
451 .disable = disable_sysint1_irq, 435 .unmask = enable_sysint1_irq,
452 .ack = ack_sysint1_irq,
453 .end = end_sysint1_irq,
454}; 436};
455 437
456static unsigned int startup_sysint2_irq(unsigned int irq) 438static void disable_sysint2_irq(unsigned int irq)
457{
458 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459
460 return 0; /* never anything pending */
461}
462
463static void shutdown_sysint2_irq(unsigned int irq)
464{ 439{
465 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 440 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
466} 441}
@@ -470,23 +445,12 @@ static void enable_sysint2_irq(unsigned int irq)
470 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 445 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
471} 446}
472 447
473#define disable_sysint2_irq shutdown_sysint2_irq
474#define ack_sysint2_irq shutdown_sysint2_irq
475
476static void end_sysint2_irq(unsigned int irq)
477{
478 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
479 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
480}
481
482static struct irq_chip sysint2_irq_type = { 448static struct irq_chip sysint2_irq_type = {
483 .typename = "SYSINT2", 449 .typename = "SYSINT2",
484 .startup = startup_sysint2_irq, 450 .ack = disable_sysint2_irq,
485 .shutdown = shutdown_sysint2_irq, 451 .mask = disable_sysint2_irq,
486 .enable = enable_sysint2_irq, 452 .mask_ack = disable_sysint2_irq,
487 .disable = disable_sysint2_irq, 453 .unmask = enable_sysint2_irq,
488 .ack = ack_sysint2_irq,
489 .end = end_sysint2_irq,
490}; 454};
491 455
492static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) 456static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
@@ -723,10 +687,12 @@ static int __init vr41xx_icu_init(void)
723 icu2_write(MGIUINTHREG, 0xffff); 687 icu2_write(MGIUINTHREG, 0xffff);
724 688
725 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 689 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
726 irq_desc[i].chip = &sysint1_irq_type; 690 set_irq_chip_and_handler(i, &sysint1_irq_type,
691 handle_level_irq);
727 692
728 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 693 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
729 irq_desc[i].chip = &sysint2_irq_type; 694 set_irq_chip_and_handler(i, &sysint2_irq_type,
695 handle_level_irq);
730 696
731 cascade_irq(INT0_IRQ, icu_get_irq); 697 cascade_irq(INT0_IRQ, icu_get_irq);
732 cascade_irq(INT1_IRQ, icu_get_irq); 698 cascade_irq(INT1_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
index 2483487344c2..128ed8d6f111 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -30,17 +30,6 @@ extern void init_8259A(int hoge);
30 30
31extern int vr4133_rockhopper; 31extern int vr4133_rockhopper;
32 32
33static unsigned int startup_i8259_irq(unsigned int irq)
34{
35 enable_8259A_irq(irq - I8259_IRQ_BASE);
36 return 0;
37}
38
39static void shutdown_i8259_irq(unsigned int irq)
40{
41 disable_8259A_irq(irq - I8259_IRQ_BASE);
42}
43
44static void enable_i8259_irq(unsigned int irq) 33static void enable_i8259_irq(unsigned int irq)
45{ 34{
46 enable_8259A_irq(irq - I8259_IRQ_BASE); 35 enable_8259A_irq(irq - I8259_IRQ_BASE);
@@ -56,20 +45,12 @@ static void ack_i8259_irq(unsigned int irq)
56 mask_and_ack_8259A(irq - I8259_IRQ_BASE); 45 mask_and_ack_8259A(irq - I8259_IRQ_BASE);
57} 46}
58 47
59static void end_i8259_irq(unsigned int irq)
60{
61 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
62 enable_8259A_irq(irq - I8259_IRQ_BASE);
63}
64
65static struct irq_chip i8259_irq_type = { 48static struct irq_chip i8259_irq_type = {
66 .typename = "XT-PIC", 49 .typename = "XT-PIC",
67 .startup = startup_i8259_irq,
68 .shutdown = shutdown_i8259_irq,
69 .enable = enable_i8259_irq,
70 .disable = disable_i8259_irq,
71 .ack = ack_i8259_irq, 50 .ack = ack_i8259_irq,
72 .end = end_i8259_irq, 51 .mask = disable_i8259_irq,
52 .mask_ack = ack_i8259_irq,
53 .unmask = enable_i8259_irq,
73}; 54};
74 55
75static int i8259_get_irq_number(int irq) 56static int i8259_get_irq_number(int irq)
@@ -104,7 +85,7 @@ void __init rockhopper_init_irq(void)
104 } 85 }
105 86
106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) 87 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
107 irq_desc[i].chip = &i8259_irq_type; 88 set_irq_chip_and_handler(i, &i8259_irq_type, handle_level_irq);
108 89
109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); 90 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
110 91
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 22:07:13 -0500