MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 16 insertions, 16 deletions

diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 86e6e54dd15d..e651105b3f0b 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -71,7 +71,7 @@ static void print_summary(uint32_t status, uint32_t l2_err,
  * already been destructively read out of the registers.
  *
  * notes: this is currently used by the cache error handler
- *        should provide locking against the interrupt handler
+ *        should provide locking against the interrupt handler
  */
 void check_bus_watcher(void)
 {
@@ -119,7 +119,7 @@ static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
                        (int)G_SCD_BERR_RID(stats->status),
                        (int)G_SCD_BERR_DCODE(stats->status));
         /* XXXKW indicate multiple errors between printings, or stats
-           collection (or both)? */
+           collection (or both)? */
         if (stats->status & M_SCD_BERR_MULTERRS)
                 len += sprintf(page+len, "Multiple errors observed since last check.\n");
         if (stats->status_printed) {
@@ -168,7 +168,7 @@ static void create_proc_decoder(struct bw_stats_struct *stats)
  * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
  *
  * notes: possible re-entry due to multiple sources
- *        should check/indicate saturation
+ *        should check/indicate saturation
  */
 static irqreturn_t sibyte_bw_int(int irq, void *data)
 {
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 340aaf626659..fca0cdb99509 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -264,7 +264,7 @@ void __init arch_init_irq(void)
                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
                             (K_INT_MBOX_0 << 3)));
 
-        /* Clear the mailboxes.  The firmware may leave them dirty */
+        /* Clear the mailboxes.  The firmware may leave them dirty */
         __raw_writeq(0xffffffffffffffffULL,
                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
         __raw_writeq(0xffffffffffffffffULL,
@@ -277,7 +277,7 @@ void __init arch_init_irq(void)
 
         /*
          * Note that the timer interrupts are also mapped, but this is
-         * done in sb1250_time_init().  Also, the profiling driver
+         * done in sb1250_time_init().  Also, the profiling driver
          * does its own management of IP7.
          */
 
@@ -294,7 +294,7 @@ static inline void dispatch_ip2(void)
 
         /*
          * Default...we've hit an IP[2] interrupt, which means we've got to
-         * check the 1250 interrupt registers to figure out what to do.  Need
+         * check the 1250 interrupt registers to figure out what to do.  Need
          * to detect which CPU we're on, now that smp_affinity is supported.
          */
         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
@@ -323,7 +323,7 @@ asmlinkage void plat_irq_dispatch(void)
         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP4)
-                do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
+                do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 
 #ifdef CONFIG_SMP
         else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 92da3155ce07..a14bd4cb0bc0 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -203,8 +203,8 @@ void __init sb1250_setup(void)
         case K_SYS_REVISION_BCM1250_PASS1:
 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
                 printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
-                            "and the kernel doesn't have the proper "
-                            "workarounds compiled in. @@@@\n");
+                            "and the kernel doesn't have the proper "
+                            "workarounds compiled in. @@@@\n");
                 bad_config = 1;
 #endif
                 break;
@@ -213,28 +213,28 @@ void __init sb1250_setup(void)
 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
     !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
                 printk("@@@@ This is a BCM1250 A3-A10 board, and the "
-                            "kernel doesn't have the proper workarounds "
-                            "compiled in. @@@@\n");
+                            "kernel doesn't have the proper workarounds "
+                            "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #ifdef CONFIG_CPU_HAS_PREFETCH
                 printk("@@@@ Prefetches may be enabled in this kernel, "
-                            "but are buggy on this board.  @@@@\n");
+                            "but are buggy on this board.  @@@@\n");
                 bad_config = 1;
 #endif
                 break;
         case K_SYS_REVISION_BCM1250_PASS2_2:
 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
                 printk("@@@@ This is a BCM1250 B1/B2. board, and the "
-                            "kernel doesn't have the proper workarounds "
-                            "compiled in. @@@@\n");
+                            "kernel doesn't have the proper workarounds "
+                            "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
     !defined(CONFIG_CPU_HAS_PREFETCH)
                 printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "
-                            "conservatively configured for an 'A' stepping. "
-                            "@@@@\n");
+                            "conservatively configured for an 'A' stepping. "
+                            "@@@@\n");
 #endif
                 break;
         default: