MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

9 files changed, 64 insertions, 64 deletions

diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
index 911dfe39c631..d03a07516f83 100644
--- a/arch/mips/sibyte/Platform
+++ b/arch/mips/sibyte/Platform
@@ -9,7 +9,7 @@ platform-$(CONFIG_SIBYTE_BCM1x80)	+= sibyte/
 #
 # Sibyte SB1250 / BCM1480 family of SOCs
 #
-cflags-$(CONFIG_SIBYTE_BCM112X) +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM112X) +=                                      \
                 -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
@@ -18,11 +18,11 @@ cflags-$(CONFIG_SIBYTE_SB1250)	+=					\
                 -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
-cflags-$(CONFIG_SIBYTE_BCM1x55) +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM1x55) +=                                      \
                 -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
-cflags-$(CONFIG_SIBYTE_BCM1x80) +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM1x80) +=                                      \
                 -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 215713e1f3c4..09d6e16a70f1 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -283,10 +283,10 @@ void __init arch_init_irq(void)
         for (cpu = 0; cpu < 4; cpu++) {
                 __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
                                                  (K_BCM1480_INT_MBOX_0_0 << 3)));
-        }
+        }
 
 
-        /* Clear the mailboxes.  The firmware may leave them dirty */
+        /* Clear the mailboxes.  The firmware may leave them dirty */
         for (cpu = 0; cpu < 4; cpu++) {
                 __raw_writeq(0xffffffffffffffffULL,
                              IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
@@ -307,7 +307,7 @@ void __init arch_init_irq(void)
 
         /*
          * Note that the timer interrupts are also mapped, but this is
-         * done in bcm1480_time_init().  Also, the profiling driver
+         * done in bcm1480_time_init().  Also, the profiling driver
          * does its own management of IP7.
          */
 
@@ -325,7 +325,7 @@ static inline void dispatch_ip2(void)
 
         /*
          * Default...we've hit an IP[2] interrupt, which means we've got to
-         * check the 1480 interrupt registers to figure out what to do.  Need
+         * check the 1480 interrupt registers to figure out what to do.  Need
          * to detect which CPU we're on, now that smp_affinity is supported.
          */
         base = A_BCM1480_IMR_MAPPER(cpu);
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index 6343011e9902..588e1806a1a3 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -127,8 +127,8 @@ static __init void prom_meminit(void)
                                 if ((initrd_pstart > addr) &&
                                     (initrd_pstart < (addr + size))) {
                                         add_memory_region(addr,
-                                                          initrd_pstart - addr,
-                                                          BOOT_MEM_RAM);
+                                                          initrd_pstart - addr,
+                                                          BOOT_MEM_RAM);
                                         rd_flag = 1;
                                 }
                                 if ((initrd_pend > addr) &&
@@ -195,7 +195,7 @@ static int __init initrd_setup(char *str)
 
         /*
          *Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
-         *  e.g. initrd=3abfd@80010000.  This is set up by the loader.
+         *  e.g. initrd=3abfd@80010000.  This is set up by the loader.
          */
         for (tmp = str; *tmp != '@'; tmp++) {
                 if (!*tmp) {
@@ -244,7 +244,7 @@ void __init prom_init(void)
         int *prom_vec = (int *) fw_arg3;
 
         _machine_restart   = cfe_linux_restart;
-        _machine_halt      = cfe_linux_halt;
+        _machine_halt      = cfe_linux_halt;
         pm_power_off = cfe_linux_halt;
 
         /*
@@ -299,7 +299,7 @@ void __init prom_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
         {
                 char *ptr;
-                /* Need to find out early whether we've got an initrd.  So scan
+                /* Need to find out early whether we've got an initrd.  So scan
                    the list looking now */
                 for (ptr = arcs_cmdline; *ptr; ptr++) {
                         while (*ptr == ' ') {
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index e8c4538c5f61..2188b39a1251 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -152,7 +152,7 @@ static u64 tb_period;
 
 static void arm_tb(void)
 {
-        u64 scdperfcnt;
+        u64 scdperfcnt;
         u64 next = (1ULL << 40) - tb_period;
         u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 
@@ -257,8 +257,8 @@ static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 
 /*
  * Requires: Already called zclk_timer_init with a value that won't
- *           saturate 40 bits.  No subsequent use of SCD performance counters
- *           or trace buffer.
+ *           saturate 40 bits.  No subsequent use of SCD performance counters
+ *           or trace buffer.
  */
 
 static int sbprof_zbprof_start(struct file *filp)
@@ -288,8 +288,8 @@ static int sbprof_zbprof_start(struct file *filp)
 
         /*
          * We grab this interrupt to prevent others from trying to use
-         * it, even though we don't want to service the interrupts
-         * (they only feed into the trace-on-interrupt mechanism)
+         * it, even though we don't want to service the interrupts
+         * (they only feed into the trace-on-interrupt mechanism)
          */
         if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
                 free_irq(K_INT_TRACE_FREEZE, &sbp);
@@ -298,7 +298,7 @@ static int sbprof_zbprof_start(struct file *filp)
 
         /*
          * I need the core to mask these, but the interrupt mapper to
-         *  pass them through.  I am exploiting my knowledge that
+         *  pass them through.  I am exploiting my knowledge that
          *  cp0_status masks out IP[5]. krw
          */
 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
@@ -328,7 +328,7 @@ static int sbprof_zbprof_start(struct file *filp)
         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 
         /* Initialize Trace Event 0-7 */
-        /*                              when interrupt  */
+        /*                              when interrupt  */
         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
@@ -479,7 +479,7 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
                         return err;
                 }
                 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
-                         cur_sample, cur_count);
+                         cur_sample, cur_count);
                 size -= cur_count;
                 sample_left -= cur_count;
                 if (!sample_left) {
@@ -540,7 +540,7 @@ static const struct file_operations sbprof_tb_fops = {
         .open           = sbprof_tb_open,
         .release        = sbprof_tb_release,
         .read           = sbprof_tb_read,
-        .unlocked_ioctl = sbprof_tb_ioctl,
+        .unlocked_ioctl = sbprof_tb_ioctl,
         .compat_ioctl   = sbprof_tb_ioctl,
         .mmap           = NULL,
         .llseek         = default_llseek,
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 86e6e54dd15d..e651105b3f0b 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -71,7 +71,7 @@ static void print_summary(uint32_t status, uint32_t l2_err,
  * already been destructively read out of the registers.
  *
  * notes: this is currently used by the cache error handler
- *        should provide locking against the interrupt handler
+ *        should provide locking against the interrupt handler
  */
 void check_bus_watcher(void)
 {
@@ -119,7 +119,7 @@ static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
                        (int)G_SCD_BERR_RID(stats->status),
                        (int)G_SCD_BERR_DCODE(stats->status));
         /* XXXKW indicate multiple errors between printings, or stats
-           collection (or both)? */
+           collection (or both)? */
         if (stats->status & M_SCD_BERR_MULTERRS)
                 len += sprintf(page+len, "Multiple errors observed since last check.\n");
         if (stats->status_printed) {
@@ -168,7 +168,7 @@ static void create_proc_decoder(struct bw_stats_struct *stats)
  * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
  *
  * notes: possible re-entry due to multiple sources
- *        should check/indicate saturation
+ *        should check/indicate saturation
  */
 static irqreturn_t sibyte_bw_int(int irq, void *data)
 {
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 340aaf626659..fca0cdb99509 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -264,7 +264,7 @@ void __init arch_init_irq(void)
                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
                             (K_INT_MBOX_0 << 3)));
 
-        /* Clear the mailboxes.  The firmware may leave them dirty */
+        /* Clear the mailboxes.  The firmware may leave them dirty */
         __raw_writeq(0xffffffffffffffffULL,
                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
         __raw_writeq(0xffffffffffffffffULL,
@@ -277,7 +277,7 @@ void __init arch_init_irq(void)
 
         /*
          * Note that the timer interrupts are also mapped, but this is
-         * done in sb1250_time_init().  Also, the profiling driver
+         * done in sb1250_time_init().  Also, the profiling driver
          * does its own management of IP7.
          */
 
@@ -294,7 +294,7 @@ static inline void dispatch_ip2(void)
 
         /*
          * Default...we've hit an IP[2] interrupt, which means we've got to
-         * check the 1250 interrupt registers to figure out what to do.  Need
+         * check the 1250 interrupt registers to figure out what to do.  Need
          * to detect which CPU we're on, now that smp_affinity is supported.
          */
         mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
@@ -323,7 +323,7 @@ asmlinkage void plat_irq_dispatch(void)
         if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
         else if (pending & CAUSEF_IP4)
-                do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
+                do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
 
 #ifdef CONFIG_SMP
         else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 92da3155ce07..a14bd4cb0bc0 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -203,8 +203,8 @@ void __init sb1250_setup(void)
         case K_SYS_REVISION_BCM1250_PASS1:
 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
                 printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
-                            "and the kernel doesn't have the proper "
-                            "workarounds compiled in. @@@@\n");
+                            "and the kernel doesn't have the proper "
+                            "workarounds compiled in. @@@@\n");
                 bad_config = 1;
 #endif
                 break;
@@ -213,28 +213,28 @@ void __init sb1250_setup(void)
 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
     !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
                 printk("@@@@ This is a BCM1250 A3-A10 board, and the "
-                            "kernel doesn't have the proper workarounds "
-                            "compiled in. @@@@\n");
+                            "kernel doesn't have the proper workarounds "
+                            "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #ifdef CONFIG_CPU_HAS_PREFETCH
                 printk("@@@@ Prefetches may be enabled in this kernel, "
-                            "but are buggy on this board.  @@@@\n");
+                            "but are buggy on this board.  @@@@\n");
                 bad_config = 1;
 #endif
                 break;
         case K_SYS_REVISION_BCM1250_PASS2_2:
 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
                 printk("@@@@ This is a BCM1250 B1/B2. board, and the "
-                            "kernel doesn't have the proper workarounds "
-                            "compiled in. @@@@\n");
+                            "kernel doesn't have the proper workarounds "
+                            "compiled in. @@@@\n");
                 bad_config = 1;
 #endif
 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
     !defined(CONFIG_CPU_HAS_PREFETCH)
                 printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "
-                            "conservatively configured for an 'A' stepping. "
-                            "@@@@\n");
+                            "conservatively configured for an 'A' stepping. "
+                            "@@@@\n");
 #endif
                 break;
         default:
diff --git a/arch/mips/sibyte/swarm/platform.c b/arch/mips/sibyte/swarm/platform.c
index 097335262fb3..9480c14ec66a 100644
--- a/arch/mips/sibyte/swarm/platform.c
+++ b/arch/mips/sibyte/swarm/platform.c
@@ -13,7 +13,7 @@
 
 #define DRV_NAME        "pata-swarm"
 
-#define SWARM_IDE_SHIFT 5
+#define SWARM_IDE_SHIFT 5
 #define SWARM_IDE_BASE  0x1f0
 #define SWARM_IDE_CTRL  0x3f6
 
@@ -123,7 +123,7 @@ static int __init sb1250_device_init(void)
         case K_SYS_SOC_TYPE_BCM1120:
         case K_SYS_SOC_TYPE_BCM1125:
         case K_SYS_SOC_TYPE_BCM1125H:
-        case K_SYS_SOC_TYPE_BCM1250_ALT2:       /* Hybrid */
+        case K_SYS_SOC_TYPE_BCM1250_ALT2:       /* Hybrid */
                 ret = platform_add_devices(sb1250_devs, 2);
                 break;
         case K_SYS_SOC_TYPE_BCM1x55:
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index 4438b2195c44..178a824b28d4 100644
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -4,8 +4,8 @@
  * Copyright (C) 2002 MontaVista Software Inc.
  * Author: jsun@mvista.com or jsun@junsun.net
  *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
@@ -28,15 +28,15 @@
  * Register bits
  */
 
-#define X1241REG_SR_BAT 0x80            /* currently on battery power */
+#define X1241REG_SR_BAT 0x80            /* currently on battery power */
 #define X1241REG_SR_RWEL 0x04           /* r/w latch is enabled, can write RTC */
 #define X1241REG_SR_WEL 0x02            /* r/w latch is unlocked, can enable r/w now */
 #define X1241REG_SR_RTCF 0x01           /* clock failed */
 #define X1241REG_BL_BP2 0x80            /* block protect 2 */
 #define X1241REG_BL_BP1 0x40            /* block protect 1 */
 #define X1241REG_BL_BP0 0x20            /* block protect 0 */
-#define X1241REG_BL_WD1 0x10
-#define X1241REG_BL_WD0 0x08
+#define X1241REG_BL_WD1 0x10
+#define X1241REG_BL_WD0 0x08
 #define X1241REG_HR_MIL 0x80            /* military time format */
 
 /*
@@ -61,50 +61,50 @@
 
 static int xicor_read(uint8_t addr)
 {
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+                ;
 
         __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
         __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
         __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
                      SMB_CSR(R_SMB_START));
 
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+                ;
 
         __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
                      SMB_CSR(R_SMB_START));
 
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+                ;
 
-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        }
+        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+                /* Clear error bit by writing a 1 */
+                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+                return -1;
+        }
 
         return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
 }
 
 static int xicor_write(uint8_t addr, int b)
 {
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+                ;
 
         __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
         __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
         __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
                      SMB_CSR(R_SMB_START));
 
-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+                ;
 
-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        } else {
+        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+                /* Clear error bit by writing a 1 */
+                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+                return -1;
+        } else {
                 return 0;
         }
 }