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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:33:08 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit89d63fe179520b11f54de1f26755b7444c79e73a (patch)
treefede06c5648335652c864fc35c951d991cbab183 /arch/mips/pci
parent22b1d707ffc99faebd86257ad19d5bb9fc624734 (diff)
[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile8
-rw-r--r--arch/mips/pci/fixup-jmr3927.c25
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c112
-rw-r--r--arch/mips/pci/fixup-rbtx4938.c52
-rw-r--r--arch/mips/pci/ops-tx3927.c87
-rw-r--r--arch/mips/pci/ops-tx4927.c514
-rw-r--r--arch/mips/pci/ops-tx4938.c214
-rw-r--r--arch/mips/pci/pci-jmr3927.c58
-rw-r--r--arch/mips/pci/pci-tx4927.c83
-rw-r--r--arch/mips/pci/pci-tx4938.c134
10 files changed, 706 insertions, 581 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4608e43de28c..908764878ac8 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
17obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o 17obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
18obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o
19obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18 20
19# 21#
20# These are still pretty much in the old state, watch, go blind. 22# These are still pretty much in the old state, watch, go blind.
@@ -41,9 +43,9 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
41obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 43obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
42obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 44obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
43obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 45obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
44obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 46obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
45obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 47obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o
46obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o 48obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o
47obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
48obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
49obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c
index 41dcd6a3aae5..d5edaf21e088 100644
--- a/arch/mips/pci/fixup-jmr3927.c
+++ b/arch/mips/pci/fixup-jmr3927.c
@@ -28,36 +28,31 @@
28 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */ 29 */
30#include <linux/types.h> 30#include <linux/types.h>
31#include <linux/pci.h> 31#include <asm/txx9/pci.h>
32#include <linux/init.h>
33
34#include <asm/txx9/jmr3927.h> 32#include <asm/txx9/jmr3927.h>
35 33
36int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 34int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
37{ 35{
38 unsigned char irq = pin; 36 unsigned char irq = pin;
39 37
40 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
41 if (dev->vendor == PCI_VENDOR_ID_EFAR &&
42 dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)
43 return irq;
44 /* IRQ rotation (PICMG) */ 38 /* IRQ rotation (PICMG) */
45 irq--; /* 0-3 */ 39 irq--; /* 0-3 */
46 if (dev->bus->parent == NULL && 40 if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
47 slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
48 /* PCI CardSlot (IDSEL=A23, DevNu=12) */ 41 /* PCI CardSlot (IDSEL=A23, DevNu=12) */
49 /* PCIA => PCIC (IDSEL=A23) */ 42 /* PCIA => PCIC (IDSEL=A23) */
50 /* NOTE: JMR3927 JP1 must be set to OPEN */ 43 /* NOTE: JMR3927 JP1 must be set to OPEN */
51 irq = (irq + 2) % 4; 44 irq = (irq + 2) % 4;
52 } else if (dev->bus->parent == NULL && 45 } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
53 slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
54 /* PCI CardSlot (IDSEL=A22, DevNu=11) */ 46 /* PCI CardSlot (IDSEL=A22, DevNu=11) */
55 /* PCIA => PCIA (IDSEL=A22) */ 47 /* PCIA => PCIA (IDSEL=A22) */
56 /* NOTE: JMR3927 JP1 must be set to OPEN */ 48 /* NOTE: JMR3927 JP1 must be set to OPEN */
57 irq = (irq + 0) % 4; 49 irq = (irq + 0) % 4;
58 } else { 50 } else {
59 /* PCI Backplane */ 51 /* PCI Backplane */
60 irq = (irq + 3 + slot) % 4; 52 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
53 irq = (irq + 33 - slot) % 4;
54 else
55 irq = (irq + 3 + slot) % 4;
61 } 56 }
62 irq++; /* 1-4 */ 57 irq++; /* 1-4 */
63 58
@@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
66 irq = JMR3927_IRQ_IOC_PCIA; 61 irq = JMR3927_IRQ_IOC_PCIA;
67 break; 62 break;
68 case 2: 63 case 2:
69 // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; 64 irq = JMR3927_IRQ_IOC_PCIB;
70 irq = JMR3927_IRQ_IOC_PCID;
71 break; 65 break;
72 case 3: 66 case 3:
73 irq = JMR3927_IRQ_IOC_PCIC; 67 irq = JMR3927_IRQ_IOC_PCIC;
74 break; 68 break;
75 case 4: 69 case 4:
76 // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; 70 irq = JMR3927_IRQ_IOC_PCID;
77 irq = JMR3927_IRQ_IOC_PCIB;
78 break; 71 break;
79 } 72 }
80 73
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 26013badfe1f..abab4852d158 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -33,102 +33,42 @@
33 * 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */ 34 */
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/pci.h> 36#include <asm/txx9/pci.h>
37#include <linux/kernel.h> 37#include <asm/txx9/rbtx4927.h>
38#include <linux/init.h>
39 38
40#include <asm/txx9/tx4927.h> 39int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
41
42#undef DEBUG
43#ifdef DEBUG
44#define DBG(x...) printk(x)
45#else
46#define DBG(x...)
47#endif
48
49/* look up table for backplane pci irq for slots 17-20 by pin # */
50static unsigned char backplane_pci_irq[4][4] = {
51 /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA,
52 /* PJ6 SLOT: 17, PIN: 2 */
53 TX4927_IRQ_IOC_PCIB,
54 /* PJ6 SLOT: 17, PIN: 3 */
55 TX4927_IRQ_IOC_PCIC,
56 /* PJ6 SLOT: 17, PIN: 4 */
57 TX4927_IRQ_IOC_PCID},
58 /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB,
59 /* SB SLOT: 18, PIN: 2 */
60 TX4927_IRQ_IOC_PCIC,
61 /* SB SLOT: 18, PIN: 3 */
62 TX4927_IRQ_IOC_PCID,
63 /* SB SLOT: 18, PIN: 4 */
64 TX4927_IRQ_IOC_PCIA},
65 /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC,
66 /* PJ5 SLOT: 19, PIN: 2 */
67 TX4927_IRQ_IOC_PCID,
68 /* PJ5 SLOT: 19, PIN: 3 */
69 TX4927_IRQ_IOC_PCIA,
70 /* PJ5 SLOT: 19, PIN: 4 */
71 TX4927_IRQ_IOC_PCIB},
72 /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID,
73 /* PJ4 SLOT: 20, PIN: 2 */
74 TX4927_IRQ_IOC_PCIA,
75 /* PJ4 SLOT: 20, PIN: 3 */
76 TX4927_IRQ_IOC_PCIB,
77 /* PJ4 SLOT: 20, PIN: 4 */
78 TX4927_IRQ_IOC_PCIC}
79};
80
81static int pci_get_irq(const struct pci_dev *dev, int pin)
82{ 40{
83 unsigned char irq = pin; 41 unsigned char irq = pin;
84 42
85 DBG("pci_get_irq: pin is %d\n", pin);
86 /* IRQ rotation */ 43 /* IRQ rotation */
87 irq--; /* 0-3 */ 44 irq--; /* 0-3 */
88 if (dev->bus->parent == NULL && 45 if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
89 PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { 46 /* PCI CardSlot (IDSEL=A23) */
90 printk("Onboard PCI_SLOT(dev->devfn) is %d\n", 47 /* PCIA => PCIA */
91 PCI_SLOT(dev->devfn)); 48 irq = (irq + 0 + slot) % 4;
92 /* IDSEL=A23 is tx4927 onboard pci slot */
93 irq = (irq + PCI_SLOT(dev->devfn)) % 4;
94 irq++; /* 1-4 */
95 DBG("irq is now %d\n", irq);
96
97 switch (irq) {
98 case 1:
99 irq = TX4927_IRQ_IOC_PCIA;
100 break;
101 case 2:
102 irq = TX4927_IRQ_IOC_PCIB;
103 break;
104 case 3:
105 irq = TX4927_IRQ_IOC_PCIC;
106 break;
107 case 4:
108 irq = TX4927_IRQ_IOC_PCID;
109 break;
110 }
111 } else { 49 } else {
112 /* PCI Backplane */ 50 /* PCI Backplane */
113 DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", 51 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
114 PCI_SLOT(dev->devfn)); 52 irq = (irq + 33 - slot) % 4;
115 irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; 53 else
54 irq = (irq + 3 + slot) % 4;
116 } 55 }
117 DBG("assigned irq %d\n", irq); 56 irq++; /* 1-4 */
118 return irq;
119}
120
121int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
122{
123 unsigned char irq;
124
125 printk("PCI Setup for pin %d \n", pin);
126
127 if (dev->device == 0x9130) /* IDE */
128 irq = 14;
129 else
130 irq = pci_get_irq(dev, pin);
131 57
58 switch (irq) {
59 case 1:
60 irq = RBTX4927_IRQ_IOC_PCIA;
61 break;
62 case 2:
63 irq = RBTX4927_IRQ_IOC_PCIB;
64 break;
65 case 3:
66 irq = RBTX4927_IRQ_IOC_PCIC;
67 break;
68 case 4:
69 irq = RBTX4927_IRQ_IOC_PCID;
70 break;
71 }
132 return irq; 72 return irq;
133} 73}
134 74
diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c
index 64d4510c0265..39c995830384 100644
--- a/arch/mips/pci/fixup-rbtx4938.c
+++ b/arch/mips/pci/fixup-rbtx4938.c
@@ -10,45 +10,28 @@
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */ 11 */
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/pci.h> 13#include <asm/txx9/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/txx9/rbtx4938.h> 14#include <asm/txx9/rbtx4938.h>
18 15
19extern struct pci_controller tx4938_pci_controller[]; 16int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
20
21static int pci_get_irq(const struct pci_dev *dev, int pin)
22{ 17{
23 int irq = pin; 18 int irq = tx4938_pcic1_map_irq(dev, slot);
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41 19
20 if (irq >= 0)
21 return irq;
22 irq = pin;
42 /* IRQ rotation */ 23 /* IRQ rotation */
43 irq--; /* 0-3 */ 24 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL && 25 if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */ 26 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */ 27 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4; 28 irq = (irq + 0 + slot) % 4;
49 } else { 29 } else {
50 /* PCI Backplane */ 30 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4; 31 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
32 irq = (irq + 33 - slot) % 4;
33 else
34 irq = (irq + 3 + slot) % 4;
52 } 35 }
53 irq++; /* 1-4 */ 36 irq++; /* 1-4 */
54 37
@@ -69,19 +52,6 @@ static int pci_get_irq(const struct pci_dev *dev, int pin)
69 return irq; 52 return irq;
70} 53}
71 54
72int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/* 55/*
86 * Do platform specific device initialization at pci_enable_device() time 56 * Do platform specific device initialization at pci_enable_device() time
87 */ 57 */
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 5d398f694682..8a17a39e5bf2 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 * 10 *
11 * Define the pci_ops for JMR3927. 11 * Define the pci_ops for TX3927.
12 * 12 *
13 * Much of the code is derived from the original DDB5074 port by 13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com> 14 * Geert Uytterhoeven <geert@sonycom.com>
@@ -39,7 +39,7 @@
39#include <linux/init.h> 39#include <linux/init.h>
40 40
41#include <asm/addrspace.h> 41#include <asm/addrspace.h>
42#include <asm/txx9/jmr3927.h> 42#include <asm/txx9/tx3927.h>
43 43
44static inline int mkaddr(unsigned char bus, unsigned char dev_fn, 44static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
45 unsigned char where) 45 unsigned char where)
@@ -68,7 +68,7 @@ static inline int check_abort(void)
68 return PCIBIOS_SUCCESSFUL; 68 return PCIBIOS_SUCCESSFUL;
69} 69}
70 70
71static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, 71static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
72 int where, int size, u32 * val) 72 int where, int size, u32 * val)
73{ 73{
74 int ret; 74 int ret;
@@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
94 return check_abort(); 94 return check_abort();
95} 95}
96 96
97static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, 97static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
98 int where, int size, u32 val) 98 int where, int size, u32 val)
99{ 99{
100 int ret; 100 int ret;
@@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
125 return check_abort(); 125 return check_abort();
126} 126}
127 127
128struct pci_ops jmr3927_pci_ops = { 128static struct pci_ops tx3927_pci_ops = {
129 jmr3927_pci_read_config, 129 .read = tx3927_pci_read_config,
130 jmr3927_pci_write_config, 130 .write = tx3927_pci_write_config,
131}; 131};
132
133void __init tx3927_pcic_setup(struct pci_controller *channel,
134 unsigned long sdram_size, int extarb)
135{
136 unsigned long flags;
137 unsigned long io_base =
138 channel->io_resource->start + mips_io_port_base - IO_BASE;
139 unsigned long io_size =
140 channel->io_resource->end - channel->io_resource->start;
141 unsigned long io_pciaddr =
142 channel->io_resource->start - channel->io_offset;
143 unsigned long mem_base =
144 channel->mem_resource->start;
145 unsigned long mem_size =
146 channel->mem_resource->end - channel->mem_resource->start;
147 unsigned long mem_pciaddr =
148 channel->mem_resource->start - channel->mem_offset;
149
150 printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
151 tx3927_pcicptr->did, tx3927_pcicptr->vid,
152 tx3927_pcicptr->rid,
153 extarb ? "External" : "Internal");
154 channel->pci_ops = &tx3927_pci_ops;
155
156 local_irq_save(flags);
157 /* Disable External PCI Config. Access */
158 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
159#ifdef __BIG_ENDIAN
160 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
161 TX3927_PCIC_LBC_TIBSE |
162 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
163#endif
164 /* LB->PCI mappings */
165 tx3927_pcicptr->iomas = ~(io_size - 1);
166 tx3927_pcicptr->ilbioma = io_base;
167 tx3927_pcicptr->ipbioma = io_pciaddr;
168 tx3927_pcicptr->mmas = ~(mem_size - 1);
169 tx3927_pcicptr->ilbmma = mem_base;
170 tx3927_pcicptr->ipbmma = mem_pciaddr;
171 /* PCI->LB mappings */
172 tx3927_pcicptr->iobas = 0xffffffff;
173 tx3927_pcicptr->ioba = 0;
174 tx3927_pcicptr->tlbioma = 0;
175 tx3927_pcicptr->mbas = ~(sdram_size - 1);
176 tx3927_pcicptr->mba = 0;
177 tx3927_pcicptr->tlbmma = 0;
178 /* Enable Direct mapping Address Space Decoder */
179 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
180
181 /* Clear All Local Bus Status */
182 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
183 /* Enable All Local Bus Interrupts */
184 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
185 /* Clear All PCI Status Error */
186 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
187 /* Enable All PCI Status Error Interrupts */
188 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
189
190 /* PCIC Int => IRC IRQ10 */
191 tx3927_pcicptr->il = TX3927_IR_PCI;
192 /* Target Control (per errata) */
193 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
194
195 /* Enable Bus Arbiter */
196 if (!extarb)
197 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
198
199 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
200 PCI_COMMAND_MEMORY |
201 PCI_COMMAND_IO |
202 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
203 local_irq_restore(flags);
204}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 54730eee451b..c6b49bccd274 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,206 +1,408 @@
1/* 1/*
2 * Copyright 2001 MontaVista Software Inc. 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 * 3 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 4 * Based on linux/arch/mips/pci/ops-tx4938.c,
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 5 * linux/arch/mips/pci/fixup-rbtx4938.c,
8 * 6 * linux/arch/mips/txx9/rbtx4938/setup.c,
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 7 * and RBTX49xx patch from CELF patch archive.
10 *
11 * Define the pci_ops for the Toshiba rbtx4927
12 *
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
15 *
16 * Copyright 2004 MontaVista Software Inc.
17 * Author: Manish Lachwani (mlachwani@mvista.com)
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 * 8 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 9 * 2003-2005 (c) MontaVista Software, Inc.
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * 12 *
35 * You should have received a copy of the GNU General Public License along 13 * This program is free software; you can redistribute it and/or modify it
36 * with this program; if not, write to the Free Software Foundation, Inc., 14 * under the terms of the GNU General Public License as published by the
37 * 675 Mass Ave, Cambridge, MA 02139, USA. 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
38 */ 17 */
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h> 18#include <linux/kernel.h>
42#include <linux/init.h> 19#include <asm/txx9/tx4927pcic.h>
43#include <asm/txx9/tx4927.h>
44
45/* initialize in setup */
46struct resource pci_io_resource = {
47 .name = "TX4927 PCI IO SPACE",
48 .start = 0x1000,
49 .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1,
50 .flags = IORESOURCE_IO
51};
52 20
53/* initialize in setup */ 21static struct {
54struct resource pci_mem_resource = { 22 struct pci_controller *channel;
55 .name = "TX4927 PCI MEM SPACE", 23 struct tx4927_pcic_reg __iomem *pcicptr;
56 .start = TX4927_PCIMEM, 24} pcicptrs[2]; /* TX4938 has 2 pcic */
57 .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, 25
58 .flags = IORESOURCE_MEM 26static void __init set_tx4927_pcicptr(struct pci_controller *channel,
59}; 27 struct tx4927_pcic_reg __iomem *pcicptr)
28{
29 int i;
30
31 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
32 if (pcicptrs[i].channel == channel) {
33 pcicptrs[i].pcicptr = pcicptr;
34 return;
35 }
36 }
37 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
38 if (!pcicptrs[i].channel) {
39 pcicptrs[i].channel = channel;
40 pcicptrs[i].pcicptr = pcicptr;
41 return;
42 }
43 }
44 BUG();
45}
60 46
61static int mkaddr(int bus, int dev_fn, int where, int *flagsp) 47struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
48 struct pci_controller *channel)
62{ 49{
63 if (bus > 0) { 50 int i;
64 /* Type 1 configuration */
65 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
66 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
67 } else {
68 if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
69 return -1;
70 51
71 /* Type 0 configuration */ 52 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
72 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | 53 if (pcicptrs[i].channel == channel)
73 ((dev_fn & 0xff) << 0x08) | (where & 0xfc); 54 return pcicptrs[i].pcicptr;
74 } 55 }
56 return NULL;
57}
58
59static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
60 struct tx4927_pcic_reg __iomem *pcicptr)
61{
62 if (bus->parent == NULL &&
63 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
64 return -1;
65 __raw_writel(((bus->number & 0xff) << 0x10)
66 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
67 | (bus->parent ? 1 : 0),
68 &pcicptr->g2pcfgadrs);
75 /* clear M_ABORT and Disable M_ABORT Int. */ 69 /* clear M_ABORT and Disable M_ABORT Int. */
76 tx4927_pcicptr->pcistatus = 70 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
77 (tx4927_pcicptr->pcistatus & 0x0000ffff) | 71 | (PCI_STATUS_REC_MASTER_ABORT << 16),
78 (PCI_STATUS_REC_MASTER_ABORT << 16); 72 &pcicptr->pcistatus);
79 tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
80 return 0; 73 return 0;
81} 74}
82 75
83static int check_abort(int flags) 76static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
84{ 77{
85 int code = PCIBIOS_SUCCESSFUL; 78 int code = PCIBIOS_SUCCESSFUL;
86 if (tx4927_pcicptr-> 79
87 pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 80 /* wait write cycle completion before checking error status */
88 tx4927_pcicptr->pcistatus = 81 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
89 (tx4927_pcicptr-> 82 ;
90 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT 83 if (__raw_readl(&pcicptr->pcistatus)
91 << 16); 84 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
92 tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; 85 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT << 16),
87 &pcicptr->pcistatus);
93 code = PCIBIOS_DEVICE_NOT_FOUND; 88 code = PCIBIOS_DEVICE_NOT_FOUND;
94 } 89 }
95 return code; 90 return code;
96} 91}
97 92
98static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, 93static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
99 int size, u32 * val) 94{
95#ifdef __BIG_ENDIAN
96 offset ^= 3;
97#endif
98 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
99}
100static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
101{
102#ifdef __BIG_ENDIAN
103 offset ^= 2;
104#endif
105 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
106}
107static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
108{
109 return __raw_readl(&pcicptr->g2pcfgdata);
110}
111static void icd_writeb(u8 val, int offset,
112 struct tx4927_pcic_reg __iomem *pcicptr)
113{
114#ifdef __BIG_ENDIAN
115 offset ^= 3;
116#endif
117 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
118}
119static void icd_writew(u16 val, int offset,
120 struct tx4927_pcic_reg __iomem *pcicptr)
121{
122#ifdef __BIG_ENDIAN
123 offset ^= 2;
124#endif
125 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
126}
127static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
100{ 128{
101 int flags, retval, dev, busno, func; 129 __raw_writel(val, &pcicptr->g2pcfgdata);
130}
102 131
103 busno = bus->number; 132static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
104 dev = PCI_SLOT(devfn); 133{
105 func = PCI_FUNC(devfn); 134 struct pci_controller *channel = bus->sysdata;
135 return get_tx4927_pcicptr(channel);
136}
106 137
107 /* check if the bus is top-level */ 138static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
108 if (bus->parent != NULL) { 139 int where, int size, u32 *val)
109 busno = bus->number; 140{
110 } else { 141 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
111 busno = 0;
112 }
113 142
114 if (mkaddr(busno, devfn, where, &flags)) 143 if (mkaddr(bus, devfn, where, pcicptr)) {
144 *val = 0xffffffff;
115 return -1; 145 return -1;
116 146 }
117 switch (size) { 147 switch (size) {
118 case 1: 148 case 1:
119 *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 149 *val = icd_readb(where & 3, pcicptr);
120 g2pcfgdata |
121#ifdef __LITTLE_ENDIAN
122 (where & 3));
123#else
124 ((where & 0x3) ^ 0x3));
125#endif
126 break; 150 break;
127 case 2: 151 case 2:
128 *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 152 *val = icd_readw(where & 3, pcicptr);
129 g2pcfgdata |
130#ifdef __LITTLE_ENDIAN
131 (where & 3));
132#else
133 ((where & 0x3) ^ 0x2));
134#endif
135 break;
136 case 4:
137 *val = tx4927_pcicptr->g2pcfgdata;
138 break; 153 break;
154 default:
155 *val = icd_readl(pcicptr);
139 } 156 }
157 return check_abort(pcicptr);
158}
140 159
141 retval = check_abort(flags); 160static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
142 if (retval == PCIBIOS_DEVICE_NOT_FOUND) 161 int where, int size, u32 val)
143 *val = 0xffffffff; 162{
163 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
144 164
145 return retval; 165 if (mkaddr(bus, devfn, where, pcicptr))
166 return -1;
167 switch (size) {
168 case 1:
169 icd_writeb(val, where & 3, pcicptr);
170 break;
171 case 2:
172 icd_writew(val, where & 3, pcicptr);
173 break;
174 default:
175 icd_writel(val, pcicptr);
176 }
177 return check_abort(pcicptr);
146} 178}
147 179
148static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, 180static struct pci_ops tx4927_pci_ops = {
149 int size, u32 val) 181 .read = tx4927_pci_config_read,
182 .write = tx4927_pci_config_write,
183};
184
185static struct {
186 u8 trdyto;
187 u8 retryto;
188 u16 gbwc;
189} tx4927_pci_opts __devinitdata = {
190 .trdyto = 0,
191 .retryto = 0,
192 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
193};
194
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb)
150{ 197{
151 int flags, dev, busno, func; 198 int i;
152 busno = bus->number; 199 unsigned long flags;
153 dev = PCI_SLOT(devfn);
154 func = PCI_FUNC(devfn);
155 200
156 /* check if the bus is top-level */ 201 set_tx4927_pcicptr(channel, pcicptr);
157 if (bus->parent != NULL) {
158 busno = bus->number;
159 } else {
160 busno = 0;
161 }
162 202
163 if (mkaddr(busno, devfn, where, &flags)) 203 if (!channel->pci_ops)
164 return -1; 204 printk(KERN_INFO
205 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
206 __raw_readl(&pcicptr->pciid) >> 16,
207 __raw_readl(&pcicptr->pciid) & 0xffff,
208 __raw_readl(&pcicptr->pciccrev) & 0xff,
209 extarb ? "External" : "Internal");
210 channel->pci_ops = &tx4927_pci_ops;
165 211
166 switch (size) { 212 local_irq_save(flags);
167 case 1: 213
168 *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 214 /* Disable All Initiator Space */
169 g2pcfgdata | 215 __raw_writel(__raw_readl(&pcicptr->pciccfg)
170#ifdef __LITTLE_ENDIAN 216 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
171 (where & 3)) = val; 217 | TX4927_PCIC_PCICCFG_G2PMEN(1)
218 | TX4927_PCIC_PCICCFG_G2PMEN(2)
219 | TX4927_PCIC_PCICCFG_G2PIOEN),
220 &pcicptr->pciccfg);
221
222 /* GB->PCI mappings */
223 __raw_writel((channel->io_resource->end - channel->io_resource->start)
224 >> 4,
225 &pcicptr->g2piomask);
226 ____raw_writeq((channel->io_resource->start +
227 channel->io_map_base - IO_BASE) |
228#ifdef __BIG_ENDIAN
229 TX4927_PCIC_G2PIOGBASE_ECHG
172#else 230#else
173 ((where & 0x3) ^ 0x3)) = val; 231 TX4927_PCIC_G2PIOGBASE_BSDIS
174#endif 232#endif
175 break; 233 , &pcicptr->g2piogbase);
176 234 ____raw_writeq(channel->io_resource->start - channel->io_offset,
177 case 2: 235 &pcicptr->g2piopbase);
178 *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 236 for (i = 0; i < 3; i++) {
179 g2pcfgdata | 237 __raw_writel(0, &pcicptr->g2pmmask[i]);
180#ifdef __LITTLE_ENDIAN 238 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
181 (where & 3)) = val; 239 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
240 }
241 if (channel->mem_resource->end) {
242 __raw_writel((channel->mem_resource->end
243 - channel->mem_resource->start) >> 4,
244 &pcicptr->g2pmmask[0]);
245 ____raw_writeq(channel->mem_resource->start |
246#ifdef __BIG_ENDIAN
247 TX4927_PCIC_G2PMnGBASE_ECHG
182#else 248#else
183 ((where & 0x3) ^ 0x2)) = val; 249 TX4927_PCIC_G2PMnGBASE_BSDIS
184#endif 250#endif
185 break; 251 , &pcicptr->g2pmgbase[0]);
186 case 4: 252 ____raw_writeq(channel->mem_resource->start -
187 tx4927_pcicptr->g2pcfgdata = val; 253 channel->mem_offset,
188 break; 254 &pcicptr->g2pmpbase[0]);
255 }
256 /* PCI->GB mappings (I/O 256B) */
257 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
258 ____raw_writeq(0, &pcicptr->p2giogbase);
259 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
260 __raw_writel(0, &pcicptr->p2gm0plbase);
261 __raw_writel(0, &pcicptr->p2gm0pubase);
262 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
263#ifdef __BIG_ENDIAN
264 TX4927_PCIC_P2GMnGBASE_TECHG
265#else
266 TX4927_PCIC_P2GMnGBASE_TBSDIS
267#endif
268 , &pcicptr->p2gmgbase[0]);
269 /* PCI->GB mappings (MEM 16MB) */
270 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
271 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
272 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
273 /* PCI->GB mappings (MEM 1MB) */
274 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
275 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
276
277 /* Clear all (including IRBER) except for GBWC */
278 __raw_writel((tx4927_pci_opts.gbwc << 16)
279 & TX4927_PCIC_PCICCFG_GBWC_MASK,
280 &pcicptr->pciccfg);
281 /* Enable Initiator Memory Space */
282 if (channel->mem_resource->end)
283 __raw_writel(__raw_readl(&pcicptr->pciccfg)
284 | TX4927_PCIC_PCICCFG_G2PMEN(0),
285 &pcicptr->pciccfg);
286 /* Enable Initiator I/O Space */
287 if (channel->io_resource->end)
288 __raw_writel(__raw_readl(&pcicptr->pciccfg)
289 | TX4927_PCIC_PCICCFG_G2PIOEN,
290 &pcicptr->pciccfg);
291 /* Enable Initiator Config */
292 __raw_writel(__raw_readl(&pcicptr->pciccfg)
293 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
294 &pcicptr->pciccfg);
295
296 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
297 __raw_writel(0, &pcicptr->pcicfg1);
298
299 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
300 | (tx4927_pci_opts.trdyto & 0xff)
301 | ((tx4927_pci_opts.retryto & 0xff) << 8),
302 &pcicptr->g2ptocnt);
303
304 /* Clear All Local Bus Status */
305 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
306 /* Enable All Local Bus Interrupts */
307 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
308 /* Clear All Initiator Status */
309 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
310 /* Enable All Initiator Interrupts */
311 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
312 /* Clear All PCI Status Error */
313 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
314 | (TX4927_PCIC_PCISTATUS_ALL << 16),
315 &pcicptr->pcistatus);
316 /* Enable All PCI Status Error Interrupts */
317 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
318
319 if (!extarb) {
320 /* Reset Bus Arbiter */
321 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
322 __raw_writel(0, &pcicptr->pbabm);
323 /* Enable Bus Arbiter */
324 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
189 } 325 }
190 326
191 return check_abort(flags); 327 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
328 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
329 &pcicptr->pcistatus);
330 local_irq_restore(flags);
331
332 printk(KERN_DEBUG
333 "PCI: COMMAND=%04x,PCIMASK=%04x,"
334 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
335 __raw_readl(&pcicptr->pcistatus) & 0xffff,
336 __raw_readl(&pcicptr->pcimask) & 0xffff,
337 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
338 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
339 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
192} 340}
193 341
194struct pci_ops tx4927_pci_ops = { 342static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
195 tx4927_pcibios_read_config, 343{
196 tx4927_pcibios_write_config 344 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
197}; 345 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
346 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
347 static struct {
348 __u32 flag;
349 const char *str;
350 } pcistat_tbl[] = {
351 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
352 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
353 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
354 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
355 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
356 { PCI_STATUS_PARITY, "MasterParityError" },
357 }, g2pstat_tbl[] = {
358 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
359 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
360 }, pcicstat_tbl[] = {
361 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
362 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
363 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
364 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
365 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
366 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
367 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
368 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
369 };
370 int i, cont;
198 371
199/* 372 printk(KERN_ERR "");
200 * h/w only supports devices 0x00 to 0x14 373 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
201 */ 374 printk(KERN_CONT "pcistat:%04x(", pcistatus);
202struct pci_controller tx4927_controller = { 375 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
203 .pci_ops = &tx4927_pci_ops, 376 if (pcistatus & pcistat_tbl[i].flag)
204 .io_resource = &pci_io_resource, 377 printk(KERN_CONT "%s%s",
205 .mem_resource = &pci_mem_resource, 378 cont++ ? " " : "", pcistat_tbl[i].str);
206}; 379 printk(KERN_CONT ") ");
380 }
381 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
382 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
383 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
384 if (g2pstatus & g2pstat_tbl[i].flag)
385 printk(KERN_CONT "%s%s",
386 cont++ ? " " : "", g2pstat_tbl[i].str);
387 printk(KERN_CONT ") ");
388 }
389 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
390 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
391 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
392 if (pcicstatus & pcicstat_tbl[i].flag)
393 printk(KERN_CONT "%s%s",
394 cont++ ? " " : "", pcicstat_tbl[i].str);
395 printk(KERN_CONT ")");
396 }
397 printk(KERN_CONT "\n");
398}
399
400void tx4927_report_pcic_status(void)
401{
402 int i;
403
404 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
405 if (pcicptrs[i].pcicptr)
406 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
407 }
408}
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
deleted file mode 100644
index 34494b82cb22..000000000000
--- a/arch/mips/pci/ops-tx4938.c
+++ /dev/null
@@ -1,214 +0,0 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/txx9/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where,
50 struct tx4938_pcic_reg *pcicptr)
51{
52 if (bus > 0) {
53 /* Type 1 configuration */
54 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
55 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
56 } else {
57 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
58 return -1;
59
60 /* Type 0 configuration */
61 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
62 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
63 }
64 /* clear M_ABORT and Disable M_ABORT Int. */
65 pcicptr->pcistatus =
66 (pcicptr->pcistatus & 0x0000ffff) |
67 (PCI_STATUS_REC_MASTER_ABORT << 16);
68 pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
69
70 return 0;
71}
72
73static int check_abort(struct tx4938_pcic_reg *pcicptr)
74{
75 int code = PCIBIOS_SUCCESSFUL;
76 /* wait write cycle completion before checking error status */
77 while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
78 ;
79 if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
80 pcicptr->pcistatus =
81 (pcicptr->
82 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
83 << 16);
84 pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
85 code = PCIBIOS_DEVICE_NOT_FOUND;
86 }
87 return code;
88}
89
90extern struct pci_controller tx4938_pci_controller[];
91extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch);
92
93static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus)
94{
95 struct pci_controller *channel = bus->sysdata;
96 return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]);
97}
98
99static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 * val)
101{
102 int retval, dev, busno, func;
103 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
104 void __iomem *cfgdata =
105 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
106
107 dev = PCI_SLOT(devfn);
108 func = PCI_FUNC(devfn);
109
110 /* check if the bus is top-level */
111 if (bus->parent != NULL)
112 busno = bus->number;
113 else {
114 busno = 0;
115 }
116
117 if (mkaddr(busno, devfn, where, pcicptr))
118 return -1;
119
120 switch (size) {
121 case 1:
122#ifdef __BIG_ENDIAN
123 cfgdata += (where & 3) ^ 3;
124#else
125 cfgdata += where & 3;
126#endif
127 *val = __raw_readb(cfgdata);
128 break;
129 case 2:
130#ifdef __BIG_ENDIAN
131 cfgdata += (where & 2) ^ 2;
132#else
133 cfgdata += where & 2;
134#endif
135 *val = __raw_readw(cfgdata);
136 break;
137 case 4:
138 *val = __raw_readl(cfgdata);
139 break;
140 }
141
142 retval = check_abort(pcicptr);
143 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
144 *val = 0xffffffff;
145
146 return retval;
147}
148
149static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
150 int size, u32 val)
151{
152 int dev, busno, func;
153 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
154 void __iomem *cfgdata =
155 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
156
157 busno = bus->number;
158 dev = PCI_SLOT(devfn);
159 func = PCI_FUNC(devfn);
160
161 /* check if the bus is top-level */
162 if (bus->parent != NULL) {
163 busno = bus->number;
164 } else {
165 busno = 0;
166 }
167
168 if (mkaddr(busno, devfn, where, pcicptr))
169 return -1;
170
171 switch (size) {
172 case 1:
173#ifdef __BIG_ENDIAN
174 cfgdata += (where & 3) ^ 3;
175#else
176 cfgdata += where & 3;
177#endif
178 __raw_writeb(val, cfgdata);
179 break;
180 case 2:
181#ifdef __BIG_ENDIAN
182 cfgdata += (where & 2) ^ 2;
183#else
184 cfgdata += where & 2;
185#endif
186 __raw_writew(val, cfgdata);
187 break;
188 case 4:
189 __raw_writel(val, cfgdata);
190 break;
191 }
192
193 return check_abort(pcicptr);
194}
195
196struct pci_ops tx4938_pci_ops = {
197 tx4938_pcibios_read_config,
198 tx4938_pcibios_write_config
199};
200
201struct pci_controller tx4938_pci_controller[] = {
202 /* h/w only supports devices 0x00 to 0x14 */
203 {
204 .pci_ops = &tx4938_pci_ops,
205 .io_resource = &pci_io_resource,
206 .mem_resource = &pci_mem_resource,
207 },
208 /* h/w only supports devices 0x00 to 0x14 */
209 {
210 .pci_ops = &tx4938_pci_ops,
211 .io_resource = &tx4938_pcic1_pci_io_resource,
212 .mem_resource = &tx4938_pcic1_pci_mem_resource,
213 }
214};
diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c
deleted file mode 100644
index 7fb6bd71901a..000000000000
--- a/arch/mips/pci/pci-jmr3927.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/txx9/jmr3927.h>
35#include <asm/debug.h>
36
37struct resource pci_io_resource = {
38 .name = "IO MEM",
39 .start = 0x1000, /* reserve regacy I/O space */
40 .end = 0x1000 + JMR3927_PCIIO_SIZE - 1,
41 .flags = IORESOURCE_IO
42};
43
44struct resource pci_mem_resource = {
45 .name = "PCI MEM",
46 .start = JMR3927_PCIMEM,
47 .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
48 .flags = IORESOURCE_MEM
49};
50
51extern struct pci_ops jmr3927_pci_ops;
52
53struct pci_controller jmr3927_controller = {
54 .pci_ops = &jmr3927_pci_ops,
55 .io_resource = &pci_io_resource,
56 .mem_resource = &pci_mem_resource,
57 .mem_offset = JMR3927_PCIMEM
58};
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
new file mode 100644
index 000000000000..27e86a09dd41
--- /dev/null
+++ b/arch/mips/pci/pci-tx4927.c
@@ -0,0 +1,83 @@
1/*
2 * linux/arch/mips/pci/pci-tx4927.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4927.h>
20
21int __init tx4927_report_pciclk(void)
22{
23 int pciclk = 0;
24
25 printk(KERN_INFO "PCIC --%s PCICLK:",
26 (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
27 " PCI66" : "");
28 if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
29 u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
30 switch ((unsigned long)ccfg &
31 TX4927_CCFG_PCIDIVMODE_MASK) {
32 case TX4927_CCFG_PCIDIVMODE_2_5:
33 pciclk = txx9_cpu_clock * 2 / 5; break;
34 case TX4927_CCFG_PCIDIVMODE_3:
35 pciclk = txx9_cpu_clock / 3; break;
36 case TX4927_CCFG_PCIDIVMODE_5:
37 pciclk = txx9_cpu_clock / 5; break;
38 case TX4927_CCFG_PCIDIVMODE_6:
39 pciclk = txx9_cpu_clock / 6; break;
40 }
41 printk("Internal(%u.%uMHz)",
42 (pciclk + 50000) / 1000000,
43 ((pciclk + 50000) / 100000) % 10);
44 } else {
45 printk("External");
46 pciclk = -1;
47 }
48 printk("\n");
49 return pciclk;
50}
51
52int __init tx4927_pciclk66_setup(void)
53{
54 int pciclk;
55
56 /* Assert M66EN */
57 tx4927_ccfg_set(TX4927_CCFG_PCI66);
58 /* Double PCICLK (if possible) */
59 if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
60 unsigned int pcidivmode = 0;
61 u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
62 pcidivmode = (unsigned long)ccfg &
63 TX4927_CCFG_PCIDIVMODE_MASK;
64 switch (pcidivmode) {
65 case TX4927_CCFG_PCIDIVMODE_5:
66 case TX4927_CCFG_PCIDIVMODE_2_5:
67 pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
68 pciclk = txx9_cpu_clock * 2 / 5;
69 break;
70 case TX4927_CCFG_PCIDIVMODE_6:
71 case TX4927_CCFG_PCIDIVMODE_3:
72 default:
73 pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
74 pciclk = txx9_cpu_clock / 3;
75 }
76 tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
77 pcidivmode);
78 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
79 (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
80 } else
81 pciclk = -1;
82 return pciclk;
83}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
new file mode 100644
index 000000000000..e5375511c2b7
--- /dev/null
+++ b/arch/mips/pci/pci-tx4938.c
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/mips/pci/pci-tx4938.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4938.h>
20
21int __init tx4938_report_pciclk(void)
22{
23 int pciclk = 0;
24
25 printk(KERN_INFO "PCIC --%s PCICLK:",
26 (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
27 " PCI66" : "");
28 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
29 u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
30 switch ((unsigned long)ccfg &
31 TX4938_CCFG_PCIDIVMODE_MASK) {
32 case TX4938_CCFG_PCIDIVMODE_4:
33 pciclk = txx9_cpu_clock / 4; break;
34 case TX4938_CCFG_PCIDIVMODE_4_5:
35 pciclk = txx9_cpu_clock * 2 / 9; break;
36 case TX4938_CCFG_PCIDIVMODE_5:
37 pciclk = txx9_cpu_clock / 5; break;
38 case TX4938_CCFG_PCIDIVMODE_5_5:
39 pciclk = txx9_cpu_clock * 2 / 11; break;
40 case TX4938_CCFG_PCIDIVMODE_8:
41 pciclk = txx9_cpu_clock / 8; break;
42 case TX4938_CCFG_PCIDIVMODE_9:
43 pciclk = txx9_cpu_clock / 9; break;
44 case TX4938_CCFG_PCIDIVMODE_10:
45 pciclk = txx9_cpu_clock / 10; break;
46 case TX4938_CCFG_PCIDIVMODE_11:
47 pciclk = txx9_cpu_clock / 11; break;
48 }
49 printk("Internal(%u.%uMHz)",
50 (pciclk + 50000) / 1000000,
51 ((pciclk + 50000) / 100000) % 10);
52 } else {
53 printk("External");
54 pciclk = -1;
55 }
56 printk("\n");
57 return pciclk;
58}
59
60void __init tx4938_report_pci1clk(void)
61{
62 __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
63 unsigned int pciclk =
64 txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
65
66 printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
67 (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
68 (pciclk + 50000) / 1000000,
69 ((pciclk + 50000) / 100000) % 10);
70}
71
72int __init tx4938_pciclk66_setup(void)
73{
74 int pciclk;
75
76 /* Assert M66EN */
77 tx4938_ccfg_set(TX4938_CCFG_PCI66);
78 /* Double PCICLK (if possible) */
79 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
80 unsigned int pcidivmode = 0;
81 u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
82 pcidivmode = (unsigned long)ccfg &
83 TX4938_CCFG_PCIDIVMODE_MASK;
84 switch (pcidivmode) {
85 case TX4938_CCFG_PCIDIVMODE_8:
86 case TX4938_CCFG_PCIDIVMODE_4:
87 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
88 pciclk = txx9_cpu_clock / 4;
89 break;
90 case TX4938_CCFG_PCIDIVMODE_9:
91 case TX4938_CCFG_PCIDIVMODE_4_5:
92 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
93 pciclk = txx9_cpu_clock * 2 / 9;
94 break;
95 case TX4938_CCFG_PCIDIVMODE_10:
96 case TX4938_CCFG_PCIDIVMODE_5:
97 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
98 pciclk = txx9_cpu_clock / 5;
99 break;
100 case TX4938_CCFG_PCIDIVMODE_11:
101 case TX4938_CCFG_PCIDIVMODE_5_5:
102 default:
103 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
104 pciclk = txx9_cpu_clock * 2 / 11;
105 break;
106 }
107 tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
108 pcidivmode);
109 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
110 (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
111 } else
112 pciclk = -1;
113 return pciclk;
114}
115
116int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
117{
118 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
119 switch (slot) {
120 case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
121 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
122 TX4938_PCFG_ETH0_SEL)
123 return TXX9_IRQ_BASE + TX4938_IR_ETH0;
124 break;
125 case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
126 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
127 TX4938_PCFG_ETH1_SEL)
128 return TXX9_IRQ_BASE + TX4938_IR_ETH1;
129 break;
130 }
131 return 0;
132 }
133 return -1;
134}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 06:27:38 -0500