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-rw-r--r--arch/mips/pci/ops-tx4927.c514
1 files changed, 358 insertions, 156 deletions
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 54730eee451b..c6b49bccd274 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,206 +1,408 @@
1/* 1/*
2 * Copyright 2001 MontaVista Software Inc. 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 * 3 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 4 * Based on linux/arch/mips/pci/ops-tx4938.c,
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 5 * linux/arch/mips/pci/fixup-rbtx4938.c,
8 * 6 * linux/arch/mips/txx9/rbtx4938/setup.c,
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 7 * and RBTX49xx patch from CELF patch archive.
10 *
11 * Define the pci_ops for the Toshiba rbtx4927
12 *
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
15 *
16 * Copyright 2004 MontaVista Software Inc.
17 * Author: Manish Lachwani (mlachwani@mvista.com)
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 * 8 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 9 * 2003-2005 (c) MontaVista Software, Inc.
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * 12 *
35 * You should have received a copy of the GNU General Public License along 13 * This program is free software; you can redistribute it and/or modify it
36 * with this program; if not, write to the Free Software Foundation, Inc., 14 * under the terms of the GNU General Public License as published by the
37 * 675 Mass Ave, Cambridge, MA 02139, USA. 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
38 */ 17 */
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h> 18#include <linux/kernel.h>
42#include <linux/init.h> 19#include <asm/txx9/tx4927pcic.h>
43#include <asm/txx9/tx4927.h>
44
45/* initialize in setup */
46struct resource pci_io_resource = {
47 .name = "TX4927 PCI IO SPACE",
48 .start = 0x1000,
49 .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1,
50 .flags = IORESOURCE_IO
51};
52 20
53/* initialize in setup */ 21static struct {
54struct resource pci_mem_resource = { 22 struct pci_controller *channel;
55 .name = "TX4927 PCI MEM SPACE", 23 struct tx4927_pcic_reg __iomem *pcicptr;
56 .start = TX4927_PCIMEM, 24} pcicptrs[2]; /* TX4938 has 2 pcic */
57 .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, 25
58 .flags = IORESOURCE_MEM 26static void __init set_tx4927_pcicptr(struct pci_controller *channel,
59}; 27 struct tx4927_pcic_reg __iomem *pcicptr)
28{
29 int i;
30
31 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
32 if (pcicptrs[i].channel == channel) {
33 pcicptrs[i].pcicptr = pcicptr;
34 return;
35 }
36 }
37 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
38 if (!pcicptrs[i].channel) {
39 pcicptrs[i].channel = channel;
40 pcicptrs[i].pcicptr = pcicptr;
41 return;
42 }
43 }
44 BUG();
45}
60 46
61static int mkaddr(int bus, int dev_fn, int where, int *flagsp) 47struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
48 struct pci_controller *channel)
62{ 49{
63 if (bus > 0) { 50 int i;
64 /* Type 1 configuration */
65 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
66 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
67 } else {
68 if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
69 return -1;
70 51
71 /* Type 0 configuration */ 52 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
72 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | 53 if (pcicptrs[i].channel == channel)
73 ((dev_fn & 0xff) << 0x08) | (where & 0xfc); 54 return pcicptrs[i].pcicptr;
74 } 55 }
56 return NULL;
57}
58
59static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
60 struct tx4927_pcic_reg __iomem *pcicptr)
61{
62 if (bus->parent == NULL &&
63 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
64 return -1;
65 __raw_writel(((bus->number & 0xff) << 0x10)
66 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
67 | (bus->parent ? 1 : 0),
68 &pcicptr->g2pcfgadrs);
75 /* clear M_ABORT and Disable M_ABORT Int. */ 69 /* clear M_ABORT and Disable M_ABORT Int. */
76 tx4927_pcicptr->pcistatus = 70 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
77 (tx4927_pcicptr->pcistatus & 0x0000ffff) | 71 | (PCI_STATUS_REC_MASTER_ABORT << 16),
78 (PCI_STATUS_REC_MASTER_ABORT << 16); 72 &pcicptr->pcistatus);
79 tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
80 return 0; 73 return 0;
81} 74}
82 75
83static int check_abort(int flags) 76static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
84{ 77{
85 int code = PCIBIOS_SUCCESSFUL; 78 int code = PCIBIOS_SUCCESSFUL;
86 if (tx4927_pcicptr-> 79
87 pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 80 /* wait write cycle completion before checking error status */
88 tx4927_pcicptr->pcistatus = 81 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
89 (tx4927_pcicptr-> 82 ;
90 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT 83 if (__raw_readl(&pcicptr->pcistatus)
91 << 16); 84 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
92 tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; 85 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT << 16),
87 &pcicptr->pcistatus);
93 code = PCIBIOS_DEVICE_NOT_FOUND; 88 code = PCIBIOS_DEVICE_NOT_FOUND;
94 } 89 }
95 return code; 90 return code;
96} 91}
97 92
98static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, 93static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
99 int size, u32 * val) 94{
95#ifdef __BIG_ENDIAN
96 offset ^= 3;
97#endif
98 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
99}
100static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
101{
102#ifdef __BIG_ENDIAN
103 offset ^= 2;
104#endif
105 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
106}
107static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
108{
109 return __raw_readl(&pcicptr->g2pcfgdata);
110}
111static void icd_writeb(u8 val, int offset,
112 struct tx4927_pcic_reg __iomem *pcicptr)
113{
114#ifdef __BIG_ENDIAN
115 offset ^= 3;
116#endif
117 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
118}
119static void icd_writew(u16 val, int offset,
120 struct tx4927_pcic_reg __iomem *pcicptr)
121{
122#ifdef __BIG_ENDIAN
123 offset ^= 2;
124#endif
125 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
126}
127static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
100{ 128{
101 int flags, retval, dev, busno, func; 129 __raw_writel(val, &pcicptr->g2pcfgdata);
130}
102 131
103 busno = bus->number; 132static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
104 dev = PCI_SLOT(devfn); 133{
105 func = PCI_FUNC(devfn); 134 struct pci_controller *channel = bus->sysdata;
135 return get_tx4927_pcicptr(channel);
136}
106 137
107 /* check if the bus is top-level */ 138static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
108 if (bus->parent != NULL) { 139 int where, int size, u32 *val)
109 busno = bus->number; 140{
110 } else { 141 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
111 busno = 0;
112 }
113 142
114 if (mkaddr(busno, devfn, where, &flags)) 143 if (mkaddr(bus, devfn, where, pcicptr)) {
144 *val = 0xffffffff;
115 return -1; 145 return -1;
116 146 }
117 switch (size) { 147 switch (size) {
118 case 1: 148 case 1:
119 *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 149 *val = icd_readb(where & 3, pcicptr);
120 g2pcfgdata |
121#ifdef __LITTLE_ENDIAN
122 (where & 3));
123#else
124 ((where & 0x3) ^ 0x3));
125#endif
126 break; 150 break;
127 case 2: 151 case 2:
128 *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 152 *val = icd_readw(where & 3, pcicptr);
129 g2pcfgdata |
130#ifdef __LITTLE_ENDIAN
131 (where & 3));
132#else
133 ((where & 0x3) ^ 0x2));
134#endif
135 break;
136 case 4:
137 *val = tx4927_pcicptr->g2pcfgdata;
138 break; 153 break;
154 default:
155 *val = icd_readl(pcicptr);
139 } 156 }
157 return check_abort(pcicptr);
158}
140 159
141 retval = check_abort(flags); 160static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
142 if (retval == PCIBIOS_DEVICE_NOT_FOUND) 161 int where, int size, u32 val)
143 *val = 0xffffffff; 162{
163 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
144 164
145 return retval; 165 if (mkaddr(bus, devfn, where, pcicptr))
166 return -1;
167 switch (size) {
168 case 1:
169 icd_writeb(val, where & 3, pcicptr);
170 break;
171 case 2:
172 icd_writew(val, where & 3, pcicptr);
173 break;
174 default:
175 icd_writel(val, pcicptr);
176 }
177 return check_abort(pcicptr);
146} 178}
147 179
148static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, 180static struct pci_ops tx4927_pci_ops = {
149 int size, u32 val) 181 .read = tx4927_pci_config_read,
182 .write = tx4927_pci_config_write,
183};
184
185static struct {
186 u8 trdyto;
187 u8 retryto;
188 u16 gbwc;
189} tx4927_pci_opts __devinitdata = {
190 .trdyto = 0,
191 .retryto = 0,
192 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
193};
194
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb)
150{ 197{
151 int flags, dev, busno, func; 198 int i;
152 busno = bus->number; 199 unsigned long flags;
153 dev = PCI_SLOT(devfn);
154 func = PCI_FUNC(devfn);
155 200
156 /* check if the bus is top-level */ 201 set_tx4927_pcicptr(channel, pcicptr);
157 if (bus->parent != NULL) {
158 busno = bus->number;
159 } else {
160 busno = 0;
161 }
162 202
163 if (mkaddr(busno, devfn, where, &flags)) 203 if (!channel->pci_ops)
164 return -1; 204 printk(KERN_INFO
205 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
206 __raw_readl(&pcicptr->pciid) >> 16,
207 __raw_readl(&pcicptr->pciid) & 0xffff,
208 __raw_readl(&pcicptr->pciccrev) & 0xff,
209 extarb ? "External" : "Internal");
210 channel->pci_ops = &tx4927_pci_ops;
165 211
166 switch (size) { 212 local_irq_save(flags);
167 case 1: 213
168 *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 214 /* Disable All Initiator Space */
169 g2pcfgdata | 215 __raw_writel(__raw_readl(&pcicptr->pciccfg)
170#ifdef __LITTLE_ENDIAN 216 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
171 (where & 3)) = val; 217 | TX4927_PCIC_PCICCFG_G2PMEN(1)
218 | TX4927_PCIC_PCICCFG_G2PMEN(2)
219 | TX4927_PCIC_PCICCFG_G2PIOEN),
220 &pcicptr->pciccfg);
221
222 /* GB->PCI mappings */
223 __raw_writel((channel->io_resource->end - channel->io_resource->start)
224 >> 4,
225 &pcicptr->g2piomask);
226 ____raw_writeq((channel->io_resource->start +
227 channel->io_map_base - IO_BASE) |
228#ifdef __BIG_ENDIAN
229 TX4927_PCIC_G2PIOGBASE_ECHG
172#else 230#else
173 ((where & 0x3) ^ 0x3)) = val; 231 TX4927_PCIC_G2PIOGBASE_BSDIS
174#endif 232#endif
175 break; 233 , &pcicptr->g2piogbase);
176 234 ____raw_writeq(channel->io_resource->start - channel->io_offset,
177 case 2: 235 &pcicptr->g2piopbase);
178 *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 236 for (i = 0; i < 3; i++) {
179 g2pcfgdata | 237 __raw_writel(0, &pcicptr->g2pmmask[i]);
180#ifdef __LITTLE_ENDIAN 238 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
181 (where & 3)) = val; 239 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
240 }
241 if (channel->mem_resource->end) {
242 __raw_writel((channel->mem_resource->end
243 - channel->mem_resource->start) >> 4,
244 &pcicptr->g2pmmask[0]);
245 ____raw_writeq(channel->mem_resource->start |
246#ifdef __BIG_ENDIAN
247 TX4927_PCIC_G2PMnGBASE_ECHG
182#else 248#else
183 ((where & 0x3) ^ 0x2)) = val; 249 TX4927_PCIC_G2PMnGBASE_BSDIS
184#endif 250#endif
185 break; 251 , &pcicptr->g2pmgbase[0]);
186 case 4: 252 ____raw_writeq(channel->mem_resource->start -
187 tx4927_pcicptr->g2pcfgdata = val; 253 channel->mem_offset,
188 break; 254 &pcicptr->g2pmpbase[0]);
255 }
256 /* PCI->GB mappings (I/O 256B) */
257 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
258 ____raw_writeq(0, &pcicptr->p2giogbase);
259 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
260 __raw_writel(0, &pcicptr->p2gm0plbase);
261 __raw_writel(0, &pcicptr->p2gm0pubase);
262 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
263#ifdef __BIG_ENDIAN
264 TX4927_PCIC_P2GMnGBASE_TECHG
265#else
266 TX4927_PCIC_P2GMnGBASE_TBSDIS
267#endif
268 , &pcicptr->p2gmgbase[0]);
269 /* PCI->GB mappings (MEM 16MB) */
270 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
271 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
272 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
273 /* PCI->GB mappings (MEM 1MB) */
274 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
275 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
276
277 /* Clear all (including IRBER) except for GBWC */
278 __raw_writel((tx4927_pci_opts.gbwc << 16)
279 & TX4927_PCIC_PCICCFG_GBWC_MASK,
280 &pcicptr->pciccfg);
281 /* Enable Initiator Memory Space */
282 if (channel->mem_resource->end)
283 __raw_writel(__raw_readl(&pcicptr->pciccfg)
284 | TX4927_PCIC_PCICCFG_G2PMEN(0),
285 &pcicptr->pciccfg);
286 /* Enable Initiator I/O Space */
287 if (channel->io_resource->end)
288 __raw_writel(__raw_readl(&pcicptr->pciccfg)
289 | TX4927_PCIC_PCICCFG_G2PIOEN,
290 &pcicptr->pciccfg);
291 /* Enable Initiator Config */
292 __raw_writel(__raw_readl(&pcicptr->pciccfg)
293 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
294 &pcicptr->pciccfg);
295
296 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
297 __raw_writel(0, &pcicptr->pcicfg1);
298
299 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
300 | (tx4927_pci_opts.trdyto & 0xff)
301 | ((tx4927_pci_opts.retryto & 0xff) << 8),
302 &pcicptr->g2ptocnt);
303
304 /* Clear All Local Bus Status */
305 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
306 /* Enable All Local Bus Interrupts */
307 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
308 /* Clear All Initiator Status */
309 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
310 /* Enable All Initiator Interrupts */
311 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
312 /* Clear All PCI Status Error */
313 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
314 | (TX4927_PCIC_PCISTATUS_ALL << 16),
315 &pcicptr->pcistatus);
316 /* Enable All PCI Status Error Interrupts */
317 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
318
319 if (!extarb) {
320 /* Reset Bus Arbiter */
321 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
322 __raw_writel(0, &pcicptr->pbabm);
323 /* Enable Bus Arbiter */
324 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
189 } 325 }
190 326
191 return check_abort(flags); 327 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
328 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
329 &pcicptr->pcistatus);
330 local_irq_restore(flags);
331
332 printk(KERN_DEBUG
333 "PCI: COMMAND=%04x,PCIMASK=%04x,"
334 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
335 __raw_readl(&pcicptr->pcistatus) & 0xffff,
336 __raw_readl(&pcicptr->pcimask) & 0xffff,
337 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
338 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
339 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
192} 340}
193 341
194struct pci_ops tx4927_pci_ops = { 342static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
195 tx4927_pcibios_read_config, 343{
196 tx4927_pcibios_write_config 344 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
197}; 345 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
346 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
347 static struct {
348 __u32 flag;
349 const char *str;
350 } pcistat_tbl[] = {
351 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
352 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
353 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
354 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
355 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
356 { PCI_STATUS_PARITY, "MasterParityError" },
357 }, g2pstat_tbl[] = {
358 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
359 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
360 }, pcicstat_tbl[] = {
361 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
362 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
363 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
364 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
365 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
366 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
367 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
368 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
369 };
370 int i, cont;
198 371
199/* 372 printk(KERN_ERR "");
200 * h/w only supports devices 0x00 to 0x14 373 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
201 */ 374 printk(KERN_CONT "pcistat:%04x(", pcistatus);
202struct pci_controller tx4927_controller = { 375 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
203 .pci_ops = &tx4927_pci_ops, 376 if (pcistatus & pcistat_tbl[i].flag)
204 .io_resource = &pci_io_resource, 377 printk(KERN_CONT "%s%s",
205 .mem_resource = &pci_mem_resource, 378 cont++ ? " " : "", pcistat_tbl[i].str);
206}; 379 printk(KERN_CONT ") ");
380 }
381 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
382 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
383 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
384 if (g2pstatus & g2pstat_tbl[i].flag)
385 printk(KERN_CONT "%s%s",
386 cont++ ? " " : "", g2pstat_tbl[i].str);
387 printk(KERN_CONT ") ");
388 }
389 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
390 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
391 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
392 if (pcicstatus & pcicstat_tbl[i].flag)
393 printk(KERN_CONT "%s%s",
394 cont++ ? " " : "", pcicstat_tbl[i].str);
395 printk(KERN_CONT ")");
396 }
397 printk(KERN_CONT "\n");
398}
399
400void tx4927_report_pcic_status(void)
401{
402 int i;
403
404 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
405 if (pcicptrs[i].pcicptr)
406 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
407 }
408}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 07:18:55 -0500