diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-11-04 02:10:35 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-11-04 02:10:35 -0500 |
commit | b6d0137d6156db54a9e6ff74458ed4342a45abb5 (patch) | |
tree | ae4139b2af5af7e382208645d4b66ff184c1e53a /arch/mips/mti-malta | |
parent | 5c1a56b5f616f7063f91eb85f0ea209658f387dc (diff) | |
parent | 51bb296b09a83ee1aae025778db38f9d2cc7bb1a (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips/mti-malta')
-rw-r--r-- | arch/mips/mti-malta/malta-amon.c | 7 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-int.c | 119 | ||||
-rw-r--r-- | arch/mips/mti-malta/malta-pci.c | 27 |
3 files changed, 100 insertions, 53 deletions
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index df9e526312a2..469d9b0cee6d 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c | |||
@@ -70,11 +70,12 @@ void amon_cpu_start(int cpu, | |||
70 | launch->sp = sp; | 70 | launch->sp = sp; |
71 | launch->a0 = a0; | 71 | launch->a0 = a0; |
72 | 72 | ||
73 | /* Make sure target sees parameters before the go bit */ | 73 | smp_wmb(); /* Target must see parameters before go */ |
74 | smp_mb(); | ||
75 | |||
76 | launch->flags |= LAUNCH_FGO; | 74 | launch->flags |= LAUNCH_FGO; |
75 | smp_wmb(); /* Target must see go before we poll */ | ||
76 | |||
77 | while ((launch->flags & LAUNCH_FGONE) == 0) | 77 | while ((launch->flags & LAUNCH_FGONE) == 0) |
78 | ; | 78 | ; |
79 | smp_rmb(); /* Target will be updating flags soon */ | ||
79 | pr_debug("launch: cpu%d gone!\n", cpu); | 80 | pr_debug("launch: cpu%d gone!\n", cpu); |
80 | } | 81 | } |
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 3e0a9b35ba5c..4c3fca18a171 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c | |||
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void) | |||
87 | dummy = BONITO_PCIMAP_CFG; | 87 | dummy = BONITO_PCIMAP_CFG; |
88 | iob(); /* sync */ | 88 | iob(); /* sync */ |
89 | 89 | ||
90 | irq = readl((u32 *)_pcictrl_bonito_pcicfg); | 90 | irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); |
91 | iob(); /* sync */ | 91 | iob(); /* sync */ |
92 | irq &= 0xff; | 92 | irq &= 0xff; |
93 | BONITO_PCIMAP_CFG = 0; | 93 | BONITO_PCIMAP_CFG = 0; |
@@ -379,38 +379,43 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = { | |||
379 | 379 | ||
380 | static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); | 380 | static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); |
381 | 381 | ||
382 | #if defined(CONFIG_MIPS_MT_SMP) | ||
383 | /* | 382 | /* |
384 | * This GIC specific tabular array defines the association between External | 383 | * This GIC specific tabular array defines the association between External |
385 | * Interrupts and CPUs/Core Interrupts. The nature of the External | 384 | * Interrupts and CPUs/Core Interrupts. The nature of the External |
386 | * Interrupts is also defined here - polarity/trigger. | 385 | * Interrupts is also defined here - polarity/trigger. |
387 | */ | 386 | */ |
387 | |||
388 | #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK | ||
388 | static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { | 389 | static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { |
389 | { GIC_EXT_INTR(0), X, X, X, X, 0 }, | 390 | { X, X, X, X, 0 }, |
390 | { GIC_EXT_INTR(1), X, X, X, X, 0 }, | 391 | { X, X, X, X, 0 }, |
391 | { GIC_EXT_INTR(2), X, X, X, X, 0 }, | 392 | { X, X, X, X, 0 }, |
392 | { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 393 | { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
393 | { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 394 | { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
394 | { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 395 | { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
395 | { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 396 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
396 | { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 397 | { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
397 | { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 398 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
398 | { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 399 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
399 | { GIC_EXT_INTR(10), X, X, X, X, 0 }, | 400 | { X, X, X, X, 0 }, |
400 | { GIC_EXT_INTR(11), X, X, X, X, 0 }, | 401 | { X, X, X, X, 0 }, |
401 | { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 402 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
402 | { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 403 | { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
403 | { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 404 | { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
404 | { GIC_EXT_INTR(15), X, X, X, X, 0 }, | 405 | { X, X, X, X, 0 }, |
405 | /* This is the end of the general interrupts now we do IPI ones */ | 406 | /* The remainder of this table is initialised by fill_ipi_map */ |
406 | }; | 407 | }; |
407 | #endif | ||
408 | 408 | ||
409 | /* | 409 | /* |
410 | * GCMP needs to be detected before any SMP initialisation | 410 | * GCMP needs to be detected before any SMP initialisation |
411 | */ | 411 | */ |
412 | int __init gcmp_probe(unsigned long addr, unsigned long size) | 412 | int __init gcmp_probe(unsigned long addr, unsigned long size) |
413 | { | 413 | { |
414 | if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { | ||
415 | gcmp_present = 0; | ||
416 | return gcmp_present; | ||
417 | } | ||
418 | |||
414 | if (gcmp_present >= 0) | 419 | if (gcmp_present >= 0) |
415 | return gcmp_present; | 420 | return gcmp_present; |
416 | 421 | ||
@@ -419,20 +424,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size) | |||
419 | gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; | 424 | gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; |
420 | 425 | ||
421 | if (gcmp_present) | 426 | if (gcmp_present) |
422 | printk(KERN_DEBUG "GCMP present\n"); | 427 | pr_debug("GCMP present\n"); |
423 | return gcmp_present; | 428 | return gcmp_present; |
424 | } | 429 | } |
425 | 430 | ||
431 | /* Return the number of IOCU's present */ | ||
432 | int __init gcmp_niocu(void) | ||
433 | { | ||
434 | return gcmp_present ? | ||
435 | (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : | ||
436 | 0; | ||
437 | } | ||
438 | |||
439 | /* Set GCMP region attributes */ | ||
440 | void __init gcmp_setregion(int region, unsigned long base, | ||
441 | unsigned long mask, int type) | ||
442 | { | ||
443 | GCMPGCBn(CMxBASE, region) = base; | ||
444 | GCMPGCBn(CMxMASK, region) = mask | type; | ||
445 | } | ||
446 | |||
426 | #if defined(CONFIG_MIPS_MT_SMP) | 447 | #if defined(CONFIG_MIPS_MT_SMP) |
427 | static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) | 448 | static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) |
428 | { | 449 | { |
429 | int intr = baseintr + cpu; | 450 | int intr = baseintr + cpu; |
430 | gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); | ||
431 | gic_intr_map[intr].cpunum = cpu; | 451 | gic_intr_map[intr].cpunum = cpu; |
432 | gic_intr_map[intr].pin = cpupin; | 452 | gic_intr_map[intr].pin = cpupin; |
433 | gic_intr_map[intr].polarity = GIC_POL_POS; | 453 | gic_intr_map[intr].polarity = GIC_POL_POS; |
434 | gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; | 454 | gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; |
435 | gic_intr_map[intr].ipiflag = 1; | 455 | gic_intr_map[intr].flags = GIC_FLAG_IPI; |
436 | ipi_map[cpu] |= (1 << (cpupin + 2)); | 456 | ipi_map[cpu] |= (1 << (cpupin + 2)); |
437 | } | 457 | } |
438 | 458 | ||
@@ -447,6 +467,12 @@ static void __init fill_ipi_map(void) | |||
447 | } | 467 | } |
448 | #endif | 468 | #endif |
449 | 469 | ||
470 | void __init arch_init_ipiirq(int irq, struct irqaction *action) | ||
471 | { | ||
472 | setup_irq(irq, action); | ||
473 | set_irq_handler(irq, handle_percpu_irq); | ||
474 | } | ||
475 | |||
450 | void __init arch_init_irq(void) | 476 | void __init arch_init_irq(void) |
451 | { | 477 | { |
452 | init_i8259_irqs(); | 478 | init_i8259_irqs(); |
@@ -458,12 +484,17 @@ void __init arch_init_irq(void) | |||
458 | GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; | 484 | GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; |
459 | gic_present = 1; | 485 | gic_present = 1; |
460 | } else { | 486 | } else { |
461 | _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); | 487 | if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { |
462 | gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & | 488 | _msc01_biu_base = (unsigned long) |
463 | MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; | 489 | ioremap_nocache(MSC01_BIU_REG_BASE, |
490 | MSC01_BIU_ADDRSPACE_SZ); | ||
491 | gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & | ||
492 | MSC01_SC_CFG_GICPRES_MSK) >> | ||
493 | MSC01_SC_CFG_GICPRES_SHF; | ||
494 | } | ||
464 | } | 495 | } |
465 | if (gic_present) | 496 | if (gic_present) |
466 | printk(KERN_DEBUG "GIC present\n"); | 497 | pr_debug("GIC present\n"); |
467 | 498 | ||
468 | switch (mips_revision_sconid) { | 499 | switch (mips_revision_sconid) { |
469 | case MIPS_REVISION_SCON_SOCIT: | 500 | case MIPS_REVISION_SCON_SOCIT: |
@@ -526,16 +557,16 @@ void __init arch_init_irq(void) | |||
526 | &corehi_irqaction); | 557 | &corehi_irqaction); |
527 | } | 558 | } |
528 | 559 | ||
529 | #if defined(CONFIG_MIPS_MT_SMP) | ||
530 | if (gic_present) { | 560 | if (gic_present) { |
531 | /* FIXME */ | 561 | /* FIXME */ |
532 | int i; | 562 | int i; |
533 | 563 | #if defined(CONFIG_MIPS_MT_SMP) | |
534 | gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; | 564 | gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; |
535 | gic_resched_int_base = gic_call_int_base - NR_CPUS; | 565 | gic_resched_int_base = gic_call_int_base - NR_CPUS; |
536 | |||
537 | fill_ipi_map(); | 566 | fill_ipi_map(); |
538 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); | 567 | #endif |
568 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, | ||
569 | ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); | ||
539 | if (!gcmp_present) { | 570 | if (!gcmp_present) { |
540 | /* Enable the GIC */ | 571 | /* Enable the GIC */ |
541 | i = REG(_msc01_biu_base, MSC01_SC_CFG); | 572 | i = REG(_msc01_biu_base, MSC01_SC_CFG); |
@@ -543,7 +574,7 @@ void __init arch_init_irq(void) | |||
543 | (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); | 574 | (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); |
544 | pr_debug("GIC Enabled\n"); | 575 | pr_debug("GIC Enabled\n"); |
545 | } | 576 | } |
546 | 577 | #if defined(CONFIG_MIPS_MT_SMP) | |
547 | /* set up ipi interrupts */ | 578 | /* set up ipi interrupts */ |
548 | if (cpu_has_vint) { | 579 | if (cpu_has_vint) { |
549 | set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); | 580 | set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); |
@@ -556,16 +587,14 @@ void __init arch_init_irq(void) | |||
556 | write_c0_status(0x1100dc00); | 587 | write_c0_status(0x1100dc00); |
557 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); | 588 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); |
558 | for (i = 0; i < NR_CPUS; i++) { | 589 | for (i = 0; i < NR_CPUS; i++) { |
559 | setup_irq(MIPS_GIC_IRQ_BASE + | 590 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
560 | GIC_RESCHED_INT(i), &irq_resched); | 591 | GIC_RESCHED_INT(i), &irq_resched); |
561 | setup_irq(MIPS_GIC_IRQ_BASE + | 592 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
562 | GIC_CALL_INT(i), &irq_call); | 593 | GIC_CALL_INT(i), &irq_call); |
563 | set_irq_handler(MIPS_GIC_IRQ_BASE + | ||
564 | GIC_RESCHED_INT(i), handle_percpu_irq); | ||
565 | set_irq_handler(MIPS_GIC_IRQ_BASE + | ||
566 | GIC_CALL_INT(i), handle_percpu_irq); | ||
567 | } | 594 | } |
595 | #endif | ||
568 | } else { | 596 | } else { |
597 | #if defined(CONFIG_MIPS_MT_SMP) | ||
569 | /* set up ipi interrupts */ | 598 | /* set up ipi interrupts */ |
570 | if (cpu_has_veic) { | 599 | if (cpu_has_veic) { |
571 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); | 600 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); |
@@ -580,14 +609,10 @@ void __init arch_init_irq(void) | |||
580 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; | 609 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; |
581 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; | 610 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; |
582 | } | 611 | } |
583 | 612 | arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); | |
584 | setup_irq(cpu_ipi_resched_irq, &irq_resched); | 613 | arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); |
585 | setup_irq(cpu_ipi_call_irq, &irq_call); | ||
586 | |||
587 | set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); | ||
588 | set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); | ||
589 | } | ||
590 | #endif | 614 | #endif |
615 | } | ||
591 | } | 616 | } |
592 | 617 | ||
593 | void malta_be_init(void) | 618 | void malta_be_init(void) |
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b9743190609a..2fbfa1a8c3a9 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
28 | 28 | ||
29 | #include <asm/gt64120.h> | 29 | #include <asm/gt64120.h> |
30 | 30 | #include <asm/gcmpregs.h> | |
31 | #include <asm/mips-boards/generic.h> | 31 | #include <asm/mips-boards/generic.h> |
32 | #include <asm/mips-boards/bonito64.h> | 32 | #include <asm/mips-boards/bonito64.h> |
33 | #include <asm/mips-boards/msc01_pci.h> | 33 | #include <asm/mips-boards/msc01_pci.h> |
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) | |||
201 | msc_mem_resource.start = start & mask; | 201 | msc_mem_resource.start = start & mask; |
202 | msc_mem_resource.end = (start & mask) | ~mask; | 202 | msc_mem_resource.end = (start & mask) | ~mask; |
203 | msc_controller.mem_offset = (start & mask) - (map & mask); | 203 | msc_controller.mem_offset = (start & mask) - (map & mask); |
204 | 204 | #ifdef CONFIG_MIPS_CMP | |
205 | if (gcmp_niocu()) | ||
206 | gcmp_setregion(0, start, mask, | ||
207 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
208 | #endif | ||
205 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); | 209 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); |
206 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); | 210 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); |
207 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); | 211 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); |
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) | |||
209 | msc_io_resource.end = (map & mask) | ~mask; | 213 | msc_io_resource.end = (map & mask) | ~mask; |
210 | msc_controller.io_offset = 0; | 214 | msc_controller.io_offset = 0; |
211 | ioport_resource.end = ~mask; | 215 | ioport_resource.end = ~mask; |
212 | 216 | #ifdef CONFIG_MIPS_CMP | |
217 | if (gcmp_niocu()) | ||
218 | gcmp_setregion(1, start, mask, | ||
219 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
220 | #endif | ||
213 | /* If ranges overlap I/O takes precedence. */ | 221 | /* If ranges overlap I/O takes precedence. */ |
214 | start = start & mask; | 222 | start = start & mask; |
215 | end = start | ~mask; | 223 | end = start | ~mask; |
@@ -241,3 +249,16 @@ void __init mips_pcibios_init(void) | |||
241 | 249 | ||
242 | register_pci_controller(controller); | 250 | register_pci_controller(controller); |
243 | } | 251 | } |
252 | |||
253 | /* Enable PCI 2.1 compatibility in PIIX4 */ | ||
254 | static void __init quirk_dlcsetup(struct pci_dev *dev) | ||
255 | { | ||
256 | u8 odlc, ndlc; | ||
257 | (void) pci_read_config_byte(dev, 0x82, &odlc); | ||
258 | /* Enable passive releases and delayed transaction */ | ||
259 | ndlc = odlc | 7; | ||
260 | (void) pci_write_config_byte(dev, 0x82, ndlc); | ||
261 | } | ||
262 | |||
263 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | ||
264 | quirk_dlcsetup); | ||