diff options
author | Paul Mundt <lethal@linux-sh.org> | 2009-11-04 02:10:35 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-11-04 02:10:35 -0500 |
commit | b6d0137d6156db54a9e6ff74458ed4342a45abb5 (patch) | |
tree | ae4139b2af5af7e382208645d4b66ff184c1e53a /arch/mips | |
parent | 5c1a56b5f616f7063f91eb85f0ea209658f387dc (diff) | |
parent | 51bb296b09a83ee1aae025778db38f9d2cc7bb1a (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/mips')
54 files changed, 544 insertions, 440 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 705a7a9170f3..03bd56a2fb6e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -1012,9 +1012,9 @@ config BOOT_ELF32 | |||
1012 | 1012 | ||
1013 | config MIPS_L1_CACHE_SHIFT | 1013 | config MIPS_L1_CACHE_SHIFT |
1014 | int | 1014 | int |
1015 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 | 1015 | default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL |
1016 | default "6" if MIPS_CPU_SCACHE | ||
1016 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON | 1017 | default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON |
1017 | default "4" if PMC_MSP4200_EVAL | ||
1018 | default "5" | 1018 | default "5" |
1019 | 1019 | ||
1020 | config HAVE_STD_PC_SERIAL_PORT | 1020 | config HAVE_STD_PC_SERIAL_PORT |
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index c88c821b4c36..d670928afcfd 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c | |||
@@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr) | |||
354 | au_sync(); | 354 | au_sync(); |
355 | } | 355 | } |
356 | 356 | ||
357 | static void au1x_ic0_maskack(unsigned int irq_nr) | ||
358 | { | ||
359 | unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; | ||
360 | |||
361 | au_writel(1 << bit, IC0_WAKECLR); | ||
362 | au_writel(1 << bit, IC0_MASKCLR); | ||
363 | au_writel(1 << bit, IC0_RISINGCLR); | ||
364 | au_writel(1 << bit, IC0_FALLINGCLR); | ||
365 | au_sync(); | ||
366 | } | ||
367 | |||
368 | static void au1x_ic1_maskack(unsigned int irq_nr) | ||
369 | { | ||
370 | unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; | ||
371 | |||
372 | au_writel(1 << bit, IC1_WAKECLR); | ||
373 | au_writel(1 << bit, IC1_MASKCLR); | ||
374 | au_writel(1 << bit, IC1_RISINGCLR); | ||
375 | au_writel(1 << bit, IC1_FALLINGCLR); | ||
376 | au_sync(); | ||
377 | } | ||
378 | |||
357 | static int au1x_ic1_setwake(unsigned int irq, unsigned int on) | 379 | static int au1x_ic1_setwake(unsigned int irq, unsigned int on) |
358 | { | 380 | { |
359 | unsigned int bit = irq - AU1000_INTC1_INT_BASE; | 381 | unsigned int bit = irq - AU1000_INTC1_INT_BASE; |
@@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) | |||
379 | /* | 401 | /* |
380 | * irq_chips for both ICs; this way the mask handlers can be | 402 | * irq_chips for both ICs; this way the mask handlers can be |
381 | * as short as possible. | 403 | * as short as possible. |
382 | * | ||
383 | * NOTE: the ->ack() callback is used by the handle_edge_irq | ||
384 | * flowhandler only, the ->mask_ack() one by handle_level_irq, | ||
385 | * so no need for an irq_chip for each type of irq (level/edge). | ||
386 | */ | 404 | */ |
387 | static struct irq_chip au1x_ic0_chip = { | 405 | static struct irq_chip au1x_ic0_chip = { |
388 | .name = "Alchemy-IC0", | 406 | .name = "Alchemy-IC0", |
389 | .ack = au1x_ic0_ack, /* edge */ | 407 | .ack = au1x_ic0_ack, |
390 | .mask = au1x_ic0_mask, | 408 | .mask = au1x_ic0_mask, |
391 | .mask_ack = au1x_ic0_mask, /* level */ | 409 | .mask_ack = au1x_ic0_maskack, |
392 | .unmask = au1x_ic0_unmask, | 410 | .unmask = au1x_ic0_unmask, |
393 | .set_type = au1x_ic_settype, | 411 | .set_type = au1x_ic_settype, |
394 | }; | 412 | }; |
395 | 413 | ||
396 | static struct irq_chip au1x_ic1_chip = { | 414 | static struct irq_chip au1x_ic1_chip = { |
397 | .name = "Alchemy-IC1", | 415 | .name = "Alchemy-IC1", |
398 | .ack = au1x_ic1_ack, /* edge */ | 416 | .ack = au1x_ic1_ack, |
399 | .mask = au1x_ic1_mask, | 417 | .mask = au1x_ic1_mask, |
400 | .mask_ack = au1x_ic1_mask, /* level */ | 418 | .mask_ack = au1x_ic1_maskack, |
401 | .unmask = au1x_ic1_unmask, | 419 | .unmask = au1x_ic1_unmask, |
402 | .set_type = au1x_ic_settype, | 420 | .set_type = au1x_ic_settype, |
403 | .set_wake = au1x_ic1_setwake, | 421 | .set_wake = au1x_ic1_setwake, |
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cc32c69a74ad..45b61c9b82b9 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c | |||
@@ -69,6 +69,7 @@ void __init board_setup(void) | |||
69 | #else | 69 | #else |
70 | au_writel(0xf, Au1500_PCI_CFG); | 70 | au_writel(0xf, Au1500_PCI_CFG); |
71 | #endif | 71 | #endif |
72 | board_pci_idsel = mtx1_pci_idsel; | ||
72 | #endif | 73 | #endif |
73 | 74 | ||
74 | /* Initialize sys_pinfunc */ | 75 | /* Initialize sys_pinfunc */ |
@@ -85,8 +86,6 @@ void __init board_setup(void) | |||
85 | alchemy_gpio_direction_output(211, 1); /* green on */ | 86 | alchemy_gpio_direction_output(211, 1); /* green on */ |
86 | alchemy_gpio_direction_output(212, 0); /* red off */ | 87 | alchemy_gpio_direction_output(212, 0); /* red off */ |
87 | 88 | ||
88 | board_pci_idsel = mtx1_pci_idsel; | ||
89 | |||
90 | printk(KERN_INFO "4G Systems MTX-1 Board\n"); | 89 | printk(KERN_INFO "4G Systems MTX-1 Board\n"); |
91 | } | 90 | } |
92 | 91 | ||
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index e2278c04459d..835f3f0319ca 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c | |||
@@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) | |||
503 | { | 503 | { |
504 | u16 chip_id; | 504 | u16 chip_id; |
505 | int res; | 505 | int res; |
506 | u32 *bootcr, val; | ||
506 | #ifdef CONFIG_SERIAL_8250 | 507 | #ifdef CONFIG_SERIAL_8250 |
507 | static struct uart_port uart_port[2]; | 508 | static struct uart_port uart_port[2]; |
508 | 509 | ||
@@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) | |||
595 | 596 | ||
596 | ar7_wdt_res.end = ar7_wdt_res.start + 0x20; | 597 | ar7_wdt_res.end = ar7_wdt_res.start + 0x20; |
597 | 598 | ||
598 | res = platform_device_register(&ar7_wdt); | 599 | bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); |
600 | val = *bootcr; | ||
601 | iounmap(bootcr); | ||
602 | |||
603 | /* Register watchdog only if enabled in hardware */ | ||
604 | if (val & AR7_WDT_HW_ENA) | ||
605 | res = platform_device_register(&ar7_wdt); | ||
599 | 606 | ||
600 | return res; | 607 | return res; |
601 | } | 608 | } |
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index c146d1ededed..00064b660809 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile | |||
@@ -1,5 +1,5 @@ | |||
1 | obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ | 1 | obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ |
2 | dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o | 2 | dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o |
3 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | 3 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
4 | 4 | ||
5 | obj-y += boards/ | 5 | obj-y += boards/ |
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 78e155d21be6..05a35cf5963d 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c | |||
@@ -24,7 +24,6 @@ | |||
24 | #include <bcm63xx_dev_enet.h> | 24 | #include <bcm63xx_dev_enet.h> |
25 | #include <bcm63xx_dev_dsp.h> | 25 | #include <bcm63xx_dev_dsp.h> |
26 | #include <bcm63xx_dev_pcmcia.h> | 26 | #include <bcm63xx_dev_pcmcia.h> |
27 | #include <bcm63xx_dev_uart.h> | ||
28 | #include <board_bcm963xx.h> | 27 | #include <board_bcm963xx.h> |
29 | 28 | ||
30 | #define PFX "board_bcm963xx: " | 29 | #define PFX "board_bcm963xx: " |
@@ -794,8 +793,6 @@ int __init board_register_devices(void) | |||
794 | { | 793 | { |
795 | u32 val; | 794 | u32 val; |
796 | 795 | ||
797 | bcm63xx_uart_register(); | ||
798 | |||
799 | if (board.has_pccard) | 796 | if (board.has_pccard) |
800 | bcm63xx_pcmcia_register(); | 797 | bcm63xx_pcmcia_register(); |
801 | 798 | ||
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 6dc43f0483e8..70378bb5e3f9 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c | |||
@@ -10,6 +10,7 @@ | |||
10 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
11 | #include <linux/module.h> | 11 | #include <linux/module.h> |
12 | #include <linux/cpu.h> | 12 | #include <linux/cpu.h> |
13 | #include <asm/cpu-info.h> | ||
13 | #include <bcm63xx_cpu.h> | 14 | #include <bcm63xx_cpu.h> |
14 | #include <bcm63xx_regs.h> | 15 | #include <bcm63xx_regs.h> |
15 | #include <bcm63xx_io.h> | 16 | #include <bcm63xx_io.h> |
@@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void) | |||
284 | { | 285 | { |
285 | unsigned int tmp, expected_cpu_id; | 286 | unsigned int tmp, expected_cpu_id; |
286 | struct cpuinfo_mips *c = ¤t_cpu_data; | 287 | struct cpuinfo_mips *c = ¤t_cpu_data; |
288 | unsigned int cpu = smp_processor_id(); | ||
287 | 289 | ||
288 | /* soc registers location depends on cpu type */ | 290 | /* soc registers location depends on cpu type */ |
289 | expected_cpu_id = 0; | 291 | expected_cpu_id = 0; |
@@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void) | |||
293 | * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c | 295 | * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c |
294 | */ | 296 | */ |
295 | case CPU_BCM3302: | 297 | case CPU_BCM3302: |
298 | __cpu_name[cpu] = "Broadcom BCM6338"; | ||
296 | expected_cpu_id = BCM6338_CPU_ID; | 299 | expected_cpu_id = BCM6338_CPU_ID; |
297 | bcm63xx_regs_base = bcm96338_regs_base; | 300 | bcm63xx_regs_base = bcm96338_regs_base; |
298 | bcm63xx_irqs = bcm96338_irqs; | 301 | bcm63xx_irqs = bcm96338_irqs; |
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c index 5f3d89c4a988..b0519461ad9b 100644 --- a/arch/mips/bcm63xx/dev-uart.c +++ b/arch/mips/bcm63xx/dev-uart.c | |||
@@ -10,7 +10,6 @@ | |||
10 | #include <linux/kernel.h> | 10 | #include <linux/kernel.h> |
11 | #include <linux/platform_device.h> | 11 | #include <linux/platform_device.h> |
12 | #include <bcm63xx_cpu.h> | 12 | #include <bcm63xx_cpu.h> |
13 | #include <bcm63xx_dev_uart.h> | ||
14 | 13 | ||
15 | static struct resource uart_resources[] = { | 14 | static struct resource uart_resources[] = { |
16 | { | 15 | { |
@@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void) | |||
39 | uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); | 38 | uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); |
40 | return platform_device_register(&bcm63xx_uart_device); | 39 | return platform_device_register(&bcm63xx_uart_device); |
41 | } | 40 | } |
41 | arch_initcall(bcm63xx_uart_register); | ||
diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c new file mode 100644 index 000000000000..3e6c716a4c11 --- /dev/null +++ b/arch/mips/bcm63xx/dev-wdt.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> | ||
7 | */ | ||
8 | |||
9 | #include <linux/init.h> | ||
10 | #include <linux/kernel.h> | ||
11 | #include <linux/platform_device.h> | ||
12 | #include <bcm63xx_cpu.h> | ||
13 | |||
14 | static struct resource wdt_resources[] = { | ||
15 | { | ||
16 | .start = -1, /* filled at runtime */ | ||
17 | .end = -1, /* filled at runtime */ | ||
18 | .flags = IORESOURCE_MEM, | ||
19 | }, | ||
20 | }; | ||
21 | |||
22 | static struct platform_device bcm63xx_wdt_device = { | ||
23 | .name = "bcm63xx-wdt", | ||
24 | .id = 0, | ||
25 | .num_resources = ARRAY_SIZE(wdt_resources), | ||
26 | .resource = wdt_resources, | ||
27 | }; | ||
28 | |||
29 | int __init bcm63xx_wdt_register(void) | ||
30 | { | ||
31 | wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); | ||
32 | wdt_resources[0].end = wdt_resources[0].start; | ||
33 | wdt_resources[0].end += RSET_WDT_SIZE - 1; | ||
34 | |||
35 | return platform_device_register(&bcm63xx_wdt_device); | ||
36 | } | ||
37 | arch_initcall(bcm63xx_wdt_register); | ||
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index b18a0ca926fa..d0056598fbfc 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c | |||
@@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void) | |||
75 | bcm6348_a1_reboot(); | 75 | bcm6348_a1_reboot(); |
76 | 76 | ||
77 | printk(KERN_INFO "triggering watchdog soft-reset...\n"); | 77 | printk(KERN_INFO "triggering watchdog soft-reset...\n"); |
78 | bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); | 78 | reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); |
79 | reg |= SYS_PLL_SOFT_RESET; | ||
80 | bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); | ||
79 | while (1) | 81 | while (1) |
80 | ; | 82 | ; |
81 | } | 83 | } |
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 384f1842bfb1..6f2acf09328d 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c | |||
@@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); | |||
17 | DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); | 17 | DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); |
18 | DEFINE_SPINLOCK(octeon_irq_msi_lock); | 18 | DEFINE_SPINLOCK(octeon_irq_msi_lock); |
19 | 19 | ||
20 | static int octeon_coreid_for_cpu(int cpu) | ||
21 | { | ||
22 | #ifdef CONFIG_SMP | ||
23 | return cpu_logical_map(cpu); | ||
24 | #else | ||
25 | return cvmx_get_core_num(); | ||
26 | #endif | ||
27 | } | ||
28 | |||
20 | static void octeon_irq_core_ack(unsigned int irq) | 29 | static void octeon_irq_core_ack(unsigned int irq) |
21 | { | 30 | { |
22 | unsigned int bit = irq - OCTEON_IRQ_SW0; | 31 | unsigned int bit = irq - OCTEON_IRQ_SW0; |
@@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq) | |||
152 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | 161 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ |
153 | unsigned long flags; | 162 | unsigned long flags; |
154 | uint64_t en0; | 163 | uint64_t en0; |
155 | #ifdef CONFIG_SMP | ||
156 | int cpu; | 164 | int cpu; |
157 | write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); | 165 | write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); |
158 | for_each_online_cpu(cpu) { | 166 | for_each_online_cpu(cpu) { |
159 | int coreid = cpu_logical_map(cpu); | 167 | int coreid = octeon_coreid_for_cpu(cpu); |
160 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 168 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); |
161 | en0 &= ~(1ull << bit); | 169 | en0 &= ~(1ull << bit); |
162 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 170 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); |
@@ -167,26 +175,57 @@ static void octeon_irq_ciu0_disable(unsigned int irq) | |||
167 | */ | 175 | */ |
168 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | 176 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); |
169 | write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); | 177 | write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); |
170 | #else | 178 | } |
171 | int coreid = cvmx_get_core_num(); | 179 | |
172 | local_irq_save(flags); | 180 | /* |
173 | en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 181 | * Enable the irq on the current core for chips that have the EN*_W1{S,C} |
174 | en0 &= ~(1ull << bit); | 182 | * registers. |
175 | cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); | 183 | */ |
176 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 184 | static void octeon_irq_ciu0_enable_v2(unsigned int irq) |
177 | local_irq_restore(flags); | 185 | { |
178 | #endif | 186 | int index = cvmx_get_core_num() * 2; |
187 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
188 | |||
189 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | ||
190 | } | ||
191 | |||
192 | /* | ||
193 | * Disable the irq on the current core for chips that have the EN*_W1{S,C} | ||
194 | * registers. | ||
195 | */ | ||
196 | static void octeon_irq_ciu0_disable_v2(unsigned int irq) | ||
197 | { | ||
198 | int index = cvmx_get_core_num() * 2; | ||
199 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
200 | |||
201 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
202 | } | ||
203 | |||
204 | /* | ||
205 | * Disable the irq on the all cores for chips that have the EN*_W1{S,C} | ||
206 | * registers. | ||
207 | */ | ||
208 | static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) | ||
209 | { | ||
210 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
211 | int index; | ||
212 | int cpu; | ||
213 | for_each_online_cpu(cpu) { | ||
214 | index = octeon_coreid_for_cpu(cpu) * 2; | ||
215 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
216 | } | ||
179 | } | 217 | } |
180 | 218 | ||
181 | #ifdef CONFIG_SMP | 219 | #ifdef CONFIG_SMP |
182 | static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) | 220 | static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) |
183 | { | 221 | { |
184 | int cpu; | 222 | int cpu; |
223 | unsigned long flags; | ||
185 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ | 224 | int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ |
186 | 225 | ||
187 | write_lock(&octeon_irq_ciu0_rwlock); | 226 | write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); |
188 | for_each_online_cpu(cpu) { | 227 | for_each_online_cpu(cpu) { |
189 | int coreid = cpu_logical_map(cpu); | 228 | int coreid = octeon_coreid_for_cpu(cpu); |
190 | uint64_t en0 = | 229 | uint64_t en0 = |
191 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); | 230 | cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); |
192 | if (cpumask_test_cpu(cpu, dest)) | 231 | if (cpumask_test_cpu(cpu, dest)) |
@@ -200,11 +239,45 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * | |||
200 | * of them are done. | 239 | * of them are done. |
201 | */ | 240 | */ |
202 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); | 241 | cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); |
203 | write_unlock(&octeon_irq_ciu0_rwlock); | 242 | write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); |
204 | 243 | ||
205 | return 0; | 244 | return 0; |
206 | } | 245 | } |
246 | |||
247 | /* | ||
248 | * Set affinity for the irq for chips that have the EN*_W1{S,C} | ||
249 | * registers. | ||
250 | */ | ||
251 | static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, | ||
252 | const struct cpumask *dest) | ||
253 | { | ||
254 | int cpu; | ||
255 | int index; | ||
256 | u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); | ||
257 | for_each_online_cpu(cpu) { | ||
258 | index = octeon_coreid_for_cpu(cpu) * 2; | ||
259 | if (cpumask_test_cpu(cpu, dest)) | ||
260 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); | ||
261 | else | ||
262 | cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); | ||
263 | } | ||
264 | return 0; | ||
265 | } | ||
266 | #endif | ||
267 | |||
268 | /* | ||
269 | * Newer octeon chips have support for lockless CIU operation. | ||
270 | */ | ||
271 | static struct irq_chip octeon_irq_chip_ciu0_v2 = { | ||
272 | .name = "CIU0", | ||
273 | .enable = octeon_irq_ciu0_enable_v2, | ||
274 | .disable = octeon_irq_ciu0_disable_all_v2, | ||
275 | .ack = octeon_irq_ciu0_disable_v2, | ||
276 | .eoi = octeon_irq_ciu0_enable_v2, | ||
277 | #ifdef CONFIG_SMP | ||
278 | .set_affinity = octeon_irq_ciu0_set_affinity_v2, | ||
207 | #endif | 279 | #endif |
280 | }; | ||
208 | 281 | ||
209 | static struct irq_chip octeon_irq_chip_ciu0 = { | 282 | static struct irq_chip octeon_irq_chip_ciu0 = { |
210 | .name = "CIU0", | 283 | .name = "CIU0", |
@@ -269,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq) | |||
269 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | 342 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ |
270 | unsigned long flags; | 343 | unsigned long flags; |
271 | uint64_t en1; | 344 | uint64_t en1; |
272 | #ifdef CONFIG_SMP | ||
273 | int cpu; | 345 | int cpu; |
274 | write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); | 346 | write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); |
275 | for_each_online_cpu(cpu) { | 347 | for_each_online_cpu(cpu) { |
276 | int coreid = cpu_logical_map(cpu); | 348 | int coreid = octeon_coreid_for_cpu(cpu); |
277 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 349 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); |
278 | en1 &= ~(1ull << bit); | 350 | en1 &= ~(1ull << bit); |
279 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | 351 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); |
@@ -284,26 +356,58 @@ static void octeon_irq_ciu1_disable(unsigned int irq) | |||
284 | */ | 356 | */ |
285 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | 357 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); |
286 | write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); | 358 | write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); |
287 | #else | 359 | } |
288 | int coreid = cvmx_get_core_num(); | 360 | |
289 | local_irq_save(flags); | 361 | /* |
290 | en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 362 | * Enable the irq on the current core for chips that have the EN*_W1{S,C} |
291 | en1 &= ~(1ull << bit); | 363 | * registers. |
292 | cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); | 364 | */ |
293 | cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); | 365 | static void octeon_irq_ciu1_enable_v2(unsigned int irq) |
294 | local_irq_restore(flags); | 366 | { |
295 | #endif | 367 | int index = cvmx_get_core_num() * 2 + 1; |
368 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | ||
369 | |||
370 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
371 | } | ||
372 | |||
373 | /* | ||
374 | * Disable the irq on the current core for chips that have the EN*_W1{S,C} | ||
375 | * registers. | ||
376 | */ | ||
377 | static void octeon_irq_ciu1_disable_v2(unsigned int irq) | ||
378 | { | ||
379 | int index = cvmx_get_core_num() * 2 + 1; | ||
380 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | ||
381 | |||
382 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
383 | } | ||
384 | |||
385 | /* | ||
386 | * Disable the irq on the all cores for chips that have the EN*_W1{S,C} | ||
387 | * registers. | ||
388 | */ | ||
389 | static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) | ||
390 | { | ||
391 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | ||
392 | int index; | ||
393 | int cpu; | ||
394 | for_each_online_cpu(cpu) { | ||
395 | index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
396 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
397 | } | ||
296 | } | 398 | } |
297 | 399 | ||
298 | #ifdef CONFIG_SMP | 400 | #ifdef CONFIG_SMP |
299 | static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) | 401 | static int octeon_irq_ciu1_set_affinity(unsigned int irq, |
402 | const struct cpumask *dest) | ||
300 | { | 403 | { |
301 | int cpu; | 404 | int cpu; |
405 | unsigned long flags; | ||
302 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ | 406 | int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ |
303 | 407 | ||
304 | write_lock(&octeon_irq_ciu1_rwlock); | 408 | write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); |
305 | for_each_online_cpu(cpu) { | 409 | for_each_online_cpu(cpu) { |
306 | int coreid = cpu_logical_map(cpu); | 410 | int coreid = octeon_coreid_for_cpu(cpu); |
307 | uint64_t en1 = | 411 | uint64_t en1 = |
308 | cvmx_read_csr(CVMX_CIU_INTX_EN1 | 412 | cvmx_read_csr(CVMX_CIU_INTX_EN1 |
309 | (coreid * 2 + 1)); | 413 | (coreid * 2 + 1)); |
@@ -318,12 +422,46 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask * | |||
318 | * of them are done. | 422 | * of them are done. |
319 | */ | 423 | */ |
320 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); | 424 | cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); |
321 | write_unlock(&octeon_irq_ciu1_rwlock); | 425 | write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); |
426 | |||
427 | return 0; | ||
428 | } | ||
322 | 429 | ||
430 | /* | ||
431 | * Set affinity for the irq for chips that have the EN*_W1{S,C} | ||
432 | * registers. | ||
433 | */ | ||
434 | static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, | ||
435 | const struct cpumask *dest) | ||
436 | { | ||
437 | int cpu; | ||
438 | int index; | ||
439 | u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); | ||
440 | for_each_online_cpu(cpu) { | ||
441 | index = octeon_coreid_for_cpu(cpu) * 2 + 1; | ||
442 | if (cpumask_test_cpu(cpu, dest)) | ||
443 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); | ||
444 | else | ||
445 | cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); | ||
446 | } | ||
323 | return 0; | 447 | return 0; |
324 | } | 448 | } |
325 | #endif | 449 | #endif |
326 | 450 | ||
451 | /* | ||
452 | * Newer octeon chips have support for lockless CIU operation. | ||
453 | */ | ||
454 | static struct irq_chip octeon_irq_chip_ciu1_v2 = { | ||
455 | .name = "CIU0", | ||
456 | .enable = octeon_irq_ciu1_enable_v2, | ||
457 | .disable = octeon_irq_ciu1_disable_all_v2, | ||
458 | .ack = octeon_irq_ciu1_disable_v2, | ||
459 | .eoi = octeon_irq_ciu1_enable_v2, | ||
460 | #ifdef CONFIG_SMP | ||
461 | .set_affinity = octeon_irq_ciu1_set_affinity_v2, | ||
462 | #endif | ||
463 | }; | ||
464 | |||
327 | static struct irq_chip octeon_irq_chip_ciu1 = { | 465 | static struct irq_chip octeon_irq_chip_ciu1 = { |
328 | .name = "CIU1", | 466 | .name = "CIU1", |
329 | .enable = octeon_irq_ciu1_enable, | 467 | .enable = octeon_irq_ciu1_enable, |
@@ -420,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = { | |||
420 | void __init arch_init_irq(void) | 558 | void __init arch_init_irq(void) |
421 | { | 559 | { |
422 | int irq; | 560 | int irq; |
561 | struct irq_chip *chip0; | ||
562 | struct irq_chip *chip1; | ||
423 | 563 | ||
424 | #ifdef CONFIG_SMP | 564 | #ifdef CONFIG_SMP |
425 | /* Set the default affinity to the boot cpu. */ | 565 | /* Set the default affinity to the boot cpu. */ |
@@ -430,6 +570,16 @@ void __init arch_init_irq(void) | |||
430 | if (NR_IRQS < OCTEON_IRQ_LAST) | 570 | if (NR_IRQS < OCTEON_IRQ_LAST) |
431 | pr_err("octeon_irq_init: NR_IRQS is set too low\n"); | 571 | pr_err("octeon_irq_init: NR_IRQS is set too low\n"); |
432 | 572 | ||
573 | if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || | ||
574 | OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || | ||
575 | OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { | ||
576 | chip0 = &octeon_irq_chip_ciu0_v2; | ||
577 | chip1 = &octeon_irq_chip_ciu1_v2; | ||
578 | } else { | ||
579 | chip0 = &octeon_irq_chip_ciu0; | ||
580 | chip1 = &octeon_irq_chip_ciu1; | ||
581 | } | ||
582 | |||
433 | /* 0 - 15 reserved for i8259 master and slave controller. */ | 583 | /* 0 - 15 reserved for i8259 master and slave controller. */ |
434 | 584 | ||
435 | /* 17 - 23 Mips internal */ | 585 | /* 17 - 23 Mips internal */ |
@@ -440,14 +590,12 @@ void __init arch_init_irq(void) | |||
440 | 590 | ||
441 | /* 24 - 87 CIU_INT_SUM0 */ | 591 | /* 24 - 87 CIU_INT_SUM0 */ |
442 | for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { | 592 | for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { |
443 | set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, | 593 | set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); |
444 | handle_percpu_irq); | ||
445 | } | 594 | } |
446 | 595 | ||
447 | /* 88 - 151 CIU_INT_SUM1 */ | 596 | /* 88 - 151 CIU_INT_SUM1 */ |
448 | for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { | 597 | for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { |
449 | set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, | 598 | set_irq_chip_and_handler(irq, chip1, handle_percpu_irq); |
450 | handle_percpu_irq); | ||
451 | } | 599 | } |
452 | 600 | ||
453 | #ifdef CONFIG_PCI_MSI | 601 | #ifdef CONFIG_PCI_MSI |
@@ -505,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void) | |||
505 | #ifdef CONFIG_HOTPLUG_CPU | 653 | #ifdef CONFIG_HOTPLUG_CPU |
506 | static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) | 654 | static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) |
507 | { | 655 | { |
508 | unsigned int isset; | 656 | unsigned int isset; |
509 | #ifdef CONFIG_SMP | 657 | int coreid = octeon_coreid_for_cpu(cpu); |
510 | int coreid = cpu_logical_map(cpu); | ||
511 | #else | ||
512 | int coreid = cvmx_get_core_num(); | ||
513 | #endif | ||
514 | int bit = (irq < OCTEON_IRQ_WDOG0) ? | 658 | int bit = (irq < OCTEON_IRQ_WDOG0) ? |
515 | irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; | 659 | irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; |
516 | if (irq < 64) { | 660 | if (irq < 64) { |
517 | isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & | 661 | isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & |
518 | (1ull << bit)) >> bit; | 662 | (1ull << bit)) >> bit; |
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 32d51a31dc48..c198efdf583e 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c | |||
@@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action) | |||
65 | cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); | 65 | cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); |
66 | } | 66 | } |
67 | 67 | ||
68 | static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) | 68 | static inline void octeon_send_ipi_mask(const struct cpumask *mask, |
69 | unsigned int action) | ||
69 | { | 70 | { |
70 | unsigned int i; | 71 | unsigned int i; |
71 | 72 | ||
72 | for_each_cpu_mask(i, mask) | 73 | for_each_cpu_mask(i, *mask) |
73 | octeon_send_ipi_single(i, action); | 74 | octeon_send_ipi_single(i, action); |
74 | } | 75 | } |
75 | 76 | ||
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index efeddc8db8b1..0b89b83e2055 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h | |||
@@ -48,9 +48,9 @@ enum fixed_addresses { | |||
48 | #define FIX_N_COLOURS 8 | 48 | #define FIX_N_COLOURS 8 |
49 | FIX_CMAP_BEGIN, | 49 | FIX_CMAP_BEGIN, |
50 | #ifdef CONFIG_MIPS_MT_SMTC | 50 | #ifdef CONFIG_MIPS_MT_SMTC |
51 | FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), | 51 | FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2), |
52 | #else | 52 | #else |
53 | FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, | 53 | FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2), |
54 | #endif | 54 | #endif |
55 | #ifdef CONFIG_HIGHMEM | 55 | #ifdef CONFIG_HIGHMEM |
56 | /* reserved pte's for temporary kernel mappings */ | 56 | /* reserved pte's for temporary kernel mappings */ |
diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h index 36fd969d64d6..c0cf76a2ca89 100644 --- a/arch/mips/include/asm/gcmpregs.h +++ b/arch/mips/include/asm/gcmpregs.h | |||
@@ -19,15 +19,20 @@ | |||
19 | #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ | 19 | #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ |
20 | 20 | ||
21 | /* Offsets to individual GCMP registers from GCMP base */ | 21 | /* Offsets to individual GCMP registers from GCMP base */ |
22 | #define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) | 22 | #define GCMPOFS(block, tag, reg) \ |
23 | (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) | ||
24 | #define GCMPOFSn(block, tag, reg, n) \ | ||
25 | (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) | ||
23 | 26 | ||
24 | #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) | 27 | #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) |
28 | #define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) | ||
25 | #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) | 29 | #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) |
26 | #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) | 30 | #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) |
27 | #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) | 31 | #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) |
28 | 32 | ||
29 | /* GCMP register access */ | 33 | /* GCMP register access */ |
30 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) | 34 | #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) |
35 | #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) | ||
31 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) | 36 | #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) |
32 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) | 37 | #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) |
33 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) | 38 | #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) |
@@ -49,10 +54,10 @@ | |||
49 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) | 54 | #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) |
50 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 | 55 | #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 |
51 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) | 56 | #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) |
52 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 | 57 | #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 |
53 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 | 58 | #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 |
54 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 | 59 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 |
55 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 | 60 | #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 |
56 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ | 61 | #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ |
57 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ | 62 | #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ |
58 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 | 63 | #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 |
@@ -115,5 +120,6 @@ | |||
115 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ | 120 | #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ |
116 | 121 | ||
117 | extern int __init gcmp_probe(unsigned long, unsigned long); | 122 | extern int __init gcmp_probe(unsigned long, unsigned long); |
118 | 123 | extern int __init gcmp_niocu(void); | |
124 | extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); | ||
119 | #endif /* _ASM_GCMPREGS_H */ | 125 | #endif /* _ASM_GCMPREGS_H */ |
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index a8f57341f123..9b9436a4d816 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h | |||
@@ -12,7 +12,6 @@ | |||
12 | #define _ASM_GICREGS_H | 12 | #define _ASM_GICREGS_H |
13 | 13 | ||
14 | #undef GICISBYTELITTLEENDIAN | 14 | #undef GICISBYTELITTLEENDIAN |
15 | #define GICISWORDLITTLEENDIAN | ||
16 | 15 | ||
17 | /* Constants */ | 16 | /* Constants */ |
18 | #define GIC_POL_POS 1 | 17 | #define GIC_POL_POS 1 |
@@ -20,11 +19,7 @@ | |||
20 | #define GIC_TRIG_EDGE 1 | 19 | #define GIC_TRIG_EDGE 1 |
21 | #define GIC_TRIG_LEVEL 0 | 20 | #define GIC_TRIG_LEVEL 0 |
22 | 21 | ||
23 | #ifdef CONFIG_SMP | ||
24 | #define GIC_NUM_INTRS (24 + NR_CPUS * 2) | 22 | #define GIC_NUM_INTRS (24 + NR_CPUS * 2) |
25 | #else | ||
26 | #define GIC_NUM_INTRS 32 | ||
27 | #endif | ||
28 | 23 | ||
29 | #define MSK(n) ((1 << (n)) - 1) | 24 | #define MSK(n) ((1 << (n)) - 1) |
30 | #define REG32(addr) (*(volatile unsigned int *) (addr)) | 25 | #define REG32(addr) (*(volatile unsigned int *) (addr)) |
@@ -70,13 +65,13 @@ | |||
70 | #define USM_VISIBLE_SECTION_SIZE 0x10000 | 65 | #define USM_VISIBLE_SECTION_SIZE 0x10000 |
71 | 66 | ||
72 | /* Register Map for Shared Section */ | 67 | /* Register Map for Shared Section */ |
73 | #if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) | ||
74 | 68 | ||
75 | #define GIC_SH_CONFIG_OFS 0x0000 | 69 | #define GIC_SH_CONFIG_OFS 0x0000 |
76 | 70 | ||
77 | /* Shared Global Counter */ | 71 | /* Shared Global Counter */ |
78 | #define GIC_SH_COUNTER_31_00_OFS 0x0010 | 72 | #define GIC_SH_COUNTER_31_00_OFS 0x0010 |
79 | #define GIC_SH_COUNTER_63_32_OFS 0x0014 | 73 | #define GIC_SH_COUNTER_63_32_OFS 0x0014 |
74 | #define GIC_SH_REVISIONID_OFS 0x0020 | ||
80 | 75 | ||
81 | /* Interrupt Polarity */ | 76 | /* Interrupt Polarity */ |
82 | #define GIC_SH_POL_31_0_OFS 0x0100 | 77 | #define GIC_SH_POL_31_0_OFS 0x0100 |
@@ -164,24 +159,31 @@ | |||
164 | (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) | 159 | (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) |
165 | #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) | 160 | #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) |
166 | 161 | ||
162 | /* Convert an interrupt number to a byte offset/bit for multi-word registers */ | ||
163 | #define GIC_INTR_OFS(intr) (((intr) / 32)*4) | ||
164 | #define GIC_INTR_BIT(intr) ((intr) % 32) | ||
165 | |||
167 | /* Polarity : Reset Value is always 0 */ | 166 | /* Polarity : Reset Value is always 0 */ |
168 | #define GIC_SH_SET_POLARITY_OFS 0x0100 | 167 | #define GIC_SH_SET_POLARITY_OFS 0x0100 |
169 | #define GIC_SET_POLARITY(intr, pol) \ | 168 | #define GIC_SET_POLARITY(intr, pol) \ |
170 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) | 169 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \ |
170 | GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr)) | ||
171 | 171 | ||
172 | /* Triggering : Reset Value is always 0 */ | 172 | /* Triggering : Reset Value is always 0 */ |
173 | #define GIC_SH_SET_TRIGGER_OFS 0x0180 | 173 | #define GIC_SH_SET_TRIGGER_OFS 0x0180 |
174 | #define GIC_SET_TRIGGER(intr, trig) \ | 174 | #define GIC_SET_TRIGGER(intr, trig) \ |
175 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) | 175 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \ |
176 | GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr)) | ||
176 | 177 | ||
177 | /* Mask manipulation */ | 178 | /* Mask manipulation */ |
178 | #define GIC_SH_SMASK_OFS 0x0380 | 179 | #define GIC_SH_SMASK_OFS 0x0380 |
179 | #define GIC_SET_INTR_MASK(intr, val) \ | 180 | #define GIC_SET_INTR_MASK(intr) \ |
180 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) | 181 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \ |
181 | 182 | GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) | |
182 | #define GIC_SH_RMASK_OFS 0x0300 | 183 | #define GIC_SH_RMASK_OFS 0x0300 |
183 | #define GIC_CLR_INTR_MASK(intr, val) \ | 184 | #define GIC_CLR_INTR_MASK(intr) \ |
184 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) | 185 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \ |
186 | GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) | ||
185 | 187 | ||
186 | /* Register Map for Local Section */ | 188 | /* Register Map for Local Section */ |
187 | #define GIC_VPE_CTL_OFS 0x0000 | 189 | #define GIC_VPE_CTL_OFS 0x0000 |
@@ -219,161 +221,6 @@ | |||
219 | #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 | 221 | #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 |
220 | #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 | 222 | #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 |
221 | 223 | ||
222 | #else /* CONFIG_CPU_BIG_ENDIAN */ | ||
223 | |||
224 | #define GIC_SH_CONFIG_OFS 0x0000 | ||
225 | |||
226 | /* Shared Global Counter */ | ||
227 | #define GIC_SH_COUNTER_31_00_OFS 0x0014 | ||
228 | #define GIC_SH_COUNTER_63_32_OFS 0x0010 | ||
229 | |||
230 | /* Interrupt Polarity */ | ||
231 | #define GIC_SH_POL_31_0_OFS 0x0104 | ||
232 | #define GIC_SH_POL_63_32_OFS 0x0100 | ||
233 | #define GIC_SH_POL_95_64_OFS 0x010c | ||
234 | #define GIC_SH_POL_127_96_OFS 0x0108 | ||
235 | #define GIC_SH_POL_159_128_OFS 0x0114 | ||
236 | #define GIC_SH_POL_191_160_OFS 0x0110 | ||
237 | #define GIC_SH_POL_223_192_OFS 0x011c | ||
238 | #define GIC_SH_POL_255_224_OFS 0x0118 | ||
239 | |||
240 | /* Edge/Level Triggering */ | ||
241 | #define GIC_SH_TRIG_31_0_OFS 0x0184 | ||
242 | #define GIC_SH_TRIG_63_32_OFS 0x0180 | ||
243 | #define GIC_SH_TRIG_95_64_OFS 0x018c | ||
244 | #define GIC_SH_TRIG_127_96_OFS 0x0188 | ||
245 | #define GIC_SH_TRIG_159_128_OFS 0x0194 | ||
246 | #define GIC_SH_TRIG_191_160_OFS 0x0190 | ||
247 | #define GIC_SH_TRIG_223_192_OFS 0x019c | ||
248 | #define GIC_SH_TRIG_255_224_OFS 0x0198 | ||
249 | |||
250 | /* Dual Edge Triggering */ | ||
251 | #define GIC_SH_DUAL_31_0_OFS 0x0204 | ||
252 | #define GIC_SH_DUAL_63_32_OFS 0x0200 | ||
253 | #define GIC_SH_DUAL_95_64_OFS 0x020c | ||
254 | #define GIC_SH_DUAL_127_96_OFS 0x0208 | ||
255 | #define GIC_SH_DUAL_159_128_OFS 0x0214 | ||
256 | #define GIC_SH_DUAL_191_160_OFS 0x0210 | ||
257 | #define GIC_SH_DUAL_223_192_OFS 0x021c | ||
258 | #define GIC_SH_DUAL_255_224_OFS 0x0218 | ||
259 | |||
260 | /* Set/Clear corresponding bit in Edge Detect Register */ | ||
261 | #define GIC_SH_WEDGE_OFS 0x0280 | ||
262 | |||
263 | /* Reset Mask - Disables Interrupt */ | ||
264 | #define GIC_SH_RMASK_31_0_OFS 0x0304 | ||
265 | #define GIC_SH_RMASK_63_32_OFS 0x0300 | ||
266 | #define GIC_SH_RMASK_95_64_OFS 0x030c | ||
267 | #define GIC_SH_RMASK_127_96_OFS 0x0308 | ||
268 | #define GIC_SH_RMASK_159_128_OFS 0x0314 | ||
269 | #define GIC_SH_RMASK_191_160_OFS 0x0310 | ||
270 | #define GIC_SH_RMASK_223_192_OFS 0x031c | ||
271 | #define GIC_SH_RMASK_255_224_OFS 0x0318 | ||
272 | |||
273 | /* Set Mask (WO) - Enables Interrupt */ | ||
274 | #define GIC_SH_SMASK_31_0_OFS 0x0384 | ||
275 | #define GIC_SH_SMASK_63_32_OFS 0x0380 | ||
276 | #define GIC_SH_SMASK_95_64_OFS 0x038c | ||
277 | #define GIC_SH_SMASK_127_96_OFS 0x0388 | ||
278 | #define GIC_SH_SMASK_159_128_OFS 0x0394 | ||
279 | #define GIC_SH_SMASK_191_160_OFS 0x0390 | ||
280 | #define GIC_SH_SMASK_223_192_OFS 0x039c | ||
281 | #define GIC_SH_SMASK_255_224_OFS 0x0398 | ||
282 | |||
283 | /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ | ||
284 | #define GIC_SH_MASK_31_0_OFS 0x0404 | ||
285 | #define GIC_SH_MASK_63_32_OFS 0x0400 | ||
286 | #define GIC_SH_MASK_95_64_OFS 0x040c | ||
287 | #define GIC_SH_MASK_127_96_OFS 0x0408 | ||
288 | #define GIC_SH_MASK_159_128_OFS 0x0414 | ||
289 | #define GIC_SH_MASK_191_160_OFS 0x0410 | ||
290 | #define GIC_SH_MASK_223_192_OFS 0x041c | ||
291 | #define GIC_SH_MASK_255_224_OFS 0x0418 | ||
292 | |||
293 | /* Pending Global Interrupts (RO) */ | ||
294 | #define GIC_SH_PEND_31_0_OFS 0x0484 | ||
295 | #define GIC_SH_PEND_63_32_OFS 0x0480 | ||
296 | #define GIC_SH_PEND_95_64_OFS 0x048c | ||
297 | #define GIC_SH_PEND_127_96_OFS 0x0488 | ||
298 | #define GIC_SH_PEND_159_128_OFS 0x0494 | ||
299 | #define GIC_SH_PEND_191_160_OFS 0x0490 | ||
300 | #define GIC_SH_PEND_223_192_OFS 0x049c | ||
301 | #define GIC_SH_PEND_255_224_OFS 0x0498 | ||
302 | |||
303 | #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 | ||
304 | |||
305 | /* Maps Interrupt X to a Pin */ | ||
306 | #define GIC_SH_MAP_TO_PIN(intr) \ | ||
307 | (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) | ||
308 | |||
309 | #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 | ||
310 | |||
311 | /* | ||
312 | * Maps Interrupt X to a VPE. This is more complex than the LE case, as | ||
313 | * odd and even registers need to be transposed. It does work - trust me! | ||
314 | */ | ||
315 | #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ | ||
316 | (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ | ||
317 | (((((vpe) / 32) ^ 1) - 1) * 4)) | ||
318 | #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) | ||
319 | |||
320 | /* Polarity */ | ||
321 | #define GIC_SH_SET_POLARITY_OFS 0x0100 | ||
322 | #define GIC_SET_POLARITY(intr, pol) \ | ||
323 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) | ||
324 | |||
325 | /* Triggering */ | ||
326 | #define GIC_SH_SET_TRIGGER_OFS 0x0180 | ||
327 | #define GIC_SET_TRIGGER(intr, trig) \ | ||
328 | GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) | ||
329 | |||
330 | /* Mask manipulation */ | ||
331 | #define GIC_SH_SMASK_OFS 0x0380 | ||
332 | #define GIC_SET_INTR_MASK(intr, val) \ | ||
333 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) | ||
334 | |||
335 | #define GIC_SH_RMASK_OFS 0x0300 | ||
336 | #define GIC_CLR_INTR_MASK(intr, val) \ | ||
337 | GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) | ||
338 | |||
339 | /* Register Map for Local Section */ | ||
340 | #define GIC_VPE_CTL_OFS 0x0000 | ||
341 | #define GIC_VPE_PEND_OFS 0x0004 | ||
342 | #define GIC_VPE_MASK_OFS 0x0008 | ||
343 | #define GIC_VPE_RMASK_OFS 0x000c | ||
344 | #define GIC_VPE_SMASK_OFS 0x0010 | ||
345 | #define GIC_VPE_WD_MAP_OFS 0x0040 | ||
346 | #define GIC_VPE_COMPARE_MAP_OFS 0x0044 | ||
347 | #define GIC_VPE_TIMER_MAP_OFS 0x0048 | ||
348 | #define GIC_VPE_PERFCTR_MAP_OFS 0x0050 | ||
349 | #define GIC_VPE_SWINT0_MAP_OFS 0x0054 | ||
350 | #define GIC_VPE_SWINT1_MAP_OFS 0x0058 | ||
351 | #define GIC_VPE_OTHER_ADDR_OFS 0x0080 | ||
352 | #define GIC_VPE_WD_CONFIG0_OFS 0x0090 | ||
353 | #define GIC_VPE_WD_COUNT0_OFS 0x0094 | ||
354 | #define GIC_VPE_WD_INITIAL0_OFS 0x0098 | ||
355 | #define GIC_VPE_COMPARE_LO_OFS 0x00a4 | ||
356 | #define GIC_VPE_COMPARE_HI_OFS 0x00a0 | ||
357 | |||
358 | #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 | ||
359 | #define GIC_VPE_EIC_SS(intr) \ | ||
360 | (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) | ||
361 | |||
362 | #define GIC_VPE_EIC_VEC_BASE 0x0800 | ||
363 | #define GIC_VPE_EIC_VEC(intr) \ | ||
364 | (GIC_VPE_EIC_VEC_BASE + (4 * intr)) | ||
365 | |||
366 | #define GIC_VPE_TENABLE_NMI_OFS 0x1000 | ||
367 | #define GIC_VPE_TENABLE_YQ_OFS 0x1004 | ||
368 | #define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 | ||
369 | #define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 | ||
370 | |||
371 | /* User Mode Visible Section Register Map */ | ||
372 | #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 | ||
373 | #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 | ||
374 | |||
375 | #endif /* !LE */ | ||
376 | |||
377 | /* Masks */ | 224 | /* Masks */ |
378 | #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 | 225 | #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 |
379 | #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) | 226 | #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) |
@@ -473,12 +320,13 @@ struct gic_intrmask_regs { | |||
473 | * in building ipi_map. | 320 | * in building ipi_map. |
474 | */ | 321 | */ |
475 | struct gic_intr_map { | 322 | struct gic_intr_map { |
476 | unsigned int intrnum; /* Ext Intr Num */ | ||
477 | unsigned int cpunum; /* Directed to this CPU */ | 323 | unsigned int cpunum; /* Directed to this CPU */ |
478 | unsigned int pin; /* Directed to this Pin */ | 324 | unsigned int pin; /* Directed to this Pin */ |
479 | unsigned int polarity; /* Polarity : +/- */ | 325 | unsigned int polarity; /* Polarity : +/- */ |
480 | unsigned int trigtype; /* Trigger : Edge/Levl */ | 326 | unsigned int trigtype; /* Trigger : Edge/Levl */ |
481 | unsigned int ipiflag; /* Is used for IPI ? */ | 327 | unsigned int flags; /* Misc flags */ |
328 | #define GIC_FLAG_IPI 0x01 | ||
329 | #define GIC_FLAG_TRANSPARENT 0x02 | ||
482 | }; | 330 | }; |
483 | 331 | ||
484 | extern void gic_init(unsigned long gic_base_addr, | 332 | extern void gic_init(unsigned long gic_base_addr, |
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index de71694614de..21cbbc706448 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h | |||
@@ -78,6 +78,9 @@ | |||
78 | #define AR7_REF_CLOCK 25000000 | 78 | #define AR7_REF_CLOCK 25000000 |
79 | #define AR7_XTAL_CLOCK 24000000 | 79 | #define AR7_XTAL_CLOCK 24000000 |
80 | 80 | ||
81 | /* DCL */ | ||
82 | #define AR7_WDT_HW_ENA 0x10 | ||
83 | |||
81 | struct plat_cpmac_data { | 84 | struct plat_cpmac_data { |
82 | int reset_bit; | 85 | int reset_bit; |
83 | int power_bit; | 86 | int power_bit; |
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index feea00148b5d..91595fa89034 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h | |||
@@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio) | |||
104 | 104 | ||
105 | if ((gpio >= 8) && (gpio <= 15)) | 105 | if ((gpio >= 8) && (gpio <= 15)) |
106 | return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ | 106 | return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ |
107 | |||
108 | return -ENXIO; | ||
107 | } | 109 | } |
108 | 110 | ||
109 | #ifdef CONFIG_SOC_AU1100 | 111 | #ifdef CONFIG_SOC_AU1100 |
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h deleted file mode 100644 index bf348f573bbc..000000000000 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h +++ /dev/null | |||
@@ -1,6 +0,0 @@ | |||
1 | #ifndef BCM63XX_DEV_UART_H_ | ||
2 | #define BCM63XX_DEV_UART_H_ | ||
3 | |||
4 | int bcm63xx_uart_register(void); | ||
5 | |||
6 | #endif /* BCM63XX_DEV_UART_H_ */ | ||
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index f6837422fe65..09a59bcc1b07 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h | |||
@@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; | |||
44 | .busy_factor = 32, \ | 44 | .busy_factor = 32, \ |
45 | .imbalance_pct = 125, \ | 45 | .imbalance_pct = 125, \ |
46 | .cache_nice_tries = 1, \ | 46 | .cache_nice_tries = 1, \ |
47 | .flags = SD_LOAD_BALANCE \ | 47 | .flags = SD_LOAD_BALANCE | \ |
48 | | SD_BALANCE_EXEC \ | 48 | SD_BALANCE_EXEC, \ |
49 | .last_balance = jiffies, \ | 49 | .last_balance = jiffies, \ |
50 | .balance_interval = 1, \ | 50 | .balance_interval = 1, \ |
51 | .nr_balance_failed = 0, \ | 51 | .nr_balance_failed = 0, \ |
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index ce5b6e270e3f..9947e57c91de 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h | |||
@@ -29,7 +29,7 @@ | |||
29 | #define cpu_has_cache_cdex_p 0 | 29 | #define cpu_has_cache_cdex_p 0 |
30 | #define cpu_has_cache_cdex_s 0 | 30 | #define cpu_has_cache_cdex_s 0 |
31 | #define cpu_has_counter 1 | 31 | #define cpu_has_counter 1 |
32 | #define cpu_has_dc_aliases 1 | 32 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) |
33 | #define cpu_has_divec 0 | 33 | #define cpu_has_divec 0 |
34 | #define cpu_has_dsp 0 | 34 | #define cpu_has_dsp 0 |
35 | #define cpu_has_ejtag 0 | 35 | #define cpu_has_ejtag 0 |
@@ -54,6 +54,5 @@ | |||
54 | #define cpu_has_vce 0 | 54 | #define cpu_has_vce 0 |
55 | #define cpu_has_vtag_icache 0 | 55 | #define cpu_has_vtag_icache 0 |
56 | #define cpu_has_watch 1 | 56 | #define cpu_has_watch 1 |
57 | #define cpu_icache_snoops_remote_store 1 | ||
58 | 57 | ||
59 | #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ | 58 | #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ |
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d9743536a621..6083db586500 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
17 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
18 | #include <asm/cacheflush.h> | 18 | #include <asm/cacheflush.h> |
19 | #include <asm/hazards.h> | ||
19 | #include <asm/tlbflush.h> | 20 | #include <asm/tlbflush.h> |
20 | #ifdef CONFIG_MIPS_MT_SMTC | 21 | #ifdef CONFIG_MIPS_MT_SMTC |
21 | #include <asm/mipsmtregs.h> | 22 | #include <asm/mipsmtregs.h> |
@@ -36,11 +37,13 @@ extern unsigned long pgd_current[]; | |||
36 | #ifdef CONFIG_32BIT | 37 | #ifdef CONFIG_32BIT |
37 | #define TLBMISS_HANDLER_SETUP() \ | 38 | #define TLBMISS_HANDLER_SETUP() \ |
38 | write_c0_context((unsigned long) smp_processor_id() << 25); \ | 39 | write_c0_context((unsigned long) smp_processor_id() << 25); \ |
40 | back_to_back_c0_hazard(); \ | ||
39 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) | 41 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
40 | #endif | 42 | #endif |
41 | #ifdef CONFIG_64BIT | 43 | #ifdef CONFIG_64BIT |
42 | #define TLBMISS_HANDLER_SETUP() \ | 44 | #define TLBMISS_HANDLER_SETUP() \ |
43 | write_c0_context((unsigned long) smp_processor_id() << 26); \ | 45 | write_c0_context((unsigned long) smp_processor_id() << 26); \ |
46 | back_to_back_c0_hazard(); \ | ||
44 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) | 47 | TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) |
45 | #endif | 48 | #endif |
46 | 49 | ||
@@ -165,12 +168,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |||
165 | * having ASID_MASK smaller than the hardware maximum, | 168 | * having ASID_MASK smaller than the hardware maximum, |
166 | * make sure no "soft" bits become "hard"... | 169 | * make sure no "soft" bits become "hard"... |
167 | */ | 170 | */ |
168 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 171 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
169 | | (cpu_context(cpu, next) & ASID_MASK)); | 172 | cpu_asid(cpu, next)); |
170 | ehb(); /* Make sure it propagates to TCStatus */ | 173 | ehb(); /* Make sure it propagates to TCStatus */ |
171 | evpe(mtflags); | 174 | evpe(mtflags); |
172 | #else | 175 | #else |
173 | write_c0_entryhi(cpu_context(cpu, next)); | 176 | write_c0_entryhi(cpu_asid(cpu, next)); |
174 | #endif /* CONFIG_MIPS_MT_SMTC */ | 177 | #endif /* CONFIG_MIPS_MT_SMTC */ |
175 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); | 178 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
176 | 179 | ||
@@ -226,11 +229,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) | |||
226 | } | 229 | } |
227 | /* See comments for similar code above */ | 230 | /* See comments for similar code above */ |
228 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | | 231 | write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | |
229 | (cpu_context(cpu, next) & ASID_MASK)); | 232 | cpu_asid(cpu, next)); |
230 | ehb(); /* Make sure it propagates to TCStatus */ | 233 | ehb(); /* Make sure it propagates to TCStatus */ |
231 | evpe(mtflags); | 234 | evpe(mtflags); |
232 | #else | 235 | #else |
233 | write_c0_entryhi(cpu_context(cpu, next)); | 236 | write_c0_entryhi(cpu_asid(cpu, next)); |
234 | #endif /* CONFIG_MIPS_MT_SMTC */ | 237 | #endif /* CONFIG_MIPS_MT_SMTC */ |
235 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); | 238 | TLBMISS_HANDLER_SETUP_PGD(next->pgd); |
236 | 239 | ||
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e600cedda976..50511aac04e9 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h | |||
@@ -1,7 +1,7 @@ | |||
1 | #ifndef _MIPS_SETUP_H | 1 | #ifndef _MIPS_SETUP_H |
2 | #define _MIPS_SETUP_H | 2 | #define _MIPS_SETUP_H |
3 | 3 | ||
4 | #define COMMAND_LINE_SIZE 256 | 4 | #define COMMAND_LINE_SIZE 4096 |
5 | 5 | ||
6 | #ifdef __KERNEL__ | 6 | #ifdef __KERNEL__ |
7 | extern void setup_early_printk(void); | 7 | extern void setup_early_printk(void); |
diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h index 8ce517574340..15278dbd7e79 100644 --- a/arch/mips/include/asm/smtc_ipi.h +++ b/arch/mips/include/asm/smtc_ipi.h | |||
@@ -45,6 +45,7 @@ struct smtc_ipi_q { | |||
45 | spinlock_t lock; | 45 | spinlock_t lock; |
46 | struct smtc_ipi *tail; | 46 | struct smtc_ipi *tail; |
47 | int depth; | 47 | int depth; |
48 | int resched_flag; /* reschedule already queued */ | ||
48 | }; | 49 | }; |
49 | 50 | ||
50 | static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) | 51 | static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) |
diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h new file mode 100644 index 000000000000..0b89006e4907 --- /dev/null +++ b/arch/mips/include/asm/spram.h | |||
@@ -0,0 +1,10 @@ | |||
1 | #ifndef _MIPS_SPRAM_H | ||
2 | #define _MIPS_SPRAM_H | ||
3 | |||
4 | #ifdef CONFIG_CPU_MIPSR2 | ||
5 | extern __init void spram_config(void); | ||
6 | #else | ||
7 | static inline void spram_config(void) { }; | ||
8 | #endif /* CONFIG_CPU_MIPSR2 */ | ||
9 | |||
10 | #endif /* _MIPS_SPRAM_H */ | ||
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 01cc1630b66c..845da2107ed1 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h | |||
@@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
86 | #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR | 86 | #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR |
87 | 87 | ||
88 | #ifdef CONFIG_DEBUG_STACK_USAGE | 88 | #ifdef CONFIG_DEBUG_STACK_USAGE |
89 | #define alloc_thread_info(tsk) \ | 89 | #define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) |
90 | ({ \ | ||
91 | struct thread_info *ret; \ | ||
92 | \ | ||
93 | ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ | ||
94 | \ | ||
95 | ret; \ | ||
96 | }) | ||
97 | #else | 90 | #else |
98 | #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) | 91 | #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) |
99 | #endif | 92 | #endif |
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 7fd170d007e7..7bd32d04c2cc 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c | |||
@@ -134,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) | |||
134 | 134 | ||
135 | static struct irqaction r4030_timer_irqaction = { | 135 | static struct irqaction r4030_timer_irqaction = { |
136 | .handler = r4030_timer_interrupt, | 136 | .handler = r4030_timer_interrupt, |
137 | .flags = IRQF_DISABLED, | 137 | .flags = IRQF_DISABLED | IRQF_TIMER, |
138 | .name = "R4030 timer", | 138 | .name = "R4030 timer", |
139 | }; | 139 | }; |
140 | 140 | ||
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index e02f79b1eb51..bfea327c636c 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c | |||
@@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void) | |||
144 | bcm1480_unmask_irq(cpu, irq); | 144 | bcm1480_unmask_irq(cpu, irq); |
145 | 145 | ||
146 | action->handler = sibyte_counter_handler; | 146 | action->handler = sibyte_counter_handler; |
147 | action->flags = IRQF_DISABLED | IRQF_PERCPU; | 147 | action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; |
148 | action->name = name; | 148 | action->name = name; |
149 | action->dev_id = cd; | 149 | action->dev_id = cd; |
150 | 150 | ||
diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c index 6996da4d74a2..00a4da277cbb 100644 --- a/arch/mips/kernel/cevt-ds1287.c +++ b/arch/mips/kernel/cevt-ds1287.c | |||
@@ -107,7 +107,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id) | |||
107 | 107 | ||
108 | static struct irqaction ds1287_irqaction = { | 108 | static struct irqaction ds1287_irqaction = { |
109 | .handler = ds1287_interrupt, | 109 | .handler = ds1287_interrupt, |
110 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 110 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
111 | .name = "ds1287", | 111 | .name = "ds1287", |
112 | }; | 112 | }; |
113 | 113 | ||
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c index 92351e00ae0e..f5d265eb6eae 100644 --- a/arch/mips/kernel/cevt-gt641xx.c +++ b/arch/mips/kernel/cevt-gt641xx.c | |||
@@ -113,7 +113,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id) | |||
113 | 113 | ||
114 | static struct irqaction gt641xx_timer0_irqaction = { | 114 | static struct irqaction gt641xx_timer0_irqaction = { |
115 | .handler = gt641xx_timer0_interrupt, | 115 | .handler = gt641xx_timer0_interrupt, |
116 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 116 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
117 | .name = "gt641xx_timer0", | 117 | .name = "gt641xx_timer0", |
118 | }; | 118 | }; |
119 | 119 | ||
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 2652362ce047..b469ad05d520 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c | |||
@@ -83,7 +83,7 @@ out: | |||
83 | 83 | ||
84 | struct irqaction c0_compare_irqaction = { | 84 | struct irqaction c0_compare_irqaction = { |
85 | .handler = c0_compare_interrupt, | 85 | .handler = c0_compare_interrupt, |
86 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 86 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
87 | .name = "timer", | 87 | .name = "timer", |
88 | }; | 88 | }; |
89 | 89 | ||
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index ac5903d1b20e..da78eeaea6e8 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c | |||
@@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void) | |||
143 | sb1250_unmask_irq(cpu, irq); | 143 | sb1250_unmask_irq(cpu, irq); |
144 | 144 | ||
145 | action->handler = sibyte_counter_handler; | 145 | action->handler = sibyte_counter_handler; |
146 | action->flags = IRQF_DISABLED | IRQF_PERCPU; | 146 | action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; |
147 | action->name = name; | 147 | action->name = name; |
148 | action->dev_id = cd; | 148 | action->dev_id = cd; |
149 | 149 | ||
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 0037f21baf0d..218ee6bda935 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c | |||
@@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) | |||
146 | 146 | ||
147 | static struct irqaction txx9tmr_irq = { | 147 | static struct irqaction txx9tmr_irq = { |
148 | .handler = txx9tmr_interrupt, | 148 | .handler = txx9tmr_interrupt, |
149 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 149 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
150 | .name = "txx9tmr", | 150 | .name = "txx9tmr", |
151 | .dev_id = &txx9_clock_event_device, | 151 | .dev_id = &txx9_clock_event_device, |
152 | }; | 152 | }; |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f709657e4dcd..7a51866068a4 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <asm/mipsregs.h> | 23 | #include <asm/mipsregs.h> |
24 | #include <asm/system.h> | 24 | #include <asm/system.h> |
25 | #include <asm/watch.h> | 25 | #include <asm/watch.h> |
26 | 26 | #include <asm/spram.h> | |
27 | /* | 27 | /* |
28 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | 28 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, |
29 | * the implementation of the "wait" feature differs between CPU families. This | 29 | * the implementation of the "wait" feature differs between CPU families. This |
@@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) | |||
711 | mips_probe_watch_registers(c); | 711 | mips_probe_watch_registers(c); |
712 | } | 712 | } |
713 | 713 | ||
714 | #ifdef CONFIG_CPU_MIPSR2 | ||
715 | extern void spram_config(void); | ||
716 | #else | ||
717 | static inline void spram_config(void) {} | ||
718 | #endif | ||
719 | |||
720 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | 714 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
721 | { | 715 | { |
722 | decode_configs(c); | 716 | decode_configs(c); |
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 531ce7b16124..ea695d9605e9 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S | |||
@@ -191,6 +191,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point | |||
191 | /* Set the SP after an empty pt_regs. */ | 191 | /* Set the SP after an empty pt_regs. */ |
192 | PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE | 192 | PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE |
193 | PTR_ADDU sp, $28 | 193 | PTR_ADDU sp, $28 |
194 | back_to_back_c0_hazard | ||
194 | set_saved_sp sp, t0, t1 | 195 | set_saved_sp sp, t0, t1 |
195 | PTR_SUBU sp, 4 * SZREG # init stack pointer | 196 | PTR_SUBU sp, 4 * SZREG # init stack pointer |
196 | 197 | ||
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index f7d8d5d0ddbf..ed5c441615e4 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c | |||
@@ -98,7 +98,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) | |||
98 | 98 | ||
99 | static struct irqaction irq0 = { | 99 | static struct irqaction irq0 = { |
100 | .handler = timer_interrupt, | 100 | .handler = timer_interrupt, |
101 | .flags = IRQF_DISABLED | IRQF_NOBALANCING, | 101 | .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, |
102 | .name = "timer" | 102 | .name = "timer" |
103 | }; | 103 | }; |
104 | 104 | ||
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index d2072cd38592..b181f2f0ea8e 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c | |||
@@ -14,38 +14,23 @@ | |||
14 | 14 | ||
15 | 15 | ||
16 | static unsigned long _gic_base; | 16 | static unsigned long _gic_base; |
17 | static unsigned int _irqbase, _mapsize, numvpes, numintrs; | 17 | static unsigned int _irqbase; |
18 | static struct gic_intr_map *_intrmap; | 18 | static unsigned int gic_irq_flags[GIC_NUM_INTRS]; |
19 | #define GIC_IRQ_FLAG_EDGE 0x0001 | ||
19 | 20 | ||
20 | static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; | 21 | struct gic_pcpu_mask pcpu_masks[NR_CPUS]; |
21 | static struct gic_pending_regs pending_regs[NR_CPUS]; | 22 | static struct gic_pending_regs pending_regs[NR_CPUS]; |
22 | static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; | 23 | static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; |
23 | 24 | ||
24 | #define gic_wedgeb2bok 0 /* | ||
25 | * Can GIC handle b2b writes to wedge register? | ||
26 | */ | ||
27 | #if gic_wedgeb2bok == 0 | ||
28 | static DEFINE_SPINLOCK(gic_wedgeb2b_lock); | ||
29 | #endif | ||
30 | |||
31 | void gic_send_ipi(unsigned int intr) | 25 | void gic_send_ipi(unsigned int intr) |
32 | { | 26 | { |
33 | #if gic_wedgeb2bok == 0 | ||
34 | unsigned long flags; | ||
35 | #endif | ||
36 | pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, | 27 | pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, |
37 | read_c0_status()); | 28 | read_c0_status()); |
38 | if (!gic_wedgeb2bok) | ||
39 | spin_lock_irqsave(&gic_wedgeb2b_lock, flags); | ||
40 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); | 29 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); |
41 | if (!gic_wedgeb2bok) { | ||
42 | (void) GIC_REG(SHARED, GIC_SH_CONFIG); | ||
43 | spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); | ||
44 | } | ||
45 | } | 30 | } |
46 | 31 | ||
47 | /* This is Malta specific and needs to be exported */ | 32 | /* This is Malta specific and needs to be exported */ |
48 | static void vpe_local_setup(unsigned int numvpes) | 33 | static void __init vpe_local_setup(unsigned int numvpes) |
49 | { | 34 | { |
50 | int i; | 35 | int i; |
51 | unsigned long timer_interrupt = 5, perf_interrupt = 5; | 36 | unsigned long timer_interrupt = 5, perf_interrupt = 5; |
@@ -105,44 +90,34 @@ unsigned int gic_get_int(void) | |||
105 | 90 | ||
106 | static unsigned int gic_irq_startup(unsigned int irq) | 91 | static unsigned int gic_irq_startup(unsigned int irq) |
107 | { | 92 | { |
108 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | ||
109 | irq -= _irqbase; | 93 | irq -= _irqbase; |
110 | GIC_SET_INTR_MASK(irq, 1); | 94 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
95 | GIC_SET_INTR_MASK(irq); | ||
111 | return 0; | 96 | return 0; |
112 | } | 97 | } |
113 | 98 | ||
114 | static void gic_irq_ack(unsigned int irq) | 99 | static void gic_irq_ack(unsigned int irq) |
115 | { | 100 | { |
116 | #if gic_wedgeb2bok == 0 | ||
117 | unsigned long flags; | ||
118 | #endif | ||
119 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | ||
120 | irq -= _irqbase; | 101 | irq -= _irqbase; |
121 | GIC_CLR_INTR_MASK(irq, 1); | 102 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
103 | GIC_CLR_INTR_MASK(irq); | ||
122 | 104 | ||
123 | if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { | 105 | if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) |
124 | if (!gic_wedgeb2bok) | ||
125 | spin_lock_irqsave(&gic_wedgeb2b_lock, flags); | ||
126 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); | 106 | GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); |
127 | if (!gic_wedgeb2bok) { | ||
128 | (void) GIC_REG(SHARED, GIC_SH_CONFIG); | ||
129 | spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); | ||
130 | } | ||
131 | } | ||
132 | } | 107 | } |
133 | 108 | ||
134 | static void gic_mask_irq(unsigned int irq) | 109 | static void gic_mask_irq(unsigned int irq) |
135 | { | 110 | { |
136 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | ||
137 | irq -= _irqbase; | 111 | irq -= _irqbase; |
138 | GIC_CLR_INTR_MASK(irq, 1); | 112 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
113 | GIC_CLR_INTR_MASK(irq); | ||
139 | } | 114 | } |
140 | 115 | ||
141 | static void gic_unmask_irq(unsigned int irq) | 116 | static void gic_unmask_irq(unsigned int irq) |
142 | { | 117 | { |
143 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); | ||
144 | irq -= _irqbase; | 118 | irq -= _irqbase; |
145 | GIC_SET_INTR_MASK(irq, 1); | 119 | pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); |
120 | GIC_SET_INTR_MASK(irq); | ||
146 | } | 121 | } |
147 | 122 | ||
148 | #ifdef CONFIG_SMP | 123 | #ifdef CONFIG_SMP |
@@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |||
155 | unsigned long flags; | 130 | unsigned long flags; |
156 | int i; | 131 | int i; |
157 | 132 | ||
158 | pr_debug(KERN_DEBUG "%s called\n", __func__); | ||
159 | irq -= _irqbase; | 133 | irq -= _irqbase; |
160 | 134 | pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq); | |
161 | cpumask_and(&tmp, cpumask, cpu_online_mask); | 135 | cpumask_and(&tmp, cpumask, cpu_online_mask); |
162 | if (cpus_empty(tmp)) | 136 | if (cpus_empty(tmp)) |
163 | return -1; | 137 | return -1; |
@@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |||
168 | /* Re-route this IRQ */ | 142 | /* Re-route this IRQ */ |
169 | GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); | 143 | GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); |
170 | 144 | ||
171 | /* | ||
172 | * FIXME: assumption that _intrmap is ordered and has no holes | ||
173 | */ | ||
174 | |||
175 | /* Update the intr_map */ | ||
176 | _intrmap[irq].cpunum = first_cpu(tmp); | ||
177 | |||
178 | /* Update the pcpu_masks */ | 145 | /* Update the pcpu_masks */ |
179 | for (i = 0; i < NR_CPUS; i++) | 146 | for (i = 0; i < NR_CPUS; i++) |
180 | clear_bit(irq, pcpu_masks[i].pcpu_mask); | 147 | clear_bit(irq, pcpu_masks[i].pcpu_mask); |
@@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = { | |||
201 | #endif | 168 | #endif |
202 | }; | 169 | }; |
203 | 170 | ||
204 | static void __init setup_intr(unsigned int intr, unsigned int cpu, | 171 | static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, |
205 | unsigned int pin, unsigned int polarity, unsigned int trigtype) | 172 | unsigned int pin, unsigned int polarity, unsigned int trigtype, |
173 | unsigned int flags) | ||
206 | { | 174 | { |
207 | /* Setup Intr to Pin mapping */ | 175 | /* Setup Intr to Pin mapping */ |
208 | if (pin & GIC_MAP_TO_NMI_MSK) { | 176 | if (pin & GIC_MAP_TO_NMI_MSK) { |
@@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu, | |||
227 | GIC_SET_TRIGGER(intr, trigtype); | 195 | GIC_SET_TRIGGER(intr, trigtype); |
228 | 196 | ||
229 | /* Init Intr Masks */ | 197 | /* Init Intr Masks */ |
230 | GIC_SET_INTR_MASK(intr, 0); | 198 | GIC_CLR_INTR_MASK(intr); |
199 | /* Initialise per-cpu Interrupt software masks */ | ||
200 | if (flags & GIC_FLAG_IPI) | ||
201 | set_bit(intr, pcpu_masks[cpu].pcpu_mask); | ||
202 | if (flags & GIC_FLAG_TRANSPARENT) | ||
203 | GIC_SET_INTR_MASK(intr); | ||
204 | if (trigtype == GIC_TRIG_EDGE) | ||
205 | gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; | ||
231 | } | 206 | } |
232 | 207 | ||
233 | static void __init gic_basic_init(void) | 208 | static void __init gic_basic_init(int numintrs, int numvpes, |
209 | struct gic_intr_map *intrmap, int mapsize) | ||
234 | { | 210 | { |
235 | unsigned int i, cpu; | 211 | unsigned int i, cpu; |
236 | 212 | ||
237 | /* Setup defaults */ | 213 | /* Setup defaults */ |
238 | for (i = 0; i < GIC_NUM_INTRS; i++) { | 214 | for (i = 0; i < numintrs; i++) { |
239 | GIC_SET_POLARITY(i, GIC_POL_POS); | 215 | GIC_SET_POLARITY(i, GIC_POL_POS); |
240 | GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); | 216 | GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); |
241 | GIC_SET_INTR_MASK(i, 0); | 217 | GIC_CLR_INTR_MASK(i); |
218 | if (i < GIC_NUM_INTRS) | ||
219 | gic_irq_flags[i] = 0; | ||
242 | } | 220 | } |
243 | 221 | ||
244 | /* Setup specifics */ | 222 | /* Setup specifics */ |
245 | for (i = 0; i < _mapsize; i++) { | 223 | for (i = 0; i < mapsize; i++) { |
246 | cpu = _intrmap[i].cpunum; | 224 | cpu = intrmap[i].cpunum; |
247 | if (cpu == X) | 225 | if (cpu == X) |
248 | continue; | 226 | continue; |
249 | 227 | if (cpu == 0 && i != 0 && intrmap[i].flags == 0) | |
250 | if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 && | ||
251 | _intrmap[i].ipiflag == 0) | ||
252 | continue; | 228 | continue; |
253 | 229 | gic_setup_intr(i, | |
254 | setup_intr(_intrmap[i].intrnum, | 230 | intrmap[i].cpunum, |
255 | _intrmap[i].cpunum, | 231 | intrmap[i].pin, |
256 | _intrmap[i].pin, | 232 | intrmap[i].polarity, |
257 | _intrmap[i].polarity, | 233 | intrmap[i].trigtype, |
258 | _intrmap[i].trigtype); | 234 | intrmap[i].flags); |
259 | /* Initialise per-cpu Interrupt software masks */ | ||
260 | if (_intrmap[i].ipiflag) | ||
261 | set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask); | ||
262 | } | 235 | } |
263 | 236 | ||
264 | vpe_local_setup(numvpes); | 237 | vpe_local_setup(numvpes); |
@@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr, | |||
273 | unsigned int irqbase) | 246 | unsigned int irqbase) |
274 | { | 247 | { |
275 | unsigned int gicconfig; | 248 | unsigned int gicconfig; |
249 | int numvpes, numintrs; | ||
276 | 250 | ||
277 | _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, | 251 | _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, |
278 | gic_addrspace_size); | 252 | gic_addrspace_size); |
279 | _irqbase = irqbase; | 253 | _irqbase = irqbase; |
280 | _intrmap = intr_map; | ||
281 | _mapsize = intr_map_size; | ||
282 | 254 | ||
283 | GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); | 255 | GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); |
284 | numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> | 256 | numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> |
@@ -290,5 +262,5 @@ void __init gic_init(unsigned long gic_base_addr, | |||
290 | 262 | ||
291 | pr_debug("%s called\n", __func__); | 263 | pr_debug("%s called\n", __func__); |
292 | 264 | ||
293 | gic_basic_init(); | 265 | gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); |
294 | } | 266 | } |
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 6242bc68add7..b77fefaff9da 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c | |||
@@ -428,3 +428,9 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs) | |||
428 | return do_fork(clone_flags, newsp, ®s, 0, | 428 | return do_fork(clone_flags, newsp, ®s, 0, |
429 | parent_tidptr, child_tidptr); | 429 | parent_tidptr, child_tidptr); |
430 | } | 430 | } |
431 | |||
432 | asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf, | ||
433 | size_t len) | ||
434 | { | ||
435 | return sys_lookup_dcookie(merge_64(a0, a1), buf, len); | ||
436 | } | ||
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 9bbf9775e0bd..14dde4ca932e 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S | |||
@@ -450,7 +450,7 @@ sys_call_table: | |||
450 | PTR sys_io_submit | 450 | PTR sys_io_submit |
451 | PTR sys_io_cancel /* 4245 */ | 451 | PTR sys_io_cancel /* 4245 */ |
452 | PTR sys_exit_group | 452 | PTR sys_exit_group |
453 | PTR sys_lookup_dcookie | 453 | PTR sys32_lookup_dcookie |
454 | PTR sys_epoll_create | 454 | PTR sys_epoll_create |
455 | PTR sys_epoll_ctl | 455 | PTR sys_epoll_ctl |
456 | PTR sys_epoll_wait /* 4250 */ | 456 | PTR sys_epoll_wait /* 4250 */ |
@@ -505,7 +505,7 @@ sys_call_table: | |||
505 | PTR sys_fchmodat | 505 | PTR sys_fchmodat |
506 | PTR sys_faccessat /* 4300 */ | 506 | PTR sys_faccessat /* 4300 */ |
507 | PTR compat_sys_pselect6 | 507 | PTR compat_sys_pselect6 |
508 | PTR sys_ppoll | 508 | PTR compat_sys_ppoll |
509 | PTR sys_unshare | 509 | PTR sys_unshare |
510 | PTR sys_splice | 510 | PTR sys_splice |
511 | PTR sys32_sync_file_range /* 4305 */ | 511 | PTR sys32_sync_file_range /* 4305 */ |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 4d181df44a40..24630fd8ef60 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -75,7 +75,6 @@ unsigned long irq_hwmask[NR_IRQS]; | |||
75 | 75 | ||
76 | asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; | 76 | asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; |
77 | 77 | ||
78 | |||
79 | /* | 78 | /* |
80 | * Number of InterProcessor Interrupt (IPI) message buffers to allocate | 79 | * Number of InterProcessor Interrupt (IPI) message buffers to allocate |
81 | */ | 80 | */ |
@@ -388,6 +387,7 @@ void smtc_prepare_cpus(int cpus) | |||
388 | IPIQ[i].head = IPIQ[i].tail = NULL; | 387 | IPIQ[i].head = IPIQ[i].tail = NULL; |
389 | spin_lock_init(&IPIQ[i].lock); | 388 | spin_lock_init(&IPIQ[i].lock); |
390 | IPIQ[i].depth = 0; | 389 | IPIQ[i].depth = 0; |
390 | IPIQ[i].resched_flag = 0; /* No reschedules queued initially */ | ||
391 | } | 391 | } |
392 | 392 | ||
393 | /* cpu_data index starts at zero */ | 393 | /* cpu_data index starts at zero */ |
@@ -741,11 +741,24 @@ void smtc_forward_irq(unsigned int irq) | |||
741 | static void smtc_ipi_qdump(void) | 741 | static void smtc_ipi_qdump(void) |
742 | { | 742 | { |
743 | int i; | 743 | int i; |
744 | struct smtc_ipi *temp; | ||
744 | 745 | ||
745 | for (i = 0; i < NR_CPUS ;i++) { | 746 | for (i = 0; i < NR_CPUS ;i++) { |
746 | printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", | 747 | pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", |
747 | i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, | 748 | i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, |
748 | IPIQ[i].depth); | 749 | IPIQ[i].depth); |
750 | temp = IPIQ[i].head; | ||
751 | |||
752 | while (temp != IPIQ[i].tail) { | ||
753 | pr_debug("%d %d %d: ", temp->type, temp->dest, | ||
754 | (int)temp->arg); | ||
755 | #ifdef SMTC_IPI_DEBUG | ||
756 | pr_debug("%u %lu\n", temp->sender, temp->stamp); | ||
757 | #else | ||
758 | pr_debug("\n"); | ||
759 | #endif | ||
760 | temp = temp->flink; | ||
761 | } | ||
749 | } | 762 | } |
750 | } | 763 | } |
751 | 764 | ||
@@ -784,11 +797,16 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) | |||
784 | int mtflags; | 797 | int mtflags; |
785 | unsigned long tcrestart; | 798 | unsigned long tcrestart; |
786 | extern void r4k_wait_irqoff(void), __pastwait(void); | 799 | extern void r4k_wait_irqoff(void), __pastwait(void); |
800 | int set_resched_flag = (type == LINUX_SMP_IPI && | ||
801 | action == SMP_RESCHEDULE_YOURSELF); | ||
787 | 802 | ||
788 | if (cpu == smp_processor_id()) { | 803 | if (cpu == smp_processor_id()) { |
789 | printk("Cannot Send IPI to self!\n"); | 804 | printk("Cannot Send IPI to self!\n"); |
790 | return; | 805 | return; |
791 | } | 806 | } |
807 | if (set_resched_flag && IPIQ[cpu].resched_flag != 0) | ||
808 | return; /* There is a reschedule queued already */ | ||
809 | |||
792 | /* Set up a descriptor, to be delivered either promptly or queued */ | 810 | /* Set up a descriptor, to be delivered either promptly or queued */ |
793 | pipi = smtc_ipi_dq(&freeIPIq); | 811 | pipi = smtc_ipi_dq(&freeIPIq); |
794 | if (pipi == NULL) { | 812 | if (pipi == NULL) { |
@@ -801,6 +819,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) | |||
801 | pipi->dest = cpu; | 819 | pipi->dest = cpu; |
802 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | 820 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { |
803 | /* If not on same VPE, enqueue and send cross-VPE interrupt */ | 821 | /* If not on same VPE, enqueue and send cross-VPE interrupt */ |
822 | IPIQ[cpu].resched_flag |= set_resched_flag; | ||
804 | smtc_ipi_nq(&IPIQ[cpu], pipi); | 823 | smtc_ipi_nq(&IPIQ[cpu], pipi); |
805 | LOCK_CORE_PRA(); | 824 | LOCK_CORE_PRA(); |
806 | settc(cpu_data[cpu].tc_id); | 825 | settc(cpu_data[cpu].tc_id); |
@@ -847,6 +866,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) | |||
847 | */ | 866 | */ |
848 | write_tc_c0_tchalt(0); | 867 | write_tc_c0_tchalt(0); |
849 | UNLOCK_CORE_PRA(); | 868 | UNLOCK_CORE_PRA(); |
869 | IPIQ[cpu].resched_flag |= set_resched_flag; | ||
850 | smtc_ipi_nq(&IPIQ[cpu], pipi); | 870 | smtc_ipi_nq(&IPIQ[cpu], pipi); |
851 | } else { | 871 | } else { |
852 | postdirect: | 872 | postdirect: |
@@ -996,12 +1016,15 @@ void deferred_smtc_ipi(void) | |||
996 | * already enabled. | 1016 | * already enabled. |
997 | */ | 1017 | */ |
998 | local_irq_save(flags); | 1018 | local_irq_save(flags); |
999 | |||
1000 | spin_lock(&q->lock); | 1019 | spin_lock(&q->lock); |
1001 | pipi = __smtc_ipi_dq(q); | 1020 | pipi = __smtc_ipi_dq(q); |
1002 | spin_unlock(&q->lock); | 1021 | spin_unlock(&q->lock); |
1003 | if (pipi != NULL) | 1022 | if (pipi != NULL) { |
1023 | if (pipi->type == LINUX_SMP_IPI && | ||
1024 | (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) | ||
1025 | IPIQ[cpu].resched_flag = 0; | ||
1004 | ipi_decode(pipi); | 1026 | ipi_decode(pipi); |
1027 | } | ||
1005 | /* | 1028 | /* |
1006 | * The use of the __raw_local restore isn't | 1029 | * The use of the __raw_local restore isn't |
1007 | * as obviously necessary here as in smtc_ipi_replay(), | 1030 | * as obviously necessary here as in smtc_ipi_replay(), |
@@ -1082,6 +1105,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm) | |||
1082 | * with interrupts off | 1105 | * with interrupts off |
1083 | */ | 1106 | */ |
1084 | local_irq_save(flags); | 1107 | local_irq_save(flags); |
1108 | if (pipi->type == LINUX_SMP_IPI && | ||
1109 | (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) | ||
1110 | IPIQ[cpu].resched_flag = 0; | ||
1085 | ipi_decode(pipi); | 1111 | ipi_decode(pipi); |
1086 | local_irq_restore(flags); | 1112 | local_irq_restore(flags); |
1087 | } | 1113 | } |
diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6ddb507a87ef..1821d12a6410 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c | |||
@@ -13,7 +13,6 @@ | |||
13 | #include <linux/ptrace.h> | 13 | #include <linux/ptrace.h> |
14 | #include <linux/stddef.h> | 14 | #include <linux/stddef.h> |
15 | 15 | ||
16 | #include <asm/cpu.h> | ||
17 | #include <asm/fpu.h> | 16 | #include <asm/fpu.h> |
18 | #include <asm/mipsregs.h> | 17 | #include <asm/mipsregs.h> |
19 | #include <asm/system.h> | 18 | #include <asm/system.h> |
@@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type, | |||
198 | offset += 2 * SPRAM_TAG_STRIDE; | 197 | offset += 2 * SPRAM_TAG_STRIDE; |
199 | } | 198 | } |
200 | } | 199 | } |
201 | 200 | void __cpuinit spram_config(void) | |
202 | __cpuinit void spram_config(void) | ||
203 | { | 201 | { |
204 | struct cpuinfo_mips *c = ¤t_cpu_data; | 202 | struct cpuinfo_mips *c = ¤t_cpu_data; |
205 | unsigned int config0; | 203 | unsigned int config0; |
@@ -208,6 +206,7 @@ __cpuinit void spram_config(void) | |||
208 | case CPU_24K: | 206 | case CPU_24K: |
209 | case CPU_34K: | 207 | case CPU_34K: |
210 | case CPU_74K: | 208 | case CPU_74K: |
209 | case CPU_1004K: | ||
211 | config0 = read_c0_config(); | 210 | config0 = read_c0_config(); |
212 | /* FIXME: addresses are Malta specific */ | 211 | /* FIXME: addresses are Malta specific */ |
213 | if (config0 & (1<<24)) { | 212 | if (config0 & (1<<24)) { |
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 03092ab2a296..60477529362e 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c | |||
@@ -1116,8 +1116,6 @@ static int vpe_open(struct inode *inode, struct file *filp) | |||
1116 | v->shared_ptr = NULL; | 1116 | v->shared_ptr = NULL; |
1117 | v->__start = 0; | 1117 | v->__start = 0; |
1118 | 1118 | ||
1119 | unlock_kernel(); | ||
1120 | |||
1121 | return 0; | 1119 | return 0; |
1122 | } | 1120 | } |
1123 | 1121 | ||
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c index f368c735cbd3..b32b4a3e5137 100644 --- a/arch/mips/loongson/common/irq.c +++ b/arch/mips/loongson/common/irq.c | |||
@@ -55,7 +55,6 @@ void __init arch_init_irq(void) | |||
55 | * int-handler is not on bootstrap | 55 | * int-handler is not on bootstrap |
56 | */ | 56 | */ |
57 | clear_c0_status(ST0_IM | ST0_BEV); | 57 | clear_c0_status(ST0_IM | ST0_BEV); |
58 | local_irq_disable(); | ||
59 | 58 | ||
60 | /* setting irq trigger mode */ | 59 | /* setting irq trigger mode */ |
61 | set_irq_trigger_mode(); | 60 | set_irq_trigger_mode(); |
diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index 1c555e6c6a9f..d9ae1dbabda7 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c | |||
@@ -62,8 +62,6 @@ ieee754dp ieee754dp_neg(ieee754dp x) | |||
62 | return ieee754dp_nanxcpt(y, "neg"); | 62 | return ieee754dp_nanxcpt(y, "neg"); |
63 | } | 63 | } |
64 | 64 | ||
65 | if (ieee754dp_isnan(x)) /* but not infinity */ | ||
66 | return ieee754dp_nanxcpt(x, "neg", x); | ||
67 | return x; | 65 | return x; |
68 | } | 66 | } |
69 | 67 | ||
@@ -76,15 +74,12 @@ ieee754dp ieee754dp_abs(ieee754dp x) | |||
76 | CLEARCX; | 74 | CLEARCX; |
77 | FLUSHXDP; | 75 | FLUSHXDP; |
78 | 76 | ||
77 | /* Clear sign ALWAYS, irrespective of NaN */ | ||
78 | DPSIGN(x) = 0; | ||
79 | |||
79 | if (xc == IEEE754_CLASS_SNAN) { | 80 | if (xc == IEEE754_CLASS_SNAN) { |
80 | SETCX(IEEE754_INVALID_OPERATION); | 81 | return ieee754dp_nanxcpt(ieee754dp_indef(), "abs"); |
81 | return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); | ||
82 | } | 82 | } |
83 | 83 | ||
84 | if (ieee754dp_isnan(x)) /* but not infinity */ | ||
85 | return ieee754dp_nanxcpt(x, "abs", x); | ||
86 | |||
87 | /* quick fix up */ | ||
88 | DPSIGN(x) = 0; | ||
89 | return x; | 84 | return x; |
90 | } | 85 | } |
diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index 770f0f4677cd..3175477d36f6 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c | |||
@@ -62,8 +62,6 @@ ieee754sp ieee754sp_neg(ieee754sp x) | |||
62 | return ieee754sp_nanxcpt(y, "neg"); | 62 | return ieee754sp_nanxcpt(y, "neg"); |
63 | } | 63 | } |
64 | 64 | ||
65 | if (ieee754sp_isnan(x)) /* but not infinity */ | ||
66 | return ieee754sp_nanxcpt(x, "neg", x); | ||
67 | return x; | 65 | return x; |
68 | } | 66 | } |
69 | 67 | ||
@@ -76,15 +74,12 @@ ieee754sp ieee754sp_abs(ieee754sp x) | |||
76 | CLEARCX; | 74 | CLEARCX; |
77 | FLUSHXSP; | 75 | FLUSHXSP; |
78 | 76 | ||
77 | /* Clear sign ALWAYS, irrespective of NaN */ | ||
78 | SPSIGN(x) = 0; | ||
79 | |||
79 | if (xc == IEEE754_CLASS_SNAN) { | 80 | if (xc == IEEE754_CLASS_SNAN) { |
80 | SETCX(IEEE754_INVALID_OPERATION); | ||
81 | return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); | 81 | return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); |
82 | } | 82 | } |
83 | 83 | ||
84 | if (ieee754sp_isnan(x)) /* but not infinity */ | ||
85 | return ieee754sp_nanxcpt(x, "abs", x); | ||
86 | |||
87 | /* quick fix up */ | ||
88 | SPSIGN(x) = 0; | ||
89 | return x; | 84 | return x; |
90 | } | 85 | } |
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 15aa1902a788..8d1f4f363049 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/swap.h> | 27 | #include <linux/swap.h> |
28 | #include <linux/proc_fs.h> | 28 | #include <linux/proc_fs.h> |
29 | #include <linux/pfn.h> | 29 | #include <linux/pfn.h> |
30 | #include <linux/hardirq.h> | ||
30 | 31 | ||
31 | #include <asm/asm-offsets.h> | 32 | #include <asm/asm-offsets.h> |
32 | #include <asm/bootinfo.h> | 33 | #include <asm/bootinfo.h> |
@@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr) | |||
132 | inc_preempt_count(); | 133 | inc_preempt_count(); |
133 | idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); | 134 | idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); |
134 | #ifdef CONFIG_MIPS_MT_SMTC | 135 | #ifdef CONFIG_MIPS_MT_SMTC |
135 | idx += FIX_N_COLOURS * smp_processor_id(); | 136 | idx += FIX_N_COLOURS * smp_processor_id() + |
137 | (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0); | ||
138 | #else | ||
139 | idx += in_interrupt() ? FIX_N_COLOURS : 0; | ||
136 | #endif | 140 | #endif |
137 | vaddr = __fix_to_virt(FIX_CMAP_END - idx); | 141 | vaddr = __fix_to_virt(FIX_CMAP_END - idx); |
138 | pte = mk_pte(page, PAGE_KERNEL); | 142 | pte = mk_pte(page, PAGE_KERNEL); |
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index df9e526312a2..469d9b0cee6d 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c | |||
@@ -70,11 +70,12 @@ void amon_cpu_start(int cpu, | |||
70 | launch->sp = sp; | 70 | launch->sp = sp; |
71 | launch->a0 = a0; | 71 | launch->a0 = a0; |
72 | 72 | ||
73 | /* Make sure target sees parameters before the go bit */ | 73 | smp_wmb(); /* Target must see parameters before go */ |
74 | smp_mb(); | ||
75 | |||
76 | launch->flags |= LAUNCH_FGO; | 74 | launch->flags |= LAUNCH_FGO; |
75 | smp_wmb(); /* Target must see go before we poll */ | ||
76 | |||
77 | while ((launch->flags & LAUNCH_FGONE) == 0) | 77 | while ((launch->flags & LAUNCH_FGONE) == 0) |
78 | ; | 78 | ; |
79 | smp_rmb(); /* Target will be updating flags soon */ | ||
79 | pr_debug("launch: cpu%d gone!\n", cpu); | 80 | pr_debug("launch: cpu%d gone!\n", cpu); |
80 | } | 81 | } |
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 3e0a9b35ba5c..4c3fca18a171 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c | |||
@@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void) | |||
87 | dummy = BONITO_PCIMAP_CFG; | 87 | dummy = BONITO_PCIMAP_CFG; |
88 | iob(); /* sync */ | 88 | iob(); /* sync */ |
89 | 89 | ||
90 | irq = readl((u32 *)_pcictrl_bonito_pcicfg); | 90 | irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); |
91 | iob(); /* sync */ | 91 | iob(); /* sync */ |
92 | irq &= 0xff; | 92 | irq &= 0xff; |
93 | BONITO_PCIMAP_CFG = 0; | 93 | BONITO_PCIMAP_CFG = 0; |
@@ -379,38 +379,43 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = { | |||
379 | 379 | ||
380 | static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); | 380 | static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); |
381 | 381 | ||
382 | #if defined(CONFIG_MIPS_MT_SMP) | ||
383 | /* | 382 | /* |
384 | * This GIC specific tabular array defines the association between External | 383 | * This GIC specific tabular array defines the association between External |
385 | * Interrupts and CPUs/Core Interrupts. The nature of the External | 384 | * Interrupts and CPUs/Core Interrupts. The nature of the External |
386 | * Interrupts is also defined here - polarity/trigger. | 385 | * Interrupts is also defined here - polarity/trigger. |
387 | */ | 386 | */ |
387 | |||
388 | #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK | ||
388 | static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { | 389 | static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { |
389 | { GIC_EXT_INTR(0), X, X, X, X, 0 }, | 390 | { X, X, X, X, 0 }, |
390 | { GIC_EXT_INTR(1), X, X, X, X, 0 }, | 391 | { X, X, X, X, 0 }, |
391 | { GIC_EXT_INTR(2), X, X, X, X, 0 }, | 392 | { X, X, X, X, 0 }, |
392 | { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 393 | { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
393 | { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 394 | { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
394 | { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 395 | { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
395 | { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 396 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
396 | { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 397 | { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
397 | { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 398 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
398 | { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 399 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
399 | { GIC_EXT_INTR(10), X, X, X, X, 0 }, | 400 | { X, X, X, X, 0 }, |
400 | { GIC_EXT_INTR(11), X, X, X, X, 0 }, | 401 | { X, X, X, X, 0 }, |
401 | { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 402 | { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
402 | { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 403 | { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
403 | { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, | 404 | { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, |
404 | { GIC_EXT_INTR(15), X, X, X, X, 0 }, | 405 | { X, X, X, X, 0 }, |
405 | /* This is the end of the general interrupts now we do IPI ones */ | 406 | /* The remainder of this table is initialised by fill_ipi_map */ |
406 | }; | 407 | }; |
407 | #endif | ||
408 | 408 | ||
409 | /* | 409 | /* |
410 | * GCMP needs to be detected before any SMP initialisation | 410 | * GCMP needs to be detected before any SMP initialisation |
411 | */ | 411 | */ |
412 | int __init gcmp_probe(unsigned long addr, unsigned long size) | 412 | int __init gcmp_probe(unsigned long addr, unsigned long size) |
413 | { | 413 | { |
414 | if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { | ||
415 | gcmp_present = 0; | ||
416 | return gcmp_present; | ||
417 | } | ||
418 | |||
414 | if (gcmp_present >= 0) | 419 | if (gcmp_present >= 0) |
415 | return gcmp_present; | 420 | return gcmp_present; |
416 | 421 | ||
@@ -419,20 +424,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size) | |||
419 | gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; | 424 | gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; |
420 | 425 | ||
421 | if (gcmp_present) | 426 | if (gcmp_present) |
422 | printk(KERN_DEBUG "GCMP present\n"); | 427 | pr_debug("GCMP present\n"); |
423 | return gcmp_present; | 428 | return gcmp_present; |
424 | } | 429 | } |
425 | 430 | ||
431 | /* Return the number of IOCU's present */ | ||
432 | int __init gcmp_niocu(void) | ||
433 | { | ||
434 | return gcmp_present ? | ||
435 | (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : | ||
436 | 0; | ||
437 | } | ||
438 | |||
439 | /* Set GCMP region attributes */ | ||
440 | void __init gcmp_setregion(int region, unsigned long base, | ||
441 | unsigned long mask, int type) | ||
442 | { | ||
443 | GCMPGCBn(CMxBASE, region) = base; | ||
444 | GCMPGCBn(CMxMASK, region) = mask | type; | ||
445 | } | ||
446 | |||
426 | #if defined(CONFIG_MIPS_MT_SMP) | 447 | #if defined(CONFIG_MIPS_MT_SMP) |
427 | static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) | 448 | static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) |
428 | { | 449 | { |
429 | int intr = baseintr + cpu; | 450 | int intr = baseintr + cpu; |
430 | gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); | ||
431 | gic_intr_map[intr].cpunum = cpu; | 451 | gic_intr_map[intr].cpunum = cpu; |
432 | gic_intr_map[intr].pin = cpupin; | 452 | gic_intr_map[intr].pin = cpupin; |
433 | gic_intr_map[intr].polarity = GIC_POL_POS; | 453 | gic_intr_map[intr].polarity = GIC_POL_POS; |
434 | gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; | 454 | gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; |
435 | gic_intr_map[intr].ipiflag = 1; | 455 | gic_intr_map[intr].flags = GIC_FLAG_IPI; |
436 | ipi_map[cpu] |= (1 << (cpupin + 2)); | 456 | ipi_map[cpu] |= (1 << (cpupin + 2)); |
437 | } | 457 | } |
438 | 458 | ||
@@ -447,6 +467,12 @@ static void __init fill_ipi_map(void) | |||
447 | } | 467 | } |
448 | #endif | 468 | #endif |
449 | 469 | ||
470 | void __init arch_init_ipiirq(int irq, struct irqaction *action) | ||
471 | { | ||
472 | setup_irq(irq, action); | ||
473 | set_irq_handler(irq, handle_percpu_irq); | ||
474 | } | ||
475 | |||
450 | void __init arch_init_irq(void) | 476 | void __init arch_init_irq(void) |
451 | { | 477 | { |
452 | init_i8259_irqs(); | 478 | init_i8259_irqs(); |
@@ -458,12 +484,17 @@ void __init arch_init_irq(void) | |||
458 | GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; | 484 | GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; |
459 | gic_present = 1; | 485 | gic_present = 1; |
460 | } else { | 486 | } else { |
461 | _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); | 487 | if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { |
462 | gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & | 488 | _msc01_biu_base = (unsigned long) |
463 | MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; | 489 | ioremap_nocache(MSC01_BIU_REG_BASE, |
490 | MSC01_BIU_ADDRSPACE_SZ); | ||
491 | gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & | ||
492 | MSC01_SC_CFG_GICPRES_MSK) >> | ||
493 | MSC01_SC_CFG_GICPRES_SHF; | ||
494 | } | ||
464 | } | 495 | } |
465 | if (gic_present) | 496 | if (gic_present) |
466 | printk(KERN_DEBUG "GIC present\n"); | 497 | pr_debug("GIC present\n"); |
467 | 498 | ||
468 | switch (mips_revision_sconid) { | 499 | switch (mips_revision_sconid) { |
469 | case MIPS_REVISION_SCON_SOCIT: | 500 | case MIPS_REVISION_SCON_SOCIT: |
@@ -526,16 +557,16 @@ void __init arch_init_irq(void) | |||
526 | &corehi_irqaction); | 557 | &corehi_irqaction); |
527 | } | 558 | } |
528 | 559 | ||
529 | #if defined(CONFIG_MIPS_MT_SMP) | ||
530 | if (gic_present) { | 560 | if (gic_present) { |
531 | /* FIXME */ | 561 | /* FIXME */ |
532 | int i; | 562 | int i; |
533 | 563 | #if defined(CONFIG_MIPS_MT_SMP) | |
534 | gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; | 564 | gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; |
535 | gic_resched_int_base = gic_call_int_base - NR_CPUS; | 565 | gic_resched_int_base = gic_call_int_base - NR_CPUS; |
536 | |||
537 | fill_ipi_map(); | 566 | fill_ipi_map(); |
538 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); | 567 | #endif |
568 | gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, | ||
569 | ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); | ||
539 | if (!gcmp_present) { | 570 | if (!gcmp_present) { |
540 | /* Enable the GIC */ | 571 | /* Enable the GIC */ |
541 | i = REG(_msc01_biu_base, MSC01_SC_CFG); | 572 | i = REG(_msc01_biu_base, MSC01_SC_CFG); |
@@ -543,7 +574,7 @@ void __init arch_init_irq(void) | |||
543 | (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); | 574 | (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); |
544 | pr_debug("GIC Enabled\n"); | 575 | pr_debug("GIC Enabled\n"); |
545 | } | 576 | } |
546 | 577 | #if defined(CONFIG_MIPS_MT_SMP) | |
547 | /* set up ipi interrupts */ | 578 | /* set up ipi interrupts */ |
548 | if (cpu_has_vint) { | 579 | if (cpu_has_vint) { |
549 | set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); | 580 | set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); |
@@ -556,16 +587,14 @@ void __init arch_init_irq(void) | |||
556 | write_c0_status(0x1100dc00); | 587 | write_c0_status(0x1100dc00); |
557 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); | 588 | printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); |
558 | for (i = 0; i < NR_CPUS; i++) { | 589 | for (i = 0; i < NR_CPUS; i++) { |
559 | setup_irq(MIPS_GIC_IRQ_BASE + | 590 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
560 | GIC_RESCHED_INT(i), &irq_resched); | 591 | GIC_RESCHED_INT(i), &irq_resched); |
561 | setup_irq(MIPS_GIC_IRQ_BASE + | 592 | arch_init_ipiirq(MIPS_GIC_IRQ_BASE + |
562 | GIC_CALL_INT(i), &irq_call); | 593 | GIC_CALL_INT(i), &irq_call); |
563 | set_irq_handler(MIPS_GIC_IRQ_BASE + | ||
564 | GIC_RESCHED_INT(i), handle_percpu_irq); | ||
565 | set_irq_handler(MIPS_GIC_IRQ_BASE + | ||
566 | GIC_CALL_INT(i), handle_percpu_irq); | ||
567 | } | 594 | } |
595 | #endif | ||
568 | } else { | 596 | } else { |
597 | #if defined(CONFIG_MIPS_MT_SMP) | ||
569 | /* set up ipi interrupts */ | 598 | /* set up ipi interrupts */ |
570 | if (cpu_has_veic) { | 599 | if (cpu_has_veic) { |
571 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); | 600 | set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); |
@@ -580,14 +609,10 @@ void __init arch_init_irq(void) | |||
580 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; | 609 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; |
581 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; | 610 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; |
582 | } | 611 | } |
583 | 612 | arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); | |
584 | setup_irq(cpu_ipi_resched_irq, &irq_resched); | 613 | arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); |
585 | setup_irq(cpu_ipi_call_irq, &irq_call); | ||
586 | |||
587 | set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); | ||
588 | set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); | ||
589 | } | ||
590 | #endif | 614 | #endif |
615 | } | ||
591 | } | 616 | } |
592 | 617 | ||
593 | void malta_be_init(void) | 618 | void malta_be_init(void) |
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b9743190609a..2fbfa1a8c3a9 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c | |||
@@ -27,7 +27,7 @@ | |||
27 | #include <linux/init.h> | 27 | #include <linux/init.h> |
28 | 28 | ||
29 | #include <asm/gt64120.h> | 29 | #include <asm/gt64120.h> |
30 | 30 | #include <asm/gcmpregs.h> | |
31 | #include <asm/mips-boards/generic.h> | 31 | #include <asm/mips-boards/generic.h> |
32 | #include <asm/mips-boards/bonito64.h> | 32 | #include <asm/mips-boards/bonito64.h> |
33 | #include <asm/mips-boards/msc01_pci.h> | 33 | #include <asm/mips-boards/msc01_pci.h> |
@@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) | |||
201 | msc_mem_resource.start = start & mask; | 201 | msc_mem_resource.start = start & mask; |
202 | msc_mem_resource.end = (start & mask) | ~mask; | 202 | msc_mem_resource.end = (start & mask) | ~mask; |
203 | msc_controller.mem_offset = (start & mask) - (map & mask); | 203 | msc_controller.mem_offset = (start & mask) - (map & mask); |
204 | 204 | #ifdef CONFIG_MIPS_CMP | |
205 | if (gcmp_niocu()) | ||
206 | gcmp_setregion(0, start, mask, | ||
207 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
208 | #endif | ||
205 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); | 209 | MSC_READ(MSC01_PCI_SC2PIOBASL, start); |
206 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); | 210 | MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); |
207 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); | 211 | MSC_READ(MSC01_PCI_SC2PIOMAPL, map); |
@@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) | |||
209 | msc_io_resource.end = (map & mask) | ~mask; | 213 | msc_io_resource.end = (map & mask) | ~mask; |
210 | msc_controller.io_offset = 0; | 214 | msc_controller.io_offset = 0; |
211 | ioport_resource.end = ~mask; | 215 | ioport_resource.end = ~mask; |
212 | 216 | #ifdef CONFIG_MIPS_CMP | |
217 | if (gcmp_niocu()) | ||
218 | gcmp_setregion(1, start, mask, | ||
219 | GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); | ||
220 | #endif | ||
213 | /* If ranges overlap I/O takes precedence. */ | 221 | /* If ranges overlap I/O takes precedence. */ |
214 | start = start & mask; | 222 | start = start & mask; |
215 | end = start | ~mask; | 223 | end = start | ~mask; |
@@ -241,3 +249,16 @@ void __init mips_pcibios_init(void) | |||
241 | 249 | ||
242 | register_pci_controller(controller); | 250 | register_pci_controller(controller); |
243 | } | 251 | } |
252 | |||
253 | /* Enable PCI 2.1 compatibility in PIIX4 */ | ||
254 | static void __init quirk_dlcsetup(struct pci_dev *dev) | ||
255 | { | ||
256 | u8 odlc, ndlc; | ||
257 | (void) pci_read_config_byte(dev, 0x82, &odlc); | ||
258 | /* Enable passive releases and delayed transaction */ | ||
259 | ndlc = odlc | 7; | ||
260 | (void) pci_write_config_byte(dev, 0x82, ndlc); | ||
261 | } | ||
262 | |||
263 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | ||
264 | quirk_dlcsetup); | ||
diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c index f080f114a1bf..7aca7d5375e5 100644 --- a/arch/mips/nxp/pnx8550/common/int.c +++ b/arch/mips/nxp/pnx8550/common/int.c | |||
@@ -172,7 +172,7 @@ static struct irqaction gic_action = { | |||
172 | 172 | ||
173 | static struct irqaction timer_action = { | 173 | static struct irqaction timer_action = { |
174 | .handler = no_action, | 174 | .handler = no_action, |
175 | .flags = IRQF_DISABLED, | 175 | .flags = IRQF_DISABLED | IRQF_TIMER, |
176 | .name = "Timer", | 176 | .name = "Timer", |
177 | }; | 177 | }; |
178 | 178 | ||
diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c index 18b192784877..8836c6203df0 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/nxp/pnx8550/common/time.c | |||
@@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) | |||
59 | 59 | ||
60 | static struct irqaction pnx8xxx_timer_irq = { | 60 | static struct irqaction pnx8xxx_timer_irq = { |
61 | .handler = pnx8xxx_timer_interrupt, | 61 | .handler = pnx8xxx_timer_interrupt, |
62 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 62 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
63 | .name = "pnx8xxx_timer", | 63 | .name = "pnx8xxx_timer", |
64 | }; | 64 | }; |
65 | 65 | ||
@@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id) | |||
72 | 72 | ||
73 | static struct irqaction monotonic_irqaction = { | 73 | static struct irqaction monotonic_irqaction = { |
74 | .handler = monotonic_interrupt, | 74 | .handler = monotonic_interrupt, |
75 | .flags = IRQF_DISABLED, | 75 | .flags = IRQF_DISABLED | IRQF_TIMER, |
76 | .name = "Monotonic timer", | 76 | .name = "Monotonic timer", |
77 | }; | 77 | }; |
78 | 78 | ||
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index deed1d5d4982..575cd1473475 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c | |||
@@ -22,7 +22,7 @@ | |||
22 | * otherwise, the oprofile tool will not recognize this and complain about | 22 | * otherwise, the oprofile tool will not recognize this and complain about |
23 | * "cpu_type 'unset' is not valid". | 23 | * "cpu_type 'unset' is not valid". |
24 | */ | 24 | */ |
25 | #define LOONGSON2_CPU_TYPE "mips/godson2" | 25 | #define LOONGSON2_CPU_TYPE "mips/loongson2" |
26 | 26 | ||
27 | #define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) | 27 | #define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) |
28 | #define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) | 28 | #define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) |
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 6d0e59ffba2e..d6802d6d1f82 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c | |||
@@ -105,7 +105,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id) | |||
105 | 105 | ||
106 | struct irqaction hub_rt_irqaction = { | 106 | struct irqaction hub_rt_irqaction = { |
107 | .handler = hub_rt_counter_handler, | 107 | .handler = hub_rt_counter_handler, |
108 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 108 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
109 | .name = "hub-rt", | 109 | .name = "hub-rt", |
110 | }; | 110 | }; |
111 | 111 | ||
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 62df6a598e0a..f3b60e671207 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c | |||
@@ -67,7 +67,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id) | |||
67 | 67 | ||
68 | static struct irqaction a20r_irqaction = { | 68 | static struct irqaction a20r_irqaction = { |
69 | .handler = a20r_interrupt, | 69 | .handler = a20r_interrupt, |
70 | .flags = IRQF_DISABLED | IRQF_PERCPU, | 70 | .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, |
71 | .name = "a20r-timer", | 71 | .name = "a20r-timer", |
72 | }; | 72 | }; |
73 | 73 | ||
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index c860810722c0..e10184c1b3e1 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c | |||
@@ -85,7 +85,7 @@ int txx9_ccfg_toeon __initdata = 1; | |||
85 | struct clk *clk_get(struct device *dev, const char *id) | 85 | struct clk *clk_get(struct device *dev, const char *id) |
86 | { | 86 | { |
87 | if (!strcmp(id, "spi-baseclk")) | 87 | if (!strcmp(id, "spi-baseclk")) |
88 | return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); | 88 | return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2); |
89 | if (!strcmp(id, "imbus_clk")) | 89 | if (!strcmp(id, "imbus_clk")) |
90 | return (struct clk *)((unsigned long)txx9_gbus_clock / 2); | 90 | return (struct clk *)((unsigned long)txx9_gbus_clock / 2); |
91 | return ERR_PTR(-ENOENT); | 91 | return ERR_PTR(-ENOENT); |
@@ -817,7 +817,8 @@ void __init txx9_iocled_init(unsigned long baseaddr, | |||
817 | out_pdev: | 817 | out_pdev: |
818 | platform_device_put(pdev); | 818 | platform_device_put(pdev); |
819 | out_gpio: | 819 | out_gpio: |
820 | gpio_remove(&iocled->chip); | 820 | if (gpiochip_remove(&iocled->chip)) |
821 | return; | ||
821 | out_unmap: | 822 | out_unmap: |
822 | iounmap(iocled->mmioaddr); | 823 | iounmap(iocled->mmioaddr); |
823 | out_free: | 824 | out_free: |