diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2015-02-19 10:00:34 -0500 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-02-19 10:00:34 -0500 |
commit | 661af35e5fd878f915ed05dbbfe383f64133f98c (patch) | |
tree | 956b7efd662b682224e61060552fdcf4201101bf /arch/mips/mm/sc-mips.c | |
parent | ca5d25642e212f73492d332d95dc90ef46a0e8dc (diff) | |
parent | f296e7c48d3155991b99f41372e1786c5be03457 (diff) |
Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/linux into mips-for-linux-next
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
-rw-r--r-- | arch/mips/mm/sc-mips.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 99eb8fabab60..4ceafd13870c 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c | |||
@@ -81,6 +81,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) | |||
81 | case CPU_PROAPTIV: | 81 | case CPU_PROAPTIV: |
82 | case CPU_P5600: | 82 | case CPU_P5600: |
83 | case CPU_BMIPS5000: | 83 | case CPU_BMIPS5000: |
84 | case CPU_QEMU_GENERIC: | ||
84 | if (config2 & (1 << 12)) | 85 | if (config2 & (1 << 12)) |
85 | return 0; | 86 | return 0; |
86 | } | 87 | } |
@@ -104,7 +105,8 @@ static inline int __init mips_sc_probe(void) | |||
104 | 105 | ||
105 | /* Ignore anything but MIPSxx processors */ | 106 | /* Ignore anything but MIPSxx processors */ |
106 | if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | | 107 | if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | |
107 | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2))) | 108 | MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | |
109 | MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6))) | ||
108 | return 0; | 110 | return 0; |
109 | 111 | ||
110 | /* Does this MIPS32/MIPS64 CPU have a config2 register? */ | 112 | /* Does this MIPS32/MIPS64 CPU have a config2 register? */ |