MIPS: Fix ISA level which causes secondary cache init bypassing and more

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 4 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
                 return;
 
         default:
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;