MIPS: Fix ISA level which causes secondary cache init bypassing and more

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 7 insertions, 13 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6bfccc227a95..ed80c3844345 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1226,10 +1226,8 @@ __cpuinit void cpu_probe(void)
         if (c->options & MIPS_CPU_FPU) {
                 c->fpu_id = cpu_get_fpu_id();
 
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
                         if (c->fpu_id & MIPS_FPIR_3D)
                                 c->ases |= MIPS_ASE_MIPS3D;
                 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a200b5bdbb87..c3abb88170fc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 #ifdef CONFIG_64BIT
         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 #endif
-        if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
+        if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
                 status_set |= ST0_XX;
         if (cpu_has_dsp)
                 status_set |= ST0_MX;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
                 return;
 
         default:
-                if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M32R2 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R1 ||
-                    c->isa_level == MIPS_CPU_ISA_M64R2) {
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                    MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
 #ifdef CONFIG_MIPS_CPU_SCACHE
                         if (mips_sc_init ()) {
                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 93d937b4b1ba..df96da7e939b 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
         c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
 
         /* Ignore anything but MIPSxx processors */
-        if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
-            c->isa_level != MIPS_CPU_ISA_M32R2 &&
-            c->isa_level != MIPS_CPU_ISA_M64R1 &&
-            c->isa_level != MIPS_CPU_ISA_M64R2)
+        if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                              MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
                 return 0;
 
         /* Does this MIPS32/MIPS64 CPU have a config2 register? */