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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/mips/loongson/common/cs5536
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/mips/loongson/common/cs5536')
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile13
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_acc.c140
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ehci.c158
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ide.c179
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c316
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c217
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ohci.c147
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_pci.c87
8 files changed, 1257 insertions, 0 deletions
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for CS5536 support.
3#
4
5obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6 cs5536_isa.o cs5536_ehci.o
7
8#
9# Enable cs5536 mfgpt Timer
10#
11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b3fd5eab6548
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
1/*
2 * the ACC Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_acc_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 8);
28 else
29 lo &= ~(0x03 << 8);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_BAR0_REG:
42 if (value == PCI_BAR_RANGE_MASK) {
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44 lo |= SOFT_BAR_ACC_FLAG;
45 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46 } else if (value & 0x01) {
47 value &= 0xfffffffc;
48 hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49 lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51 }
52 break;
53 case PCI_ACC_INT_REG:
54 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55 /* disable all the usb interrupt in PIC */
56 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57 if (value) /* enable all the acc interrupt in PIC */
58 lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60 break;
61 default:
62 break;
63 }
64}
65
66u32 pci_acc_read_reg(int reg)
67{
68 u32 hi, lo;
69 u32 conf_data = 0;
70
71 switch (reg) {
72 case PCI_VENDOR_ID:
73 conf_data =
74 CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75 break;
76 case PCI_COMMAND:
77 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78 if (((lo & 0xfff00000) || (hi & 0x000000ff))
79 && ((hi & 0xf0000000) == 0xa0000000))
80 conf_data |= PCI_COMMAND_IO;
81 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82 if ((lo & 0x300) == 0x300)
83 conf_data |= PCI_COMMAND_MASTER;
84 break;
85 case PCI_STATUS:
86 conf_data |= PCI_STATUS_66MHZ;
87 conf_data |= PCI_STATUS_FAST_BACK;
88 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89 if (lo & SB_PARE_ERR_FLAG)
90 conf_data |= PCI_STATUS_PARITY;
91 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92 break;
93 case PCI_CLASS_REVISION:
94 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95 conf_data = lo & 0x000000ff;
96 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97 break;
98 case PCI_CACHE_LINE_SIZE:
99 conf_data =
100 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101 PCI_NORMAL_LATENCY_TIMER);
102 break;
103 case PCI_BAR0_REG:
104 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105 if (lo & SOFT_BAR_ACC_FLAG) {
106 conf_data = CS5536_ACC_RANGE |
107 PCI_BASE_ADDRESS_SPACE_IO;
108 lo &= ~SOFT_BAR_ACC_FLAG;
109 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110 } else {
111 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112 conf_data = (hi & 0x000000ff) << 12;
113 conf_data |= (lo & 0xfff00000) >> 20;
114 conf_data |= 0x01;
115 conf_data &= ~0x02;
116 }
117 break;
118 case PCI_CARDBUS_CIS:
119 conf_data = PCI_CARDBUS_CIS_POINTER;
120 break;
121 case PCI_SUBSYSTEM_VENDOR_ID:
122 conf_data =
123 CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124 break;
125 case PCI_ROM_ADDRESS:
126 conf_data = PCI_EXPANSION_ROM_BAR;
127 break;
128 case PCI_CAPABILITY_LIST:
129 conf_data = PCI_CAPLIST_USB_POINTER;
130 break;
131 case PCI_INTERRUPT_LINE:
132 conf_data =
133 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134 break;
135 default:
136 break;
137 }
138
139 return conf_data;
140}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..eaf8b86e3318
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
1/*
2 * the EHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ehci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_EHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58 }
59 break;
60 case PCI_EHCI_LEGSMIEN_REG:
61 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62 hi &= 0x003f0000;
63 hi |= (value & 0x3f) << 16;
64 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65 break;
66 case PCI_EHCI_FLADJ_REG:
67 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68 hi &= ~0x00003f00;
69 hi |= value & 0x00003f00;
70 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71 break;
72 default:
73 break;
74 }
75}
76
77u32 pci_ehci_read_reg(int reg)
78{
79 u32 conf_data = 0;
80 u32 hi, lo;
81
82 switch (reg) {
83 case PCI_VENDOR_ID:
84 conf_data =
85 CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86 break;
87 case PCI_COMMAND:
88 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89 if (hi & PCI_COMMAND_MASTER)
90 conf_data |= PCI_COMMAND_MASTER;
91 if (hi & PCI_COMMAND_MEMORY)
92 conf_data |= PCI_COMMAND_MEMORY;
93 break;
94 case PCI_STATUS:
95 conf_data |= PCI_STATUS_66MHZ;
96 conf_data |= PCI_STATUS_FAST_BACK;
97 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98 if (lo & SB_PARE_ERR_FLAG)
99 conf_data |= PCI_STATUS_PARITY;
100 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101 break;
102 case PCI_CLASS_REVISION:
103 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104 conf_data = lo & 0x000000ff;
105 conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106 break;
107 case PCI_CACHE_LINE_SIZE:
108 conf_data =
109 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110 PCI_NORMAL_LATENCY_TIMER);
111 break;
112 case PCI_BAR0_REG:
113 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114 if (lo & SOFT_BAR_EHCI_FLAG) {
115 conf_data = CS5536_EHCI_RANGE |
116 PCI_BASE_ADDRESS_SPACE_MEMORY;
117 lo &= ~SOFT_BAR_EHCI_FLAG;
118 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119 } else {
120 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121 conf_data = lo & 0xfffff000;
122 }
123 break;
124 case PCI_CARDBUS_CIS:
125 conf_data = PCI_CARDBUS_CIS_POINTER;
126 break;
127 case PCI_SUBSYSTEM_VENDOR_ID:
128 conf_data =
129 CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130 break;
131 case PCI_ROM_ADDRESS:
132 conf_data = PCI_EXPANSION_ROM_BAR;
133 break;
134 case PCI_CAPABILITY_LIST:
135 conf_data = PCI_CAPLIST_USB_POINTER;
136 break;
137 case PCI_INTERRUPT_LINE:
138 conf_data =
139 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140 break;
141 case PCI_EHCI_LEGSMIEN_REG:
142 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143 conf_data = (hi & 0x003f0000) >> 16;
144 break;
145 case PCI_EHCI_LEGSMISTS_REG:
146 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147 conf_data = (hi & 0x3f000000) >> 24;
148 break;
149 case PCI_EHCI_FLADJ_REG:
150 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151 conf_data = hi & 0x00003f00;
152 break;
153 default:
154 break;
155 }
156
157 return conf_data;
158}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..9a96b5664c78
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
1/*
2 * the IDE Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ide_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 4);
28 else
29 lo &= ~(0x03 << 4);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_CACHE_LINE_SIZE:
42 value &= 0x0000ff00;
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44 hi &= 0xffffff00;
45 hi |= (value >> 8);
46 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47 break;
48 case PCI_BAR4_REG:
49 if (value == PCI_BAR_RANGE_MASK) {
50 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51 lo |= SOFT_BAR_IDE_FLAG;
52 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53 } else if (value & 0x01) {
54 lo = (value & 0xfffffff0) | 0x1;
55 _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56
57 value &= 0xfffffffc;
58 hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59 lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61 }
62 break;
63 case PCI_IDE_CFG_REG:
64 if (value == CS5536_IDE_FLASH_SIGNATURE) {
65 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66 lo |= 0x01;
67 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68 } else
69 _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70 break;
71 case PCI_IDE_DTC_REG:
72 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73 break;
74 case PCI_IDE_CAST_REG:
75 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76 break;
77 case PCI_IDE_ETC_REG:
78 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79 break;
80 case PCI_IDE_PM_REG:
81 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82 break;
83 default:
84 break;
85 }
86}
87
88u32 pci_ide_read_reg(int reg)
89{
90 u32 conf_data = 0;
91 u32 hi, lo;
92
93 switch (reg) {
94 case PCI_VENDOR_ID:
95 conf_data =
96 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97 break;
98 case PCI_COMMAND:
99 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100 if (lo & 0xfffffff0)
101 conf_data |= PCI_COMMAND_IO;
102 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103 if ((lo & 0x30) == 0x30)
104 conf_data |= PCI_COMMAND_MASTER;
105 break;
106 case PCI_STATUS:
107 conf_data |= PCI_STATUS_66MHZ;
108 conf_data |= PCI_STATUS_FAST_BACK;
109 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110 if (lo & SB_PARE_ERR_FLAG)
111 conf_data |= PCI_STATUS_PARITY;
112 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113 break;
114 case PCI_CLASS_REVISION:
115 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116 conf_data = lo & 0x000000ff;
117 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118 break;
119 case PCI_CACHE_LINE_SIZE:
120 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121 hi &= 0x000000f8;
122 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123 break;
124 case PCI_BAR4_REG:
125 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126 if (lo & SOFT_BAR_IDE_FLAG) {
127 conf_data = CS5536_IDE_RANGE |
128 PCI_BASE_ADDRESS_SPACE_IO;
129 lo &= ~SOFT_BAR_IDE_FLAG;
130 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131 } else {
132 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133 conf_data = lo & 0xfffffff0;
134 conf_data |= 0x01;
135 conf_data &= ~0x02;
136 }
137 break;
138 case PCI_CARDBUS_CIS:
139 conf_data = PCI_CARDBUS_CIS_POINTER;
140 break;
141 case PCI_SUBSYSTEM_VENDOR_ID:
142 conf_data =
143 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144 break;
145 case PCI_ROM_ADDRESS:
146 conf_data = PCI_EXPANSION_ROM_BAR;
147 break;
148 case PCI_CAPABILITY_LIST:
149 conf_data = PCI_CAPLIST_POINTER;
150 break;
151 case PCI_INTERRUPT_LINE:
152 conf_data =
153 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154 break;
155 case PCI_IDE_CFG_REG:
156 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157 conf_data = lo;
158 break;
159 case PCI_IDE_DTC_REG:
160 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161 conf_data = lo;
162 break;
163 case PCI_IDE_CAST_REG:
164 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165 conf_data = lo;
166 break;
167 case PCI_IDE_ETC_REG:
168 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169 conf_data = lo;
170 case PCI_IDE_PM_REG:
171 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172 conf_data = lo;
173 break;
174 default:
175 break;
176 }
177
178 return conf_data;
179}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..f5c0818831b2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
1/*
2 * the ISA Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19/* common variables for PCI_ISA_READ/WRITE_BAR */
20static const u32 divil_msr_reg[6] = {
21 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24};
25
26static const u32 soft_bar_flag[6] = {
27 SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28 SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29};
30
31static const u32 sb_msr_reg[6] = {
32 SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33 SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34};
35
36static const u32 bar_space_range[6] = {
37 CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38 CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39};
40
41static const int bar_space_len[6] = {
42 CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43 CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44};
45
46/*
47 * enable the divil module bar space.
48 *
49 * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50 * and the RCONFx(0~5) reg to use the modules.
51 */
52static void divil_lbar_enable(void)
53{
54 u32 hi, lo;
55 int offset;
56
57 /*
58 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59 */
60
61 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63 hi |= 0x01;
64 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65 }
66}
67
68/*
69 * disable the divil module bar space.
70 */
71static void divil_lbar_disable(void)
72{
73 u32 hi, lo;
74 int offset;
75
76 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78 hi &= ~0x01;
79 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80 }
81}
82
83/*
84 * BAR write: write value to the n BAR
85 */
86
87void pci_isa_write_bar(int n, u32 value)
88{
89 u32 hi = 0, lo = value;
90
91 if (value == PCI_BAR_RANGE_MASK) {
92 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93 lo |= soft_bar_flag[n];
94 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95 } else if (value & 0x01) {
96 /* NATIVE reg */
97 hi = 0x0000f001;
98 lo &= bar_space_range[n];
99 _wrmsr(divil_msr_reg[n], hi, lo);
100
101 /* RCONFx is 4bytes in units for I/O space */
102 hi = ((value & 0x000ffffc) << 12) |
103 ((bar_space_len[n] - 4) << 12) | 0x01;
104 lo = ((value & 0x000ffffc) << 12) | 0x01;
105 _wrmsr(sb_msr_reg[n], hi, lo);
106 }
107}
108
109/*
110 * BAR read: read the n BAR
111 */
112
113u32 pci_isa_read_bar(int n)
114{
115 u32 conf_data = 0;
116 u32 hi, lo;
117
118 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119 if (lo & soft_bar_flag[n]) {
120 conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121 lo &= ~soft_bar_flag[n];
122 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123 } else {
124 _rdmsr(divil_msr_reg[n], &hi, &lo);
125 conf_data = lo & bar_space_range[n];
126 conf_data |= 0x01;
127 conf_data &= ~0x02;
128 }
129 return conf_data;
130}
131
132/*
133 * isa_write: ISA write transfer
134 *
135 * We assume that this is not a bus master transfer.
136 */
137void pci_isa_write_reg(int reg, u32 value)
138{
139 u32 hi = 0, lo = value;
140 u32 temp;
141
142 switch (reg) {
143 case PCI_COMMAND:
144 if (value & PCI_COMMAND_IO)
145 divil_lbar_enable();
146 else
147 divil_lbar_disable();
148 break;
149 case PCI_STATUS:
150 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151 temp = lo & 0x0000ffff;
152 if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153 (lo & SB_TAS_ERR_EN))
154 temp |= SB_TAS_ERR_FLAG;
155
156 if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157 (lo & SB_TAR_ERR_EN))
158 temp |= SB_TAR_ERR_FLAG;
159
160 if ((value & PCI_STATUS_REC_MASTER_ABORT)
161 && (lo & SB_MAR_ERR_EN))
162 temp |= SB_MAR_ERR_FLAG;
163
164 if ((value & PCI_STATUS_DETECTED_PARITY)
165 && (lo & SB_PARE_ERR_EN))
166 temp |= SB_PARE_ERR_FLAG;
167
168 lo = temp;
169 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170 break;
171 case PCI_CACHE_LINE_SIZE:
172 value &= 0x0000ff00;
173 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174 hi &= 0xffffff00;
175 hi |= (value >> 8);
176 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177 break;
178 case PCI_BAR0_REG:
179 pci_isa_write_bar(0, value);
180 break;
181 case PCI_BAR1_REG:
182 pci_isa_write_bar(1, value);
183 break;
184 case PCI_BAR2_REG:
185 pci_isa_write_bar(2, value);
186 break;
187 case PCI_BAR3_REG:
188 pci_isa_write_bar(3, value);
189 break;
190 case PCI_BAR4_REG:
191 pci_isa_write_bar(4, value);
192 break;
193 case PCI_BAR5_REG:
194 pci_isa_write_bar(5, value);
195 break;
196 case PCI_UART1_INT_REG:
197 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198 /* disable uart1 interrupt in PIC */
199 lo &= ~(0xf << 24);
200 if (value) /* enable uart1 interrupt in PIC */
201 lo |= (CS5536_UART1_INTR << 24);
202 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203 break;
204 case PCI_UART2_INT_REG:
205 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206 /* disable uart2 interrupt in PIC */
207 lo &= ~(0xf << 28);
208 if (value) /* enable uart2 interrupt in PIC */
209 lo |= (CS5536_UART2_INTR << 28);
210 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211 break;
212 case PCI_ISA_FIXUP_REG:
213 if (value) {
214 /* enable the TARGET ABORT/MASTER ABORT etc. */
215 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216 lo |= 0x00000063;
217 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218 }
219
220 default:
221 /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222 break;
223 }
224}
225
226/*
227 * isa_read: ISA read transfers
228 *
229 * We assume that this is not a bus master transfer.
230 */
231u32 pci_isa_read_reg(int reg)
232{
233 u32 conf_data = 0;
234 u32 hi, lo;
235
236 switch (reg) {
237 case PCI_VENDOR_ID:
238 conf_data =
239 CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240 break;
241 case PCI_COMMAND:
242 /* we just check the first LBAR for the IO enable bit, */
243 /* maybe we should changed later. */
244 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245 if (hi & 0x01)
246 conf_data |= PCI_COMMAND_IO;
247 break;
248 case PCI_STATUS:
249 conf_data |= PCI_STATUS_66MHZ;
250 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251 conf_data |= PCI_STATUS_FAST_BACK;
252
253 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254 if (lo & SB_TAS_ERR_FLAG)
255 conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256 if (lo & SB_TAR_ERR_FLAG)
257 conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258 if (lo & SB_MAR_ERR_FLAG)
259 conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260 if (lo & SB_PARE_ERR_FLAG)
261 conf_data |= PCI_STATUS_DETECTED_PARITY;
262 break;
263 case PCI_CLASS_REVISION:
264 _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265 conf_data = lo & 0x000000ff;
266 conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267 break;
268 case PCI_CACHE_LINE_SIZE:
269 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270 hi &= 0x000000f8;
271 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272 break;
273 /*
274 * we only use the LBAR of DIVIL, no RCONF used.
275 * all of them are IO space.
276 */
277 case PCI_BAR0_REG:
278 return pci_isa_read_bar(0);
279 break;
280 case PCI_BAR1_REG:
281 return pci_isa_read_bar(1);
282 break;
283 case PCI_BAR2_REG:
284 return pci_isa_read_bar(2);
285 break;
286 case PCI_BAR3_REG:
287 break;
288 case PCI_BAR4_REG:
289 return pci_isa_read_bar(4);
290 break;
291 case PCI_BAR5_REG:
292 return pci_isa_read_bar(5);
293 break;
294 case PCI_CARDBUS_CIS:
295 conf_data = PCI_CARDBUS_CIS_POINTER;
296 break;
297 case PCI_SUBSYSTEM_VENDOR_ID:
298 conf_data =
299 CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300 break;
301 case PCI_ROM_ADDRESS:
302 conf_data = PCI_EXPANSION_ROM_BAR;
303 break;
304 case PCI_CAPABILITY_LIST:
305 conf_data = PCI_CAPLIST_POINTER;
306 break;
307 case PCI_INTERRUPT_LINE:
308 /* no interrupt used here */
309 conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310 break;
311 default:
312 break;
313 }
314
315 return conf_data;
316}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..8c807c965199
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
1/*
2 * CS5536 General timer functions
3 *
4 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua, yanh@lemote.com
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu zhangjin, wuzhangjin@gmail.com
9 *
10 * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/jiffies.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <asm/time.h>
27
28#include <cs5536/cs5536_mfgpt.h>
29
30DEFINE_SPINLOCK(mfgpt_lock);
31EXPORT_SYMBOL(mfgpt_lock);
32
33static u32 mfgpt_base;
34
35/*
36 * Initialize the MFGPT timer.
37 *
38 * This is also called after resume to bring the MFGPT into operation again.
39 */
40
41/* disable counter */
42void disable_mfgpt0_counter(void)
43{
44 outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
45}
46EXPORT_SYMBOL(disable_mfgpt0_counter);
47
48/* enable counter, comparator2 to event mode, 14.318MHz clock */
49void enable_mfgpt0_counter(void)
50{
51 outw(0xe310, MFGPT0_SETUP);
52}
53EXPORT_SYMBOL(enable_mfgpt0_counter);
54
55static void init_mfgpt_timer(enum clock_event_mode mode,
56 struct clock_event_device *evt)
57{
58 spin_lock(&mfgpt_lock);
59
60 switch (mode) {
61 case CLOCK_EVT_MODE_PERIODIC:
62 outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
63 outw(0, MFGPT0_CNT); /* set counter to 0 */
64 enable_mfgpt0_counter();
65 break;
66
67 case CLOCK_EVT_MODE_SHUTDOWN:
68 case CLOCK_EVT_MODE_UNUSED:
69 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
70 evt->mode == CLOCK_EVT_MODE_ONESHOT)
71 disable_mfgpt0_counter();
72 break;
73
74 case CLOCK_EVT_MODE_ONESHOT:
75 /* The oneshot mode have very high deviation, Not use it! */
76 break;
77
78 case CLOCK_EVT_MODE_RESUME:
79 /* Nothing to do here */
80 break;
81 }
82 spin_unlock(&mfgpt_lock);
83}
84
85static struct clock_event_device mfgpt_clockevent = {
86 .name = "mfgpt",
87 .features = CLOCK_EVT_FEAT_PERIODIC,
88 .set_mode = init_mfgpt_timer,
89 .irq = CS5536_MFGPT_INTR,
90};
91
92static irqreturn_t timer_interrupt(int irq, void *dev_id)
93{
94 u32 basehi;
95
96 /*
97 * get MFGPT base address
98 *
99 * NOTE: do not remove me, it's need for the value of mfgpt_base is
100 * variable
101 */
102 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
103
104 /* ack */
105 outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
106
107 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
108
109 return IRQ_HANDLED;
110}
111
112static struct irqaction irq5 = {
113 .handler = timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
115 .name = "timer"
116};
117
118/*
119 * Initialize the conversion factor and the min/max deltas of the clock event
120 * structure and register the clock event source with the framework.
121 */
122void __init setup_mfgpt0_timer(void)
123{
124 u32 basehi;
125 struct clock_event_device *cd = &mfgpt_clockevent;
126 unsigned int cpu = smp_processor_id();
127
128 cd->cpumask = cpumask_of(cpu);
129 clockevent_set_clock(cd, MFGPT_TICK_RATE);
130 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
131 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
132
133 /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
134 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
135
136 /* Enable Interrupt Gate 5 */
137 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
138
139 /* get MFGPT base address */
140 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
141
142 clockevents_register_device(cd);
143
144 setup_irq(CS5536_MFGPT_INTR, &irq5);
145}
146
147/*
148 * Since the MFGPT overflows every tick, its not very useful
149 * to just read by itself. So use jiffies to emulate a free
150 * running counter:
151 */
152static cycle_t mfgpt_read(struct clocksource *cs)
153{
154 unsigned long flags;
155 int count;
156 u32 jifs;
157 static int old_count;
158 static u32 old_jifs;
159
160 spin_lock_irqsave(&mfgpt_lock, flags);
161 /*
162 * Although our caller may have the read side of xtime_lock,
163 * this is now a seqlock, and we are cheating in this routine
164 * by having side effects on state that we cannot undo if
165 * there is a collision on the seqlock and our caller has to
166 * retry. (Namely, old_jifs and old_count.) So we must treat
167 * jiffies as volatile despite the lock. We read jiffies
168 * before latching the timer count to guarantee that although
169 * the jiffies value might be older than the count (that is,
170 * the counter may underflow between the last point where
171 * jiffies was incremented and the point where we latch the
172 * count), it cannot be newer.
173 */
174 jifs = jiffies;
175 /* read the count */
176 count = inw(MFGPT0_CNT);
177
178 /*
179 * It's possible for count to appear to go the wrong way for this
180 * reason:
181 *
182 * The timer counter underflows, but we haven't handled the resulting
183 * interrupt and incremented jiffies yet.
184 *
185 * Previous attempts to handle these cases intelligently were buggy, so
186 * we just do the simple thing now.
187 */
188 if (count < old_count && jifs == old_jifs)
189 count = old_count;
190
191 old_count = count;
192 old_jifs = jifs;
193
194 spin_unlock_irqrestore(&mfgpt_lock, flags);
195
196 return (cycle_t) (jifs * COMPARE) + count;
197}
198
199static struct clocksource clocksource_mfgpt = {
200 .name = "mfgpt",
201 .rating = 120, /* Functional for real use, but not desired */
202 .read = mfgpt_read,
203 .mask = CLOCKSOURCE_MASK(32),
204 .mult = 0,
205 .shift = 22,
206};
207
208int __init init_mfgpt_clocksource(void)
209{
210 if (num_possible_cpus() > 1) /* MFGPT does not scale! */
211 return 0;
212
213 clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
214 return clocksource_register(&clocksource_mfgpt);
215}
216
217arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..db5900aadd6b
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
1/*
2 * the OHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ohci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58 }
59 break;
60 case PCI_OHCI_INT_REG:
61 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63 if (value) /* enable all the usb interrupt in PIC */
64 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66 break;
67 default:
68 break;
69 }
70}
71
72u32 pci_ohci_read_reg(int reg)
73{
74 u32 conf_data = 0;
75 u32 hi, lo;
76
77 switch (reg) {
78 case PCI_VENDOR_ID:
79 conf_data =
80 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81 break;
82 case PCI_COMMAND:
83 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84 if (hi & PCI_COMMAND_MASTER)
85 conf_data |= PCI_COMMAND_MASTER;
86 if (hi & PCI_COMMAND_MEMORY)
87 conf_data |= PCI_COMMAND_MEMORY;
88 break;
89 case PCI_STATUS:
90 conf_data |= PCI_STATUS_66MHZ;
91 conf_data |= PCI_STATUS_FAST_BACK;
92 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93 if (lo & SB_PARE_ERR_FLAG)
94 conf_data |= PCI_STATUS_PARITY;
95 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96 break;
97 case PCI_CLASS_REVISION:
98 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99 conf_data = lo & 0x000000ff;
100 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101 break;
102 case PCI_CACHE_LINE_SIZE:
103 conf_data =
104 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105 PCI_NORMAL_LATENCY_TIMER);
106 break;
107 case PCI_BAR0_REG:
108 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109 if (lo & SOFT_BAR_OHCI_FLAG) {
110 conf_data = CS5536_OHCI_RANGE |
111 PCI_BASE_ADDRESS_SPACE_MEMORY;
112 lo &= ~SOFT_BAR_OHCI_FLAG;
113 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114 } else {
115 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116 conf_data = lo & 0xffffff00;
117 conf_data &= ~0x0000000f; /* 32bit mem */
118 }
119 break;
120 case PCI_CARDBUS_CIS:
121 conf_data = PCI_CARDBUS_CIS_POINTER;
122 break;
123 case PCI_SUBSYSTEM_VENDOR_ID:
124 conf_data =
125 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126 break;
127 case PCI_ROM_ADDRESS:
128 conf_data = PCI_EXPANSION_ROM_BAR;
129 break;
130 case PCI_CAPABILITY_LIST:
131 conf_data = PCI_CAPLIST_USB_POINTER;
132 break;
133 case PCI_INTERRUPT_LINE:
134 conf_data =
135 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136 break;
137 case PCI_OHCI_INT_REG:
138 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139 if ((lo & 0x00000f00) == CS5536_USB_INTR)
140 conf_data = 1;
141 break;
142 default:
143 break;
144 }
145
146 return conf_data;
147}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..6dfeab11af08
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
1/*
2 * read/write operation to the PCI config space of CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * the Virtual Support Module(VSM) for virtulizing the PCI
16 * configure space are defined in cs5536_modulename.c respectively,
17 *
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
21 */
22
23#include <linux/types.h>
24#include <cs5536/cs5536_vsm.h>
25
26enum {
27 CS5536_FUNC_START = -1,
28 CS5536_ISA_FUNC,
29 reserved_func,
30 CS5536_IDE_FUNC,
31 CS5536_ACC_FUNC,
32 CS5536_OHCI_FUNC,
33 CS5536_EHCI_FUNC,
34 CS5536_FUNC_END,
35};
36
37static const cs5536_pci_vsm_write vsm_conf_write[] = {
38 [CS5536_ISA_FUNC] pci_isa_write_reg,
39 [reserved_func] NULL,
40 [CS5536_IDE_FUNC] pci_ide_write_reg,
41 [CS5536_ACC_FUNC] pci_acc_write_reg,
42 [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43 [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44};
45
46static const cs5536_pci_vsm_read vsm_conf_read[] = {
47 [CS5536_ISA_FUNC] pci_isa_read_reg,
48 [reserved_func] NULL,
49 [CS5536_IDE_FUNC] pci_ide_read_reg,
50 [CS5536_ACC_FUNC] pci_acc_read_reg,
51 [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52 [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53};
54
55/*
56 * write to PCI config space and transfer it to MSR write.
57 */
58void cs5536_pci_conf_write4(int function, int reg, u32 value)
59{
60 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61 return;
62 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63 return;
64
65 if (vsm_conf_write[function] != NULL)
66 vsm_conf_write[function](reg, value);
67}
68
69/*
70 * read PCI config space and transfer it to MSR access.
71 */
72u32 cs5536_pci_conf_read4(int function, int reg)
73{
74 u32 data = 0;
75
76 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77 return 0;
78 if ((reg < 0) || ((reg & 0x03) != 0))
79 return 0;
80 if (reg > 0x100)
81 return 0xffffffff;
82
83 if (vsm_conf_read[function] != NULL)
84 data = vsm_conf_read[function](reg);
85
86 return data;
87}
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