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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/mips/loongson/common
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/mips/loongson/common')
-rw-r--r--arch/mips/loongson/common/Makefile18
-rw-r--r--arch/mips/loongson/common/bonito-irq.c13
-rw-r--r--arch/mips/loongson/common/cmdline.c13
-rw-r--r--arch/mips/loongson/common/cs5536/Makefile13
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_acc.c140
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ehci.c158
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ide.c179
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_isa.c316
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c217
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_ohci.c147
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_pci.c87
-rw-r--r--arch/mips/loongson/common/early_printk.c19
-rw-r--r--arch/mips/loongson/common/env.c32
-rw-r--r--arch/mips/loongson/common/init.c21
-rw-r--r--arch/mips/loongson/common/irq.c12
-rw-r--r--arch/mips/loongson/common/machtype.c37
-rw-r--r--arch/mips/loongson/common/mem.c96
-rw-r--r--arch/mips/loongson/common/pci.c20
-rw-r--r--arch/mips/loongson/common/platform.c30
-rw-r--r--arch/mips/loongson/common/pm.c161
-rw-r--r--arch/mips/loongson/common/reset.c40
-rw-r--r--arch/mips/loongson/common/serial.c76
-rw-r--r--arch/mips/loongson/common/setup.c15
-rw-r--r--arch/mips/loongson/common/time.c7
-rw-r--r--arch/mips/loongson/common/uart_base.c45
25 files changed, 1832 insertions, 80 deletions
diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile
index 656b3cc0a2a6..7668c4de1151 100644
--- a/arch/mips/loongson/common/Makefile
+++ b/arch/mips/loongson/common/Makefile
@@ -3,9 +3,23 @@
3# 3#
4 4
5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ 5obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6 pci.o bonito-irq.o mem.o machtype.o 6 pci.o bonito-irq.o mem.o machtype.o platform.o
7 7
8# 8#
9# Early printk support 9# Serial port support
10# 10#
11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12obj-$(CONFIG_SERIAL_8250) += serial.o
13obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
14
15#
16# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
17# space
18#
19obj-$(CONFIG_CS5536) += cs5536/
20
21#
22# Suspend Support
23#
24
25obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..2dc2a4cc632a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -12,18 +12,19 @@
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/compiler.h>
15 16
16#include <loongson.h> 17#include <loongson.h>
17 18
18static inline void bonito_irq_enable(unsigned int irq) 19static inline void bonito_irq_enable(unsigned int irq)
19{ 20{
20 BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); 21 LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
21 mmiowb(); 22 mmiowb();
22} 23}
23 24
24static inline void bonito_irq_disable(unsigned int irq) 25static inline void bonito_irq_disable(unsigned int irq)
25{ 26{
26 BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); 27 LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
27 mmiowb(); 28 mmiowb();
28} 29}
29 30
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = {
35 .unmask = bonito_irq_enable, 36 .unmask = bonito_irq_enable,
36}; 37};
37 38
38static struct irqaction dma_timeout_irqaction = { 39static struct irqaction __maybe_unused dma_timeout_irqaction = {
39 .handler = no_action, 40 .handler = no_action,
40 .name = "dma_timeout", 41 .name = "dma_timeout",
41}; 42};
@@ -44,8 +45,10 @@ void bonito_irq_init(void)
44{ 45{
45 u32 i; 46 u32 i;
46 47
47 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) 48 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 49 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
49 50
50 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); 51#ifdef CONFIG_CPU_LOONGSON2E
52 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
53#endif
51} 54}
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 75f1b243ee4e..1a06defc4f7f 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -9,8 +9,8 @@
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com 10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 * 11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 12 * Copyright (C) 2009 Lemote Inc.
13 * Author: Wu Zhangjin, wuzj@lemote.com 13 * Author: Wu Zhangjin, wuzhangjin@gmail.com
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the 16 * under the terms of the GNU General Public License as published by the
@@ -21,12 +21,11 @@
21 21
22#include <loongson.h> 22#include <loongson.h>
23 23
24int prom_argc;
25/* pmon passes arguments in 32bit pointers */
26int *_prom_argv;
27
28void __init prom_init_cmdline(void) 24void __init prom_init_cmdline(void)
29{ 25{
26 int prom_argc;
27 /* pmon passes arguments in 32bit pointers */
28 int *_prom_argv;
30 int i; 29 int i;
31 long l; 30 long l;
32 31
@@ -49,4 +48,6 @@ void __init prom_init_cmdline(void)
49 strcat(arcs_cmdline, " console=ttyS0,115200"); 48 strcat(arcs_cmdline, " console=ttyS0,115200");
50 if ((strstr(arcs_cmdline, "root=")) == NULL) 49 if ((strstr(arcs_cmdline, "root=")) == NULL)
51 strcat(arcs_cmdline, " root=/dev/hda1"); 50 strcat(arcs_cmdline, " root=/dev/hda1");
51
52 prom_init_machtype();
52} 53}
diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile
new file mode 100644
index 000000000000..510d4cdc2378
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for CS5536 support.
3#
4
5obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6 cs5536_isa.o cs5536_ehci.o
7
8#
9# Enable cs5536 mfgpt Timer
10#
11obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12
13EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
new file mode 100644
index 000000000000..b3fd5eab6548
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -0,0 +1,140 @@
1/*
2 * the ACC Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_acc_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 8);
28 else
29 lo &= ~(0x03 << 8);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_BAR0_REG:
42 if (value == PCI_BAR_RANGE_MASK) {
43 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44 lo |= SOFT_BAR_ACC_FLAG;
45 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46 } else if (value & 0x01) {
47 value &= 0xfffffffc;
48 hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49 lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51 }
52 break;
53 case PCI_ACC_INT_REG:
54 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55 /* disable all the usb interrupt in PIC */
56 lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57 if (value) /* enable all the acc interrupt in PIC */
58 lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60 break;
61 default:
62 break;
63 }
64}
65
66u32 pci_acc_read_reg(int reg)
67{
68 u32 hi, lo;
69 u32 conf_data = 0;
70
71 switch (reg) {
72 case PCI_VENDOR_ID:
73 conf_data =
74 CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75 break;
76 case PCI_COMMAND:
77 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78 if (((lo & 0xfff00000) || (hi & 0x000000ff))
79 && ((hi & 0xf0000000) == 0xa0000000))
80 conf_data |= PCI_COMMAND_IO;
81 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82 if ((lo & 0x300) == 0x300)
83 conf_data |= PCI_COMMAND_MASTER;
84 break;
85 case PCI_STATUS:
86 conf_data |= PCI_STATUS_66MHZ;
87 conf_data |= PCI_STATUS_FAST_BACK;
88 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89 if (lo & SB_PARE_ERR_FLAG)
90 conf_data |= PCI_STATUS_PARITY;
91 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92 break;
93 case PCI_CLASS_REVISION:
94 _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95 conf_data = lo & 0x000000ff;
96 conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97 break;
98 case PCI_CACHE_LINE_SIZE:
99 conf_data =
100 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101 PCI_NORMAL_LATENCY_TIMER);
102 break;
103 case PCI_BAR0_REG:
104 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105 if (lo & SOFT_BAR_ACC_FLAG) {
106 conf_data = CS5536_ACC_RANGE |
107 PCI_BASE_ADDRESS_SPACE_IO;
108 lo &= ~SOFT_BAR_ACC_FLAG;
109 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110 } else {
111 _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112 conf_data = (hi & 0x000000ff) << 12;
113 conf_data |= (lo & 0xfff00000) >> 20;
114 conf_data |= 0x01;
115 conf_data &= ~0x02;
116 }
117 break;
118 case PCI_CARDBUS_CIS:
119 conf_data = PCI_CARDBUS_CIS_POINTER;
120 break;
121 case PCI_SUBSYSTEM_VENDOR_ID:
122 conf_data =
123 CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124 break;
125 case PCI_ROM_ADDRESS:
126 conf_data = PCI_EXPANSION_ROM_BAR;
127 break;
128 case PCI_CAPABILITY_LIST:
129 conf_data = PCI_CAPLIST_USB_POINTER;
130 break;
131 case PCI_INTERRUPT_LINE:
132 conf_data =
133 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134 break;
135 default:
136 break;
137 }
138
139 return conf_data;
140}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
new file mode 100644
index 000000000000..eaf8b86e3318
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -0,0 +1,158 @@
1/*
2 * the EHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ehci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_EHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58 }
59 break;
60 case PCI_EHCI_LEGSMIEN_REG:
61 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62 hi &= 0x003f0000;
63 hi |= (value & 0x3f) << 16;
64 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65 break;
66 case PCI_EHCI_FLADJ_REG:
67 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68 hi &= ~0x00003f00;
69 hi |= value & 0x00003f00;
70 _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71 break;
72 default:
73 break;
74 }
75}
76
77u32 pci_ehci_read_reg(int reg)
78{
79 u32 conf_data = 0;
80 u32 hi, lo;
81
82 switch (reg) {
83 case PCI_VENDOR_ID:
84 conf_data =
85 CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86 break;
87 case PCI_COMMAND:
88 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89 if (hi & PCI_COMMAND_MASTER)
90 conf_data |= PCI_COMMAND_MASTER;
91 if (hi & PCI_COMMAND_MEMORY)
92 conf_data |= PCI_COMMAND_MEMORY;
93 break;
94 case PCI_STATUS:
95 conf_data |= PCI_STATUS_66MHZ;
96 conf_data |= PCI_STATUS_FAST_BACK;
97 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98 if (lo & SB_PARE_ERR_FLAG)
99 conf_data |= PCI_STATUS_PARITY;
100 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101 break;
102 case PCI_CLASS_REVISION:
103 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104 conf_data = lo & 0x000000ff;
105 conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106 break;
107 case PCI_CACHE_LINE_SIZE:
108 conf_data =
109 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110 PCI_NORMAL_LATENCY_TIMER);
111 break;
112 case PCI_BAR0_REG:
113 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114 if (lo & SOFT_BAR_EHCI_FLAG) {
115 conf_data = CS5536_EHCI_RANGE |
116 PCI_BASE_ADDRESS_SPACE_MEMORY;
117 lo &= ~SOFT_BAR_EHCI_FLAG;
118 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119 } else {
120 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121 conf_data = lo & 0xfffff000;
122 }
123 break;
124 case PCI_CARDBUS_CIS:
125 conf_data = PCI_CARDBUS_CIS_POINTER;
126 break;
127 case PCI_SUBSYSTEM_VENDOR_ID:
128 conf_data =
129 CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130 break;
131 case PCI_ROM_ADDRESS:
132 conf_data = PCI_EXPANSION_ROM_BAR;
133 break;
134 case PCI_CAPABILITY_LIST:
135 conf_data = PCI_CAPLIST_USB_POINTER;
136 break;
137 case PCI_INTERRUPT_LINE:
138 conf_data =
139 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140 break;
141 case PCI_EHCI_LEGSMIEN_REG:
142 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143 conf_data = (hi & 0x003f0000) >> 16;
144 break;
145 case PCI_EHCI_LEGSMISTS_REG:
146 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147 conf_data = (hi & 0x3f000000) >> 24;
148 break;
149 case PCI_EHCI_FLADJ_REG:
150 _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151 conf_data = hi & 0x00003f00;
152 break;
153 default:
154 break;
155 }
156
157 return conf_data;
158}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
new file mode 100644
index 000000000000..9a96b5664c78
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -0,0 +1,179 @@
1/*
2 * the IDE Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ide_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 lo |= (0x03 << 4);
28 else
29 lo &= ~(0x03 << 4);
30 _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31 break;
32 case PCI_STATUS:
33 if (value & PCI_STATUS_PARITY) {
34 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35 if (lo & SB_PARE_ERR_FLAG) {
36 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38 }
39 }
40 break;
41 case PCI_CACHE_LINE_SIZE:
42 value &= 0x0000ff00;
43 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44 hi &= 0xffffff00;
45 hi |= (value >> 8);
46 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47 break;
48 case PCI_BAR4_REG:
49 if (value == PCI_BAR_RANGE_MASK) {
50 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51 lo |= SOFT_BAR_IDE_FLAG;
52 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53 } else if (value & 0x01) {
54 lo = (value & 0xfffffff0) | 0x1;
55 _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56
57 value &= 0xfffffffc;
58 hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59 lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60 _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61 }
62 break;
63 case PCI_IDE_CFG_REG:
64 if (value == CS5536_IDE_FLASH_SIGNATURE) {
65 _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66 lo |= 0x01;
67 _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68 } else
69 _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70 break;
71 case PCI_IDE_DTC_REG:
72 _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73 break;
74 case PCI_IDE_CAST_REG:
75 _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76 break;
77 case PCI_IDE_ETC_REG:
78 _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79 break;
80 case PCI_IDE_PM_REG:
81 _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82 break;
83 default:
84 break;
85 }
86}
87
88u32 pci_ide_read_reg(int reg)
89{
90 u32 conf_data = 0;
91 u32 hi, lo;
92
93 switch (reg) {
94 case PCI_VENDOR_ID:
95 conf_data =
96 CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97 break;
98 case PCI_COMMAND:
99 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100 if (lo & 0xfffffff0)
101 conf_data |= PCI_COMMAND_IO;
102 _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103 if ((lo & 0x30) == 0x30)
104 conf_data |= PCI_COMMAND_MASTER;
105 break;
106 case PCI_STATUS:
107 conf_data |= PCI_STATUS_66MHZ;
108 conf_data |= PCI_STATUS_FAST_BACK;
109 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110 if (lo & SB_PARE_ERR_FLAG)
111 conf_data |= PCI_STATUS_PARITY;
112 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113 break;
114 case PCI_CLASS_REVISION:
115 _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116 conf_data = lo & 0x000000ff;
117 conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118 break;
119 case PCI_CACHE_LINE_SIZE:
120 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121 hi &= 0x000000f8;
122 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123 break;
124 case PCI_BAR4_REG:
125 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126 if (lo & SOFT_BAR_IDE_FLAG) {
127 conf_data = CS5536_IDE_RANGE |
128 PCI_BASE_ADDRESS_SPACE_IO;
129 lo &= ~SOFT_BAR_IDE_FLAG;
130 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131 } else {
132 _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133 conf_data = lo & 0xfffffff0;
134 conf_data |= 0x01;
135 conf_data &= ~0x02;
136 }
137 break;
138 case PCI_CARDBUS_CIS:
139 conf_data = PCI_CARDBUS_CIS_POINTER;
140 break;
141 case PCI_SUBSYSTEM_VENDOR_ID:
142 conf_data =
143 CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144 break;
145 case PCI_ROM_ADDRESS:
146 conf_data = PCI_EXPANSION_ROM_BAR;
147 break;
148 case PCI_CAPABILITY_LIST:
149 conf_data = PCI_CAPLIST_POINTER;
150 break;
151 case PCI_INTERRUPT_LINE:
152 conf_data =
153 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154 break;
155 case PCI_IDE_CFG_REG:
156 _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157 conf_data = lo;
158 break;
159 case PCI_IDE_DTC_REG:
160 _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161 conf_data = lo;
162 break;
163 case PCI_IDE_CAST_REG:
164 _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165 conf_data = lo;
166 break;
167 case PCI_IDE_ETC_REG:
168 _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169 conf_data = lo;
170 case PCI_IDE_PM_REG:
171 _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172 conf_data = lo;
173 break;
174 default:
175 break;
176 }
177
178 return conf_data;
179}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
new file mode 100644
index 000000000000..f5c0818831b2
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -0,0 +1,316 @@
1/*
2 * the ISA Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19/* common variables for PCI_ISA_READ/WRITE_BAR */
20static const u32 divil_msr_reg[6] = {
21 DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22 DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23 DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24};
25
26static const u32 soft_bar_flag[6] = {
27 SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28 SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29};
30
31static const u32 sb_msr_reg[6] = {
32 SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33 SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34};
35
36static const u32 bar_space_range[6] = {
37 CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38 CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39};
40
41static const int bar_space_len[6] = {
42 CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43 CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44};
45
46/*
47 * enable the divil module bar space.
48 *
49 * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50 * and the RCONFx(0~5) reg to use the modules.
51 */
52static void divil_lbar_enable(void)
53{
54 u32 hi, lo;
55 int offset;
56
57 /*
58 * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59 */
60
61 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63 hi |= 0x01;
64 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65 }
66}
67
68/*
69 * disable the divil module bar space.
70 */
71static void divil_lbar_disable(void)
72{
73 u32 hi, lo;
74 int offset;
75
76 for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77 _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78 hi &= ~0x01;
79 _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80 }
81}
82
83/*
84 * BAR write: write value to the n BAR
85 */
86
87void pci_isa_write_bar(int n, u32 value)
88{
89 u32 hi = 0, lo = value;
90
91 if (value == PCI_BAR_RANGE_MASK) {
92 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93 lo |= soft_bar_flag[n];
94 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95 } else if (value & 0x01) {
96 /* NATIVE reg */
97 hi = 0x0000f001;
98 lo &= bar_space_range[n];
99 _wrmsr(divil_msr_reg[n], hi, lo);
100
101 /* RCONFx is 4bytes in units for I/O space */
102 hi = ((value & 0x000ffffc) << 12) |
103 ((bar_space_len[n] - 4) << 12) | 0x01;
104 lo = ((value & 0x000ffffc) << 12) | 0x01;
105 _wrmsr(sb_msr_reg[n], hi, lo);
106 }
107}
108
109/*
110 * BAR read: read the n BAR
111 */
112
113u32 pci_isa_read_bar(int n)
114{
115 u32 conf_data = 0;
116 u32 hi, lo;
117
118 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119 if (lo & soft_bar_flag[n]) {
120 conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121 lo &= ~soft_bar_flag[n];
122 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123 } else {
124 _rdmsr(divil_msr_reg[n], &hi, &lo);
125 conf_data = lo & bar_space_range[n];
126 conf_data |= 0x01;
127 conf_data &= ~0x02;
128 }
129 return conf_data;
130}
131
132/*
133 * isa_write: ISA write transfer
134 *
135 * We assume that this is not a bus master transfer.
136 */
137void pci_isa_write_reg(int reg, u32 value)
138{
139 u32 hi = 0, lo = value;
140 u32 temp;
141
142 switch (reg) {
143 case PCI_COMMAND:
144 if (value & PCI_COMMAND_IO)
145 divil_lbar_enable();
146 else
147 divil_lbar_disable();
148 break;
149 case PCI_STATUS:
150 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151 temp = lo & 0x0000ffff;
152 if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153 (lo & SB_TAS_ERR_EN))
154 temp |= SB_TAS_ERR_FLAG;
155
156 if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157 (lo & SB_TAR_ERR_EN))
158 temp |= SB_TAR_ERR_FLAG;
159
160 if ((value & PCI_STATUS_REC_MASTER_ABORT)
161 && (lo & SB_MAR_ERR_EN))
162 temp |= SB_MAR_ERR_FLAG;
163
164 if ((value & PCI_STATUS_DETECTED_PARITY)
165 && (lo & SB_PARE_ERR_EN))
166 temp |= SB_PARE_ERR_FLAG;
167
168 lo = temp;
169 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170 break;
171 case PCI_CACHE_LINE_SIZE:
172 value &= 0x0000ff00;
173 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174 hi &= 0xffffff00;
175 hi |= (value >> 8);
176 _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177 break;
178 case PCI_BAR0_REG:
179 pci_isa_write_bar(0, value);
180 break;
181 case PCI_BAR1_REG:
182 pci_isa_write_bar(1, value);
183 break;
184 case PCI_BAR2_REG:
185 pci_isa_write_bar(2, value);
186 break;
187 case PCI_BAR3_REG:
188 pci_isa_write_bar(3, value);
189 break;
190 case PCI_BAR4_REG:
191 pci_isa_write_bar(4, value);
192 break;
193 case PCI_BAR5_REG:
194 pci_isa_write_bar(5, value);
195 break;
196 case PCI_UART1_INT_REG:
197 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198 /* disable uart1 interrupt in PIC */
199 lo &= ~(0xf << 24);
200 if (value) /* enable uart1 interrupt in PIC */
201 lo |= (CS5536_UART1_INTR << 24);
202 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203 break;
204 case PCI_UART2_INT_REG:
205 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206 /* disable uart2 interrupt in PIC */
207 lo &= ~(0xf << 28);
208 if (value) /* enable uart2 interrupt in PIC */
209 lo |= (CS5536_UART2_INTR << 28);
210 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211 break;
212 case PCI_ISA_FIXUP_REG:
213 if (value) {
214 /* enable the TARGET ABORT/MASTER ABORT etc. */
215 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216 lo |= 0x00000063;
217 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218 }
219
220 default:
221 /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222 break;
223 }
224}
225
226/*
227 * isa_read: ISA read transfers
228 *
229 * We assume that this is not a bus master transfer.
230 */
231u32 pci_isa_read_reg(int reg)
232{
233 u32 conf_data = 0;
234 u32 hi, lo;
235
236 switch (reg) {
237 case PCI_VENDOR_ID:
238 conf_data =
239 CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240 break;
241 case PCI_COMMAND:
242 /* we just check the first LBAR for the IO enable bit, */
243 /* maybe we should changed later. */
244 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245 if (hi & 0x01)
246 conf_data |= PCI_COMMAND_IO;
247 break;
248 case PCI_STATUS:
249 conf_data |= PCI_STATUS_66MHZ;
250 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251 conf_data |= PCI_STATUS_FAST_BACK;
252
253 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254 if (lo & SB_TAS_ERR_FLAG)
255 conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256 if (lo & SB_TAR_ERR_FLAG)
257 conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258 if (lo & SB_MAR_ERR_FLAG)
259 conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260 if (lo & SB_PARE_ERR_FLAG)
261 conf_data |= PCI_STATUS_DETECTED_PARITY;
262 break;
263 case PCI_CLASS_REVISION:
264 _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265 conf_data = lo & 0x000000ff;
266 conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267 break;
268 case PCI_CACHE_LINE_SIZE:
269 _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270 hi &= 0x000000f8;
271 conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272 break;
273 /*
274 * we only use the LBAR of DIVIL, no RCONF used.
275 * all of them are IO space.
276 */
277 case PCI_BAR0_REG:
278 return pci_isa_read_bar(0);
279 break;
280 case PCI_BAR1_REG:
281 return pci_isa_read_bar(1);
282 break;
283 case PCI_BAR2_REG:
284 return pci_isa_read_bar(2);
285 break;
286 case PCI_BAR3_REG:
287 break;
288 case PCI_BAR4_REG:
289 return pci_isa_read_bar(4);
290 break;
291 case PCI_BAR5_REG:
292 return pci_isa_read_bar(5);
293 break;
294 case PCI_CARDBUS_CIS:
295 conf_data = PCI_CARDBUS_CIS_POINTER;
296 break;
297 case PCI_SUBSYSTEM_VENDOR_ID:
298 conf_data =
299 CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300 break;
301 case PCI_ROM_ADDRESS:
302 conf_data = PCI_EXPANSION_ROM_BAR;
303 break;
304 case PCI_CAPABILITY_LIST:
305 conf_data = PCI_CAPLIST_POINTER;
306 break;
307 case PCI_INTERRUPT_LINE:
308 /* no interrupt used here */
309 conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310 break;
311 default:
312 break;
313 }
314
315 return conf_data;
316}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
new file mode 100644
index 000000000000..8c807c965199
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -0,0 +1,217 @@
1/*
2 * CS5536 General timer functions
3 *
4 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5 * Author: Yanhua, yanh@lemote.com
6 *
7 * Copyright (C) 2009 Lemote Inc.
8 * Author: Wu zhangjin, wuzhangjin@gmail.com
9 *
10 * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18#include <linux/io.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/jiffies.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/clockchips.h>
25
26#include <asm/time.h>
27
28#include <cs5536/cs5536_mfgpt.h>
29
30DEFINE_SPINLOCK(mfgpt_lock);
31EXPORT_SYMBOL(mfgpt_lock);
32
33static u32 mfgpt_base;
34
35/*
36 * Initialize the MFGPT timer.
37 *
38 * This is also called after resume to bring the MFGPT into operation again.
39 */
40
41/* disable counter */
42void disable_mfgpt0_counter(void)
43{
44 outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
45}
46EXPORT_SYMBOL(disable_mfgpt0_counter);
47
48/* enable counter, comparator2 to event mode, 14.318MHz clock */
49void enable_mfgpt0_counter(void)
50{
51 outw(0xe310, MFGPT0_SETUP);
52}
53EXPORT_SYMBOL(enable_mfgpt0_counter);
54
55static void init_mfgpt_timer(enum clock_event_mode mode,
56 struct clock_event_device *evt)
57{
58 spin_lock(&mfgpt_lock);
59
60 switch (mode) {
61 case CLOCK_EVT_MODE_PERIODIC:
62 outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
63 outw(0, MFGPT0_CNT); /* set counter to 0 */
64 enable_mfgpt0_counter();
65 break;
66
67 case CLOCK_EVT_MODE_SHUTDOWN:
68 case CLOCK_EVT_MODE_UNUSED:
69 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
70 evt->mode == CLOCK_EVT_MODE_ONESHOT)
71 disable_mfgpt0_counter();
72 break;
73
74 case CLOCK_EVT_MODE_ONESHOT:
75 /* The oneshot mode have very high deviation, Not use it! */
76 break;
77
78 case CLOCK_EVT_MODE_RESUME:
79 /* Nothing to do here */
80 break;
81 }
82 spin_unlock(&mfgpt_lock);
83}
84
85static struct clock_event_device mfgpt_clockevent = {
86 .name = "mfgpt",
87 .features = CLOCK_EVT_FEAT_PERIODIC,
88 .set_mode = init_mfgpt_timer,
89 .irq = CS5536_MFGPT_INTR,
90};
91
92static irqreturn_t timer_interrupt(int irq, void *dev_id)
93{
94 u32 basehi;
95
96 /*
97 * get MFGPT base address
98 *
99 * NOTE: do not remove me, it's need for the value of mfgpt_base is
100 * variable
101 */
102 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
103
104 /* ack */
105 outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
106
107 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
108
109 return IRQ_HANDLED;
110}
111
112static struct irqaction irq5 = {
113 .handler = timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
115 .name = "timer"
116};
117
118/*
119 * Initialize the conversion factor and the min/max deltas of the clock event
120 * structure and register the clock event source with the framework.
121 */
122void __init setup_mfgpt0_timer(void)
123{
124 u32 basehi;
125 struct clock_event_device *cd = &mfgpt_clockevent;
126 unsigned int cpu = smp_processor_id();
127
128 cd->cpumask = cpumask_of(cpu);
129 clockevent_set_clock(cd, MFGPT_TICK_RATE);
130 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
131 cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
132
133 /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
134 _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
135
136 /* Enable Interrupt Gate 5 */
137 _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
138
139 /* get MFGPT base address */
140 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
141
142 clockevents_register_device(cd);
143
144 setup_irq(CS5536_MFGPT_INTR, &irq5);
145}
146
147/*
148 * Since the MFGPT overflows every tick, its not very useful
149 * to just read by itself. So use jiffies to emulate a free
150 * running counter:
151 */
152static cycle_t mfgpt_read(struct clocksource *cs)
153{
154 unsigned long flags;
155 int count;
156 u32 jifs;
157 static int old_count;
158 static u32 old_jifs;
159
160 spin_lock_irqsave(&mfgpt_lock, flags);
161 /*
162 * Although our caller may have the read side of xtime_lock,
163 * this is now a seqlock, and we are cheating in this routine
164 * by having side effects on state that we cannot undo if
165 * there is a collision on the seqlock and our caller has to
166 * retry. (Namely, old_jifs and old_count.) So we must treat
167 * jiffies as volatile despite the lock. We read jiffies
168 * before latching the timer count to guarantee that although
169 * the jiffies value might be older than the count (that is,
170 * the counter may underflow between the last point where
171 * jiffies was incremented and the point where we latch the
172 * count), it cannot be newer.
173 */
174 jifs = jiffies;
175 /* read the count */
176 count = inw(MFGPT0_CNT);
177
178 /*
179 * It's possible for count to appear to go the wrong way for this
180 * reason:
181 *
182 * The timer counter underflows, but we haven't handled the resulting
183 * interrupt and incremented jiffies yet.
184 *
185 * Previous attempts to handle these cases intelligently were buggy, so
186 * we just do the simple thing now.
187 */
188 if (count < old_count && jifs == old_jifs)
189 count = old_count;
190
191 old_count = count;
192 old_jifs = jifs;
193
194 spin_unlock_irqrestore(&mfgpt_lock, flags);
195
196 return (cycle_t) (jifs * COMPARE) + count;
197}
198
199static struct clocksource clocksource_mfgpt = {
200 .name = "mfgpt",
201 .rating = 120, /* Functional for real use, but not desired */
202 .read = mfgpt_read,
203 .mask = CLOCKSOURCE_MASK(32),
204 .mult = 0,
205 .shift = 22,
206};
207
208int __init init_mfgpt_clocksource(void)
209{
210 if (num_possible_cpus() > 1) /* MFGPT does not scale! */
211 return 0;
212
213 clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
214 return clocksource_register(&clocksource_mfgpt);
215}
216
217arch_initcall(init_mfgpt_clocksource);
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
new file mode 100644
index 000000000000..db5900aadd6b
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -0,0 +1,147 @@
1/*
2 * the OHCI Virtual Support Module of AMD CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <cs5536/cs5536.h>
17#include <cs5536/cs5536_pci.h>
18
19void pci_ohci_write_reg(int reg, u32 value)
20{
21 u32 hi = 0, lo = value;
22
23 switch (reg) {
24 case PCI_COMMAND:
25 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26 if (value & PCI_COMMAND_MASTER)
27 hi |= PCI_COMMAND_MASTER;
28 else
29 hi &= ~PCI_COMMAND_MASTER;
30
31 if (value & PCI_COMMAND_MEMORY)
32 hi |= PCI_COMMAND_MEMORY;
33 else
34 hi &= ~PCI_COMMAND_MEMORY;
35 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36 break;
37 case PCI_STATUS:
38 if (value & PCI_STATUS_PARITY) {
39 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40 if (lo & SB_PARE_ERR_FLAG) {
41 lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42 _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43 }
44 }
45 break;
46 case PCI_BAR0_REG:
47 if (value == PCI_BAR_RANGE_MASK) {
48 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49 lo |= SOFT_BAR_OHCI_FLAG;
50 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51 } else if ((value & 0x01) == 0x00) {
52 _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53
54 value &= 0xfffffff0;
55 hi = 0x40000000 | ((value & 0xff000000) >> 24);
56 lo = 0x000fffff | ((value & 0x00fff000) << 8);
57 _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58 }
59 break;
60 case PCI_OHCI_INT_REG:
61 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62 lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63 if (value) /* enable all the usb interrupt in PIC */
64 lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65 _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66 break;
67 default:
68 break;
69 }
70}
71
72u32 pci_ohci_read_reg(int reg)
73{
74 u32 conf_data = 0;
75 u32 hi, lo;
76
77 switch (reg) {
78 case PCI_VENDOR_ID:
79 conf_data =
80 CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81 break;
82 case PCI_COMMAND:
83 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84 if (hi & PCI_COMMAND_MASTER)
85 conf_data |= PCI_COMMAND_MASTER;
86 if (hi & PCI_COMMAND_MEMORY)
87 conf_data |= PCI_COMMAND_MEMORY;
88 break;
89 case PCI_STATUS:
90 conf_data |= PCI_STATUS_66MHZ;
91 conf_data |= PCI_STATUS_FAST_BACK;
92 _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93 if (lo & SB_PARE_ERR_FLAG)
94 conf_data |= PCI_STATUS_PARITY;
95 conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96 break;
97 case PCI_CLASS_REVISION:
98 _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99 conf_data = lo & 0x000000ff;
100 conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101 break;
102 case PCI_CACHE_LINE_SIZE:
103 conf_data =
104 CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105 PCI_NORMAL_LATENCY_TIMER);
106 break;
107 case PCI_BAR0_REG:
108 _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109 if (lo & SOFT_BAR_OHCI_FLAG) {
110 conf_data = CS5536_OHCI_RANGE |
111 PCI_BASE_ADDRESS_SPACE_MEMORY;
112 lo &= ~SOFT_BAR_OHCI_FLAG;
113 _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114 } else {
115 _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116 conf_data = lo & 0xffffff00;
117 conf_data &= ~0x0000000f; /* 32bit mem */
118 }
119 break;
120 case PCI_CARDBUS_CIS:
121 conf_data = PCI_CARDBUS_CIS_POINTER;
122 break;
123 case PCI_SUBSYSTEM_VENDOR_ID:
124 conf_data =
125 CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126 break;
127 case PCI_ROM_ADDRESS:
128 conf_data = PCI_EXPANSION_ROM_BAR;
129 break;
130 case PCI_CAPABILITY_LIST:
131 conf_data = PCI_CAPLIST_USB_POINTER;
132 break;
133 case PCI_INTERRUPT_LINE:
134 conf_data =
135 CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136 break;
137 case PCI_OHCI_INT_REG:
138 _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139 if ((lo & 0x00000f00) == CS5536_USB_INTR)
140 conf_data = 1;
141 break;
142 default:
143 break;
144 }
145
146 return conf_data;
147}
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
new file mode 100644
index 000000000000..6dfeab11af08
--- /dev/null
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -0,0 +1,87 @@
1/*
2 * read/write operation to the PCI config space of CS5536
3 *
4 * Copyright (C) 2007 Lemote, Inc.
5 * Author : jlliu, liujl@lemote.com
6 *
7 * Copyright (C) 2009 Lemote, Inc.
8 * Author: Wu Zhangjin, wuzhangjin@gmail.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * the Virtual Support Module(VSM) for virtulizing the PCI
16 * configure space are defined in cs5536_modulename.c respectively,
17 *
18 * after this virtulizing, user can access the PCI configure space
19 * directly as a normal multi-function PCI device which follows
20 * the PCI-2.2 spec.
21 */
22
23#include <linux/types.h>
24#include <cs5536/cs5536_vsm.h>
25
26enum {
27 CS5536_FUNC_START = -1,
28 CS5536_ISA_FUNC,
29 reserved_func,
30 CS5536_IDE_FUNC,
31 CS5536_ACC_FUNC,
32 CS5536_OHCI_FUNC,
33 CS5536_EHCI_FUNC,
34 CS5536_FUNC_END,
35};
36
37static const cs5536_pci_vsm_write vsm_conf_write[] = {
38 [CS5536_ISA_FUNC] pci_isa_write_reg,
39 [reserved_func] NULL,
40 [CS5536_IDE_FUNC] pci_ide_write_reg,
41 [CS5536_ACC_FUNC] pci_acc_write_reg,
42 [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43 [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44};
45
46static const cs5536_pci_vsm_read vsm_conf_read[] = {
47 [CS5536_ISA_FUNC] pci_isa_read_reg,
48 [reserved_func] NULL,
49 [CS5536_IDE_FUNC] pci_ide_read_reg,
50 [CS5536_ACC_FUNC] pci_acc_read_reg,
51 [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52 [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53};
54
55/*
56 * write to PCI config space and transfer it to MSR write.
57 */
58void cs5536_pci_conf_write4(int function, int reg, u32 value)
59{
60 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61 return;
62 if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63 return;
64
65 if (vsm_conf_write[function] != NULL)
66 vsm_conf_write[function](reg, value);
67}
68
69/*
70 * read PCI config space and transfer it to MSR access.
71 */
72u32 cs5536_pci_conf_read4(int function, int reg)
73{
74 u32 data = 0;
75
76 if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77 return 0;
78 if ((reg < 0) || ((reg & 0x03) != 0))
79 return 0;
80 if (reg > 0x100)
81 return 0xffffffff;
82
83 if (vsm_conf_read[function] != NULL)
84 data = vsm_conf_read[function](reg);
85
86 return data;
87}
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index bc73edc0cfd8..a71736f00443 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -1,8 +1,8 @@
1/* early printk support 1/* early printk support
2 * 2 *
3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca> 3 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 4 * Copyright (c) 2009 Lemote Inc.
5 * Author: Wu Zhangjin, wuzj@lemote.com 5 * Author: Wu Zhangjin, wuzhangjin@gmail.com
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the 8 * under the terms of the GNU General Public License as published by the
@@ -12,26 +12,29 @@
12#include <linux/serial_reg.h> 12#include <linux/serial_reg.h>
13 13
14#include <loongson.h> 14#include <loongson.h>
15#include <machine.h>
16 15
17#define PORT(base, offset) (u8 *)(base + offset) 16#define PORT(base, offset) (u8 *)(base + offset)
18 17
19static inline unsigned int serial_in(phys_addr_t base, int offset) 18static inline unsigned int serial_in(unsigned char *base, int offset)
20{ 19{
21 return readb(PORT(base, offset)); 20 return readb(PORT(base, offset));
22} 21}
23 22
24static inline void serial_out(phys_addr_t base, int offset, int value) 23static inline void serial_out(unsigned char *base, int offset, int value)
25{ 24{
26 writeb(value, PORT(base, offset)); 25 writeb(value, PORT(base, offset));
27} 26}
28 27
29void prom_putchar(char c) 28void prom_putchar(char c)
30{ 29{
31 phys_addr_t uart_base = 30 int timeout;
32 (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); 31 unsigned char *uart_base;
33 32
34 while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) 33 uart_base = (unsigned char *)_loongson_uart_base;
34 timeout = 1024;
35
36 while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
37 (timeout-- > 0))
35 ; 38 ;
36 39
37 serial_out(uart_base, UART_TX, c); 40 serial_out(uart_base, UART_TX, c);
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index b9ef50385541..ae4cff97a56c 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -9,24 +9,24 @@
9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology 9 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
10 * Author: Fuxin Zhang, zhangfx@lemote.com 10 * Author: Fuxin Zhang, zhangfx@lemote.com
11 * 11 *
12 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 12 * Copyright (C) 2009 Lemote Inc.
13 * Author: Wu Zhangjin, wuzj@lemote.com 13 * Author: Wu Zhangjin, wuzhangjin@gmail.com
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the 16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your 17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version. 18 * option) any later version.
19 */ 19 */
20#include <linux/module.h>
21
20#include <asm/bootinfo.h> 22#include <asm/bootinfo.h>
21 23
22#include <loongson.h> 24#include <loongson.h>
23 25
24unsigned long bus_clock, cpu_clock_freq; 26unsigned long cpu_clock_freq;
27EXPORT_SYMBOL(cpu_clock_freq);
25unsigned long memsize, highmemsize; 28unsigned long memsize, highmemsize;
26 29
27/* pmon passes arguments in 32bit pointers */
28int *_prom_envp;
29
30#define parse_even_earlier(res, option, p) \ 30#define parse_even_earlier(res, option, p) \
31do { \ 31do { \
32 if (strncmp(option, (char *)p, strlen(option)) == 0) \ 32 if (strncmp(option, (char *)p, strlen(option)) == 0) \
@@ -36,6 +36,10 @@ do { \
36 36
37void __init prom_init_env(void) 37void __init prom_init_env(void)
38{ 38{
39 /* pmon passes arguments in 32bit pointers */
40 int *_prom_envp;
41 unsigned long bus_clock;
42 unsigned int processor_id;
39 long l; 43 long l;
40 44
41 /* firmware arguments are initialized in head.S */ 45 /* firmware arguments are initialized in head.S */
@@ -52,6 +56,22 @@ void __init prom_init_env(void)
52 } 56 }
53 if (memsize == 0) 57 if (memsize == 0)
54 memsize = 256; 58 memsize = 256;
59 if (bus_clock == 0)
60 bus_clock = 66000000;
61 if (cpu_clock_freq == 0) {
62 processor_id = (&current_cpu_data)->processor_id;
63 switch (processor_id & PRID_REV_MASK) {
64 case PRID_REV_LOONGSON2E:
65 cpu_clock_freq = 533080000;
66 break;
67 case PRID_REV_LOONGSON2F:
68 cpu_clock_freq = 797000000;
69 break;
70 default:
71 cpu_clock_freq = 100000000;
72 break;
73 }
74 }
55 75
56 pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", 76 pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n",
57 bus_clock, cpu_clock_freq, memsize, highmemsize); 77 bus_clock, cpu_clock_freq, memsize, highmemsize);
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..19d341591254 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com 3 * Author: Wu Zhangjin, wuzhangjin@gmail.com
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -10,19 +10,28 @@
10 10
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12 12
13#include <asm/bootinfo.h>
14
15#include <loongson.h> 13#include <loongson.h>
16 14
15/* Loongson CPU address windows config space base address */
16unsigned long __maybe_unused _loongson_addrwincfg_base;
17
17void __init prom_init(void) 18void __init prom_init(void)
18{ 19{
19 /* init base address of io space */ 20 /* init base address of io space */
20 set_io_port_base((unsigned long) 21 set_io_port_base((unsigned long)
21 ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); 22 ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
23
24#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
25 _loongson_addrwincfg_base = (unsigned long)
26 ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
27#endif
22 28
23 prom_init_cmdline(); 29 prom_init_cmdline();
24 prom_init_env(); 30 prom_init_env();
25 prom_init_memory(); 31 prom_init_memory();
32
33 /*init the uart base address */
34 prom_init_uart_base();
26} 35}
27 36
28void __init prom_free_prom_memory(void) 37void __init prom_free_prom_memory(void)
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index b32b4a3e5137..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
20 int i; 20 int i;
21 21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */ 22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = BONITO_INTISR; 23 int_status = LOONGSON_INTISR;
24 if (int_status & (1 << 10)) { 24 if (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) { 25 while (int_status & (1 << 10)) {
26 udelay(1); 26 udelay(1);
27 int_status = BONITO_INTISR; 27 int_status = LOONGSON_INTISR;
28 } 28 }
29 } 29 }
30 30
31 /* Get pending sources, masked by current enables */ 31 /* Get pending sources, masked by current enables */
32 int_status = BONITO_INTISR & BONITO_INTEN; 32 int_status = LOONGSON_INTISR & LOONGSON_INTEN;
33 33
34 if (int_status != 0) { 34 if (int_status != 0) {
35 i = __ffs(int_status); 35 i = __ffs(int_status);
36 int_status &= ~(1 << i); 36 int_status &= ~(1 << i);
37 do_IRQ(BONITO_IRQ_BASE + i); 37 do_IRQ(LOONGSON_IRQ_BASE + i);
38 } 38 }
39} 39}
40 40
@@ -60,13 +60,13 @@ void __init arch_init_irq(void)
60 set_irq_trigger_mode(); 60 set_irq_trigger_mode();
61 61
62 /* no steer */ 62 /* no steer */
63 BONITO_INTSTEER = 0; 63 LOONGSON_INTSTEER = 0;
64 64
65 /* 65 /*
66 * Mask out all interrupt by writing "1" to all bit position in 66 * Mask out all interrupt by writing "1" to all bit position in
67 * the interrupt reset reg. 67 * the interrupt reset reg.
68 */ 68 */
69 BONITO_INTENCLR = ~0; 69 LOONGSON_INTENCLR = ~0;
70 70
71 /* machine specific irq init */ 71 /* machine specific irq init */
72 mach_init_irq(); 72 mach_init_irq();
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 7b348248de7d..81fbe6b73f91 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzj@lemote.com 3 * Author: Wu Zhangjin, wuzhangjin@gmail.com
4 * 4 *
5 * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org> 5 * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org>
6 * 6 *
@@ -15,36 +15,51 @@
15#include <loongson.h> 15#include <loongson.h>
16#include <machine.h> 16#include <machine.h>
17 17
18/* please ensure the length of the machtype string is less than 50 */
19#define MACHTYPE_LEN 50
20
18static const char *system_types[] = { 21static const char *system_types[] = {
19 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", 22 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine",
20 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", 23 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box",
21 [MACH_LEMOTE_FL2F] "lemote-fuloong-2f-box", 24 [MACH_LEMOTE_FL2F] "lemote-fuloong-2f-box",
22 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches", 25 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches",
23 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", 26 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches",
24 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches", 27 [MACH_DEXXON_GDIUM2F10] "dexxon-gdium-2f",
28 [MACH_LEMOTE_NAS] "lemote-nas-2f",
29 [MACH_LEMOTE_LL2F] "lemote-lynloong-2f",
25 [MACH_LOONGSON_END] NULL, 30 [MACH_LOONGSON_END] NULL,
26}; 31};
27 32
28const char *get_system_type(void) 33const char *get_system_type(void)
29{ 34{
30 if (mips_machtype == MACH_UNKNOWN)
31 mips_machtype = LOONGSON_MACHTYPE;
32
33 return system_types[mips_machtype]; 35 return system_types[mips_machtype];
34} 36}
35 37
36static __init int machtype_setup(char *str) 38void __weak __init mach_prom_init_machtype(void)
39{
40}
41
42void __init prom_init_machtype(void)
37{ 43{
44 char *p, str[MACHTYPE_LEN];
38 int machtype = MACH_LEMOTE_FL2E; 45 int machtype = MACH_LEMOTE_FL2E;
39 46
40 if (!str) 47 mips_machtype = LOONGSON_MACHTYPE;
41 return -EINVAL; 48
49 p = strstr(arcs_cmdline, "machtype=");
50 if (!p) {
51 mach_prom_init_machtype();
52 return;
53 }
54 p += strlen("machtype=");
55 strncpy(str, p, MACHTYPE_LEN);
56 p = strstr(str, " ");
57 if (p)
58 *p = '\0';
42 59
43 for (; system_types[machtype]; machtype++) 60 for (; system_types[machtype]; machtype++)
44 if (strstr(system_types[machtype], str)) { 61 if (strstr(system_types[machtype], str)) {
45 mips_machtype = machtype; 62 mips_machtype = machtype;
46 break; 63 break;
47 } 64 }
48 return 0;
49} 65}
50__setup("machtype=", machtype_setup);
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index 7c92f79b6480..30eba6001205 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -12,24 +12,108 @@
12 12
13#include <loongson.h> 13#include <loongson.h>
14#include <mem.h> 14#include <mem.h>
15#include <pci.h>
15 16
16void __init prom_init_memory(void) 17void __init prom_init_memory(void)
17{ 18{
18 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); 19 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
20
21 add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
22 20), BOOT_MEM_RESERVED);
23
24#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
25 {
26 int bit;
27
28 bit = fls(memsize + highmemsize);
29 if (bit != ffs(memsize + highmemsize))
30 bit += 20;
31 else
32 bit = bit + 20 - 1;
33
34 /* set cpu window3 to map CPU to DDR: 2G -> 2G */
35 LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
36 0x80000000ul, (1 << bit));
37 mmiowb();
38 }
39#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
40
19#ifdef CONFIG_64BIT 41#ifdef CONFIG_64BIT
20 if (highmemsize > 0) 42 if (highmemsize > 0)
21 add_memory_region(LOONGSON_HIGHMEM_START, 43 add_memory_region(LOONGSON_HIGHMEM_START,
22 highmemsize << 20, BOOT_MEM_RAM); 44 highmemsize << 20, BOOT_MEM_RAM);
23#endif /* CONFIG_64BIT */ 45
46 add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
47 LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
48
49#endif /* !CONFIG_64BIT */
24} 50}
25 51
26/* override of arch/mips/mm/cache.c: __uncached_access */ 52/* override of arch/mips/mm/cache.c: __uncached_access */
27int __uncached_access(struct file *file, unsigned long addr) 53int __uncached_access(struct file *file, unsigned long addr)
28{ 54{
29 if (file->f_flags & O_SYNC) 55 if (file->f_flags & O_DSYNC)
30 return 1; 56 return 1;
31 57
32 return addr >= __pa(high_memory) || 58 return addr >= __pa(high_memory) ||
33 ((addr >= LOONGSON_MMIO_MEM_START) && 59 ((addr >= LOONGSON_MMIO_MEM_START) &&
34 (addr < LOONGSON_MMIO_MEM_END)); 60 (addr < LOONGSON_MMIO_MEM_END));
35} 61}
62
63#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
64
65#include <linux/pci.h>
66#include <linux/sched.h>
67#include <asm/current.h>
68
69static unsigned long uca_start, uca_end;
70
71pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
72 unsigned long size, pgprot_t vma_prot)
73{
74 unsigned long offset = pfn << PAGE_SHIFT;
75 unsigned long end = offset + size;
76
77 if (__uncached_access(file, offset)) {
78 if (uca_start && (offset >= uca_start) &&
79 (end <= uca_end))
80 return __pgprot((pgprot_val(vma_prot) &
81 ~_CACHE_MASK) |
82 _CACHE_UNCACHED_ACCELERATED);
83 else
84 return pgprot_noncached(vma_prot);
85 }
86 return vma_prot;
87}
88
89static int __init find_vga_mem_init(void)
90{
91 struct pci_dev *dev = 0;
92 struct resource *r;
93 int idx;
94
95 if (uca_start)
96 return 0;
97
98 for_each_pci_dev(dev) {
99 if ((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
100 for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
101 r = &dev->resource[idx];
102 if (!r->start && r->end)
103 continue;
104 if (r->flags & IORESOURCE_IO)
105 continue;
106 if (r->flags & IORESOURCE_MEM) {
107 uca_start = r->start;
108 uca_end = r->end;
109 return 0;
110 }
111 }
112 }
113 }
114
115 return 0;
116}
117
118late_initcall(find_vga_mem_init);
119#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..31d8c5ecd16c 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
27}; 27};
28 28
29static struct pci_controller loongson_pci_controller = { 29static struct pci_controller loongson_pci_controller = {
30 .pci_ops = &bonito64_pci_ops, 30 .pci_ops = &loongson_pci_ops,
31 .io_resource = &loongson_pci_io_resource, 31 .io_resource = &loongson_pci_io_resource,
32 .mem_resource = &loongson_pci_mem_resource, 32 .mem_resource = &loongson_pci_mem_resource,
33 .mem_offset = 0x00000000UL, 33 .mem_offset = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
45 * [<2G] [384M,448M] [320M,384M] [0M,64M] 45 * [<2G] [384M,448M] [320M,384M] [0M,64M]
46 */ 46 */
47 BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | 47 LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
48 BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | 48 LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
49 BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | 49 LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
50 BONITO_PCIMAP_WIN(0, 0); 50 LOONGSON_PCIMAP_WIN(0, 0);
51 51
52 /* 52 /*
53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] 53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
54 */ 54 */
55 BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ 55 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */ 56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; 57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; 58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void)
67 /* can not change gnt to break pci transfer when device's gnt not 67 /* can not change gnt to break pci transfer when device's gnt not
68 deassert for some broken device */ 68 deassert for some broken device */
69 LOONGSON_PXARB_CFG = 0x00fe0105ul; 69 LOONGSON_PXARB_CFG = 0x00fe0105ul;
70
71#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
72 /*
73 * set cpu addr window2 to map CPU address space to PCI address space
74 */
75 LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
76 LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
77#endif
70} 78}
71 79
72static int __init pcibios_init(void) 80static int __init pcibios_init(void)
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
new file mode 100644
index 000000000000..ed007a2e0e1f
--- /dev/null
+++ b/arch/mips/loongson/common/platform.c
@@ -0,0 +1,30 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzhangjin@gmail.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/err.h>
12#include <linux/platform_device.h>
13
14static struct platform_device loongson2_cpufreq_device = {
15 .name = "loongson2_cpufreq",
16 .id = -1,
17};
18
19static int __init loongson2_cpufreq_init(void)
20{
21 struct cpuinfo_mips *c = &current_cpu_data;
22
23 /* Only 2F revision and it's successors support CPUFreq */
24 if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
25 return platform_device_register(&loongson2_cpufreq_device);
26
27 return -ENODEV;
28}
29
30arch_initcall(loongson2_cpufreq_init);
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
new file mode 100644
index 000000000000..6c1fd9001712
--- /dev/null
+++ b/arch/mips/loongson/common/pm.c
@@ -0,0 +1,161 @@
1/*
2 * loongson-specific suspend support
3 *
4 * Copyright (C) 2009 Lemote Inc.
5 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/suspend.h>
13#include <linux/interrupt.h>
14#include <linux/pm.h>
15
16#include <asm/i8259.h>
17#include <asm/mipsregs.h>
18
19#include <loongson.h>
20
21static unsigned int __maybe_unused cached_master_mask; /* i8259A */
22static unsigned int __maybe_unused cached_slave_mask;
23static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
24
25void arch_suspend_disable_irqs(void)
26{
27 /* disable all mips events */
28 local_irq_disable();
29
30#ifdef CONFIG_I8259
31 /* disable all events of i8259A */
32 cached_slave_mask = inb(PIC_SLAVE_IMR);
33 cached_master_mask = inb(PIC_MASTER_IMR);
34
35 outb(0xff, PIC_SLAVE_IMR);
36 inb(PIC_SLAVE_IMR);
37 outb(0xff, PIC_MASTER_IMR);
38 inb(PIC_MASTER_IMR);
39#endif
40 /* disable all events of bonito */
41 cached_bonito_irq_mask = LOONGSON_INTEN;
42 LOONGSON_INTENCLR = 0xffff;
43 (void)LOONGSON_INTENCLR;
44}
45
46void arch_suspend_enable_irqs(void)
47{
48 /* enable all mips events */
49 local_irq_enable();
50#ifdef CONFIG_I8259
51 /* only enable the cached events of i8259A */
52 outb(cached_slave_mask, PIC_SLAVE_IMR);
53 outb(cached_master_mask, PIC_MASTER_IMR);
54#endif
55 /* enable all cached events of bonito */
56 LOONGSON_INTENSET = cached_bonito_irq_mask;
57 (void)LOONGSON_INTENSET;
58}
59
60/*
61 * Setup the board-specific events for waking up loongson from wait mode
62 */
63void __weak setup_wakeup_events(void)
64{
65}
66
67/*
68 * Check wakeup events
69 */
70int __weak wakeup_loongson(void)
71{
72 return 1;
73}
74
75/*
76 * If the events are really what we want to wakeup the CPU, wake it up
77 * otherwise put the CPU asleep again.
78 */
79static void wait_for_wakeup_events(void)
80{
81 while (!wakeup_loongson())
82 LOONGSON_CHIPCFG0 &= ~0x7;
83}
84
85/*
86 * Stop all perf counters
87 *
88 * $24 is the control register of Loongson perf counter
89 */
90static inline void stop_perf_counters(void)
91{
92 __write_64bit_c0_register($24, 0, 0);
93}
94
95
96static void loongson_suspend_enter(void)
97{
98 static unsigned int cached_cpu_freq;
99
100 /* setup wakeup events via enabling the IRQs */
101 setup_wakeup_events();
102
103 stop_perf_counters();
104
105 cached_cpu_freq = LOONGSON_CHIPCFG0;
106
107 /* Put CPU into wait mode */
108 LOONGSON_CHIPCFG0 &= ~0x7;
109
110 /* wait for the given events to wakeup cpu from wait mode */
111 wait_for_wakeup_events();
112
113 LOONGSON_CHIPCFG0 = cached_cpu_freq;
114 mmiowb();
115}
116
117void __weak mach_suspend(void)
118{
119}
120
121void __weak mach_resume(void)
122{
123}
124
125static int loongson_pm_enter(suspend_state_t state)
126{
127 mach_suspend();
128
129 /* processor specific suspend */
130 loongson_suspend_enter();
131
132 mach_resume();
133
134 return 0;
135}
136
137static int loongson_pm_valid_state(suspend_state_t state)
138{
139 switch (state) {
140 case PM_SUSPEND_ON:
141 case PM_SUSPEND_STANDBY:
142 case PM_SUSPEND_MEM:
143 return 1;
144
145 default:
146 return 0;
147 }
148}
149
150static struct platform_suspend_ops loongson_pm_ops = {
151 .valid = loongson_pm_valid_state,
152 .enter = loongson_pm_enter,
153};
154
155static int __init loongson_pm_init(void)
156{
157 suspend_set_ops(&loongson_pm_ops);
158
159 return 0;
160}
161arch_initcall(loongson_pm_init);
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..9e10d6225d9b 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -6,8 +6,8 @@
6 * 6 *
7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology 7 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
8 * Author: Fuxin Zhang, zhangfx@lemote.com 8 * Author: Fuxin Zhang, zhangfx@lemote.com
9 * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology 9 * Copyright (C) 2009 Lemote, Inc.
10 * Author: Zhangjin Wu, wuzj@lemote.com 10 * Author: Zhangjin Wu, wuzhangjin@gmail.com
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/pm.h> 13#include <linux/pm.h>
@@ -16,27 +16,53 @@
16 16
17#include <loongson.h> 17#include <loongson.h>
18 18
19static inline void loongson_reboot(void)
20{
21#ifndef CONFIG_CPU_JUMP_WORKAROUNDS
22 ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
23#else
24 void (*func)(void);
25
26 func = (void *)ioremap_nocache(LOONGSON_BOOT_BASE, 4);
27
28 __asm__ __volatile__(
29 " .set noat \n"
30 " jr %[func] \n"
31 " .set at \n"
32 : /* No outputs */
33 : [func] "r" (func));
34#endif
35}
36
19static void loongson_restart(char *command) 37static void loongson_restart(char *command)
20{ 38{
21 /* do preparation for reboot */ 39 /* do preparation for reboot */
22 mach_prepare_reboot(); 40 mach_prepare_reboot();
23 41
24 /* reboot via jumping to boot base address */ 42 /* reboot via jumping to boot base address */
25 ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); 43 loongson_reboot();
26} 44}
27 45
28static void loongson_halt(void) 46static void loongson_poweroff(void)
29{ 47{
30 mach_prepare_shutdown(); 48 mach_prepare_shutdown();
31 while (1) 49 unreachable();
32 ; 50}
51
52static void loongson_halt(void)
53{
54 pr_notice("\n\n** You can safely turn off the power now **\n\n");
55 while (1) {
56 if (cpu_wait)
57 cpu_wait();
58 }
33} 59}
34 60
35static int __init mips_reboot_setup(void) 61static int __init mips_reboot_setup(void)
36{ 62{
37 _machine_restart = loongson_restart; 63 _machine_restart = loongson_restart;
38 _machine_halt = loongson_halt; 64 _machine_halt = loongson_halt;
39 pm_power_off = loongson_halt; 65 pm_power_off = loongson_poweroff;
40 66
41 return 0; 67 return 0;
42} 68}
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
new file mode 100644
index 000000000000..7580873143c8
--- /dev/null
+++ b/arch/mips/loongson/common/serial.c
@@ -0,0 +1,76 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * Copyright (C) 2009 Lemote, Inc.
9 * Author: Yan hua (yanhua@lemote.com)
10 * Author: Wu Zhangjin (wuzhangjin@gmail.com)
11 */
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/serial_8250.h>
16
17#include <asm/bootinfo.h>
18
19#include <loongson.h>
20#include <machine.h>
21
22#define PORT(int) \
23{ \
24 .irq = int, \
25 .uartclk = 1843200, \
26 .iotype = UPIO_PORT, \
27 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
28 .regshift = 0, \
29}
30
31#define PORT_M(int) \
32{ \
33 .irq = MIPS_CPU_IRQ_BASE + (int), \
34 .uartclk = 3686400, \
35 .iotype = UPIO_MEM, \
36 .membase = (void __iomem *)NULL, \
37 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
38 .regshift = 0, \
39}
40
41static struct plat_serial8250_port uart8250_data[][2] = {
42 [MACH_LOONGSON_UNKNOWN] {},
43 [MACH_LEMOTE_FL2E] {PORT(4), {} },
44 [MACH_LEMOTE_FL2F] {PORT(3), {} },
45 [MACH_LEMOTE_ML2F7] {PORT_M(3), {} },
46 [MACH_LEMOTE_YL2F89] {PORT_M(3), {} },
47 [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} },
48 [MACH_LEMOTE_NAS] {PORT_M(3), {} },
49 [MACH_LEMOTE_LL2F] {PORT(3), {} },
50 [MACH_LOONGSON_END] {},
51};
52
53static struct platform_device uart8250_device = {
54 .name = "serial8250",
55 .id = PLAT8250_DEV_PLATFORM,
56};
57
58static int __init serial_init(void)
59{
60 unsigned char iotype;
61
62 iotype = uart8250_data[mips_machtype][0].iotype;
63
64 if (UPIO_MEM == iotype)
65 uart8250_data[mips_machtype][0].membase =
66 (void __iomem *)_loongson_uart_base;
67 else if (UPIO_PORT == iotype)
68 uart8250_data[mips_machtype][0].iobase =
69 loongson_uart_base - LOONGSON_PCIIO_BASE;
70
71 uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
72
73 return platform_device_register(&uart8250_device);
74}
75
76device_initcall(serial_init);
diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c
index 4cd2aa9a342c..27d826bc7103 100644
--- a/arch/mips/loongson/common/setup.c
+++ b/arch/mips/loongson/common/setup.c
@@ -41,15 +41,12 @@ void __init plat_mem_setup(void)
41 conswitchp = &vga_con; 41 conswitchp = &vga_con;
42 42
43 screen_info = (struct screen_info) { 43 screen_info = (struct screen_info) {
44 0, 25, /* orig-x, orig-y */ 44 .orig_x = 0,
45 0, /* unused */ 45 .orig_y = 25,
46 0, /* orig-video-page */ 46 .orig_video_cols = 80,
47 0, /* orig-video-mode */ 47 .orig_video_lines = 25,
48 80, /* orig-video-cols */ 48 .orig_video_isVGA = VIDEO_TYPE_VGAC,
49 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ 49 .orig_video_points = 16,
50 25, /* orig-video-lines */
51 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
52 16 /* orig-video-points */
53 }; 50 };
54#elif defined(CONFIG_DUMMY_CONSOLE) 51#elif defined(CONFIG_DUMMY_CONSOLE)
55 conswitchp = &dummy_con; 52 conswitchp = &dummy_con;
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 6e08c8270abe..9fdd01f6c56a 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -2,8 +2,8 @@
2 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology 2 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
3 * Author: Fuxin Zhang, zhangfx@lemote.com 3 * Author: Fuxin Zhang, zhangfx@lemote.com
4 * 4 *
5 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology 5 * Copyright (C) 2009 Lemote Inc.
6 * Author: Wu Zhangjin, wuzj@lemote.com 6 * Author: Wu Zhangjin, wuzhangjin@gmail.com
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -14,11 +14,14 @@
14#include <asm/time.h> 14#include <asm/time.h>
15 15
16#include <loongson.h> 16#include <loongson.h>
17#include <cs5536/cs5536_mfgpt.h>
17 18
18void __init plat_time_init(void) 19void __init plat_time_init(void)
19{ 20{
20 /* setup mips r4k timer */ 21 /* setup mips r4k timer */
21 mips_hpt_frequency = cpu_clock_freq / 2; 22 mips_hpt_frequency = cpu_clock_freq / 2;
23
24 setup_mfgpt0_timer();
22} 25}
23 26
24void read_persistent_clock(struct timespec *ts) 27void read_persistent_clock(struct timespec *ts)
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
new file mode 100644
index 000000000000..d69ea54bc3d1
--- /dev/null
+++ b/arch/mips/loongson/common/uart_base.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2009 Lemote Inc.
3 * Author: Wu Zhangjin, wuzhangjin@gmail.com
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/module.h>
12#include <asm/bootinfo.h>
13
14#include <loongson.h>
15
16/* ioremapped */
17unsigned long _loongson_uart_base;
18EXPORT_SYMBOL(_loongson_uart_base);
19/* raw */
20unsigned long loongson_uart_base;
21EXPORT_SYMBOL(loongson_uart_base);
22
23void prom_init_loongson_uart_base(void)
24{
25 switch (mips_machtype) {
26 case MACH_LEMOTE_FL2E:
27 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
28 break;
29 case MACH_LEMOTE_FL2F:
30 case MACH_LEMOTE_LL2F:
31 loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
32 break;
33 case MACH_LEMOTE_ML2F7:
34 case MACH_LEMOTE_YL2F89:
35 case MACH_DEXXON_GDIUM2F10:
36 case MACH_LEMOTE_NAS:
37 default:
38 /* The CPU provided serial port */
39 loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
40 break;
41 }
42
43 _loongson_uart_base =
44 (unsigned long)ioremap_nocache(loongson_uart_base, 8);
45}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-05 13:52:10 -0400