aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2015-04-13 10:03:32 -0400
committerRalf Baechle <ralf@linux-mips.org>2015-04-13 10:03:32 -0400
commit3e20a26b02bd4f24945c87407df51948dd488620 (patch)
treef466d3b2a47a98ec2910724e17ee2f3a93c1a49e /arch/mips/kernel
parent98b0429b7abd5c05efdb23f3eba02ec3f696748e (diff)
parent5306a5450824691e27d68f711758515debedeeac (diff)
Merge branch '4.0-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c4
-rw-r--r--arch/mips/kernel/entry.S3
-rw-r--r--arch/mips/kernel/proc.c1
-rw-r--r--arch/mips/kernel/smp-cps.c6
-rw-r--r--arch/mips/kernel/unaligned.c340
5 files changed, 244 insertions, 110 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 73ab840f13bd..e36515dcd3b2 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -600,6 +600,10 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
600 c->options |= MIPS_CPU_MAAR; 600 c->options |= MIPS_CPU_MAAR;
601 if (config5 & MIPS_CONF5_LLB) 601 if (config5 & MIPS_CONF5_LLB)
602 c->options |= MIPS_CPU_RW_LLB; 602 c->options |= MIPS_CPU_RW_LLB;
603#ifdef CONFIG_XPA
604 if (config5 & MIPS_CONF5_MVH)
605 c->options |= MIPS_CPU_XPA;
606#endif
603 607
604 return config5 & MIPS_CONF_M; 608 return config5 & MIPS_CONF_M;
605} 609}
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index af41ba6db960..7791840cf22c 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -10,6 +10,7 @@
10 10
11#include <asm/asm.h> 11#include <asm/asm.h>
12#include <asm/asmmacro.h> 12#include <asm/asmmacro.h>
13#include <asm/compiler.h>
13#include <asm/regdef.h> 14#include <asm/regdef.h>
14#include <asm/mipsregs.h> 15#include <asm/mipsregs.h>
15#include <asm/stackframe.h> 16#include <asm/stackframe.h>
@@ -185,7 +186,7 @@ syscall_exit_work:
185 * For C code use the inline version named instruction_hazard(). 186 * For C code use the inline version named instruction_hazard().
186 */ 187 */
187LEAF(mips_ihb) 188LEAF(mips_ihb)
188 .set mips32r2 189 .set MIPS_ISA_LEVEL_RAW
189 jr.hb ra 190 jr.hb ra
190 nop 191 nop
191 END(mips_ihb) 192 END(mips_ihb)
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 130af7d26a9c..298b2b773d12 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -120,6 +120,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
120 if (cpu_has_msa) seq_printf(m, "%s", " msa"); 120 if (cpu_has_msa) seq_printf(m, "%s", " msa");
121 if (cpu_has_eva) seq_printf(m, "%s", " eva"); 121 if (cpu_has_eva) seq_printf(m, "%s", " eva");
122 if (cpu_has_htw) seq_printf(m, "%s", " htw"); 122 if (cpu_has_htw) seq_printf(m, "%s", " htw");
123 if (cpu_has_xpa) seq_printf(m, "%s", " xpa");
123 seq_printf(m, "\n"); 124 seq_printf(m, "\n");
124 125
125 if (cpu_has_mmips) { 126 if (cpu_has_mmips) {
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index bed7590e475f..d5589bedd0a4 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -88,6 +88,12 @@ static void __init cps_smp_setup(void)
88 88
89 /* Make core 0 coherent with everything */ 89 /* Make core 0 coherent with everything */
90 write_gcr_cl_coherence(0xff); 90 write_gcr_cl_coherence(0xff);
91
92#ifdef CONFIG_MIPS_MT_FPAFF
93 /* If we have an FPU, enroll ourselves in the FPU-full mask */
94 if (cpu_has_fpu)
95 cpu_set(0, mt_fpu_cpumask);
96#endif /* CONFIG_MIPS_MT_FPAFF */
91} 97}
92 98
93static void __init cps_prepare_cpus(unsigned int max_cpus) 99static void __init cps_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 27af5634a69b..af84bef0c90d 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -107,10 +107,11 @@ static u32 unaligned_action;
107extern void show_registers(struct pt_regs *regs); 107extern void show_registers(struct pt_regs *regs);
108 108
109#ifdef __BIG_ENDIAN 109#ifdef __BIG_ENDIAN
110#define LoadHW(addr, value, res) \ 110#define _LoadHW(addr, value, res, type) \
111do { \
111 __asm__ __volatile__ (".set\tnoat\n" \ 112 __asm__ __volatile__ (".set\tnoat\n" \
112 "1:\t"user_lb("%0", "0(%2)")"\n" \ 113 "1:\t"type##_lb("%0", "0(%2)")"\n" \
113 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 114 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
114 "sll\t%0, 0x8\n\t" \ 115 "sll\t%0, 0x8\n\t" \
115 "or\t%0, $1\n\t" \ 116 "or\t%0, $1\n\t" \
116 "li\t%1, 0\n" \ 117 "li\t%1, 0\n" \
@@ -125,13 +126,15 @@ extern void show_registers(struct pt_regs *regs);
125 STR(PTR)"\t2b, 4b\n\t" \ 126 STR(PTR)"\t2b, 4b\n\t" \
126 ".previous" \ 127 ".previous" \
127 : "=&r" (value), "=r" (res) \ 128 : "=&r" (value), "=r" (res) \
128 : "r" (addr), "i" (-EFAULT)); 129 : "r" (addr), "i" (-EFAULT)); \
130} while(0)
129 131
130#ifndef CONFIG_CPU_MIPSR6 132#ifndef CONFIG_CPU_MIPSR6
131#define LoadW(addr, value, res) \ 133#define _LoadW(addr, value, res, type) \
134do { \
132 __asm__ __volatile__ ( \ 135 __asm__ __volatile__ ( \
133 "1:\t"user_lwl("%0", "(%2)")"\n" \ 136 "1:\t"type##_lwl("%0", "(%2)")"\n" \
134 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 137 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
135 "li\t%1, 0\n" \ 138 "li\t%1, 0\n" \
136 "3:\n\t" \ 139 "3:\n\t" \
137 ".insn\n\t" \ 140 ".insn\n\t" \
@@ -144,21 +147,24 @@ extern void show_registers(struct pt_regs *regs);
144 STR(PTR)"\t2b, 4b\n\t" \ 147 STR(PTR)"\t2b, 4b\n\t" \
145 ".previous" \ 148 ".previous" \
146 : "=&r" (value), "=r" (res) \ 149 : "=&r" (value), "=r" (res) \
147 : "r" (addr), "i" (-EFAULT)); 150 : "r" (addr), "i" (-EFAULT)); \
151} while(0)
152
148#else 153#else
149/* MIPSR6 has no lwl instruction */ 154/* MIPSR6 has no lwl instruction */
150#define LoadW(addr, value, res) \ 155#define _LoadW(addr, value, res, type) \
156do { \
151 __asm__ __volatile__ ( \ 157 __asm__ __volatile__ ( \
152 ".set\tpush\n" \ 158 ".set\tpush\n" \
153 ".set\tnoat\n\t" \ 159 ".set\tnoat\n\t" \
154 "1:"user_lb("%0", "0(%2)")"\n\t" \ 160 "1:"type##_lb("%0", "0(%2)")"\n\t" \
155 "2:"user_lbu("$1", "1(%2)")"\n\t" \ 161 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
156 "sll\t%0, 0x8\n\t" \ 162 "sll\t%0, 0x8\n\t" \
157 "or\t%0, $1\n\t" \ 163 "or\t%0, $1\n\t" \
158 "3:"user_lbu("$1", "2(%2)")"\n\t" \ 164 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
159 "sll\t%0, 0x8\n\t" \ 165 "sll\t%0, 0x8\n\t" \
160 "or\t%0, $1\n\t" \ 166 "or\t%0, $1\n\t" \
161 "4:"user_lbu("$1", "3(%2)")"\n\t" \ 167 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
162 "sll\t%0, 0x8\n\t" \ 168 "sll\t%0, 0x8\n\t" \
163 "or\t%0, $1\n\t" \ 169 "or\t%0, $1\n\t" \
164 "li\t%1, 0\n" \ 170 "li\t%1, 0\n" \
@@ -176,14 +182,17 @@ extern void show_registers(struct pt_regs *regs);
176 STR(PTR)"\t4b, 11b\n\t" \ 182 STR(PTR)"\t4b, 11b\n\t" \
177 ".previous" \ 183 ".previous" \
178 : "=&r" (value), "=r" (res) \ 184 : "=&r" (value), "=r" (res) \
179 : "r" (addr), "i" (-EFAULT)); 185 : "r" (addr), "i" (-EFAULT)); \
186} while(0)
187
180#endif /* CONFIG_CPU_MIPSR6 */ 188#endif /* CONFIG_CPU_MIPSR6 */
181 189
182#define LoadHWU(addr, value, res) \ 190#define _LoadHWU(addr, value, res, type) \
191do { \
183 __asm__ __volatile__ ( \ 192 __asm__ __volatile__ ( \
184 ".set\tnoat\n" \ 193 ".set\tnoat\n" \
185 "1:\t"user_lbu("%0", "0(%2)")"\n" \ 194 "1:\t"type##_lbu("%0", "0(%2)")"\n" \
186 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 195 "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
187 "sll\t%0, 0x8\n\t" \ 196 "sll\t%0, 0x8\n\t" \
188 "or\t%0, $1\n\t" \ 197 "or\t%0, $1\n\t" \
189 "li\t%1, 0\n" \ 198 "li\t%1, 0\n" \
@@ -199,13 +208,15 @@ extern void show_registers(struct pt_regs *regs);
199 STR(PTR)"\t2b, 4b\n\t" \ 208 STR(PTR)"\t2b, 4b\n\t" \
200 ".previous" \ 209 ".previous" \
201 : "=&r" (value), "=r" (res) \ 210 : "=&r" (value), "=r" (res) \
202 : "r" (addr), "i" (-EFAULT)); 211 : "r" (addr), "i" (-EFAULT)); \
212} while(0)
203 213
204#ifndef CONFIG_CPU_MIPSR6 214#ifndef CONFIG_CPU_MIPSR6
205#define LoadWU(addr, value, res) \ 215#define _LoadWU(addr, value, res, type) \
216do { \
206 __asm__ __volatile__ ( \ 217 __asm__ __volatile__ ( \
207 "1:\t"user_lwl("%0", "(%2)")"\n" \ 218 "1:\t"type##_lwl("%0", "(%2)")"\n" \
208 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 219 "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
209 "dsll\t%0, %0, 32\n\t" \ 220 "dsll\t%0, %0, 32\n\t" \
210 "dsrl\t%0, %0, 32\n\t" \ 221 "dsrl\t%0, %0, 32\n\t" \
211 "li\t%1, 0\n" \ 222 "li\t%1, 0\n" \
@@ -220,9 +231,11 @@ extern void show_registers(struct pt_regs *regs);
220 STR(PTR)"\t2b, 4b\n\t" \ 231 STR(PTR)"\t2b, 4b\n\t" \
221 ".previous" \ 232 ".previous" \
222 : "=&r" (value), "=r" (res) \ 233 : "=&r" (value), "=r" (res) \
223 : "r" (addr), "i" (-EFAULT)); 234 : "r" (addr), "i" (-EFAULT)); \
235} while(0)
224 236
225#define LoadDW(addr, value, res) \ 237#define _LoadDW(addr, value, res) \
238do { \
226 __asm__ __volatile__ ( \ 239 __asm__ __volatile__ ( \
227 "1:\tldl\t%0, (%2)\n" \ 240 "1:\tldl\t%0, (%2)\n" \
228 "2:\tldr\t%0, 7(%2)\n\t" \ 241 "2:\tldr\t%0, 7(%2)\n\t" \
@@ -238,21 +251,24 @@ extern void show_registers(struct pt_regs *regs);
238 STR(PTR)"\t2b, 4b\n\t" \ 251 STR(PTR)"\t2b, 4b\n\t" \
239 ".previous" \ 252 ".previous" \
240 : "=&r" (value), "=r" (res) \ 253 : "=&r" (value), "=r" (res) \
241 : "r" (addr), "i" (-EFAULT)); 254 : "r" (addr), "i" (-EFAULT)); \
255} while(0)
256
242#else 257#else
243/* MIPSR6 has not lwl and ldl instructions */ 258/* MIPSR6 has not lwl and ldl instructions */
244#define LoadWU(addr, value, res) \ 259#define _LoadWU(addr, value, res, type) \
260do { \
245 __asm__ __volatile__ ( \ 261 __asm__ __volatile__ ( \
246 ".set\tpush\n\t" \ 262 ".set\tpush\n\t" \
247 ".set\tnoat\n\t" \ 263 ".set\tnoat\n\t" \
248 "1:"user_lbu("%0", "0(%2)")"\n\t" \ 264 "1:"type##_lbu("%0", "0(%2)")"\n\t" \
249 "2:"user_lbu("$1", "1(%2)")"\n\t" \ 265 "2:"type##_lbu("$1", "1(%2)")"\n\t" \
250 "sll\t%0, 0x8\n\t" \ 266 "sll\t%0, 0x8\n\t" \
251 "or\t%0, $1\n\t" \ 267 "or\t%0, $1\n\t" \
252 "3:"user_lbu("$1", "2(%2)")"\n\t" \ 268 "3:"type##_lbu("$1", "2(%2)")"\n\t" \
253 "sll\t%0, 0x8\n\t" \ 269 "sll\t%0, 0x8\n\t" \
254 "or\t%0, $1\n\t" \ 270 "or\t%0, $1\n\t" \
255 "4:"user_lbu("$1", "3(%2)")"\n\t" \ 271 "4:"type##_lbu("$1", "3(%2)")"\n\t" \
256 "sll\t%0, 0x8\n\t" \ 272 "sll\t%0, 0x8\n\t" \
257 "or\t%0, $1\n\t" \ 273 "or\t%0, $1\n\t" \
258 "li\t%1, 0\n" \ 274 "li\t%1, 0\n" \
@@ -270,9 +286,11 @@ extern void show_registers(struct pt_regs *regs);
270 STR(PTR)"\t4b, 11b\n\t" \ 286 STR(PTR)"\t4b, 11b\n\t" \
271 ".previous" \ 287 ".previous" \
272 : "=&r" (value), "=r" (res) \ 288 : "=&r" (value), "=r" (res) \
273 : "r" (addr), "i" (-EFAULT)); 289 : "r" (addr), "i" (-EFAULT)); \
290} while(0)
274 291
275#define LoadDW(addr, value, res) \ 292#define _LoadDW(addr, value, res) \
293do { \
276 __asm__ __volatile__ ( \ 294 __asm__ __volatile__ ( \
277 ".set\tpush\n\t" \ 295 ".set\tpush\n\t" \
278 ".set\tnoat\n\t" \ 296 ".set\tnoat\n\t" \
@@ -317,16 +335,19 @@ extern void show_registers(struct pt_regs *regs);
317 STR(PTR)"\t8b, 11b\n\t" \ 335 STR(PTR)"\t8b, 11b\n\t" \
318 ".previous" \ 336 ".previous" \
319 : "=&r" (value), "=r" (res) \ 337 : "=&r" (value), "=r" (res) \
320 : "r" (addr), "i" (-EFAULT)); 338 : "r" (addr), "i" (-EFAULT)); \
339} while(0)
340
321#endif /* CONFIG_CPU_MIPSR6 */ 341#endif /* CONFIG_CPU_MIPSR6 */
322 342
323 343
324#define StoreHW(addr, value, res) \ 344#define _StoreHW(addr, value, res, type) \
345do { \
325 __asm__ __volatile__ ( \ 346 __asm__ __volatile__ ( \
326 ".set\tnoat\n" \ 347 ".set\tnoat\n" \
327 "1:\t"user_sb("%1", "1(%2)")"\n" \ 348 "1:\t"type##_sb("%1", "1(%2)")"\n" \
328 "srl\t$1, %1, 0x8\n" \ 349 "srl\t$1, %1, 0x8\n" \
329 "2:\t"user_sb("$1", "0(%2)")"\n" \ 350 "2:\t"type##_sb("$1", "0(%2)")"\n" \
330 ".set\tat\n\t" \ 351 ".set\tat\n\t" \
331 "li\t%0, 0\n" \ 352 "li\t%0, 0\n" \
332 "3:\n\t" \ 353 "3:\n\t" \
@@ -340,13 +361,15 @@ extern void show_registers(struct pt_regs *regs);
340 STR(PTR)"\t2b, 4b\n\t" \ 361 STR(PTR)"\t2b, 4b\n\t" \
341 ".previous" \ 362 ".previous" \
342 : "=r" (res) \ 363 : "=r" (res) \
343 : "r" (value), "r" (addr), "i" (-EFAULT)); 364 : "r" (value), "r" (addr), "i" (-EFAULT));\
365} while(0)
344 366
345#ifndef CONFIG_CPU_MIPSR6 367#ifndef CONFIG_CPU_MIPSR6
346#define StoreW(addr, value, res) \ 368#define _StoreW(addr, value, res, type) \
369do { \
347 __asm__ __volatile__ ( \ 370 __asm__ __volatile__ ( \
348 "1:\t"user_swl("%1", "(%2)")"\n" \ 371 "1:\t"type##_swl("%1", "(%2)")"\n" \
349 "2:\t"user_swr("%1", "3(%2)")"\n\t" \ 372 "2:\t"type##_swr("%1", "3(%2)")"\n\t"\
350 "li\t%0, 0\n" \ 373 "li\t%0, 0\n" \
351 "3:\n\t" \ 374 "3:\n\t" \
352 ".insn\n\t" \ 375 ".insn\n\t" \
@@ -359,9 +382,11 @@ extern void show_registers(struct pt_regs *regs);
359 STR(PTR)"\t2b, 4b\n\t" \ 382 STR(PTR)"\t2b, 4b\n\t" \
360 ".previous" \ 383 ".previous" \
361 : "=r" (res) \ 384 : "=r" (res) \
362 : "r" (value), "r" (addr), "i" (-EFAULT)); 385 : "r" (value), "r" (addr), "i" (-EFAULT)); \
386} while(0)
363 387
364#define StoreDW(addr, value, res) \ 388#define _StoreDW(addr, value, res) \
389do { \
365 __asm__ __volatile__ ( \ 390 __asm__ __volatile__ ( \
366 "1:\tsdl\t%1,(%2)\n" \ 391 "1:\tsdl\t%1,(%2)\n" \
367 "2:\tsdr\t%1, 7(%2)\n\t" \ 392 "2:\tsdr\t%1, 7(%2)\n\t" \
@@ -377,20 +402,23 @@ extern void show_registers(struct pt_regs *regs);
377 STR(PTR)"\t2b, 4b\n\t" \ 402 STR(PTR)"\t2b, 4b\n\t" \
378 ".previous" \ 403 ".previous" \
379 : "=r" (res) \ 404 : "=r" (res) \
380 : "r" (value), "r" (addr), "i" (-EFAULT)); 405 : "r" (value), "r" (addr), "i" (-EFAULT)); \
406} while(0)
407
381#else 408#else
382/* MIPSR6 has no swl and sdl instructions */ 409/* MIPSR6 has no swl and sdl instructions */
383#define StoreW(addr, value, res) \ 410#define _StoreW(addr, value, res, type) \
411do { \
384 __asm__ __volatile__ ( \ 412 __asm__ __volatile__ ( \
385 ".set\tpush\n\t" \ 413 ".set\tpush\n\t" \
386 ".set\tnoat\n\t" \ 414 ".set\tnoat\n\t" \
387 "1:"user_sb("%1", "3(%2)")"\n\t" \ 415 "1:"type##_sb("%1", "3(%2)")"\n\t" \
388 "srl\t$1, %1, 0x8\n\t" \ 416 "srl\t$1, %1, 0x8\n\t" \
389 "2:"user_sb("$1", "2(%2)")"\n\t" \ 417 "2:"type##_sb("$1", "2(%2)")"\n\t" \
390 "srl\t$1, $1, 0x8\n\t" \ 418 "srl\t$1, $1, 0x8\n\t" \
391 "3:"user_sb("$1", "1(%2)")"\n\t" \ 419 "3:"type##_sb("$1", "1(%2)")"\n\t" \
392 "srl\t$1, $1, 0x8\n\t" \ 420 "srl\t$1, $1, 0x8\n\t" \
393 "4:"user_sb("$1", "0(%2)")"\n\t" \ 421 "4:"type##_sb("$1", "0(%2)")"\n\t" \
394 ".set\tpop\n\t" \ 422 ".set\tpop\n\t" \
395 "li\t%0, 0\n" \ 423 "li\t%0, 0\n" \
396 "10:\n\t" \ 424 "10:\n\t" \
@@ -407,9 +435,11 @@ extern void show_registers(struct pt_regs *regs);
407 ".previous" \ 435 ".previous" \
408 : "=&r" (res) \ 436 : "=&r" (res) \
409 : "r" (value), "r" (addr), "i" (-EFAULT) \ 437 : "r" (value), "r" (addr), "i" (-EFAULT) \
410 : "memory"); 438 : "memory"); \
439} while(0)
411 440
412#define StoreDW(addr, value, res) \ 441#define StoreDW(addr, value, res) \
442do { \
413 __asm__ __volatile__ ( \ 443 __asm__ __volatile__ ( \
414 ".set\tpush\n\t" \ 444 ".set\tpush\n\t" \
415 ".set\tnoat\n\t" \ 445 ".set\tnoat\n\t" \
@@ -449,15 +479,18 @@ extern void show_registers(struct pt_regs *regs);
449 ".previous" \ 479 ".previous" \
450 : "=&r" (res) \ 480 : "=&r" (res) \
451 : "r" (value), "r" (addr), "i" (-EFAULT) \ 481 : "r" (value), "r" (addr), "i" (-EFAULT) \
452 : "memory"); 482 : "memory"); \
483} while(0)
484
453#endif /* CONFIG_CPU_MIPSR6 */ 485#endif /* CONFIG_CPU_MIPSR6 */
454 486
455#else /* __BIG_ENDIAN */ 487#else /* __BIG_ENDIAN */
456 488
457#define LoadHW(addr, value, res) \ 489#define _LoadHW(addr, value, res, type) \
490do { \
458 __asm__ __volatile__ (".set\tnoat\n" \ 491 __asm__ __volatile__ (".set\tnoat\n" \
459 "1:\t"user_lb("%0", "1(%2)")"\n" \ 492 "1:\t"type##_lb("%0", "1(%2)")"\n" \
460 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 493 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
461 "sll\t%0, 0x8\n\t" \ 494 "sll\t%0, 0x8\n\t" \
462 "or\t%0, $1\n\t" \ 495 "or\t%0, $1\n\t" \
463 "li\t%1, 0\n" \ 496 "li\t%1, 0\n" \
@@ -472,13 +505,15 @@ extern void show_registers(struct pt_regs *regs);
472 STR(PTR)"\t2b, 4b\n\t" \ 505 STR(PTR)"\t2b, 4b\n\t" \
473 ".previous" \ 506 ".previous" \
474 : "=&r" (value), "=r" (res) \ 507 : "=&r" (value), "=r" (res) \
475 : "r" (addr), "i" (-EFAULT)); 508 : "r" (addr), "i" (-EFAULT)); \
509} while(0)
476 510
477#ifndef CONFIG_CPU_MIPSR6 511#ifndef CONFIG_CPU_MIPSR6
478#define LoadW(addr, value, res) \ 512#define _LoadW(addr, value, res, type) \
513do { \
479 __asm__ __volatile__ ( \ 514 __asm__ __volatile__ ( \
480 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 515 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
481 "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 516 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
482 "li\t%1, 0\n" \ 517 "li\t%1, 0\n" \
483 "3:\n\t" \ 518 "3:\n\t" \
484 ".insn\n\t" \ 519 ".insn\n\t" \
@@ -491,21 +526,24 @@ extern void show_registers(struct pt_regs *regs);
491 STR(PTR)"\t2b, 4b\n\t" \ 526 STR(PTR)"\t2b, 4b\n\t" \
492 ".previous" \ 527 ".previous" \
493 : "=&r" (value), "=r" (res) \ 528 : "=&r" (value), "=r" (res) \
494 : "r" (addr), "i" (-EFAULT)); 529 : "r" (addr), "i" (-EFAULT)); \
530} while(0)
531
495#else 532#else
496/* MIPSR6 has no lwl instruction */ 533/* MIPSR6 has no lwl instruction */
497#define LoadW(addr, value, res) \ 534#define _LoadW(addr, value, res, type) \
535do { \
498 __asm__ __volatile__ ( \ 536 __asm__ __volatile__ ( \
499 ".set\tpush\n" \ 537 ".set\tpush\n" \
500 ".set\tnoat\n\t" \ 538 ".set\tnoat\n\t" \
501 "1:"user_lb("%0", "3(%2)")"\n\t" \ 539 "1:"type##_lb("%0", "3(%2)")"\n\t" \
502 "2:"user_lbu("$1", "2(%2)")"\n\t" \ 540 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
503 "sll\t%0, 0x8\n\t" \ 541 "sll\t%0, 0x8\n\t" \
504 "or\t%0, $1\n\t" \ 542 "or\t%0, $1\n\t" \
505 "3:"user_lbu("$1", "1(%2)")"\n\t" \ 543 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
506 "sll\t%0, 0x8\n\t" \ 544 "sll\t%0, 0x8\n\t" \
507 "or\t%0, $1\n\t" \ 545 "or\t%0, $1\n\t" \
508 "4:"user_lbu("$1", "0(%2)")"\n\t" \ 546 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
509 "sll\t%0, 0x8\n\t" \ 547 "sll\t%0, 0x8\n\t" \
510 "or\t%0, $1\n\t" \ 548 "or\t%0, $1\n\t" \
511 "li\t%1, 0\n" \ 549 "li\t%1, 0\n" \
@@ -523,15 +561,18 @@ extern void show_registers(struct pt_regs *regs);
523 STR(PTR)"\t4b, 11b\n\t" \ 561 STR(PTR)"\t4b, 11b\n\t" \
524 ".previous" \ 562 ".previous" \
525 : "=&r" (value), "=r" (res) \ 563 : "=&r" (value), "=r" (res) \
526 : "r" (addr), "i" (-EFAULT)); 564 : "r" (addr), "i" (-EFAULT)); \
565} while(0)
566
527#endif /* CONFIG_CPU_MIPSR6 */ 567#endif /* CONFIG_CPU_MIPSR6 */
528 568
529 569
530#define LoadHWU(addr, value, res) \ 570#define _LoadHWU(addr, value, res, type) \
571do { \
531 __asm__ __volatile__ ( \ 572 __asm__ __volatile__ ( \
532 ".set\tnoat\n" \ 573 ".set\tnoat\n" \
533 "1:\t"user_lbu("%0", "1(%2)")"\n" \ 574 "1:\t"type##_lbu("%0", "1(%2)")"\n" \
534 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 575 "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
535 "sll\t%0, 0x8\n\t" \ 576 "sll\t%0, 0x8\n\t" \
536 "or\t%0, $1\n\t" \ 577 "or\t%0, $1\n\t" \
537 "li\t%1, 0\n" \ 578 "li\t%1, 0\n" \
@@ -547,13 +588,15 @@ extern void show_registers(struct pt_regs *regs);
547 STR(PTR)"\t2b, 4b\n\t" \ 588 STR(PTR)"\t2b, 4b\n\t" \
548 ".previous" \ 589 ".previous" \
549 : "=&r" (value), "=r" (res) \ 590 : "=&r" (value), "=r" (res) \
550 : "r" (addr), "i" (-EFAULT)); 591 : "r" (addr), "i" (-EFAULT)); \
592} while(0)
551 593
552#ifndef CONFIG_CPU_MIPSR6 594#ifndef CONFIG_CPU_MIPSR6
553#define LoadWU(addr, value, res) \ 595#define _LoadWU(addr, value, res, type) \
596do { \
554 __asm__ __volatile__ ( \ 597 __asm__ __volatile__ ( \
555 "1:\t"user_lwl("%0", "3(%2)")"\n" \ 598 "1:\t"type##_lwl("%0", "3(%2)")"\n" \
556 "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 599 "2:\t"type##_lwr("%0", "(%2)")"\n\t"\
557 "dsll\t%0, %0, 32\n\t" \ 600 "dsll\t%0, %0, 32\n\t" \
558 "dsrl\t%0, %0, 32\n\t" \ 601 "dsrl\t%0, %0, 32\n\t" \
559 "li\t%1, 0\n" \ 602 "li\t%1, 0\n" \
@@ -568,9 +611,11 @@ extern void show_registers(struct pt_regs *regs);
568 STR(PTR)"\t2b, 4b\n\t" \ 611 STR(PTR)"\t2b, 4b\n\t" \
569 ".previous" \ 612 ".previous" \
570 : "=&r" (value), "=r" (res) \ 613 : "=&r" (value), "=r" (res) \
571 : "r" (addr), "i" (-EFAULT)); 614 : "r" (addr), "i" (-EFAULT)); \
615} while(0)
572 616
573#define LoadDW(addr, value, res) \ 617#define _LoadDW(addr, value, res) \
618do { \
574 __asm__ __volatile__ ( \ 619 __asm__ __volatile__ ( \
575 "1:\tldl\t%0, 7(%2)\n" \ 620 "1:\tldl\t%0, 7(%2)\n" \
576 "2:\tldr\t%0, (%2)\n\t" \ 621 "2:\tldr\t%0, (%2)\n\t" \
@@ -586,21 +631,24 @@ extern void show_registers(struct pt_regs *regs);
586 STR(PTR)"\t2b, 4b\n\t" \ 631 STR(PTR)"\t2b, 4b\n\t" \
587 ".previous" \ 632 ".previous" \
588 : "=&r" (value), "=r" (res) \ 633 : "=&r" (value), "=r" (res) \
589 : "r" (addr), "i" (-EFAULT)); 634 : "r" (addr), "i" (-EFAULT)); \
635} while(0)
636
590#else 637#else
591/* MIPSR6 has not lwl and ldl instructions */ 638/* MIPSR6 has not lwl and ldl instructions */
592#define LoadWU(addr, value, res) \ 639#define _LoadWU(addr, value, res, type) \
640do { \
593 __asm__ __volatile__ ( \ 641 __asm__ __volatile__ ( \
594 ".set\tpush\n\t" \ 642 ".set\tpush\n\t" \
595 ".set\tnoat\n\t" \ 643 ".set\tnoat\n\t" \
596 "1:"user_lbu("%0", "3(%2)")"\n\t" \ 644 "1:"type##_lbu("%0", "3(%2)")"\n\t" \
597 "2:"user_lbu("$1", "2(%2)")"\n\t" \ 645 "2:"type##_lbu("$1", "2(%2)")"\n\t" \
598 "sll\t%0, 0x8\n\t" \ 646 "sll\t%0, 0x8\n\t" \
599 "or\t%0, $1\n\t" \ 647 "or\t%0, $1\n\t" \
600 "3:"user_lbu("$1", "1(%2)")"\n\t" \ 648 "3:"type##_lbu("$1", "1(%2)")"\n\t" \
601 "sll\t%0, 0x8\n\t" \ 649 "sll\t%0, 0x8\n\t" \
602 "or\t%0, $1\n\t" \ 650 "or\t%0, $1\n\t" \
603 "4:"user_lbu("$1", "0(%2)")"\n\t" \ 651 "4:"type##_lbu("$1", "0(%2)")"\n\t" \
604 "sll\t%0, 0x8\n\t" \ 652 "sll\t%0, 0x8\n\t" \
605 "or\t%0, $1\n\t" \ 653 "or\t%0, $1\n\t" \
606 "li\t%1, 0\n" \ 654 "li\t%1, 0\n" \
@@ -618,9 +666,11 @@ extern void show_registers(struct pt_regs *regs);
618 STR(PTR)"\t4b, 11b\n\t" \ 666 STR(PTR)"\t4b, 11b\n\t" \
619 ".previous" \ 667 ".previous" \
620 : "=&r" (value), "=r" (res) \ 668 : "=&r" (value), "=r" (res) \
621 : "r" (addr), "i" (-EFAULT)); 669 : "r" (addr), "i" (-EFAULT)); \
670} while(0)
622 671
623#define LoadDW(addr, value, res) \ 672#define _LoadDW(addr, value, res) \
673do { \
624 __asm__ __volatile__ ( \ 674 __asm__ __volatile__ ( \
625 ".set\tpush\n\t" \ 675 ".set\tpush\n\t" \
626 ".set\tnoat\n\t" \ 676 ".set\tnoat\n\t" \
@@ -665,15 +715,17 @@ extern void show_registers(struct pt_regs *regs);
665 STR(PTR)"\t8b, 11b\n\t" \ 715 STR(PTR)"\t8b, 11b\n\t" \
666 ".previous" \ 716 ".previous" \
667 : "=&r" (value), "=r" (res) \ 717 : "=&r" (value), "=r" (res) \
668 : "r" (addr), "i" (-EFAULT)); 718 : "r" (addr), "i" (-EFAULT)); \
719} while(0)
669#endif /* CONFIG_CPU_MIPSR6 */ 720#endif /* CONFIG_CPU_MIPSR6 */
670 721
671#define StoreHW(addr, value, res) \ 722#define _StoreHW(addr, value, res, type) \
723do { \
672 __asm__ __volatile__ ( \ 724 __asm__ __volatile__ ( \
673 ".set\tnoat\n" \ 725 ".set\tnoat\n" \
674 "1:\t"user_sb("%1", "0(%2)")"\n" \ 726 "1:\t"type##_sb("%1", "0(%2)")"\n" \
675 "srl\t$1,%1, 0x8\n" \ 727 "srl\t$1,%1, 0x8\n" \
676 "2:\t"user_sb("$1", "1(%2)")"\n" \ 728 "2:\t"type##_sb("$1", "1(%2)")"\n" \
677 ".set\tat\n\t" \ 729 ".set\tat\n\t" \
678 "li\t%0, 0\n" \ 730 "li\t%0, 0\n" \
679 "3:\n\t" \ 731 "3:\n\t" \
@@ -687,12 +739,15 @@ extern void show_registers(struct pt_regs *regs);
687 STR(PTR)"\t2b, 4b\n\t" \ 739 STR(PTR)"\t2b, 4b\n\t" \
688 ".previous" \ 740 ".previous" \
689 : "=r" (res) \ 741 : "=r" (res) \
690 : "r" (value), "r" (addr), "i" (-EFAULT)); 742 : "r" (value), "r" (addr), "i" (-EFAULT));\
743} while(0)
744
691#ifndef CONFIG_CPU_MIPSR6 745#ifndef CONFIG_CPU_MIPSR6
692#define StoreW(addr, value, res) \ 746#define _StoreW(addr, value, res, type) \
747do { \
693 __asm__ __volatile__ ( \ 748 __asm__ __volatile__ ( \
694 "1:\t"user_swl("%1", "3(%2)")"\n" \ 749 "1:\t"type##_swl("%1", "3(%2)")"\n" \
695 "2:\t"user_swr("%1", "(%2)")"\n\t" \ 750 "2:\t"type##_swr("%1", "(%2)")"\n\t"\
696 "li\t%0, 0\n" \ 751 "li\t%0, 0\n" \
697 "3:\n\t" \ 752 "3:\n\t" \
698 ".insn\n\t" \ 753 ".insn\n\t" \
@@ -705,9 +760,11 @@ extern void show_registers(struct pt_regs *regs);
705 STR(PTR)"\t2b, 4b\n\t" \ 760 STR(PTR)"\t2b, 4b\n\t" \
706 ".previous" \ 761 ".previous" \
707 : "=r" (res) \ 762 : "=r" (res) \
708 : "r" (value), "r" (addr), "i" (-EFAULT)); 763 : "r" (value), "r" (addr), "i" (-EFAULT)); \
764} while(0)
709 765
710#define StoreDW(addr, value, res) \ 766#define _StoreDW(addr, value, res) \
767do { \
711 __asm__ __volatile__ ( \ 768 __asm__ __volatile__ ( \
712 "1:\tsdl\t%1, 7(%2)\n" \ 769 "1:\tsdl\t%1, 7(%2)\n" \
713 "2:\tsdr\t%1, (%2)\n\t" \ 770 "2:\tsdr\t%1, (%2)\n\t" \
@@ -723,20 +780,23 @@ extern void show_registers(struct pt_regs *regs);
723 STR(PTR)"\t2b, 4b\n\t" \ 780 STR(PTR)"\t2b, 4b\n\t" \
724 ".previous" \ 781 ".previous" \
725 : "=r" (res) \ 782 : "=r" (res) \
726 : "r" (value), "r" (addr), "i" (-EFAULT)); 783 : "r" (value), "r" (addr), "i" (-EFAULT)); \
784} while(0)
785
727#else 786#else
728/* MIPSR6 has no swl and sdl instructions */ 787/* MIPSR6 has no swl and sdl instructions */
729#define StoreW(addr, value, res) \ 788#define _StoreW(addr, value, res, type) \
789do { \
730 __asm__ __volatile__ ( \ 790 __asm__ __volatile__ ( \
731 ".set\tpush\n\t" \ 791 ".set\tpush\n\t" \
732 ".set\tnoat\n\t" \ 792 ".set\tnoat\n\t" \
733 "1:"user_sb("%1", "0(%2)")"\n\t" \ 793 "1:"type##_sb("%1", "0(%2)")"\n\t" \
734 "srl\t$1, %1, 0x8\n\t" \ 794 "srl\t$1, %1, 0x8\n\t" \
735 "2:"user_sb("$1", "1(%2)")"\n\t" \ 795 "2:"type##_sb("$1", "1(%2)")"\n\t" \
736 "srl\t$1, $1, 0x8\n\t" \ 796 "srl\t$1, $1, 0x8\n\t" \
737 "3:"user_sb("$1", "2(%2)")"\n\t" \ 797 "3:"type##_sb("$1", "2(%2)")"\n\t" \
738 "srl\t$1, $1, 0x8\n\t" \ 798 "srl\t$1, $1, 0x8\n\t" \
739 "4:"user_sb("$1", "3(%2)")"\n\t" \ 799 "4:"type##_sb("$1", "3(%2)")"\n\t" \
740 ".set\tpop\n\t" \ 800 ".set\tpop\n\t" \
741 "li\t%0, 0\n" \ 801 "li\t%0, 0\n" \
742 "10:\n\t" \ 802 "10:\n\t" \
@@ -753,9 +813,11 @@ extern void show_registers(struct pt_regs *regs);
753 ".previous" \ 813 ".previous" \
754 : "=&r" (res) \ 814 : "=&r" (res) \
755 : "r" (value), "r" (addr), "i" (-EFAULT) \ 815 : "r" (value), "r" (addr), "i" (-EFAULT) \
756 : "memory"); 816 : "memory"); \
817} while(0)
757 818
758#define StoreDW(addr, value, res) \ 819#define _StoreDW(addr, value, res) \
820do { \
759 __asm__ __volatile__ ( \ 821 __asm__ __volatile__ ( \
760 ".set\tpush\n\t" \ 822 ".set\tpush\n\t" \
761 ".set\tnoat\n\t" \ 823 ".set\tnoat\n\t" \
@@ -795,10 +857,28 @@ extern void show_registers(struct pt_regs *regs);
795 ".previous" \ 857 ".previous" \
796 : "=&r" (res) \ 858 : "=&r" (res) \
797 : "r" (value), "r" (addr), "i" (-EFAULT) \ 859 : "r" (value), "r" (addr), "i" (-EFAULT) \
798 : "memory"); 860 : "memory"); \
861} while(0)
862
799#endif /* CONFIG_CPU_MIPSR6 */ 863#endif /* CONFIG_CPU_MIPSR6 */
800#endif 864#endif
801 865
866#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
867#define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user)
868#define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel)
869#define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user)
870#define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel)
871#define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user)
872#define LoadW(addr, value, res) _LoadW(addr, value, res, kernel)
873#define LoadWE(addr, value, res) _LoadW(addr, value, res, user)
874#define LoadDW(addr, value, res) _LoadDW(addr, value, res)
875
876#define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel)
877#define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user)
878#define StoreW(addr, value, res) _StoreW(addr, value, res, kernel)
879#define StoreWE(addr, value, res) _StoreW(addr, value, res, user)
880#define StoreDW(addr, value, res) _StoreDW(addr, value, res)
881
802static void emulate_load_store_insn(struct pt_regs *regs, 882static void emulate_load_store_insn(struct pt_regs *regs,
803 void __user *addr, unsigned int __user *pc) 883 void __user *addr, unsigned int __user *pc)
804{ 884{
@@ -870,7 +950,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
870 set_fs(seg); 950 set_fs(seg);
871 goto sigbus; 951 goto sigbus;
872 } 952 }
873 LoadHW(addr, value, res); 953 LoadHWE(addr, value, res);
874 if (res) { 954 if (res) {
875 set_fs(seg); 955 set_fs(seg);
876 goto fault; 956 goto fault;
@@ -883,7 +963,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
883 set_fs(seg); 963 set_fs(seg);
884 goto sigbus; 964 goto sigbus;
885 } 965 }
886 LoadW(addr, value, res); 966 LoadWE(addr, value, res);
887 if (res) { 967 if (res) {
888 set_fs(seg); 968 set_fs(seg);
889 goto fault; 969 goto fault;
@@ -896,7 +976,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
896 set_fs(seg); 976 set_fs(seg);
897 goto sigbus; 977 goto sigbus;
898 } 978 }
899 LoadHWU(addr, value, res); 979 LoadHWUE(addr, value, res);
900 if (res) { 980 if (res) {
901 set_fs(seg); 981 set_fs(seg);
902 goto fault; 982 goto fault;
@@ -911,7 +991,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
911 } 991 }
912 compute_return_epc(regs); 992 compute_return_epc(regs);
913 value = regs->regs[insn.spec3_format.rt]; 993 value = regs->regs[insn.spec3_format.rt];
914 StoreHW(addr, value, res); 994 StoreHWE(addr, value, res);
915 if (res) { 995 if (res) {
916 set_fs(seg); 996 set_fs(seg);
917 goto fault; 997 goto fault;
@@ -924,7 +1004,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
924 } 1004 }
925 compute_return_epc(regs); 1005 compute_return_epc(regs);
926 value = regs->regs[insn.spec3_format.rt]; 1006 value = regs->regs[insn.spec3_format.rt];
927 StoreW(addr, value, res); 1007 StoreWE(addr, value, res);
928 if (res) { 1008 if (res) {
929 set_fs(seg); 1009 set_fs(seg);
930 goto fault; 1010 goto fault;
@@ -941,7 +1021,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
941 if (!access_ok(VERIFY_READ, addr, 2)) 1021 if (!access_ok(VERIFY_READ, addr, 2))
942 goto sigbus; 1022 goto sigbus;
943 1023
944 LoadHW(addr, value, res); 1024 if (config_enabled(CONFIG_EVA)) {
1025 if (segment_eq(get_fs(), get_ds()))
1026 LoadHW(addr, value, res);
1027 else
1028 LoadHWE(addr, value, res);
1029 } else {
1030 LoadHW(addr, value, res);
1031 }
1032
945 if (res) 1033 if (res)
946 goto fault; 1034 goto fault;
947 compute_return_epc(regs); 1035 compute_return_epc(regs);
@@ -952,7 +1040,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
952 if (!access_ok(VERIFY_READ, addr, 4)) 1040 if (!access_ok(VERIFY_READ, addr, 4))
953 goto sigbus; 1041 goto sigbus;
954 1042
955 LoadW(addr, value, res); 1043 if (config_enabled(CONFIG_EVA)) {
1044 if (segment_eq(get_fs(), get_ds()))
1045 LoadW(addr, value, res);
1046 else
1047 LoadWE(addr, value, res);
1048 } else {
1049 LoadW(addr, value, res);
1050 }
1051
956 if (res) 1052 if (res)
957 goto fault; 1053 goto fault;
958 compute_return_epc(regs); 1054 compute_return_epc(regs);
@@ -963,7 +1059,15 @@ static void emulate_load_store_insn(struct pt_regs *regs,
963 if (!access_ok(VERIFY_READ, addr, 2)) 1059 if (!access_ok(VERIFY_READ, addr, 2))
964 goto sigbus; 1060 goto sigbus;
965 1061
966 LoadHWU(addr, value, res); 1062 if (config_enabled(CONFIG_EVA)) {
1063 if (segment_eq(get_fs(), get_ds()))
1064 LoadHWU(addr, value, res);
1065 else
1066 LoadHWUE(addr, value, res);
1067 } else {
1068 LoadHWU(addr, value, res);
1069 }
1070
967 if (res) 1071 if (res)
968 goto fault; 1072 goto fault;
969 compute_return_epc(regs); 1073 compute_return_epc(regs);
@@ -1022,7 +1126,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
1022 1126
1023 compute_return_epc(regs); 1127 compute_return_epc(regs);
1024 value = regs->regs[insn.i_format.rt]; 1128 value = regs->regs[insn.i_format.rt];
1025 StoreHW(addr, value, res); 1129
1130 if (config_enabled(CONFIG_EVA)) {
1131 if (segment_eq(get_fs(), get_ds()))
1132 StoreHW(addr, value, res);
1133 else
1134 StoreHWE(addr, value, res);
1135 } else {
1136 StoreHW(addr, value, res);
1137 }
1138
1026 if (res) 1139 if (res)
1027 goto fault; 1140 goto fault;
1028 break; 1141 break;
@@ -1033,7 +1146,16 @@ static void emulate_load_store_insn(struct pt_regs *regs,
1033 1146
1034 compute_return_epc(regs); 1147 compute_return_epc(regs);
1035 value = regs->regs[insn.i_format.rt]; 1148 value = regs->regs[insn.i_format.rt];
1036 StoreW(addr, value, res); 1149
1150 if (config_enabled(CONFIG_EVA)) {
1151 if (segment_eq(get_fs(), get_ds()))
1152 StoreW(addr, value, res);
1153 else
1154 StoreWE(addr, value, res);
1155 } else {
1156 StoreW(addr, value, res);
1157 }
1158
1037 if (res) 1159 if (res)
1038 goto fault; 1160 goto fault;
1039 break; 1161 break;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 17:58:12 -0400