aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2014-03-17 19:53:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-03-17 19:53:18 -0400
commit8a21d9f63dd47485964b930af41304d88dee0e9b (patch)
tree7484f1d2354bf401c328f0e7d392ed78a1125d39 /arch/mips/include
parent9f8b483cf34d1492fdabf9b03ab3f9c74c242554 (diff)
parent06e2e88292e9ea6f5a23ead2e9c5ccf8bbd99e93 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "A fair number of fixes all across arch/mips. Nothing really stands out though APRP, the FPU code and syscall tracing code received multiple patches those all were small" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: mark O32+FP64 experimental for now MIPS: ftrace: Fix icache flush range error MIPS: Fix syscall tracing interface MIPS: asm: syscall: Fix copying system call arguments MIPS: Octeon: Fix fall through on bar type OCTEON_DMA_BAR_TYPE_SMALL MIPS: FPU: Fix conflict of register usage MIPS: Replace CONFIG_MIPS64 and CONFIG_MIPS32_R2 MIPS: math-emu: Fix prefx detection and COP1X function field definition MIPS: APRP: Choose the correct VPE loader by fixing the linking MIPS: APRP: Unregister rtlx interrupt hook at module exit MIPS: APRP: Fix the linking of rtlx interrupt hook MIPS: bcm47xx: Include missing errno.h for ENXIO MIPS: Alchemy: Fix unchecked kstrtoul return value MIPS: Fix randconfig build error.
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/asmmacro.h4
-rw-r--r--arch/mips/include/asm/fpu.h2
-rw-r--r--arch/mips/include/asm/syscall.h10
-rw-r--r--arch/mips/include/uapi/asm/inst.h4
4 files changed, 11 insertions, 9 deletions
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 3220c93ea981..69a9a22d014a 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -106,7 +106,7 @@
106 .endm 106 .endm
107 107
108 .macro fpu_save_double thread status tmp 108 .macro fpu_save_double thread status tmp
109#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 109#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
110 sll \tmp, \status, 5 110 sll \tmp, \status, 5
111 bgez \tmp, 10f 111 bgez \tmp, 10f
112 fpu_save_16odd \thread 112 fpu_save_16odd \thread
@@ -159,7 +159,7 @@
159 .endm 159 .endm
160 160
161 .macro fpu_restore_double thread status tmp 161 .macro fpu_restore_double thread status tmp
162#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 162#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
163 sll \tmp, \status, 5 163 sll \tmp, \status, 5
164 bgez \tmp, 10f # 16 register mode? 164 bgez \tmp, 10f # 16 register mode?
165 165
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 6b9749540edf..58e50cbdb1a6 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -57,7 +57,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
57 return 0; 57 return 0;
58 58
59 case FPU_64BIT: 59 case FPU_64BIT:
60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64)) 60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
61 /* we only have a 32-bit FPU */ 61 /* we only have a 32-bit FPU */
62 return SIGFPE; 62 return SIGFPE;
63#endif 63#endif
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 33e8dbfc1b63..f35b131977e6 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_MIPS_SYSCALL_H 13#ifndef __ASM_MIPS_SYSCALL_H
14#define __ASM_MIPS_SYSCALL_H 14#define __ASM_MIPS_SYSCALL_H
15 15
16#include <linux/compiler.h>
16#include <linux/audit.h> 17#include <linux/audit.h>
17#include <linux/elf-em.h> 18#include <linux/elf-em.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -39,14 +40,14 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
39 40
40#ifdef CONFIG_32BIT 41#ifdef CONFIG_32BIT
41 case 4: case 5: case 6: case 7: 42 case 4: case 5: case 6: case 7:
42 return get_user(*arg, (int *)usp + 4 * n); 43 return get_user(*arg, (int *)usp + n);
43#endif 44#endif
44 45
45#ifdef CONFIG_64BIT 46#ifdef CONFIG_64BIT
46 case 4: case 5: case 6: case 7: 47 case 4: case 5: case 6: case 7:
47#ifdef CONFIG_MIPS32_O32 48#ifdef CONFIG_MIPS32_O32
48 if (test_thread_flag(TIF_32BIT_REGS)) 49 if (test_thread_flag(TIF_32BIT_REGS))
49 return get_user(*arg, (int *)usp + 4 * n); 50 return get_user(*arg, (int *)usp + n);
50 else 51 else
51#endif 52#endif
52 *arg = regs->regs[4 + n]; 53 *arg = regs->regs[4 + n];
@@ -57,6 +58,8 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
57 default: 58 default:
58 BUG(); 59 BUG();
59 } 60 }
61
62 unreachable();
60} 63}
61 64
62static inline long syscall_get_return_value(struct task_struct *task, 65static inline long syscall_get_return_value(struct task_struct *task,
@@ -83,11 +86,10 @@ static inline void syscall_get_arguments(struct task_struct *task,
83 unsigned int i, unsigned int n, 86 unsigned int i, unsigned int n,
84 unsigned long *args) 87 unsigned long *args)
85{ 88{
86 unsigned long arg;
87 int ret; 89 int ret;
88 90
89 while (n--) 91 while (n--)
90 ret |= mips_get_syscall_arg(&arg, task, regs, i++); 92 ret |= mips_get_syscall_arg(args++, task, regs, i++);
91 93
92 /* 94 /*
93 * No way to communicate an error because this is a void function. 95 * No way to communicate an error because this is a void function.
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index b39ba25b41cc..f25181b19941 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -163,8 +163,8 @@ enum cop1_sdw_func {
163 */ 163 */
164enum cop1x_func { 164enum cop1x_func {
165 lwxc1_op = 0x00, ldxc1_op = 0x01, 165 lwxc1_op = 0x00, ldxc1_op = 0x01,
166 pfetch_op = 0x07, swxc1_op = 0x08, 166 swxc1_op = 0x08, sdxc1_op = 0x09,
167 sdxc1_op = 0x09, madd_s_op = 0x20, 167 pfetch_op = 0x0f, madd_s_op = 0x20,
168 madd_d_op = 0x21, madd_e_op = 0x22, 168 madd_d_op = 0x21, madd_e_op = 0x22,
169 msub_s_op = 0x28, msub_d_op = 0x29, 169 msub_s_op = 0x28, msub_d_op = 0x29,
170 msub_e_op = 0x2a, nmadd_s_op = 0x30, 170 msub_e_op = 0x2a, nmadd_s_op = 0x30,