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authorLinus Torvalds <torvalds@linux-foundation.org>2014-03-17 19:53:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-03-17 19:53:18 -0400
commit8a21d9f63dd47485964b930af41304d88dee0e9b (patch)
tree7484f1d2354bf401c328f0e7d392ed78a1125d39
parent9f8b483cf34d1492fdabf9b03ab3f9c74c242554 (diff)
parent06e2e88292e9ea6f5a23ead2e9c5ccf8bbd99e93 (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "A fair number of fixes all across arch/mips. Nothing really stands out though APRP, the FPU code and syscall tracing code received multiple patches those all were small" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: mark O32+FP64 experimental for now MIPS: ftrace: Fix icache flush range error MIPS: Fix syscall tracing interface MIPS: asm: syscall: Fix copying system call arguments MIPS: Octeon: Fix fall through on bar type OCTEON_DMA_BAR_TYPE_SMALL MIPS: FPU: Fix conflict of register usage MIPS: Replace CONFIG_MIPS64 and CONFIG_MIPS32_R2 MIPS: math-emu: Fix prefx detection and COP1X function field definition MIPS: APRP: Choose the correct VPE loader by fixing the linking MIPS: APRP: Unregister rtlx interrupt hook at module exit MIPS: APRP: Fix the linking of rtlx interrupt hook MIPS: bcm47xx: Include missing errno.h for ENXIO MIPS: Alchemy: Fix unchecked kstrtoul return value MIPS: Fix randconfig build error.
-rw-r--r--arch/mips/Kconfig12
-rw-r--r--arch/mips/alchemy/board-gpr.c4
-rw-r--r--arch/mips/alchemy/board-mtx1.c4
-rw-r--r--arch/mips/bcm47xx/board.c1
-rw-r--r--arch/mips/include/asm/asmmacro.h4
-rw-r--r--arch/mips/include/asm/fpu.h2
-rw-r--r--arch/mips/include/asm/syscall.h10
-rw-r--r--arch/mips/include/uapi/asm/inst.h4
-rw-r--r--arch/mips/kernel/ftrace.c5
-rw-r--r--arch/mips/kernel/r4k_fpu.S16
-rw-r--r--arch/mips/kernel/rtlx-cmp.c3
-rw-r--r--arch/mips/kernel/rtlx-mt.c3
-rw-r--r--arch/mips/math-emu/cp1emu.c6
-rw-r--r--arch/mips/mti-malta/malta-amon.c2
-rw-r--r--arch/mips/mti-malta/malta-int.c4
-rw-r--r--arch/mips/pci/msi-octeon.c1
16 files changed, 46 insertions, 35 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dcae3a7035db..153447452d5e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2353,9 +2353,8 @@ config SECCOMP
2353 If unsure, say Y. Only embedded should say N here. 2353 If unsure, say Y. Only embedded should say N here.
2354 2354
2355config MIPS_O32_FP64_SUPPORT 2355config MIPS_O32_FP64_SUPPORT
2356 bool "Support for O32 binaries using 64-bit FP" 2356 bool "Support for O32 binaries using 64-bit FP (EXPERIMENTAL)"
2357 depends on 32BIT || MIPS32_O32 2357 depends on 32BIT || MIPS32_O32
2358 default y
2359 help 2358 help
2360 When this is enabled, the kernel will support use of 64-bit floating 2359 When this is enabled, the kernel will support use of 64-bit floating
2361 point registers with binaries using the O32 ABI along with the 2360 point registers with binaries using the O32 ABI along with the
@@ -2367,7 +2366,14 @@ config MIPS_O32_FP64_SUPPORT
2367 of your kernel & potentially improve FP emulation performance by 2366 of your kernel & potentially improve FP emulation performance by
2368 saying N here. 2367 saying N here.
2369 2368
2370 If unsure, say Y. 2369 Although binutils currently supports use of this flag the details
2370 concerning its effect upon the O32 ABI in userland are still being
2371 worked on. In order to avoid userland becoming dependant upon current
2372 behaviour before the details have been finalised, this option should
2373 be considered experimental and only enabled by those working upon
2374 said details.
2375
2376 If unsure, say N.
2371 2377
2372config USE_OF 2378config USE_OF
2373 bool 2379 bool
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index 9edc35ff8cf1..acf9a2a37f5a 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -53,10 +53,8 @@ void __init prom_init(void)
53 prom_init_cmdline(); 53 prom_init_cmdline();
54 54
55 memsize_str = prom_getenv("memsize"); 55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str) 56 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
57 memsize = 0x04000000; 57 memsize = 0x04000000;
58 else
59 strict_strtoul(memsize_str, 0, &memsize);
60 add_memory_region(0, memsize, BOOT_MEM_RAM); 58 add_memory_region(0, memsize, BOOT_MEM_RAM);
61} 59}
62 60
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 9969dbab19e3..25a59a23547e 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -52,10 +52,8 @@ void __init prom_init(void)
52 prom_init_cmdline(); 52 prom_init_cmdline();
53 53
54 memsize_str = prom_getenv("memsize"); 54 memsize_str = prom_getenv("memsize");
55 if (!memsize_str) 55 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
56 memsize = 0x04000000; 56 memsize = 0x04000000;
57 else
58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 58}
61 59
diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c
index 6d612e2b949b..cdd8246f92b3 100644
--- a/arch/mips/bcm47xx/board.c
+++ b/arch/mips/bcm47xx/board.c
@@ -1,3 +1,4 @@
1#include <linux/errno.h>
1#include <linux/export.h> 2#include <linux/export.h>
2#include <linux/string.h> 3#include <linux/string.h>
3#include <bcm47xx_board.h> 4#include <bcm47xx_board.h>
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index 3220c93ea981..69a9a22d014a 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -106,7 +106,7 @@
106 .endm 106 .endm
107 107
108 .macro fpu_save_double thread status tmp 108 .macro fpu_save_double thread status tmp
109#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 109#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
110 sll \tmp, \status, 5 110 sll \tmp, \status, 5
111 bgez \tmp, 10f 111 bgez \tmp, 10f
112 fpu_save_16odd \thread 112 fpu_save_16odd \thread
@@ -159,7 +159,7 @@
159 .endm 159 .endm
160 160
161 .macro fpu_restore_double thread status tmp 161 .macro fpu_restore_double thread status tmp
162#if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 162#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
163 sll \tmp, \status, 5 163 sll \tmp, \status, 5
164 bgez \tmp, 10f # 16 register mode? 164 bgez \tmp, 10f # 16 register mode?
165 165
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 6b9749540edf..58e50cbdb1a6 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -57,7 +57,7 @@ static inline int __enable_fpu(enum fpu_mode mode)
57 return 0; 57 return 0;
58 58
59 case FPU_64BIT: 59 case FPU_64BIT:
60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64)) 60#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
61 /* we only have a 32-bit FPU */ 61 /* we only have a 32-bit FPU */
62 return SIGFPE; 62 return SIGFPE;
63#endif 63#endif
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index 33e8dbfc1b63..f35b131977e6 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -13,6 +13,7 @@
13#ifndef __ASM_MIPS_SYSCALL_H 13#ifndef __ASM_MIPS_SYSCALL_H
14#define __ASM_MIPS_SYSCALL_H 14#define __ASM_MIPS_SYSCALL_H
15 15
16#include <linux/compiler.h>
16#include <linux/audit.h> 17#include <linux/audit.h>
17#include <linux/elf-em.h> 18#include <linux/elf-em.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
@@ -39,14 +40,14 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
39 40
40#ifdef CONFIG_32BIT 41#ifdef CONFIG_32BIT
41 case 4: case 5: case 6: case 7: 42 case 4: case 5: case 6: case 7:
42 return get_user(*arg, (int *)usp + 4 * n); 43 return get_user(*arg, (int *)usp + n);
43#endif 44#endif
44 45
45#ifdef CONFIG_64BIT 46#ifdef CONFIG_64BIT
46 case 4: case 5: case 6: case 7: 47 case 4: case 5: case 6: case 7:
47#ifdef CONFIG_MIPS32_O32 48#ifdef CONFIG_MIPS32_O32
48 if (test_thread_flag(TIF_32BIT_REGS)) 49 if (test_thread_flag(TIF_32BIT_REGS))
49 return get_user(*arg, (int *)usp + 4 * n); 50 return get_user(*arg, (int *)usp + n);
50 else 51 else
51#endif 52#endif
52 *arg = regs->regs[4 + n]; 53 *arg = regs->regs[4 + n];
@@ -57,6 +58,8 @@ static inline unsigned long mips_get_syscall_arg(unsigned long *arg,
57 default: 58 default:
58 BUG(); 59 BUG();
59 } 60 }
61
62 unreachable();
60} 63}
61 64
62static inline long syscall_get_return_value(struct task_struct *task, 65static inline long syscall_get_return_value(struct task_struct *task,
@@ -83,11 +86,10 @@ static inline void syscall_get_arguments(struct task_struct *task,
83 unsigned int i, unsigned int n, 86 unsigned int i, unsigned int n,
84 unsigned long *args) 87 unsigned long *args)
85{ 88{
86 unsigned long arg;
87 int ret; 89 int ret;
88 90
89 while (n--) 91 while (n--)
90 ret |= mips_get_syscall_arg(&arg, task, regs, i++); 92 ret |= mips_get_syscall_arg(args++, task, regs, i++);
91 93
92 /* 94 /*
93 * No way to communicate an error because this is a void function. 95 * No way to communicate an error because this is a void function.
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index b39ba25b41cc..f25181b19941 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -163,8 +163,8 @@ enum cop1_sdw_func {
163 */ 163 */
164enum cop1x_func { 164enum cop1x_func {
165 lwxc1_op = 0x00, ldxc1_op = 0x01, 165 lwxc1_op = 0x00, ldxc1_op = 0x01,
166 pfetch_op = 0x07, swxc1_op = 0x08, 166 swxc1_op = 0x08, sdxc1_op = 0x09,
167 sdxc1_op = 0x09, madd_s_op = 0x20, 167 pfetch_op = 0x0f, madd_s_op = 0x20,
168 madd_d_op = 0x21, madd_e_op = 0x22, 168 madd_d_op = 0x21, madd_e_op = 0x22,
169 msub_s_op = 0x28, msub_d_op = 0x29, 169 msub_s_op = 0x28, msub_d_op = 0x29,
170 msub_e_op = 0x2a, nmadd_s_op = 0x30, 170 msub_e_op = 0x2a, nmadd_s_op = 0x30,
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 185ba258361b..374ed74cd516 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -111,11 +111,10 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
111 safe_store_code(new_code1, ip, faulted); 111 safe_store_code(new_code1, ip, faulted);
112 if (unlikely(faulted)) 112 if (unlikely(faulted))
113 return -EFAULT; 113 return -EFAULT;
114 ip += 4; 114 safe_store_code(new_code2, ip + 4, faulted);
115 safe_store_code(new_code2, ip, faulted);
116 if (unlikely(faulted)) 115 if (unlikely(faulted))
117 return -EFAULT; 116 return -EFAULT;
118 flush_icache_range(ip, ip + 8); /* original ip + 12 */ 117 flush_icache_range(ip, ip + 8);
119 return 0; 118 return 0;
120} 119}
121#endif 120#endif
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 253b2fb52026..73b0ddf910d4 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -35,9 +35,9 @@
35LEAF(_save_fp_context) 35LEAF(_save_fp_context)
36 cfc1 t1, fcr31 36 cfc1 t1, fcr31
37 37
38#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 38#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
39 .set push 39 .set push
40#ifdef CONFIG_MIPS32_R2 40#ifdef CONFIG_CPU_MIPS32_R2
41 .set mips64r2 41 .set mips64r2
42 mfc0 t0, CP0_STATUS 42 mfc0 t0, CP0_STATUS
43 sll t0, t0, 5 43 sll t0, t0, 5
@@ -146,11 +146,11 @@ LEAF(_save_fp_context32)
146 * - cp1 status/control register 146 * - cp1 status/control register
147 */ 147 */
148LEAF(_restore_fp_context) 148LEAF(_restore_fp_context)
149 EX lw t0, SC_FPC_CSR(a0) 149 EX lw t1, SC_FPC_CSR(a0)
150 150
151#if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 151#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
152 .set push 152 .set push
153#ifdef CONFIG_MIPS32_R2 153#ifdef CONFIG_CPU_MIPS32_R2
154 .set mips64r2 154 .set mips64r2
155 mfc0 t0, CP0_STATUS 155 mfc0 t0, CP0_STATUS
156 sll t0, t0, 5 156 sll t0, t0, 5
@@ -191,7 +191,7 @@ LEAF(_restore_fp_context)
191 EX ldc1 $f26, SC_FPREGS+208(a0) 191 EX ldc1 $f26, SC_FPREGS+208(a0)
192 EX ldc1 $f28, SC_FPREGS+224(a0) 192 EX ldc1 $f28, SC_FPREGS+224(a0)
193 EX ldc1 $f30, SC_FPREGS+240(a0) 193 EX ldc1 $f30, SC_FPREGS+240(a0)
194 ctc1 t0, fcr31 194 ctc1 t1, fcr31
195 jr ra 195 jr ra
196 li v0, 0 # success 196 li v0, 0 # success
197 END(_restore_fp_context) 197 END(_restore_fp_context)
@@ -199,7 +199,7 @@ LEAF(_restore_fp_context)
199#ifdef CONFIG_MIPS32_COMPAT 199#ifdef CONFIG_MIPS32_COMPAT
200LEAF(_restore_fp_context32) 200LEAF(_restore_fp_context32)
201 /* Restore an o32 sigcontext. */ 201 /* Restore an o32 sigcontext. */
202 EX lw t0, SC32_FPC_CSR(a0) 202 EX lw t1, SC32_FPC_CSR(a0)
203 203
204 mfc0 t0, CP0_STATUS 204 mfc0 t0, CP0_STATUS
205 sll t0, t0, 5 205 sll t0, t0, 5
@@ -239,7 +239,7 @@ LEAF(_restore_fp_context32)
239 EX ldc1 $f26, SC32_FPREGS+208(a0) 239 EX ldc1 $f26, SC32_FPREGS+208(a0)
240 EX ldc1 $f28, SC32_FPREGS+224(a0) 240 EX ldc1 $f28, SC32_FPREGS+224(a0)
241 EX ldc1 $f30, SC32_FPREGS+240(a0) 241 EX ldc1 $f30, SC32_FPREGS+240(a0)
242 ctc1 t0, fcr31 242 ctc1 t1, fcr31
243 jr ra 243 jr ra
244 li v0, 0 # success 244 li v0, 0 # success
245 END(_restore_fp_context32) 245 END(_restore_fp_context32)
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c
index 56dc69635153..758fb3cd2326 100644
--- a/arch/mips/kernel/rtlx-cmp.c
+++ b/arch/mips/kernel/rtlx-cmp.c
@@ -112,5 +112,8 @@ void __exit rtlx_module_exit(void)
112 112
113 for (i = 0; i < RTLX_CHANNELS; i++) 113 for (i = 0; i < RTLX_CHANNELS; i++)
114 device_destroy(mt_class, MKDEV(major, i)); 114 device_destroy(mt_class, MKDEV(major, i));
115
115 unregister_chrdev(major, RTLX_MODULE_NAME); 116 unregister_chrdev(major, RTLX_MODULE_NAME);
117
118 aprp_hook = NULL;
116} 119}
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c
index 91d61ba422b4..9c1aca00fd54 100644
--- a/arch/mips/kernel/rtlx-mt.c
+++ b/arch/mips/kernel/rtlx-mt.c
@@ -144,5 +144,8 @@ void __exit rtlx_module_exit(void)
144 144
145 for (i = 0; i < RTLX_CHANNELS; i++) 145 for (i = 0; i < RTLX_CHANNELS; i++)
146 device_destroy(mt_class, MKDEV(major, i)); 146 device_destroy(mt_class, MKDEV(major, i));
147
147 unregister_chrdev(major, RTLX_MODULE_NAME); 148 unregister_chrdev(major, RTLX_MODULE_NAME);
149
150 aprp_hook = NULL;
148} 151}
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 506925b2c3f3..0b4e2e38294b 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1538,10 +1538,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1538 break; 1538 break;
1539 } 1539 }
1540 1540
1541 case 0x7: /* 7 */ 1541 case 0x3:
1542 if (MIPSInst_FUNC(ir) != pfetch_op) { 1542 if (MIPSInst_FUNC(ir) != pfetch_op)
1543 return SIGILL; 1543 return SIGILL;
1544 } 1544
1545 /* ignore prefx operation */ 1545 /* ignore prefx operation */
1546 break; 1546 break;
1547 1547
diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 592ac0427426..84ac523b0ce0 100644
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -72,7 +72,7 @@ int amon_cpu_start(int cpu,
72 return 0; 72 return 0;
73} 73}
74 74
75#ifdef CONFIG_MIPS_VPE_LOADER 75#ifdef CONFIG_MIPS_VPE_LOADER_CMP
76int vpe_run(struct vpe *v) 76int vpe_run(struct vpe *v)
77{ 77{
78 struct vpe_notifications *n; 78 struct vpe_notifications *n;
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index ca3e3a46a42f..2242181a6284 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -119,7 +119,7 @@ static void malta_hw0_irqdispatch(void)
119 119
120 do_IRQ(MALTA_INT_BASE + irq); 120 do_IRQ(MALTA_INT_BASE + irq);
121 121
122#ifdef MIPS_VPE_APSP_API 122#ifdef CONFIG_MIPS_VPE_APSP_API_MT
123 if (aprp_hook) 123 if (aprp_hook)
124 aprp_hook(); 124 aprp_hook();
125#endif 125#endif
@@ -310,7 +310,7 @@ static void ipi_call_dispatch(void)
310 310
311static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 311static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
312{ 312{
313#ifdef MIPS_VPE_APSP_API 313#ifdef CONFIG_MIPS_VPE_APSP_API_CMP
314 if (aprp_hook) 314 if (aprp_hook)
315 aprp_hook(); 315 aprp_hook();
316#endif 316#endif
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index d37be36dc659..2b91b0e61566 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -150,6 +150,7 @@ msi_irq_allocated:
150 msg.address_lo = 150 msg.address_lo =
151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff; 151 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32; 152 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
153 break;
153 case OCTEON_DMA_BAR_TYPE_BIG: 154 case OCTEON_DMA_BAR_TYPE_BIG:
154 /* When using big bar, Bar 0 is based at 0 */ 155 /* When using big bar, Bar 0 is based at 0 */
155 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff; 156 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;