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authorThomas Langer <thomas.langer@lantiq.com>2012-05-02 06:27:38 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-05-15 11:49:22 -0400
commit7705f6867bfc6f2ea42c3965a85df72abf070c86 (patch)
tree556ac1fafeb72b372873c404ab7e4cf47a917e63 /arch/mips/include
parenta8d096ef78c4d9a664754e1fad5e82dec2feec68 (diff)
MIPS: lantiq: fix early printk
The code was using a 32bit write operations in the early_printk code. This resulted in 3 zero bytes also being written to the serial port. This patch changes the memory access to 8bit. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3721/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 8a3c6be669d2..8bc9030525c0 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -34,6 +34,12 @@
34#define LTQ_ASC1_BASE_ADDR 0x1E100C00 34#define LTQ_ASC1_BASE_ADDR 0x1E100C00
35#define LTQ_ASC_SIZE 0x400 35#define LTQ_ASC_SIZE 0x400
36 36
37/*
38 * during early_printk no ioremap is possible
39 * lets use KSEG1 instead
40 */
41#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
42
37/* RCU - reset control unit */ 43/* RCU - reset control unit */
38#define LTQ_RCU_BASE_ADDR 0x1F203000 44#define LTQ_RCU_BASE_ADDR 0x1F203000
39#define LTQ_RCU_SIZE 0x1000 45#define LTQ_RCU_SIZE 0x1000